Memory, storage system, and memory operation method

Abstract

The present invention relates to the technical field of storage. Disclosed are a memory, a storage system, and a memory operation method. The method comprises: receiving an operation instruction from a controller; mapping a plurality of initial word line identifiers in the operation instruction into a plurality of physical word line identifiers; and by means of a plurality of first-type word lines indicated by the plurality of physical word line identifiers, executing an operation corresponding to the operation instruction on a plurality of first-type memory cell rows, wherein at least one third-type memory cell row is distributed between a first memory cell row and a second memory cell row among the plurality of first-type memory cell rows, and data stored in the plurality of first-type memory cell rows corresponds to a same piece of verification data. By means of the method, a plurality of pieces of data corresponding to a same piece of verification data can be written into discontinuous memory cell rows. In this way, the data stored in the adjacent memory cell rows can be respectively corrected by means of at least two pieces of verification data, thereby improving the data protection capability.

Description

Memory, memory system, and memory operating method Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a memory, a storage system, and a memory operating method. Background Art

[0002] When writing data to a memory device like a 3D NAND (NAND gate), verification data can be generated based on the written data to prevent errors when subsequently reading the data. This data is then verified against the verification data when it is read from the memory. If the verification fails, the correct data can be recovered based on the verification data. Ensuring successful data recovery in the event of a verification failure is a current research hotspot.

[0003] Summary of the Invention

[0004] The embodiments of the present application provide a memory, a storage system, and a memory operation method, which can be used to improve data protection capabilities. The technical solution is as follows:

[0005] In one aspect, a memory is provided, comprising:

[0006] a memory array comprising a plurality of memory cell rows;

[0007] a plurality of word lines, the plurality of word lines being coupled to the plurality of memory cell rows, respectively; and

[0008] a peripheral circuit coupled to the plurality of word lines and configured to:

[0009] receiving an operation instruction from a controller, wherein the operation instruction carries a plurality of initial word line identifiers;

[0010] Mapping the multiple initial word line identifiers to multiple physical word line identifiers;

[0011] Executing the operation corresponding to the operation instruction on a plurality of first-type memory cell rows through a plurality of first-type word lines indicated by the plurality of physical word line identifiers;

[0012] Among them, at least one third type memory cell row is distributed between the first memory cell row and the second memory cell row in the plurality of first type memory cell rows, and the data stored in the plurality of first type memory cell rows correspond to the same verification data.

[0013] Optionally, the peripheral circuit is configured as:

[0014] Each of the multiple initial word line identifiers is used as a pseudo word line identifier, and a physical word line identifier corresponding to each initial word line identifier is obtained from a stored mapping relationship between the pseudo word line identifier and the physical word line identifier.

[0015] Optionally, the mapping relationship includes a mapping relationship between a first pseudo word line identifier and a first physical word line identifier, and a mapping relationship between a second pseudo word line identifier and a second physical word line identifier;

[0016] The two memory cell rows coupled to the two word lines indicated by the first pseudo word line identifier and the second pseudo word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical identifier.

[0017] Optionally, the first pseudo word line is identified as a first pseudo word line number, the second pseudo word line is identified as a second pseudo word line number, and a difference between the first pseudo word line number and the second pseudo word line number is 1;

[0018] The first physical word line is identified as a first physical word line number, the second physical word line is identified as a second physical word line number, and a difference between the first physical word line number and the second physical word line number is greater than 1.

[0019] Optionally, the first pseudo word line number is smaller than the second pseudo word line number;

[0020] The second physical word line number is the sum of the first physical word line number and a reference value, where the reference value is a positive integer.

[0021] Optionally, at least one third-type memory cell row is distributed between every two adjacent memory cell rows in the plurality of first-type memory cell rows.

[0022] Optionally, the number of the third type of memory cell rows distributed between every two adjacent memory cell rows in the plurality of first type of memory cell rows is a reference number.

[0023] Optionally, the peripheral circuit is configured as:

[0024] If a word line mapping instruction is received from the controller, an operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers is performed.

[0025] Optionally, the peripheral circuit is further configured to:

[0026] If the word line mapping instruction is not received from the controller, performing the operation corresponding to the operation instruction on a plurality of second-type memory cell rows through a plurality of second-type word lines indicated by the plurality of initial word line identifiers;

[0027] The plurality of second-type memory cell rows are a plurality of continuous memory cell rows in the memory array, and the data stored in the plurality of second-type memory cell rows correspond to the same verification data.

[0028] Optionally, the operation instruction includes a write instruction, and the write instruction further carries a plurality of to-be-written data corresponding one-to-one to the plurality of initial word line identifiers;

[0029] The peripheral circuit is configured as follows:

[0030] The data to be written corresponding to each initial word line identifier is used as the data to be written corresponding to the corresponding physical word line identifier, and a programming operation is performed on the multiple first type storage cell rows through the multiple first type word lines to store the multiple data to be written in the multiple first type storage cell rows.

[0031] Optionally, the operation instruction includes a read instruction;

[0032] The peripheral circuit is configured as follows:

[0033] A read operation is performed on the plurality of first-type memory cell rows through the plurality of first-type word lines to obtain data respectively stored in the plurality of first-type memory cell rows.

[0034] Optionally, the peripheral circuit is further configured to:

[0035] If data stored in a third storage cell row among the plurality of first-type storage cell rows is erroneous data, determining an initial word line identifier corresponding to the physical word line identifier of the third storage cell row;

[0036] Acquiring the verification data based on the determined initial word line identifier;

[0037] The data stored in the third memory cell row is corrected based on the verification data.

[0038] In another aspect, a memory system is provided, the memory system including a memory, and a controller coupled to the memory and configured to control the memory;

[0039] The controller is configured to: send the operation instruction to the memory, wherein the operation instruction carries a plurality of initial word line identifiers;

[0040] The memory is configured to: receive the operation instruction, map the multiple initial word line identifiers to multiple physical word line identifiers; and perform the operation corresponding to the operation instruction on multiple first-type memory cell rows through multiple first-type word lines indicated by the multiple physical word line identifiers;

[0041] Among them, at least one third type memory cell row is distributed between the first memory cell row and the second memory cell row in the plurality of first type memory cell rows, and the data stored in the plurality of first type memory cell rows correspond to the same verification data.

[0042] Optionally, the controller is further configured to: send a word line mapping instruction to the memory;

[0043] The memory is further configured to, in response to the word line mapping instruction, execute an operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers.

[0044] Optionally, the controller is further configured to: not send the word line mapping instruction to the memory;

[0045] The memory is further configured to: perform the operation corresponding to the operation instruction on a plurality of second-type memory cell rows through a plurality of second-type word lines indicated by the plurality of initial word line identifiers;

[0046] The plurality of second-type memory cell rows are a plurality of continuous memory cell rows in the memory array, and the data stored in the plurality of second-type memory cell rows correspond to the same verification data.

[0047] Optionally, the operation instruction includes a write instruction, and the write instruction further carries a plurality of to-be-written data corresponding one-to-one to the plurality of initial word line identifiers;

[0048] The memory is configured to: use the to-be-written data corresponding to each initial word line identifier as the to-be-written data corresponding to the corresponding physical word line identifier, and perform a programming operation on the multiple first-category memory cell rows through the multiple first-category word lines to store the multiple to-be-written data in the multiple first-category memory cell rows.

[0049] Optionally, the operation instruction includes a read instruction;

[0050] The memory is configured to: perform a read operation on the plurality of first-type memory cell rows through the plurality of first-type word lines to obtain data respectively stored in the plurality of first-type memory cell rows;

[0051] The memory is further configured to: send a read data result to the controller, the read data result carrying the data respectively stored in the plurality of first-type memory cell rows;

[0052] The controller is configured to receive the read data result.

[0053] In another aspect, a method for operating a memory is provided, the method comprising:

[0054] receiving an operation instruction from a controller, wherein the operation instruction carries a plurality of initial word line identifiers;

[0055] Mapping the multiple initial word line identifiers to multiple physical word line identifiers;

[0056] Executing the operation corresponding to the operation instruction on a plurality of first-type memory cell rows through a plurality of first-type word lines indicated by the plurality of physical word line identifiers;

[0057] Among them, at least one third type memory cell row is distributed between the first memory cell row and the second memory cell row in the plurality of first type memory cell rows, and the data stored in the plurality of first type memory cell rows correspond to the same verification data.

[0058] Optionally, mapping the multiple initial word line identifiers to multiple physical word line identifiers includes:

[0059] Each of the multiple initial word line identifiers is used as a pseudo word line identifier, and a physical word line identifier corresponding to each initial word line identifier is obtained from a stored mapping relationship between the pseudo word line identifier and the physical word line identifier.

[0060] Optionally, the mapping relationship includes a mapping relationship between a first pseudo word line identifier and a first physical word line identifier, and a mapping relationship between a second pseudo word line identifier and a second physical word line identifier;

[0061] The two memory cell rows coupled to the two word lines indicated by the first pseudo word line identifier and the second pseudo word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical identifier.

[0062] Optionally, the first pseudo word line is identified as a first pseudo word line number, the second pseudo word line is identified as a second pseudo word line number, and a difference between the first pseudo word line number and the second pseudo word line number is 1;

[0063] The first physical word line is identified as a first physical word line number, the second physical word line is identified as a second physical word line number, and a difference between the first physical word line number and the second physical word line number is greater than 1.

[0064] Optionally, the first pseudo word line number is smaller than the second pseudo word line number;

[0065] The second physical word line number is the sum of the first physical word line number and a reference value, where the reference value is a positive integer.

[0066] Optionally, at least one third-type memory cell row is distributed between every two adjacent memory cell rows in the plurality of first-type memory cell rows.

[0067] Optionally, the number of the third type of memory cell rows distributed between every two adjacent memory cell rows in the plurality of first type of memory cell rows is a reference number.

[0068] Optionally, mapping the multiple initial word line identifiers to multiple physical word line identifiers includes:

[0069] If a word line mapping instruction is received from the controller, an operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers is performed.

[0070] Optionally, the method further includes:

[0071] If the word line mapping instruction is not received from the controller, performing the operation corresponding to the operation instruction on a plurality of second-type memory cell rows through a plurality of second-type word lines indicated by the plurality of initial word line identifiers;

[0072] The plurality of second-type memory cell rows are a plurality of consecutive memory cell rows in the memory array, and the data stored in the plurality of second-type memory cell rows correspond to the same verification data.

[0073] Optionally, the operation instruction includes a write instruction, and the write instruction further carries a plurality of to-be-written data corresponding one-to-one to the plurality of initial word line identifiers;

[0074] The plurality of first-category word lines indicated by the plurality of physical word line identifiers execute the operation corresponding to the operation instruction on a plurality of first-category memory cell rows, including:

[0075] The data to be written corresponding to each initial word line identifier is used as the data to be written corresponding to the corresponding physical word line identifier, and a programming operation is performed on the multiple first type storage cell rows through the multiple first type word lines to store the multiple data to be written in the multiple first type storage cell rows.

[0076] Optionally, the operation instruction includes a read instruction;

[0077] The plurality of first-category word lines indicated by the plurality of physical word line identifiers execute the operation corresponding to the operation instruction on a plurality of first-category memory cell rows, including:

[0078] A read operation is performed on the plurality of first-type memory cell rows through the plurality of first-type word lines to obtain data respectively stored in the plurality of first-type memory cell rows.

[0079] Optionally, the method further includes:

[0080] If data stored in a third storage cell row among the plurality of first-type storage cell rows is erroneous data, determining an initial word line identifier corresponding to the physical word line identifier of the third storage cell row;

[0081] Acquiring the verification data based on the determined initial word line identifier;

[0082] The data stored in the third memory cell row is corrected based on the verification data.

[0083] In an embodiment of the present application, since at least one third-type storage cell row is distributed between the first storage cell row and the second storage cell row in the plurality of first-type storage cell rows, and the data stored in the plurality of first-type storage cell rows corresponds to the same verification data, the method provided in the embodiment of the present application can achieve writing of multiple data corresponding to the same verification data into discontinuous storage cell rows. In this way, it is possible to achieve that the data stored in adjacent storage cell rows in the storage array correspond to different verification data. In this way, even if the charges between adjacent storage cell rows affect each other due to the small spacing between them, thereby causing the data stored in adjacent storage cell rows to be erroneous at the same time, since the data stored in the adjacent storage cell rows correspond to different verification data, the data stored in the adjacent storage cell rows can be corrected separately by at least two verification data, thereby improving data protection capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0085] FIG1 is a schematic diagram of a storage system 10 provided in an embodiment of the present application;

[0086] FIG2 is a schematic diagram of a storage device provided in an embodiment of the present application;

[0087] FIG3 is a schematic diagram of another storage device provided in an embodiment of the present application;

[0088] FIG4 is a schematic diagram of a memory 100 provided in an embodiment of the present application;

[0089] FIG5 is a cross-sectional schematic diagram of a memory array 110 including memory strings 111 provided in an embodiment of the present application;

[0090] FIG6 is a schematic diagram of a peripheral circuit provided in an embodiment of the present application;

[0091] FIG7 is a flow chart of a method for operating a memory provided by an embodiment of the present application;

[0092] FIG8 is a flow chart of another memory operation method provided by an embodiment of the present application;

[0093] FIG9 is a flowchart of a data write process provided by an embodiment of the present application;

[0094] FIG10 is a flow chart of reading data provided by an embodiment of the present application;

[0095] FIG11 is a flow chart of another memory operation method provided by an embodiment of the present application;

[0096] FIG12 is a flow chart of another memory operation method provided by an embodiment of the present application;

[0097] FIG13 is a schematic structural diagram of a controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0098] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0099] FIG1 is a schematic diagram of a storage system 10 provided in an embodiment of the present application. As shown in FIG1 , the storage system 10 includes: one or more memories 100 , and a controller 200 coupled to the memories 100 and configured to control the memories 100 .

[0100] The controller 200 can be configured to control operations performed by the memory 100, such as read, erase, and program operations. The controller 200 can also be configured to manage various functions related to data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, conversion of logical addresses to physical addresses, wear leveling, etc. Optionally, the controller 200 can also be configured to process error correction codes (ECC) for data read from or written to the memory 100. The controller 200 can also perform any other suitable functions, such as formatting the memory 100.

[0101] The controller 200 can also communicate with the external device according to a specific communication protocol. For example, the controller 200 can communicate with the external device through at least one of various interface protocols. The interface protocol can be a Universal Serial Bus (USB) protocol, a Multi-Media Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Development Environment (IDE) protocol, a FireWire protocol, etc.

[0102] In some embodiments, the controller 200 and one or more memories 100 can be integrated into various types of electronic devices. The electronic device can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. In this scenario, as shown in FIG1 , the storage system 10 further includes a host 300. The controller 200 is coupled to the host 300. The controller 200 can manage the data stored in the memory 100 and communicate with the host 300 to implement the functions of the aforementioned electronic device.

[0103] In other embodiments, the controller 200 and one or more memories 100 may be integrated into various types of storage devices.

[0104] As an example, as shown in FIG2 , the controller 200 and the single memory 100 may be integrated into a memory card 400. The memory card 400 may include a Personal Computer Memory Card International Association (PCMCIA, PC) card, a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multi-Media Card (MMC), a RS-MMC, a micro-MMC, a Secure Digital (SD) card, a Universal Flash Storage (UFS), etc. As shown in FIG2 , the memory card 400 may further include a connector 410 for coupling the memory card 400 to a host.

[0105] As another example, as shown in FIG3 , the controller 200 and the plurality of memories 100 may be integrated into a solid-state drive (SSD) 500. The SSD 500 may further include a connector 510 for coupling the SSD 500 to a host. The storage capacity and / or operating speed of the SSD 500 may be greater than the storage capacity and / or operating speed of the memory card 400.

[0106] In addition, the memory 100 in FIG1 to FIG3 can be any memory involved in the embodiments of the present application. For example, it can be a 3D NAND (NAND gate) memory. The structure of the memory 100 is explained below.

[0107] FIG4 is a schematic diagram of a memory 100 provided in an embodiment of the present application. As shown in FIG4 , the memory 100 includes:

[0108] A memory array 110 , wherein the memory array 110 includes a plurality of memory cell rows;

[0109] a plurality of word lines 120 , wherein the plurality of word lines 120 are respectively coupled to the plurality of memory cell rows;

[0110] The peripheral circuit 130 is coupled to the plurality of word lines 120 and is configured to perform operations such as programming (i.e., writing data) or reading data on a selected memory cell row among the plurality of memory cell rows, wherein the selected memory cell row is a memory cell row coupled to the selected word line, wherein, in order to perform operations such as programming or reading data, the peripheral circuit 130 is configured to execute the memory operation method provided in the embodiment of the present application.

[0111] Memory array 110 may be a NAND flash memory array. As shown in FIG1 , a NAND flash memory array includes a plurality of memory strings 111 arranged in an array on a substrate, with each memory string 111 extending vertically above the substrate (not shown). In some embodiments, each memory string 111 includes a plurality of memory cells 112 coupled in series and stacked vertically.

[0112] As shown in FIG4 , each memory string 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also known as a bottom select gate (BSG), or source select gate, and the drain select gate is also known as an upper select gate, top select gate (TSG), or drain select gate. The source select gate 113 and the drain select gate 114 may be configured to activate the selected memory string 111 during read and program operations.

[0113] In some embodiments, the drain select gate 114 of each memory string 111 is coupled to a corresponding bit line 115 , and data can be read from or written to the bit line 115 via an output bus (not shown).

[0114] In some embodiments, each memory string 111 is configured to apply a select voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 114 via one or more DSG lines 116. And / or, in some embodiments, each memory string 111 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 113) or a deselect voltage (e.g., 0V) to the corresponding source select gate 113 via one or more SSG lines 117.

[0115] As shown in FIG4 , the memory strings 111 may be organized into a plurality of blocks 140. For any one of the plurality of blocks 140, the block 140 may have a source line (SL) 118, through which the sources of all the memory strings 111 in the block 140 are coupled. The source line is also referred to as a common source line or an array common source (ACS).

[0116] The source line 118 can be used for grounding, so that in certain subsequent operations, the source of each memory cell in the memory string in the block 140 can be grounded. Optionally, in some other operations, the source of each memory cell in the memory string in the block 140 can also be connected to a high voltage via the source line 118.

[0117] Each block 140 is a basic data unit for an erase operation, that is, all memory cells 112 on the same block 140 are erased simultaneously. To erase the memory cells 112 in a selected block, a source line coupled to the selected block may be biased with an erase voltage (Vers), such as a high positive voltage (20V or higher).

[0118] It will be appreciated that in alternative embodiments, the erase operation may be performed at the half-block level, at the quarter-block level, or at any suitable fractional level having any suitable number of blocks or blocks.

[0119] As shown in FIG. 4 , the same layer of memory cells 112 of adjacent memory strings 111 in the same block 140 may be coupled via word lines 120 , which are used to select which layer of memory cells 112 in the block 140 are affected by read and program operations.

[0120] In some embodiments, each word line 120 is coupled to a page 150 to which memory cells 112 belong. Page 150 is the basic unit of data for programming operations. The size of a page 150 may be related to the number of memory strings 111 coupled by word lines 120 in a block 140. Each word line 120 may be coupled to the control gate (i.e., gate electrode) of each memory cell 112 in a corresponding page 150. It will be appreciated that a memory cell row is a plurality of memory cells 112 located in the same page 150.

[0121] It should be noted that the memory cells in the same layer of a block 140 correspond to the same word line, but the memory cells in the same layer can be divided into one or more pages. In other words, one word line can be coupled to one or more pages. For example, for SLC, one word line is coupled to one page, and for MLC, one word line is coupled to two pages.

[0122] FIG5 is a schematic cross-sectional view of a memory array 110 including memory strings 111 according to an embodiment of the present application. As shown in FIG5 , the memory strings 111 may extend vertically above the substrate 101 and through the stacked layers 102. The substrate 101 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0123] The stack 102 may include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104. The number of pairs of gate conductive layers 103 and gate-to-gate dielectric layers 104 in the stack 102 may determine the number of memory cells 112 in the memory array 110.

[0124] The gate conductive layer 103 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 103 includes a metal layer, such as a tungsten layer. In other embodiments, each gate conductive layer 103 includes a doped polysilicon layer. In addition, each gate conductive layer 103 may include a control gate surrounding the memory cell 112 and may extend laterally at the top of the stacked layer 102 as a DSG line 116, extend laterally at the bottom of the stacked layer 102 as an SSG line 117, or extend laterally between the DSG line 116 and the SSG line 117 as a word line 120.

[0125] As shown in FIG5 , the memory string 111 includes a channel structure 105 extending vertically through the stacked layer 102. In some embodiments, the channel structure 105 includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). The semiconductor channel includes silicon, such as polycrystalline silicon. The memory film is a composite dielectric layer including a tunneling layer, a memory layer (also called a "charge trapping / storage layer"), and a barrier layer.

[0126] In some embodiments, the channel structure 105 has a cylindrical shape (eg, a pillar shape), and the layers in the semiconductor channel and the memory film are arranged radially in this order from the center of the pillar toward the outer surface of the pillar.

[0127] It should be understood that, although not shown in FIG. 5 , the memory array 110 may further include other additional components, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, and the like.

[0128] 4 , peripheral circuitry 130 may be coupled to memory array 110 via bit lines 115, word lines 120, source lines 118, SSG lines 117, and DSG lines 116. Peripheral circuitry 130 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 110 by applying and sensing voltage and / or current signals to and from memory cells 112 via bit lines 115, word lines 120, source lines 118, SSG lines 117, and DSG lines 116.

[0129] The peripheral circuits 130 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG6 shows some exemplary peripheral circuits 130, which include a page buffer / sense amplifier 131, a column decoder / bit line (BL) driver 132, a row decoder / word line (WL) driver 133, a voltage generator 134, a control logic unit 135, a register 136, an interface 137, and a data bus 138. It should be understood that in some examples, additional peripheral circuits not shown in FIG6 may also be included.

[0130] The page buffer / sense amplifier 131 can be configured to read data from the memory array 110 and program (write) data to the memory array 110 based on control signals from the control logic unit 135. For example, the page buffer / sense amplifier 131 can store a page of program data (write data) to be programmed into one page 130 of the memory array 110. The page buffer / sense amplifier 131 can also perform verification operations to ensure that the data has been correctly programmed into the memory cell 112 coupled to the selected word line 120. The page buffer / sense amplifier 131 can also sense the low-power signal from the bit line 115, which represents the data bit stored in the memory cell 112, and amplify the small voltage swing to a recognizable logic level during a read operation.

[0131] The column decoder / bit line driver 132 may be configured to be controlled by the control logic unit 135 and select one or more memory strings 111 by applying a bit line voltage generated from the voltage generator 134 .

[0132] The row decoder / word line driver 133 can be configured to be controlled by the control logic unit 135 and select / deselect the block 140 of the memory array 110 and select / deselect the word line 120 of the block 140. The row decoder / word line driver 133 can also be configured to drive the word line 120 using the word line voltage (VWL) generated from the voltage generator 134. In some embodiments, the row decoder / word line driver 133 can also select / deselect and drive the SSG line 117 and the DSG line 116. As described in detail below, the row decoder / word line driver 133 is configured to perform an erase operation on the memory cell 112 coupled to the selected word line(s) 120.

[0133] The voltage generator 134 may be configured to be controlled by the control logic unit 135 and generate word line voltages (eg, read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 110 .

[0134] The control logic unit 135 may be coupled to each of the above-described peripheral circuits and configured to control operations of the respective circuits.

[0135] The register 136 may be coupled to the control logic unit 135 and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each circuit in the peripheral circuit.

[0136] Interface (I / F) 137 may be coupled to control logic unit 135 and function as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 135, as well as buffer status information received from control logic unit 135 and relay it to the host. Interface 137 may also be coupled to column decoder / bit line driver 132 via data bus 138 and function as a data I / O interface and data buffer to buffer data and relay it to or from memory array 110.

[0137] The above description of the memory-related hardware embodiment has similar beneficial effects as the following method embodiment. For technical details not disclosed in the memory-related hardware embodiment, please refer to the description of the method embodiment of this application for understanding.

[0138] Based on the memory shown in Figures 1 to 6, the controller 200 can write data to the memory cells in the memory array 110, or read data from the memory cells in the memory array 110 through the peripheral circuit 130 in the memory 100. After writing data to the memory cell, the charge stored in the memory cell reaches a specified state, but the charge stored in the memory cell may subsequently change due to the influence of the surrounding environment. In this way, after reading data from the memory cell, an error in the read data may occur. Based on this, after writing data to the memory array, verification data is also generated for the written data and the verification data is stored. If an error in the read data occurs when reading data later, the read data can be corrected based on the stored verification data to restore the correct data.

[0139] There are multiple ways to generate parity data. For example, methods include 1WL_RAID (redundant array of independent disks), 2WL_RAID, ..., nWL_RAID, etc. 1WL_RAID can be understood as generating one set of parity data for data stored in several consecutive storage cell rows. nWL_RAID can be understood as generating n sets of parity data for data stored in several consecutive storage cell rows, where n is a positive integer greater than 1.

[0140] A larger value for n indicates a greater amount of parity data generated for data stored in consecutive storage cell rows. This allows for recovery of the correct data based on this multiple copies of parity data, even if data stored in two or more consecutive storage cell rows is incorrect. Therefore, a larger value for n indicates a greater protection capability for the nWL_RAID mode.

[0141] The check data can be stored in SRAM (static random-access memory). In this scenario, when n is large, it is easy to increase the cost of SRAM. Alternatively, the check data can also be stored in a storage array. In this scenario, when n is large, it is easy to make the operation of writing data to the memory cumbersome, thereby reducing the write performance of the memory. Based on this, in many scenarios, the check data can be generated by 1WL_RAID to avoid the problems caused by nWL_RAID.

[0142] Currently, the number of WL layers in 3D NAND is increasing, resulting in a continuous decrease in the width between adjacent WLs. In this case, the charges stored in adjacent storage cell rows coupled by adjacent WLs can easily affect each other, resulting in a greater probability of simultaneous errors in the data stored in adjacent storage cell rows coupled by adjacent WLs. However, in the 1WL_RAID mode, since there is only one copy of parity data for the data stored in several consecutive storage cell rows, only one storage cell row among these consecutive storage cell rows is allowed to store data errors. If the data stored in two or more (including two) storage cell rows are all erroneous, the correct data cannot be restored based on the parity data.

[0143] Based on this, embodiments of the present application provide a memory operation method. By using the method provided in embodiments of the present application, while generating parity data using the 1WL_RAID method, data stored in adjacent memory cell rows can be allowed to fail simultaneously, indirectly achieving the protection capability of the nWL_RAID method.

[0144] The following is an explanation of the operating method of the memory provided in the embodiment of the present application.

[0145] Figure 7 is a flow chart of a memory operation method provided by an embodiment of the present application. This method is applied to the peripheral circuit of the memory shown in Figures 1-6, and is exemplarily applied to the control logic unit within the peripheral circuit. Subsequent embodiments will be explained using the peripheral circuit as the execution subject. As shown in Figure 7, this method includes the following steps.

[0146] Step 701: The peripheral circuit receives an operation instruction from a controller, where the operation instruction carries a plurality of initial word line identifiers.

[0147] In some embodiments, the controller can write data to the memory array using an operation instruction. In this scenario, the controller sends an operation instruction including a write instruction to the memory, and the peripheral circuit of the memory receives the operation instruction. The write instruction also carries a plurality of data to be written corresponding to a plurality of initial word line identifiers. The peripheral circuit then writes the proxy write data into the memory cell rows corresponding to the plurality of initial word line identifiers through steps 702 and 703.

[0148] When the controller sends a write instruction to the memory, it also generates a copy of verification data corresponding to the multiple data to be written. For example, the write instruction can also carry the verification data so that the verification data is also stored in the storage array. Optionally, the controller can also store the verification data in another storage device, such as SRAM. The embodiment of the present application does not limit the manner in which the controller stores the verification data.

[0149] In other embodiments, the controller can read data from the memory array using an operation instruction. In this scenario, the controller sends an operation instruction including a read instruction to the memory, and the peripheral circuit of the memory receives the operation instruction. Subsequently, the peripheral circuit can read data from the memory cell rows corresponding to the multiple initial word line identifiers through steps 702 and 703.

[0150] The initial word line identifier is used to uniquely identify a word line. For example, the initial word line identifier may be an initial word line number. For example, the multiple initial word line identifiers may be WL1-WL5. Alternatively, the initial word line identifier may be another symbol capable of identifying a word line, for example, the multiple initial word line identifiers may be W1a-WLe.

[0151] Step 702: The peripheral circuit maps a plurality of initial word line identifiers to a plurality of physical word line identifiers.

[0152] In an embodiment of the present application, in order to avoid writing multiple data to be written corresponding to the same verification data into several consecutive rows of storage cells, the peripheral circuit can also map multiple initial word line identifiers in the write instruction to multiple physical word line identifiers when receiving the write instruction sent by the controller, so that the storage cell rows indicated by the mapped multiple physical word line identifiers are discontinuous.

[0153] That is, in an embodiment of the present application, the peripheral circuit does not directly write data according to the word line indicated by the initial word line identifier in the write instruction, but maps the initial word line identifier in the write instruction according to certain rules, so as to facilitate subsequent writing of data according to the word line indicated by the mapped physical word line identifier.

[0154] Correspondingly, when the peripheral circuit receives a read instruction from the controller, it also needs to map the initial word line identifier carried in the read instruction to a physical word line identifier in order to read the correct data.

[0155] In some embodiments, the peripheral circuit may map multiple initial word line identifiers to multiple physical word line identifiers by taking each of the multiple initial word line identifiers as a pseudo word line identifier, and obtaining the physical word line identifier corresponding to each initial word line identifier from the stored mapping relationship between the pseudo word line identifier and the physical word line identifier.

[0156] Figure 8 is a flow chart of another memory operation method provided by an embodiment of the present application. As shown in Figure 8, upon receiving an operation instruction from the controller, the peripheral circuit first maps the initial word line identifier in the operation instruction to a physical word line identifier according to the mapping relationship between the pseudo word line identifier and the physical word line identifier, and then executes the operation instruction based on the mapped physical word line identifier.

[0157] To improve the efficiency of writing or reading data, a mapping relationship between pseudo word line identifiers and physical word line identifiers can be pre-configured in the peripheral circuit so that when the peripheral circuit needs to write data, it can directly map the initial word line identifier based on the mapping relationship.

[0158] Alternatively, the above mapping relationship may not be configured in the peripheral circuit. In this scenario, the peripheral circuit can temporarily map the initial word line identifier according to a certain algorithm when writing or reading data. The subsequent embodiments use the mapping relationship as an example for illustration.

[0159] For ease of understanding, the mapping relationship is explained below.

[0160] In some embodiments, the mapping relationship includes a mapping relationship between a first pseudo word line identifier and a first physical word line identifier, and a mapping relationship between a second pseudo word line identifier and a second physical word line identifier, wherein two memory cell rows coupled to two word lines indicated by the first pseudo word line identifier and the second pseudo word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to two word lines indicated by the first physical word line identifier and the second physical identifier.

[0161] The mapping relationship may include multiple pseudo word line identifiers and physical word line identifiers corresponding to the multiple pseudo word line identifiers. The first pseudo word line identifier and the second pseudo word line identifier may be two of the multiple pseudo word line identifiers.

[0162] Since the two memory cell rows coupled with the two word lines indicated by the first pseudo word line identifier and the second pseudo word line identifier are adjacent, and there are other memory cell rows distributed between the two memory cell rows coupled with the two word lines indicated by the first physical word line identifier and the second physical identifier, through this mapping relationship, it can be achieved that: when the memory cell rows indicated by multiple initial word line identifiers are continuous, the memory cell rows indicated by the multiple physical word line identifiers after mapping are discontinuous.

[0163] For example, the first pseudo word line is identified as a first pseudo word line number, the second pseudo word line is identified as a second pseudo word line number, and the difference between the first pseudo word line number and the second pseudo word line number is 1, that is, the two memory cell rows indicated by the first pseudo word line number and the second pseudo word line number are adjacent. The first physical word line is identified as a first physical word line number, the second physical word line is identified as a second physical word line number, and the difference between the first physical word line number and the second physical word line number is greater than 1, that is, other memory cell rows are distributed between the two memory cell rows indicated by the first physical word line number and the second physical word line number.

[0164] In some scenarios, the difference between the two physical word line numbers mapped from each pair of adjacent pseudo word line numbers can be set to a fixed value. In this scenario, when the first pseudo word line number is smaller than the second pseudo word line number, the second physical word line number can be the sum of the first physical word line number and a reference value, where the reference value is a positive integer.

[0165] For example, if the reference value is 5, the difference between the two physical word line numbers after mapping each of the two adjacent pseudo word line labels is 5.

[0166] Table 1 is a schematic diagram of a mapping relationship provided by an embodiment of the present application. As shown in Table 1, the physical word line identifiers corresponding to the pseudo word line identifiers WL1-WL5 are WL1, WL6, WL11, WL16, and WL21, respectively. The physical word line identifiers corresponding to the pseudo word line identifiers WL6-WL10 are WL26, WL31, WL36, WL41, and WL46, respectively. The physical word line identifiers corresponding to the pseudo word line identifiers WL11-WL15 are WL51, WL56, WL61, WL66, and WL71, respectively.

[0167] Among them, the five data corresponding to the pseudo word line identifiers WL1-WL5 correspond to the same verification data, the five data corresponding to the pseudo word line identifiers WL6-WL10 correspond to the same verification data, and the five data corresponding to the pseudo word line identifiers WL11-WL16 correspond to the same verification data. The explanations of other verification data in Table 1 are no longer explained one by one.

[0168] As shown in Table 1, for the five data corresponding to the same set of verification data, when the controller needs to write these five data, although the five initial word line numbers carried in the write instruction sent by the controller are five consecutive initial word line numbers, after the peripheral circuit maps these five initial word line numbers according to Table 1, the difference between the two physical word line numbers corresponding to every two adjacent initial word line numbers in these five initial word line numbers is 5, thereby realizing that these five data are written into five storage cell rows in sequence, and there are five other storage cell rows distributed between every two adjacent storage cell rows in these five storage cell rows.

[0169] Table 1

[0170] The mapping relationship shown in Table 1 can be pre-written by a technician into the peripheral circuit. For example, it can be written into a register of the peripheral circuit. When the control logic unit in the peripheral circuit needs to map the initial identifier to a physical word line identifier, it obtains the mapping relationship from the register.

[0171] In other scenarios, the difference between the two physical word line numbers after each adjacent pseudo word line number is mapped may not be set to a fixed value. For example, it may be set to a difference that changes according to a certain rule. For example, the physical word line identifiers corresponding to pseudo word line identifiers WL1-WL5 are WL1, WL3, WL6, WL10, and WL15, respectively. The difference between the two physical word line numbers after each adjacent pseudo word line number is mapped increases in the order of 2, 3, 4, and 5.

[0172] In other scenarios, each pseudo word line number can also be processed according to certain mathematical rules, and the resulting number is the corresponding physical word line number. In this way, it is also possible to achieve that the two physical word line numbers after the adjacent pseudo word line numbers are mapped are not adjacent. For example, the physical word line identifiers corresponding to the pseudo word line identifiers WL1-WL5 are WL2, WL6, WL12, WL20, and WL30 respectively. Among them, the physical word line number after each pseudo word line number is mapped is obtained by multiplying the pseudo word line number by 2.

[0173] The above examples are used to illustrate the expression forms of the mapping relationship. It should be noted that the mapping relationship provided in the embodiments of the present application is not limited to the above-mentioned expression forms. The mapping relationship provided in the embodiments of the present application includes any mapping relationship that can map adjacent pseudo word line numbers to two discontinuous physical word line numbers, and no further examples will be given here.

[0174] In addition, the above description is based on an example in which the word line identifier is a word line number. Optionally, when the word line identifier is another symbol for identifying a word line, the mapping relationship can also be designed with reference to the above method.

[0175] Step 703: The peripheral circuit performs an operation corresponding to the operation instruction on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by a plurality of physical word line identifiers. At least one third-type memory cell row is located between a first memory cell row and a second memory cell row in the plurality of first-type memory cell rows, and the data stored in the plurality of first-type memory cell rows corresponds to the same check data.

[0176] The first type of memory cell rows can be understood as memory cell rows coupled to the first type of word lines, and therefore, the first type of memory cell rows can also be referred to as selected memory cell rows. The third type of memory cell rows can be understood as memory cell rows other than the memory cell rows coupled to the first type of word lines, and therefore, the third type of memory cell rows can also be referred to as unselected memory cell rows.

[0177] In some embodiments, in order to maximize the protection capability of the verification data, at least one third-type memory cell row is distributed between every two adjacent memory cell rows in the plurality of first-type memory cell rows.

[0178] That is, for several data corresponding to the same verification data, there are no adjacent storage unit rows in the storage unit rows storing these data, so as to avoid the inability to restore the correct data when the data in the adjacent storage rows are all wrong.

[0179] For example, the number of the third type of memory cell rows distributed between every two adjacent memory cell rows in the plurality of first type of memory cell rows is a reference number.

[0180] For example, when the difference between the two physical self-word line identifiers corresponding to the two adjacent pseudo-word line identifiers in the mapping relationship in step 702 is a parameter value, the number of third-type memory cell rows distributed between every two adjacent memory cell rows in the plurality of first-type memory cell rows is a reference number. The reference value is the same as the reference number, for example, 5 in reference Table 1.

[0181] Optionally, at least one third-type memory cell row may be distributed between some adjacent memory cell rows in the plurality of first-type memory cell rows, so that some adjacent memory cell rows are physically adjacent. This solution can also improve the protection capability of the verification data compared to the plurality of first-type memory cell rows being a continuous section of memory cell rows in the memory array.

[0182] Among them, when the physical word line identifier corresponding to the initial word line is obtained through the mapping relationship in step 702, the specific situation of the third type of storage cell rows distributed between each adjacent two storage cell rows in multiple first type storage cell rows is related to the physical word line identifier corresponding to the pseudo word line identifier in the mapping relationship.

[0183] As shown in Table 1, assuming that the initial word lines are labeled WL1-WL5, the corresponding physical word line labels after mapping are WL1, WL6, WL11, WL16, and WL21. In this scenario, the first-category memory cell rows are five memory cell rows coupled to WL1, WL6, WL11, WL16, and WL21. Five third-category memory cell rows are distributed between every two adjacent memory cell rows.

[0184] For other examples of the third type of memory cell rows distributed between every two adjacent memory cell rows in the plurality of first type memory cell rows, reference may be made to the above content, and no further examples will be given here.

[0185] In addition, based on step 701, it can be known that the operation instruction may include a write instruction or a read instruction. Step 703 is explained below in two scenarios.

[0186] Scenario 1: The operation instruction includes a write instruction.

[0187] In scenario one, the implementation method of performing the operation corresponding to the operation instruction on multiple first-class storage cell rows through multiple first-class word lines indicated by multiple physical word line identifiers can be: using the to-be-written data corresponding to each initial word line identifier as the to-be-written data corresponding to the corresponding physical word line identifier, and performing programming operations on multiple first-class storage cell rows through multiple first-class word lines to store the multiple to-be-written data in multiple first-class storage cell rows.

[0188] Since at least one third-type storage cell row is distributed between the first storage cell row and the second storage cell row in the plurality of first-type storage cell rows, and the data stored in the plurality of first-type storage cell rows corresponds to the same verification data, the method provided in the embodiment of the present application can achieve writing of multiple data corresponding to the same verification data into discontinuous storage cell rows. In this way, the data stored in adjacent storage cell rows in the storage array can correspond to different verification data. In this way, even if the charges between adjacent storage cell rows affect each other due to the small spacing between them, thereby causing the data stored in adjacent storage cell rows to be erroneous at the same time, since the data stored in the adjacent storage cell rows correspond to different verification data, the data stored in the adjacent storage cell rows can be corrected separately by at least two verification data, thereby improving data protection capabilities.

[0189] Figure 9 is a data writing flow chart provided by an embodiment of the present application. As shown in Figure 9, the data writing flow chart includes the following steps.

[0190] (1) The controller obtains the data to be written to the storage array.

[0191] (2) The controller divides the data to be written into multiple copies of data, each copy of which corresponds to a part of the continuous WL number, for example, WL1-5 corresponds to a copy of the data to be written, and WL6-10 corresponds to a copy of the data to be written.

[0192] (3) The controller generates multiple verification data based on the multiple copies of data.

[0193] In some embodiments, the check data can be generated using a parity check. For example, for any piece of data, the total number of bits in the binary encoding of the data that are 1 is determined, and then check data is generated to record the parity of this total number. This facilitates subsequent verification of the read data based on the check data.

[0194] The above is used to illustrate the method of generating verification data. Optionally, other methods can also be used to generate verification data, which will not be described one by one here.

[0195] (4) The controller sends a write instruction to the memory, which carries multiple copies of data and a continuous WL number corresponding to each copy of data.

[0196] (5) The memory receives the write instruction and performs the following operations on each piece of data and the corresponding consecutive WL number:

[0197] Each WL number in the continuous WL number is used as a pseudo WL number, and mapped according to the mapping relationship to obtain the physical WL number corresponding to each pseudo WL number, to obtain several discontinuous physical WL numbers, and then the data is written in sequence into several discontinuous storage unit rows indicated by the discontinuous physical WL numbers.

[0198] In addition, in the data writing process, since several data corresponding to the same verification data are written into non-contiguous memory cell rows, when writing data into the memory array, program disturb (program disturb) generated when writing data to adjacent memory cell rows can be reduced.

[0199] Scenario 2: The operation instruction includes a read instruction.

[0200] In scenario two, the operation corresponding to the operation instruction performed on multiple first-class storage cell rows by multiple first-class word lines indicated by multiple physical word line identifiers can be implemented by performing a read operation on multiple first-class storage cell rows through multiple first-class word lines to obtain data stored in the multiple first-class storage cell rows respectively.

[0201] In addition, after obtaining the data stored in the plurality of first-type memory cell rows, the peripheral circuit may also send a read data result to the controller, the read data result carrying the data stored in the plurality of first-type memory cell rows, so that the controller receives the read data result. The controller determines the data read this time based on the read data result.

[0202] In addition, after the peripheral circuit obtains the data stored in multiple first-type storage cell rows, if the data stored in the third storage cell row among the multiple first-type storage cell rows is erroneous data, the initial word line identifier corresponding to the physical word line identifier of the third storage cell row is determined; verification data is obtained based on the determined initial word line identifier; and the data stored in the third storage cell row is corrected based on the verification data.

[0203] After acquiring the data stored in the plurality of first-type memory cell rows, the peripheral circuit can verify whether the plurality of data contains erroneous data. The embodiments of the present application do not limit the manner in which the peripheral circuit verifies whether the read data contains erroneous data. For example, the peripheral circuit can send the read data to a controller, and a host connected to the controller can determine whether the read data contains erroneous data.

[0204] In some embodiments, when the controller writes data to the storage array, it also generates a correspondence between the initial word line identifier and the verification data. The correspondence can be stored in the storage array or in other storage devices. When the correspondence is stored in the storage array, the peripheral circuit can obtain the identifier of the verification data corresponding to the initial word line identifier corresponding to the physical word line identifier of the third storage cell row based on the correspondence, and then obtain the verification data based on the identifier of the verification data. When the correspondence is stored in other storage devices, the peripheral circuit can send the initial word line identifier corresponding to the physical word line identifier of the third storage cell row to the other storage devices, and the other storage devices obtain the identifier of the verification data corresponding to the initial word line identifier corresponding to the physical word line identifier of the third storage cell row based on the correspondence, and then the peripheral circuit obtains the verification data based on the identifier of the verification data.

[0205] There are multiple implementations for the peripheral circuit to obtain the verification data based on the verification data identifier. For example, when the verification data is stored in a storage array, the peripheral circuit can directly read the verification data based on the verification data identifier. For another example, when the verification data is stored in another storage device, the peripheral circuit can directly read the verification data from the other storage device via a controller based on the verification data identifier.

[0206] In addition, the implementation method for the peripheral circuit to determine the initial word line identifier corresponding to the physical word line identifier of the third memory cell row can refer to the implementation method for mapping the initial word line identifier to the physical word line identifier in step 702. For example, the initial word line identifier corresponding to the physical word line identifier of the third memory cell row can be determined using the mapping relationship shown in Table 1, which will not be described in detail here.

[0207] In addition, in some embodiments, after obtaining the data stored in the plurality of first-type memory cell rows, the peripheral circuit may directly send the plurality of data to the controller, which then determines whether the plurality of data contains errors and corrects the errors based on a pre-stored mapping relationship between the initial word line identifier and the verification data. In this scenario, since the controller stores the mapping relationship between the initial word line identifier and the verification data, the controller does not need to perform word line mapping and can directly correct the errors based on the pre-stored mapping relationship between the initial word line identifier and the verification data.

[0208] Figure 10 is a data reading flow chart provided by an embodiment of the present application. As shown in Figure 10, the data reading flow chart includes the following steps.

[0209] (1) The controller sends a read command to the memory. The read command carries several consecutive WL numbers corresponding to the data to be read, such as WL1-5, WL6-10, etc.

[0210] (2) The memory receives a read instruction and performs the following operations on each part of the consecutive WL numbers:

[0211] Each WL number in this part of continuous WL numbers is used as a pseudo WL number, and mapped according to the mapping relationship to obtain the physical WL number corresponding to each pseudo WL number, and then the corresponding data is read from the storage unit row indicated by the physical WL corresponding to each pseudo WL number to obtain the data corresponding to this part of continuous WL numbers, and the read data result is sent to the controller.

[0212] (3) The controller verifies and corrects the read data results based on the check data corresponding to each part of the continuous WL number.

[0213] The following further explains the technical effects of the solution provided in the embodiment of the present application in combination with Table 1 and Table 2.

[0214] Table 2

[0215] In Table 2, when the peripheral circuit receives a write instruction, it directly writes data according to the word line indicated by the initial word line identifier. For example, the 5 initial word lines carried by the write instruction are numbered WL1-5 and 5 data, and these 5 data correspond to the same verification data. When the peripheral circuit receives the write instruction, it directly stores these 5 data in the 5 storage cell rows respectively coupled to WL1-5. In this way, the 5 data corresponding to the same verification data are written into 5 consecutive storage cell rows. If the data stored in two adjacent storage cell rows in the 5 consecutive storage cell rows are both wrong, it is impossible to recover the data stored in these two adjacent storage cell rows based on the verification data.

[0216] However, as shown in Table 1, for the five data corresponding to the same verification data, although the five initial word line numbers carried in the write instruction sent by the controller are five consecutive initial word line numbers, after the peripheral circuit maps these five initial word line numbers according to Table 1, the difference between the two physical word line numbers corresponding to each two adjacent initial word line numbers in these five initial word line numbers is 5.

[0217] For example, a write instruction carries five initial word line numbers, WL1-5, and five data items, corresponding to the same set of parity data. Upon receiving the write instruction, the peripheral circuit determines, based on Table 1, the physical word line numbers WL1, WL6, WL11, WL16, and WL21 mapped to the initial word line numbers WL1-5. These five data items are stored in the five memory cell rows coupled to WL1, WL6, WL11, WL16, and WL21, respectively. In this way, the five data items corresponding to the same parity data are written to the five alternate memory cell rows, with five third-category memory cell rows distributed between every two adjacent memory cell rows. Subsequently, if the data stored in two adjacent memory cell rows in a series of consecutive memory cell rows are both erroneous, for example, if the data stored in two adjacent memory cell rows coupled to WL1 and WL2 are both erroneous, since the data stored in the two adjacent memory cell rows coupled to WL1 and WL2 correspond to different parity data, corrections can be performed based on the corresponding parity data.

[0218] In addition, in the embodiment of the present application, the controller may further control the peripheral circuit to determine whether to execute the operation instruction according to step 702 and step 703. Based on this, in some embodiments, in step 702, the implementation method of mapping the multiple initial word line identifiers to the multiple physical word line identifiers may be: upon receiving the word line mapping instruction from the controller, the peripheral circuit executes the operation of mapping the multiple initial word line identifiers to the multiple physical word line identifiers.

[0219] FIG11 is a flow chart of another memory operation instruction provided by an embodiment of the present application. As shown in FIG11 , when the peripheral circuit receives an operation instruction from the controller, it first determines whether a word line mapping instruction from the controller is currently received. If the judgment result is yes, then steps 702 and 703 are executed. That is, the peripheral circuit maps multiple initial word line identifiers to multiple physical word line identifiers, and performs the operation corresponding to the operation instruction on multiple first-class word lines indicated by the multiple physical word line identifiers. Among them, there is at least one third-class memory cell row distributed between the first memory cell row and the second memory cell row in the multiple first-class memory cell rows, and the data stored in the multiple first-class memory cell rows corresponds to the same verification data.

[0220] Accordingly, if the peripheral circuit does not receive a word line mapping instruction from the controller, the peripheral circuit performs an operation corresponding to the operation instruction on multiple second-class storage cell rows through multiple second-class word lines indicated by multiple initial word line identifiers; wherein the multiple second-class storage cell rows are multiple consecutive storage cell rows in the storage array, and the data stored in the multiple second-class storage cell rows corresponds to the same verification data.

[0221] Figure 12 is a schematic diagram of a flow chart of operation instructions for another memory device provided by an embodiment of the present application. As shown in Figure 12, upon receiving an operation instruction from a controller, the peripheral circuit first determines whether a wordline mapping instruction has been received from the controller. If the determination result is negative, steps 702 and 703 are not executed. Instead, the operation corresponding to the operation instruction is performed on multiple second-type memory cell rows using multiple second-type wordlines indicated by multiple initial wordline identifiers.

[0222] Based on this, in scenarios where the peripheral circuit needs to determine whether to execute operation instructions according to steps 702 and 703, for example, in scenarios where the data to be written is of high importance, the controller can send a word line mapping instruction to the peripheral circuit so that the peripheral circuit executes steps 702 and 703 in response to the word line mapping instruction, thereby improving the protection capability of the verification data on the data to be written.

[0223] Optionally, in a scenario where it is not necessary for the peripheral circuit to execute the operation instructions according to steps 702 and 703, for example, in a scenario where the importance of the data to be written is average, the controller may not send a word line mapping instruction to the peripheral circuit, so that the peripheral circuit directly performs the operation on the storage cell row indicated by the initial word line identifier.

[0224] The word line mapping instruction may be a predix CMD (a type of command).

[0225] In summary, in the embodiment of the present application, since there is at least one third-type storage cell row distributed between the first storage cell row and the second storage cell row in the plurality of first-type storage cell rows, and the data stored in the plurality of first-type storage cell rows corresponds to the same verification data, the method provided in the embodiment of the present application can achieve writing of multiple data corresponding to the same verification data into discontinuous storage cell rows. In this way, it is possible to achieve that the data stored in adjacent storage cell rows in the storage array correspond to different verification data. In this way, even if the charges between adjacent storage cell rows affect each other due to the small spacing between them, thereby causing the data stored in adjacent storage cell rows to be erroneous at the same time, since the data stored in the adjacent storage cell rows correspond to different verification data, the data stored in the adjacent storage cell rows can be corrected separately by at least two verification data, thereby improving the data protection capability.

[0226] Based on the embodiment shown in Figure 7, an embodiment of the present application also provides a memory, which includes: a memory array, the memory array includes multiple rows of memory cells; multiple word lines, the multiple word lines are respectively coupled to the multiple rows of memory cells; and a peripheral circuit, the peripheral circuit is coupled to the multiple word lines and is configured to implement the operating method of the memory provided by the embodiment of the present application.

[0227] Specifically, the peripheral circuit is configured to: receive an operation instruction from a controller, the operation instruction carrying multiple initial word line identifiers; map the multiple initial word line identifiers to multiple physical word line identifiers; perform operations corresponding to the operation instructions on multiple first-class storage cell rows through multiple first-class word lines indicated by the multiple physical word line identifiers; wherein, at least one third-class storage cell row is distributed between the first storage cell row and the second storage cell row in the multiple first-class storage cell rows, and the data stored in the multiple first-class storage cell rows corresponds to the same verification data.

[0228] Optionally, the peripheral circuit is configured to: take each of the multiple initial word line identifiers as a pseudo word line identifier, and obtain the physical word line identifier corresponding to each initial word line identifier from a stored mapping relationship between the pseudo word line identifier and the physical word line identifier.

[0229] Optionally, the mapping relationship includes a mapping relationship between a first pseudo word line identifier and a first physical word line identifier, and a mapping relationship between a second pseudo word line identifier and a second physical word line identifier; the two memory cell rows coupled by the two word lines indicated by the first pseudo word line identifier and the second pseudo word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled by the first physical word line identifier and the two word lines indicated by the second physical identifier.

[0230] Optionally, the first pseudo word line is identified as a first pseudo word line number, the second pseudo word line is identified as a second pseudo word line number, and the difference between the first pseudo word line number and the second pseudo word line number is 1; the first physical word line is identified as a first physical word line number, the second physical word line is identified as a second physical word line number, and the difference between the first physical word line number and the second physical word line number is greater than 1.

[0231] Optionally, the first pseudo word line number is smaller than the second pseudo word line number; the second physical word line number is the sum of the first physical word line number and a reference value, and the reference value is a positive integer.

[0232] Optionally, at least one third-type memory cell row is distributed between every two adjacent memory cell rows in the plurality of first-type memory cell rows.

[0233] Optionally, the number of the third type of memory cell rows distributed between every two adjacent memory cell rows in the plurality of first type of memory cell rows is a reference number.

[0234] Optionally, the peripheral circuit is configured to: if a word line mapping instruction is received from the controller, execute an operation of mapping the plurality of initial word line identifiers to a plurality of physical word line identifiers.

[0235] Optionally, the peripheral circuit is further configured to: if no word line mapping instruction is received from the controller, then perform an operation corresponding to the operation instruction on multiple second-class storage cell rows through multiple second-class word lines indicated by multiple initial word line identifiers; wherein the multiple second-class storage cell rows are multiple consecutive storage cell rows in the storage array, and the data stored in the multiple second-class storage cell rows corresponds to the same verification data.

[0236] Optionally, the operation instruction includes a write instruction, and the write instruction further carries a plurality of to-be-written data corresponding one-to-one with the plurality of initial word line identifiers. The peripheral circuit is configured to: use the to-be-written data corresponding to each initial word line identifier as the to-be-written data corresponding to the corresponding physical word line identifier, and perform a programming operation on the plurality of first-category memory cell rows via the plurality of first-category word lines to store the plurality of to-be-written data in the plurality of first-category memory cell rows.

[0237] Optionally, the operation instruction includes a read instruction. The peripheral circuit is configured to: perform a read operation on the plurality of first-type memory cell rows through the plurality of first-type word lines to obtain data respectively stored in the plurality of first-type memory cell rows.

[0238] Optionally, the peripheral circuit is further configured to: if the data stored in the third storage cell row among the multiple first-type storage cell rows is erroneous data, determine the initial word line identifier corresponding to the physical word line identifier of the third storage cell row; obtain verification data based on the determined initial word line identifier; and correct the data stored in the third storage cell row based on the verification data.

[0239] The specific implementation of the functions of the above peripheral circuits can refer to the embodiment shown in FIG7 , which will not be described in detail here.

[0240] In addition, an embodiment of the present application further provides a storage system, which includes a memory and a controller coupled to the memory and configured to control the memory.

[0241] The controller is configured to send an operation instruction to the memory, the operation instruction carrying multiple initial word line identifiers. The memory is configured to receive the operation instruction, map the multiple initial word line identifiers to multiple physical word line identifiers, and perform an operation corresponding to the operation instruction on multiple first-category memory cell rows via multiple first-category word lines indicated by the multiple physical word line identifiers.

[0242] Among them, at least one third type memory cell row is distributed between the first memory cell row and the second memory cell row in the plurality of first type memory cell rows, and data stored in the plurality of first type memory cell rows correspond to the same verification data.

[0243] Optionally, the controller is further configured to: send a word line mapping instruction to the memory; and the memory is further configured to: execute an operation of mapping the multiple initial word line identifiers into multiple physical word line identifiers in response to the word line mapping instruction.

[0244] Optionally, the controller is further configured to: not send a wordline mapping instruction to the memory; and the memory is further configured to: perform an operation corresponding to the operation instruction on a plurality of second-type memory cell rows using a plurality of second-type wordlines indicated by a plurality of initial wordline identifiers. The plurality of second-type memory cell rows are a plurality of consecutive memory cell rows in the memory array, and the data stored in the plurality of second-type memory cell rows corresponds to the same check data.

[0245] Optionally, the operation instruction includes a write instruction, and the write instruction further carries a plurality of to-be-written data corresponding one-to-one with the plurality of initial word line identifiers. The memory is configured to: use the to-be-written data corresponding to each initial word line identifier as the to-be-written data corresponding to the corresponding physical word line identifier, and perform a programming operation on the plurality of first-category memory cell rows via the plurality of first-category word lines to store the plurality of to-be-written data in the plurality of first-category memory cell rows.

[0246] Optionally, the operation instruction includes a read instruction. The memory is configured to: perform a read operation on the plurality of first-category memory cell rows via the plurality of first-category word lines to obtain data respectively stored in the plurality of first-category memory cell rows; the memory is further configured to: send a read data result to the controller, the read data result carrying the data respectively stored in the plurality of first-category memory cell rows; and the controller is configured to: receive the read data result.

[0247] The implementation of the functions of the above controller and memory can refer to the embodiment shown in Figure 7, and will not be repeated here.

[0248] Figure 13 is a schematic diagram of the structure of a controller provided by an embodiment of the present application. As shown in Figure 13, the controller 1300 includes a processing unit 1301, which can be, for example, an MCU (microcontroller unit).

[0249] The controller 1300 is used to implement the functions of the controller in the aforementioned embodiment to implement the storage system provided by the embodiment of the present application. Specific implementation methods can refer to the embodiment shown in FIG7 and will not be described in detail here.

[0250] In addition, an embodiment of the present application further provides a peripheral circuit, in which a control logic unit includes at least one software module, and the at least one software module is used to implement any step in the memory operation method in the embodiment shown in FIG. 7 .

[0251] In addition, an embodiment of the present application further provides a computer storage medium, on which instructions are stored. When the instructions are executed by a peripheral circuit in the memory, any step in the memory operation method in the embodiment shown in FIG. 7 is implemented.

[0252] On the other hand, a computer program product including instructions is provided, which implements any step of the memory operation method in the embodiment shown in FIG. 7 when the instructions are executed in a peripheral circuit.

[0253] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0254] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A memory, characterized in that: The memory comprises: A memory array, the memory array comprising a plurality of memory cell rows; a plurality of word lines, the plurality of word lines being respectively coupled to the plurality of memory cell rows; and a peripheral circuit coupled to the plurality of word lines and configured to: receiving an operation instruction from a controller, wherein the operation instruction carries a plurality of initial word line identifiers; Mapping the multiple initial word line identifiers to multiple physical word line identifiers; Execute the operation corresponding to the operation instruction on a plurality of first-type storage cell rows through a plurality of first-type word lines indicated by the plurality of physical word line identifiers; Among them, at least one third type of storage cell row is distributed between the first storage cell row and the second storage cell row in the plurality of first type of storage cell rows, and the data stored in the plurality of first type of storage cell rows correspond to the same verification data.

2. The memory according to claim 1, wherein: The peripheral circuit is configured as: Each of the multiple initial word line identifiers is used as a pseudo word line identifier, and a physical word line identifier corresponding to each initial word line identifier is obtained from a stored mapping relationship between the pseudo word line identifier and the physical word line identifier.

3. The memory according to claim 2, wherein: The mapping relationship includes a mapping relationship between a first pseudo word line identifier and a first physical word line identifier, and a mapping relationship between a second pseudo word line identifier and a second physical word line identifier; The two memory cell rows coupled to the two word lines indicated by the first pseudo word line identifier and the second pseudo word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical identifier.

4. The memory according to claim 3, wherein: The first pseudo word line is identified as a first pseudo word line number, the second pseudo word line is identified as a second pseudo word line number, and a difference between the first pseudo word line number and the second pseudo word line number is 1; The first physical word line is identified as a first physical word line number, the second physical word line is identified as a second physical word line number, and the difference between the first physical word line number and the second physical word line number is The value is greater than 1.

5. The memory according to claim 4, wherein: The first pseudo word line number is smaller than the second pseudo word line number; The second physical word line number is the sum of the first physical word line number and a reference value, and the reference value is a positive integer.

6. The memory according to claim 1, wherein: At least one third type of memory cell row is distributed between every two adjacent memory cell rows in the plurality of first type of memory cell rows.

7. The memory according to claim 6, wherein: The number of the third type of memory cell rows distributed between every two adjacent memory cell rows in the plurality of first type of memory cell rows is a reference number.

8. The memory according to claim 1, wherein: The peripheral circuit is configured as: If a word line mapping instruction is received from the controller, an operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers is performed.

9. The memory according to claim 8, characterized in that The peripheral circuit is further configured as: If the word line mapping instruction is not received from the controller, performing the operation corresponding to the operation instruction on a plurality of second-type memory cell rows through a plurality of second-type word lines indicated by the plurality of initial word line identifiers; The plurality of second-type storage cell rows are a plurality of continuous storage cell rows in the storage array, and the data stored in the plurality of second-type storage cell rows correspond to the same verification data.

10. The memory according to claim 1, wherein: The operation instruction includes a write instruction, and the write instruction also carries a plurality of to-be-written data corresponding one-to-one to the plurality of initial word line identifiers; The peripheral circuit is configured as: The data to be written corresponding to each initial word line identifier is used as the data to be written corresponding to the corresponding physical word line identifier, and a programming operation is performed on the multiple first-type storage cell rows through the multiple first-type word lines to store the multiple data to be written in the multiple first-type storage cell rows.

11. The memory according to claim 1, wherein: The operation instruction includes a read instruction; The peripheral circuit is configured as: A read operation is performed on the plurality of first-type memory cell rows through the plurality of first-type word lines to obtain data respectively stored in the plurality of first-type memory cell rows.

12. The memory according to claim 11, wherein: The peripheral circuit is further configured as: If data stored in a third storage cell row among the plurality of first-type storage cell rows is erroneous data, determining an initial word line identifier corresponding to the physical word line identifier of the third storage cell row; Acquiring the verification data based on the determined initial word line identifier; The data stored in the third memory cell row is corrected based on the verification data.

13. A storage system, characterized in that: The storage system includes a memory, and a controller coupled to the memory and configured to control the memory; The controller is configured to: send the operation instruction to the memory, wherein the operation instruction carries a plurality of initial word line identifiers; The memory is configured to: receive the operation instruction, map the multiple initial word line identifiers to multiple physical word line identifiers; perform the operation corresponding to the operation instruction on multiple first-type storage cell rows through multiple first-type word lines indicated by the multiple physical word line identifiers; Among them, at least one third type of storage cell row is distributed between the first storage cell row and the second storage cell row in the plurality of first type of storage cell rows, and the data stored in the plurality of first type of storage cell rows correspond to the same verification data.

14. The storage system according to claim 13, characterized in that: The controller is further configured to: send a word line mapping instruction to the memory; The memory is further configured to, in response to the word line mapping instruction, execute an operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers.

15. The storage system according to claim 14, characterized in that: The controller is further configured to: not send the word line mapping instruction to the memory; The memory is further configured to: perform the operation corresponding to the operation instruction on a plurality of second-type storage cell rows through a plurality of second-type word lines indicated by the plurality of initial word line identifiers; The plurality of second-type storage cell rows are a plurality of continuous storage cell rows in the storage array, and the data stored in the plurality of second-type storage cell rows correspond to the same verification data.

16. The storage system according to claim 13, characterized in that: The operation instruction includes a write instruction, and the write instruction also carries a plurality of to-be-written data corresponding one-to-one to the plurality of initial word line identifiers; The memory is configured to: use the to-be-written data corresponding to each initial word line identifier as the to-be-written data corresponding to the corresponding physical word line identifier, and perform programming operations on the multiple first-category storage cell rows through the multiple first-category word lines to store the multiple to-be-written data in the multiple first-category storage cell rows.

17. The storage system according to claim 13, characterized in that: The operation instruction includes a read instruction; The memory is configured to: perform a read operation on the plurality of first-type memory cell rows through the plurality of first-type word lines to obtain data respectively stored in the plurality of first-type memory cell rows; The memory is further configured to: send a read data result to the controller, the read data result carrying the data respectively stored in the plurality of first-type storage unit rows; The controller is configured to receive the read data result.

18. A method for operating a memory, characterized in that: The method comprises: receiving an operation instruction from a controller, wherein the operation instruction carries a plurality of initial word line identifiers; Mapping the multiple initial word line identifiers to multiple physical word line identifiers; Execute the operation corresponding to the operation instruction on a plurality of first-type storage cell rows through a plurality of first-type word lines indicated by the plurality of physical word line identifiers; Among them, at least one third type of storage cell row is distributed between the first storage cell row and the second storage cell row in the plurality of first type of storage cell rows, and the data stored in the plurality of first type of storage cell rows correspond to the same verification data.

19. The method according to claim 18, characterized in that Mapping the multiple initial word line identifiers to multiple physical word line identifiers includes: Each of the multiple initial word line identifiers is used as a pseudo word line identifier, and a physical word line identifier corresponding to each initial word line identifier is obtained from a stored mapping relationship between the pseudo word line identifier and the physical word line identifier.

20. The method of claim 19, wherein: The mapping relationship includes a mapping relationship between a first pseudo word line identifier and a first physical word line identifier, and a mapping relationship between a second pseudo word line identifier and a second physical word line identifier; The two memory cell rows coupled with the two word lines indicated by the first pseudo word line identifier and the second pseudo word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled with the two word lines indicated by the first physical word line identifier and the second physical identifier.

21. The method of claim 20, wherein: The first pseudo word line is identified as a first pseudo word line number, the second pseudo word line is identified as a second pseudo word line number, and a difference between the first pseudo word line number and the second pseudo word line number is 1; The first physical word line is identified as a first physical word line number, the second physical word line is identified as a second physical word line number, and a difference between the first physical word line number and the second physical word line number is greater than 1.

22. The memory according to claim 21, wherein: The first pseudo word line number is smaller than the second pseudo word line number; The second physical word line number is the sum of the first physical word line number and a reference value, and the reference value is a positive integer.

23. The method of claim 18, wherein: At least one third type of memory cell row is distributed between every two adjacent memory cell rows in the plurality of first type of memory cell rows.

24. The method of claim 23, wherein: The number of the third type of memory cell rows distributed between every two adjacent memory cell rows in the plurality of first type of memory cell rows is a reference number.

25. The method of claim 18, wherein: Mapping the multiple initial word line identifiers to multiple physical word line identifiers includes: If a word line mapping instruction is received from the controller, an operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers is performed.

26. The method of claim 25, wherein: The method further comprises: If the word line mapping instruction is not received from the controller, performing the operation corresponding to the operation instruction on a plurality of second-type memory cell rows through a plurality of second-type word lines indicated by the plurality of initial word line identifiers; The plurality of second-type storage cell rows are a plurality of continuous storage cell rows in the storage array, and the data stored in the plurality of second-type storage cell rows correspond to the same verification data.

27. The method of claim 18, wherein: The operation instruction includes a write instruction, and the write instruction also carries a plurality of to-be-written data corresponding one-to-one to the plurality of initial word line identifiers; The plurality of first-category word lines indicated by the plurality of physical word line identifiers perform the operation corresponding to the operation instruction on the plurality of first-category storage cell rows, including: The data to be written corresponding to each initial word line identifier is used as the data to be written corresponding to the corresponding physical word line identifier, and a programming operation is performed on the multiple first-type storage cell rows through the multiple first-type word lines to store the multiple data to be written in the multiple first-type storage cell rows.

28. The method of claim 18, wherein: The operation instruction includes a read instruction; The plurality of first-category word lines indicated by the plurality of physical word line identifiers perform the operation corresponding to the operation instruction on the plurality of first-category storage cell rows, including: A read operation is performed on the plurality of first-type memory cell rows through the plurality of first-type word lines to obtain data respectively stored in the plurality of first-type memory cell rows.

29. The method of claim 28, wherein: The method further comprises: If data stored in a third storage cell row among the plurality of first-type storage cell rows is erroneous data, determining an initial word line identifier corresponding to the physical word line identifier of the third storage cell row; Acquiring the verification data based on the determined initial word line identifier; The data stored in the third memory cell row is corrected based on the verification data.

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