Driving substrate and display panel

Abstract

A driving substrate (100) and a display panel. A metal layer (12) comprises a first signal line (121) and scan lines (122). Second signal lines (14) are located in a GOA region (NA), a hollow region (lk) is provided between every two adjacent second signal lines (14), and one scan line (122) is correspondingly connected to one second signal line (14). The metal layer (12) further comprises a plurality of electrostatic leads (123) connected to the first signal line (121). In an orthographic projection pattern on a plane where the driving substrate (100) is located, the electrostatic leads (123) are located in the hollow regions (lk), and the end of each electrostatic lead (123) distant from the first signal line (121) comprises a tip (jd).

Description

Drive substrate and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving substrate and a display panel. Background Art

[0002] In the related art, during the production of the gate layer in the array substrate manufacturing process, static electricity is generated due to friction during operation of the equipment. The static electricity is conducted from the in-plane wiring of the array substrate to the gate driver on array (GOA) area, but the wiring of the gate layer in the display area is not connected to the wiring in the GOA area. The GOA area is composed of metal patterns of different shapes and sizes. Since the metal patterns are of different areas, there is a potential difference between the different patterns, which makes it easy for static electricity to occur. On the one hand, the display area will release static electricity to the wiring in the GOA area, resulting in irregular damage to the wiring in the GOA area. On the other hand, the static electricity accumulation in the gate layer of the GOA area can easily cause a short circuit between the gate layer and the source and drain layer, resulting in poor functionality of the GOA area. SUMMARY OF THE INVENTION

[0003] The embodiments of the present application provide a driving substrate and a display panel, which can improve the functional yield of the GOA area.

[0004] In a first aspect, an embodiment of the present application provides a driving substrate, comprising a pixel driving area and a GOA area located on at least one side of the pixel driving area, comprising:

[0005] substrate;

[0006] a metal layer, the metal layer being disposed on the substrate, the metal layer comprising a first signal line and a scan line, the first signal line being located in the GOA region, the scan line being located in the pixel driving region, and an extension direction of the first signal line intersecting with an extension direction of the scan line;

[0007] a first insulating layer, the first insulating layer covering the metal layer and the substrate;

[0008] a second signal line, the second signal line being arranged on a side of the first insulating layer away from the substrate, the second signal line being located in the GOA region, a hollow region being defined between two adjacent second signal lines, the second signal line being arranged to intersect the first signal line, and one scan line being connected to one second signal line;

[0009] The metal layer further includes a plurality of electrostatic leads connected to the first signal line. In the orthographic projection pattern of the plane where the drive substrate is located, the electrostatic leads are located in the hollow area, and one end of the electrostatic lead away from the first signal line includes a tip.

[0010] In one embodiment, the driving substrate also includes a second insulating layer, the second signal line includes a first segment, a transition segment and a second segment, the first segment and the second segment are on the same layer and are disconnected, the second insulating layer covers the first segment, the second segment and the side of the first insulating layer away from the substrate, the transition segment is arranged on the side of the second insulating layer away from the substrate, one end of the transition segment is connected to the first segment, and the other end of the transition segment is connected to the second segment.

[0011] In one embodiment, a plurality of first vias and a plurality of second vias are provided on the second insulating layer, the plurality of first vias expose the first segment, the plurality of second vias expose the second segment, one end of the transition segment is connected to the first segment through the first vias, and the other end of the transition segment is connected to the second segment through the second vias.

[0012] In one embodiment, the first section includes a first connecting portion and at least two first sub-wires, one end of the at least two first sub-wires is connected to an output electrode of a thin film transistor, and the other end of the at least two first sub-wires is connected to the first connecting portion, and the plurality of first vias expose the first connecting portion;

[0013] The second section includes a second connecting portion and at least two second sub-lines, the second connecting portion is adjacent to and opposite to the first connecting portion, one end of at least two second sub-lines is connected to the second connecting portion, and the other end of at least two second sub-lines is connected to the scan line, and a plurality of second vias expose the second connecting portion;

[0014] One end of the transition section is connected to the first connection portion through the first via hole, and the other end of the transition section is connected to the second connection portion through the second via hole.

[0015] In one embodiment, the second segment further includes a third connecting portion, the third connecting portion being connected to a side of the plurality of second sub-lines away from the first connecting portion, the scan line including a fourth connecting portion and a scan line body, the scan line body being connected to a side of the fourth connecting portion away from the second signal line, and the third connecting portion and the fourth connecting portion being arranged to overlap;

[0016] The second insulating layer is also provided with a plurality of third vias and a plurality of fourth vias, the third vias exposing the third connecting portion, and the fourth vias exposing the fourth connecting portion. The driving substrate also includes a bridge wire, which is provided on a side of the second insulating layer away from the substrate, one end of the bridge wire is connected to the third connecting portion through the third via hole, and the other end of the bridge wire is connected to the fourth connecting portion through the fourth via hole.

[0017] In one embodiment, in the orthographic projection pattern of the plane where the driving substrate is located, a spike is formed at a portion where the fourth connection portion overlaps with the third connection portion.

[0018] In one embodiment, there is a gap between the first section and the second section, and the tip of the electrostatic lead is arranged on one side of the gap and in the extending direction of the gap.

[0019] In one embodiment, in the extending direction of the first signal line, the electrostatic leads and the second signal lines are alternately arranged.

[0020] In a second aspect, an embodiment of the present application provides a driving substrate, comprising a pixel driving area and a GOA area located on at least one side of the pixel driving area, comprising:

[0021] substrate;

[0022] a metal layer, the metal layer being disposed on the substrate, the metal layer comprising a first signal line and a scan line, the first signal line being located in the GOA region, the scan line being located in the pixel driving region, and an extension direction of the first signal line intersecting with an extension direction of the scan line;

[0023] a first insulating layer, the first insulating layer covering the metal layer and the substrate;

[0024] a second signal line, the second signal line being arranged on a side of the first insulating layer away from the substrate, the second signal line being located in the GOA area, a hollow area being provided between two adjacent second signal lines, the second signal line being arranged to cross the first signal line, one scan line being connected to one second signal line, the second signal line comprising a first segment, a transfer segment, and a second segment, the first segment and the second segment being arranged in the same layer and being disconnected, and a gap being provided between the first segment and the second segment;

[0025] a second insulating layer, the second insulating layer covering the first segment, the second segment, and a side of the first insulating layer away from the substrate, the transition segment being provided on a side of the second insulating layer away from the substrate, one end of the transition segment being connected to the first segment, and the other end of the transition segment being connected to the second segment;

[0026] The metal layer further includes a plurality of first electrostatic leads and at least one second electrostatic lead, wherein the plurality of first electrostatic leads are connected to one first signal line, the second electrostatic lead is connected to a side of the first electrostatic lead away from the first signal line, and the second electrostatic lead is connected to at least two first electrostatic leads;

[0027] In the orthographic projection pattern of the plane where the driving substrate is located, the first electrostatic lead is located in the hollow area, the second electrostatic lead passes through the gap and avoids the first segment and the second segment, and the end of the second electrostatic lead away from the first electrostatic lead includes a tip, and the tip of the second electrostatic lead is located in the hollow area.

[0028] In one embodiment, a plurality of first vias and a plurality of second vias are provided on the second insulating layer, the plurality of first vias expose the first segment, the plurality of second vias expose the second segment, one end of the transition segment is connected to the first segment through the first vias, and the other end of the transition segment is connected to the second segment through the second vias.

[0029] In one embodiment, the first section includes a first connecting portion and at least two first sub-wires, one end of the at least two first sub-wires is connected to an output electrode of a thin film transistor, and the other end of the at least two first sub-wires is connected to the first connecting portion, and the plurality of first vias expose the first connecting portion;

[0030] The second section includes a second connecting portion and at least two second sub-lines, the second connecting portion is adjacent to and opposite to the first connecting portion, one end of at least two second sub-lines is connected to the second connecting portion, and the other end of at least two second sub-lines is connected to the scan line, and a plurality of second vias expose the second connecting portion;

[0031] One end of the transition section is connected to the first connection portion through the first via hole, and the other end of the transition section is connected to the second connection portion through the second via hole.

[0032] In one embodiment, the second segment further includes a third connecting portion, the third connecting portion being connected to a side of the plurality of second sub-lines away from the first connecting portion, the scan line including a fourth connecting portion and a scan line body, the scan line body being connected to a side of the fourth connecting portion away from the second signal line, and the third connecting portion and the fourth connecting portion being arranged to overlap;

[0033] The second insulating layer is also provided with a plurality of third vias and a plurality of fourth vias, the third vias exposing the third connecting portion, and the fourth vias exposing the fourth connecting portion. The driving substrate also includes a bridge wire, which is provided on a side of the second insulating layer away from the substrate, one end of the bridge wire is connected to the third connecting portion through the third via hole, and the other end of the bridge wire is connected to the fourth connecting portion through the fourth via hole.

[0034] In one embodiment, in the orthographic projection pattern of the plane where the driving substrate is located, a spike is formed at a portion where the fourth connection portion overlaps with the third connection portion.

[0035] In one embodiment, in the extending direction of the first signal line, the electrostatic leads and the second signal lines are alternately arranged.

[0036] In a third aspect, an embodiment of the present application provides a display panel, which includes a driving substrate as described in any one of the above embodiments.

[0037] The driving substrate includes a pixel driving area and a GOA area located on at least one side of the pixel driving area, and the driving substrate includes:

[0038] substrate;

[0039] a metal layer, the metal layer being disposed on the substrate, the metal layer comprising a first signal line and a scan line, the first signal line being located in the GOA region, the scan line being located in the pixel driving region, and an extension direction of the first signal line intersecting with an extension direction of the scan line;

[0040] a first insulating layer, the first insulating layer covering the metal layer and the substrate;

[0041] a second signal line, the second signal line being arranged on a side of the first insulating layer away from the substrate, the second signal line being located in the GOA region, a hollow region being defined between two adjacent second signal lines, the second signal line being arranged to intersect the first signal line, and one scan line being connected to one second signal line;

[0042] The metal layer further includes a plurality of electrostatic leads connected to the first signal line. In the orthographic projection pattern of the plane where the drive substrate is located, the electrostatic leads are located in the hollow area, and one end of the electrostatic lead away from the first signal line includes a tip.

[0043] In one embodiment, the driving substrate also includes a second insulating layer, the second signal line includes a first segment, a transition segment and a second segment, the first segment and the second segment are on the same layer and are disconnected, the second insulating layer covers the first segment, the second segment and the side of the first insulating layer away from the substrate, the transition segment is arranged on the side of the second insulating layer away from the substrate, one end of the transition segment is connected to the first segment, and the other end of the transition segment is connected to the second segment.

[0044] In one embodiment, a plurality of first vias and a plurality of second vias are provided on the second insulating layer, the plurality of first vias expose the first segment, the plurality of second vias expose the second segment, one end of the transition segment is connected to the first segment through the first vias, and the other end of the transition segment is connected to the second segment through the second vias.

[0045] In one embodiment, the first section includes a first connecting portion and at least two first sub-wires, one end of the at least two first sub-wires is connected to an output electrode of a thin film transistor, and the other end of the at least two first sub-wires is connected to the first connecting portion, and the plurality of first vias expose the first connecting portion;

[0046] The second section includes a second connecting portion and at least two second sub-lines, the second connecting portion is adjacent to and opposite to the first connecting portion, one end of at least two second sub-lines is connected to the second connecting portion, and the other end of at least two second sub-lines is connected to the scan line, and a plurality of second vias expose the second connecting portion;

[0047] One end of the transition section is connected to the first connection portion through the first via hole, and the other end of the transition section is connected to the second connection portion through the second via hole.

[0048] In one embodiment, the second segment further includes a third connecting portion, the third connecting portion being connected to a side of the plurality of second sub-lines away from the first connecting portion, the scan line including a fourth connecting portion and a scan line body, the scan line body being connected to a side of the fourth connecting portion away from the second signal line, and the third connecting portion and the fourth connecting portion being arranged to overlap;

[0049] The second insulating layer is also provided with a plurality of third vias and a plurality of fourth vias, the third vias exposing the third connecting portion, and the fourth vias exposing the fourth connecting portion. The driving substrate also includes a bridge wire, which is provided on a side of the second insulating layer away from the substrate, one end of the bridge wire is connected to the third connecting portion through the third via hole, and the other end of the bridge wire is connected to the fourth connecting portion through the fourth via hole.

[0050] In one embodiment, in the orthographic projection pattern of the plane where the driving substrate is located, a spike is formed at a portion where the fourth connection portion overlaps with the third connection portion. Beneficial effects

[0051] Beneficial effects of the embodiments of the present application:

[0052] In an embodiment of the present application, an electrostatic lead is provided to guide the static electricity of the first signal line to the hollow area between the second signal lines. When the electrostatic lead is damaged by static electricity, it will not affect the signal transmission of the first signal line, nor will it cause a short circuit between the electrostatic lead and the second signal line, thereby improving the yield of the GOA functional area. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] FIG1 is a schematic top view of a driving substrate provided in an embodiment of the present application;

[0054] FIG2 is a schematic cross-sectional view of FIG1 along line M1N1;

[0055] FIG3 is another schematic top view of the driving substrate provided in an embodiment of the present application;

[0056] FIG4 is a schematic cross-sectional view of the structure along line M2N2 in FIG3 . Modes for Carrying Out the Invention

[0057] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as labels and do not impose numerical requirements or establish an order.

[0058] 1 and 2 , an embodiment of the present application provides a driving substrate 100 , including a pixel driving area AA and a GOA area NA located on at least one side of the pixel driving area AA, which includes a substrate 11 , a metal layer 12 , a first insulating layer 13 and a second signal line 14 .

[0059] The metal layer 12 is disposed on the substrate 11. The metal layer 12 includes a first signal line 121 and a scan line 122. The first signal line 121 is located in the GOA area NA, and the scan line 122 is located in the pixel driving area AA. The extension direction of the first signal line 121 intersects the extension direction of the scan line 122.

[0060] The first insulating layer 13 covers the metal layer 12 and the substrate 11. Second signal lines 14 are disposed on a side of the first insulating layer 13 away from the substrate 11. The second signal lines 14 are located in the GOA area NA. A hollow area 1k is defined between two adjacent second signal lines 14. The second signal lines 14 intersect with the first signal lines 121. A scan line 122 is connected to each second signal line 14.

[0061] The metal layer 12 further includes a plurality of electrostatic leads 123 connected to a first signal line 121. In the orthographic projection pattern of the driving substrate 100, the electrostatic leads 123 are located in the hollow area 1k, and one end of the electrostatic lead 123 away from the first signal line 121 includes a tip jd.

[0062] It is understandable that the end of the electrostatic lead 123 includes a tip jd to facilitate static discharge.

[0063] Optionally, the electrostatic lead 123 includes a main line and a tip jd connected to an end of the main line. The width of the tip jd decreases from the connection point between the tip jd and the main line in a direction away from the connection point.

[0064] It should be understood that as long as a feature has a decreasing width in the top view, the feature can be a tip. Since the tip jd decreases in width, it can accommodate less electrostatic charge, so the same electrostatic charge is more easily discharged at the tip jd than at the main line.

[0065] The driving substrate 100 of this embodiment guides the static electricity of the first signal line 121 to the hollow area 1k between the second signal lines 14 by providing an electrostatic lead 123. When the electrostatic lead 123 releases static electricity, since the electrostatic release point (explosion point) of the electrostatic lead 123 is in the hollow area 1k, the static electricity release will not affect the signal transmission of the first signal line 121, nor will it cause a short circuit between the electrostatic lead 123 and the second signal line 14, thereby improving the yield of the GOA area NA.

[0066] In addition, multiple electrostatic leads 123 are used to connect the first signal line 121, so that each electrostatic lead 123 guides static electricity in a part of the first signal line 121, thereby improving the uniformity of static electricity guidance by each electrostatic lead 123 and reducing the risk of electrostatic charge concentration.

[0067] Optionally, the first signal line 121 may be an STV (Start Vertical) signal line. The first signal line 121 is connected to at least one GOA unit, and the other end of the first signal line 121 is connected to the chip-on-film.

[0068] In some embodiments, the first signal line 121 may also be other signal lines, such as a common electrode line, a power signal line, etc.

[0069] In one embodiment, the electrostatic leads 123 and the second signal lines 14 are alternately arranged along the extension direction of the first signal line 121. This arrangement allows each electrostatic lead 123 to guide static electricity from a portion of the first signal line 121, improving the uniformity of static electricity released by each electrostatic lead 123 and reducing the amount of static electricity released by a single electrostatic lead 123, thereby reducing the severity of electrostatic injuries.

[0070] In one embodiment, the drive substrate 100 further includes a second insulating layer 15. The second signal line 14 includes a first segment 14a, a transition segment 14b, and a second segment 14c. The first segment 14a and the second segment 14c are arranged on the same layer and are separated. The second insulating layer 15 covers the first segment 14a, the second segment 14c, and the side of the first insulating layer 13 facing away from the substrate 11. The transition segment 14b is arranged on the side of the second insulating layer 15 facing away from the substrate 11. One end of the transition segment 14b is connected to the first segment 14a, and the other end of the transition segment 14b is connected to the second segment 14c.

[0071] The driving substrate 100 of this embodiment uses a transition section 14b to connect the disconnected first section 14a and the second section 14c. Since the transition section 14b is a surface structure and is located above the second insulating layer 15, the transition section 14b is used to connect the first section 14a and the second section 14c to improve the static discharge path.

[0072] For example, when static electricity is generated in the pixel driving area AA, the static electricity can be sequentially conducted to the second segment 14c, the transfer segment 14b, and the first segment 14a through the scanning line 122. Compared with the prior art method in which the first segment and the second segment are in the same layer and directly connected, the static electricity release path is improved.

[0073] In one embodiment, the end of the electrostatic lead 123 is connected to a tip jd, and the extension direction of the tip jd is consistent with the extension direction of the electrostatic lead 123. A gap jx is defined between the first segment 14a and the second segment 14c. The tip jd of the electrostatic lead 123 is disposed on one side of the gap jx and in the extension direction of the gap jx.

[0074] The tip jd of the electrostatic lead 123 is set corresponding to the extension direction of the gap jx. Since the transition section 14b is set on the second insulating layer 15, it is far away from the electrostatic lead 123, and there is no metal layer 12 in the four directions of the upper, lower, left and right of the electrostatic lead 123, which reduces the risk of static electricity breaking through the adjacent second signal line 14 after discharge, and reduces the risk of short circuit with the second signal line 14.

[0075] Optionally, the width of the electrostatic lead 123 is between 9 microns and 11 microns, for example, 9 microns, 10 microns or 11 microns.

[0076] Optionally, the tip jd of the electrostatic lead 123 is located in the center area of ​​two adjacent gaps jx. Optionally, the distance between the electrostatic lead 123 and the transition section 14b is between 30 microns and 50 microns, such as 30 microns, 35 microns, 40 microns, 45 microns or 50 microns.

[0077] It is understandable that the greater the distance between the electrostatic lead 123 and the transition section 14b, the more space is required, making it less conducive to achieving a narrow bezel. On the other hand, the smaller the distance, the greater the risk of electrostatic discharge damaging the transition section 14b. Therefore, to ensure a narrow bezel and enhance the safety of the second signal line 14, a distance between 30 and 50 microns is selected.

[0078] In some embodiments, the end of an electrostatic lead 123 may also include multiple tips, and the extension directions of the multiple tips are different, as long as the tip jd is set in the hollow area lk.

[0079] In one embodiment, the second insulating layer 15 is provided with a plurality of first vias k1 and a plurality of second vias k2. The plurality of first vias k1 expose the first segment 14a, and the plurality of second vias k2 expose the second segment 14c. One end of the transition segment 14b is connected to the first segment 14a via the first vias k1, and the other end of the transition segment 14b is connected to the second segment 14c via the second vias k2.

[0080] The transfer section 14b uses multiple first vias k1 to connect to the first section 14a, and uses multiple second vias k2 to connect to the second section 14c, which can reduce the impedance of the second signal line 14, and static electricity can be transmitted through multiple vias, thereby improving the static electricity release path, thereby reducing the risk of the second signal line 14 being damaged by static electricity.

[0081] Optionally, the plurality of first via holes k1 are arranged along an extension direction parallel to the first signal line 121 . The plurality of second via holes k2 are arranged along an extension direction parallel to the first signal line 121 .

[0082] In one embodiment, the first segment 14a includes a first connecting portion a1 and at least two first sub-lines a2. One end of the at least two first sub-lines a2 is connected to an output electrode of a thin-film transistor (TFT), and the other end of the at least two first sub-lines a2 is connected to the first connecting portion a1. A plurality of first vias k1 expose the first connecting portion a1.

[0083] The second segment 14c includes a second connecting portion c1 and at least two second sub-lines c2. The second connecting portion c1 is adjacent to and opposite to the first connecting portion a1. One end of the at least two second sub-lines c2 is connected to the second connecting portion c1, and the other end of the at least two second sub-lines c2 is connected to the scan line 122. A plurality of second vias k2 expose the second connecting portion c1.

[0084] One end of the transition section 14 b is connected to the first connection portion a1 through a first via hole k1 , and the other end of the transition section 14 b is connected to the second connection portion c1 through a second via hole k2 .

[0085] The first segment 14a utilizes at least two first sub-lines a2 spaced apart and connected to the same first connection portion a1, which increases the path for static discharge. Furthermore, even if one first sub-line a2 is damaged, the remaining first sub-line a2 remains operational, improving the stability of signal transmission by the second signal line 14. Furthermore, the use of a strip-type connection reduces the overlap between the first segment 14a and the first signal line 121, compared to a wider, single-line structure for the second signal line. This reduces the risk of shorting between the first segment 14a and the first signal line 121 due to static damage.

[0086] The second segment 14c utilizes at least two second sub-lines c2 spaced apart and connected to the same second connection portion c1, which increases the path for static discharge. Furthermore, even if one second sub-line c2 is damaged, the remaining second sub-line c2 remains operational, improving the stability of signal transmission by the second signal line 14. Furthermore, the use of a strip-type connection reduces the overlap between the second segment 14c and the first signal line 121, compared to a wider, single-line second signal line, thereby reducing the risk of shorting between the second segment 14c and the first signal line 121 due to static damage.

[0087] Optionally, the plurality of first via holes k1 are arranged along a direction parallel to the extending direction of the first signal line 121 . The plurality of second via holes k2 are arranged along a direction parallel to the extending direction of the first signal line 121 .

[0088] Optionally, the transition section 14b completely covers the first connection portion a1 and the second connection portion c1, thereby increasing the static electricity release area and reducing the risk of injury from static electricity.

[0089] In one embodiment, the second segment 14c further includes a third connection portion c3, which is connected to a side of the plurality of second sub-lines c2 away from the first connection portion a1. The scan line 122 includes a fourth connection portion 12a and a scan line body 12b, which is connected to a side of the fourth connection portion 12a away from the second signal line 14. The third connection portion c3 and the fourth connection portion 12a are arranged to overlap.

[0090] The second insulating layer 15 is further provided with a plurality of third vias k3 and a plurality of fourth vias k4. The third vias k3 expose the third connection portion c3. The fourth vias k4 expose the fourth connection portion 12a. The drive substrate 100 also includes a bridge wire 16, which is disposed on a side of the second insulating layer 15 away from the substrate 11. One end of the bridge wire 16 is connected to the third connection portion c3 via the third vias k3. The other end of the bridge wire 16 is connected to the fourth connection portion 12a via the fourth vias k4.

[0091] The bridge line 16 uses multiple third vias k3 to connect the third connection part c3, and uses multiple fourth vias k4 to connect the fourth connection part 12a, which can reduce the impedance between the second signal line 14 and the scan line 122, and static electricity can be transmitted through multiple vias, thereby improving the static electricity release path, thereby reducing the risk of the second signal line 14 being damaged by static electricity.

[0092] In addition, the third connection portion c3 and the fourth connection portion 12a are arranged in an overlapping manner. Once the fourth connection portion 12a is damaged by static electricity, the third connection portion c3 and the fourth connection portion 12a are short-circuited. However, since the third connection portion c3 and the fourth connection portion 12a transmit the same signal, even if the two are short-circuited due to static electricity, it will not affect the transmission of the signal. On the contrary, the short-circuiting of the two increases the signal transmission path, reduces the impedance and improves the static electricity release path.

[0093] In one embodiment, in the orthographic projection pattern of the plane where the driving substrate 100 is located, a spike is formed at the portion where the fourth connection portion 12 a overlaps with the third connection portion c3 .

[0094] The spike formed on the fourth connection portion 12a increases the probability of static electricity being released at the spike, reducing the risk of static electricity being released at other locations on the signal line. This increased probability of static electricity being released at the spike increases the probability of shorting the third connection portion c3 and the fourth connection portion 12a, further increasing the signal transmission path, reducing impedance, and improving the static electricity release path.

[0095] 3 and 4 , an embodiment of the present application provides another driving substrate 100 , which includes a pixel driving area AA and a GOA area NA located on at least one side of the pixel driving area AA, and includes a substrate 11 , a metal layer 12 , a first insulating layer 13 , a second signal line 14 , and a second insulating layer 15 .

[0096] The metal layer 12 is disposed on the substrate 11. The metal layer 12 includes a first signal line 121 and a scan line 122. The first signal line 121 is located in the GOA area NA, and the scan line 122 is located in the pixel driving area AA. The extension direction of the first signal line 121 intersects the extension direction of the scan line 122.

[0097] The first insulating layer 13 covers the metal layer 12 and the substrate 11. Second signal lines 14 are disposed on a side of the first insulating layer 13 away from the substrate 11. The second signal lines 14 are located in the GOA area NA. A hollow area 1k is defined between two adjacent second signal lines 14. The second signal lines 14 intersect with the first signal lines 121. A scan line 122 is connected to each second signal line 14.

[0098] The second signal line 14 includes a first section 14a, a transition section 14b, and a second section 14c. The first section 14a and the second section 14c are arranged on the same layer and are separated from each other. A gap jx is formed between the first section 14a and the second section 14c.

[0099] The second insulating layer 15 covers the first segment 14a, the second segment 14c, and the side of the first insulating layer 13 away from the substrate 11. The transition segment 14b is disposed on the side of the second insulating layer 15 away from the substrate 11. One end of the transition segment 14b is connected to the first segment 14a, and the other end of the transition segment 14b is connected to the second segment 14c.

[0100] The metal layer 12 further includes a plurality of first electrostatic leads 12h and at least one second electrostatic lead 12v. The plurality of first electrostatic leads 12h are connected to a first signal line 121. The second electrostatic lead 12v is connected to a side of the first electrostatic lead 12h away from the first signal line 121. A second electrostatic lead 12v is connected to at least two first electrostatic leads 12h.

[0101] In an orthographic projection pattern of the plane where the drive substrate 100 is located, the first electrostatic lead 12h is located in the hollow area 1k. The second electrostatic lead 12v passes through the gap jx and avoids the first segment 14a and the second segment 14c. The end of the second electrostatic lead 12v away from the first electrostatic lead 12h includes a tip jd. The tip jd of the second electrostatic lead 12v is located in the hollow area 1k.

[0102] The embodiments of the present application utilize multiple first electrostatic leads 12h connected to a first signal line 121, allowing each first electrostatic lead 12h to guide static electricity in a portion of the first signal line 121. This improves the uniformity of static electricity guidance by each first electrostatic lead 12h and reduces the risk of electrostatic charge concentration. Furthermore, the tips jd of the first and second electrostatic leads 12h, 12v, are located in the hollow region 1k. When static electricity damage occurs to the tips jd of the first and second electrostatic leads 12h, 12v, because the explosion point of the tips jd of the first and second electrostatic leads 12h, 12v is in the hollow region 1k, static electricity will not affect the signal transmission of the first signal line 121, nor will it cause a short circuit between the second electrostatic lead 12v and the second signal line 14, thereby improving the yield of the GOA region NA.

[0103] In addition, compared with the above embodiment, this embodiment guides multiple first electrostatic leads 12h to one electrostatic release point through the first electrostatic lead 12h of the second electrostatic lead 12v connection part, thereby reducing the number of static release points (explosion points) set and improving the safety of the driving substrate 100.

[0104] Moreover, the second electrostatic lead 12v passes through the gap jx and avoids the first section 14a and the second section 14c. Once static electricity is released in the second electrostatic lead 12v, the risk of short circuit between the second electrostatic lead 12v and the second signal line 14 is reduced.

[0105] Optionally, the connection between the first electrostatic lead 12h and the second electrostatic lead 12v is an end angle structure, which is located between two adjacent transition sections 14b and in the hollow area 1k. The setting of the end angle structure can also increase the probability of electrostatic discharge.

[0106] In one embodiment, the first electrostatic leads 12h and the second signal lines 14 are alternately arranged in the extending direction of the first signal line 121. This arrangement improves the uniformity of static electricity conduction by each first electrostatic lead 12h and reduces the risk of electrostatic charge concentration.

[0107] In one embodiment, the end of the second electrostatic lead 12v is connected to a tip jd, and the extension direction of the tip jd is consistent with the extension direction of the second electrostatic lead 12v. The tip jd of the second electrostatic lead 12v is arranged on one side of the gap jx and is located in the extension direction of the gap jx.

[0108] The tip jd of the second electrostatic lead 12v is set corresponding to the extension direction of the gap jx. Since the transition section 14b is set on the second insulating layer 15, it is far away from the second electrostatic lead 12v, and there is no metal layer 12 in the four directions of the top, bottom, left and right of the tip jd of the second electrostatic lead 12v, which reduces the risk of static electricity breaking through the adjacent second signal line 14 after discharge, and reduces the risk of short circuit with the second signal line 14.

[0109] Optionally, the width of the first electrostatic lead 12h is between 9 microns and 11 microns, for example, 9 microns, 10 microns or 11 microns.

[0110] Optionally, the width of the second electrostatic lead 12v is between 8 microns and 10 microns, for example, 8 microns, 9 microns, or 10 microns. The smaller width of the second electrostatic lead 12v causes the second electrostatic lead 12v to be farther away from the first segment 14a and the second segment 14c, respectively, thereby reducing the risk of shorting between the second electrostatic lead 12v and the second signal line 14.

[0111] Optionally, the tip jd of the second electrostatic lead 12v is located in the center area of ​​two adjacent gaps jx. Optionally, the distance between the tip jd of the second electrostatic lead 12v and the transition section 14b is between 30 microns and 50 microns, for example, 30 microns, 35 microns, 40 microns, 45 microns, or 50 microns.

[0112] It is understood that the greater the distance between the tip jd of the second electrostatic lead 12v and the transition section 14b, the more space is required, making it less conducive to achieving a narrow frame. On the other hand, the smaller the distance, the greater the risk of electrostatic discharge damaging the transition section 14b. Therefore, to ensure a narrow frame and enhance the safety of the second signal line 14, a distance between 30 and 50 microns is selected.

[0113] In some embodiments, the end of a second electrostatic lead 12v may also include multiple tips, and the extension directions of the multiple tips are different, as long as the tip jd is arranged in the hollow area lk.

[0114] In one embodiment, the second insulating layer 15 is provided with a plurality of first vias k1 and a plurality of second vias k2. The plurality of first vias k1 expose the first segment 14a, and the plurality of second vias k2 expose the second segment 14c. One end of the transition segment 14b is connected to the first segment 14a via the first vias k1, and the other end of the transition segment 14b is connected to the second segment 14c via the second vias k2.

[0115] The transfer section 14b uses multiple first vias k1 to connect to the first section 14a, and uses multiple second vias k2 to connect to the second section 14c, which can reduce the impedance of the second signal line 14, and static electricity can be transmitted through multiple vias, thereby improving the static electricity release path, thereby reducing the risk of the second signal line 14 being damaged by static electricity.

[0116] Optionally, the plurality of first via holes k1 are arranged along an extension direction parallel to the first signal line 121 . The plurality of second via holes k2 are arranged along an extension direction parallel to the first signal line 121 .

[0117] In one embodiment, the first segment 14a includes a first connecting portion a1 and at least two first sub-lines a2. One end of the at least two first sub-lines a2 is connected to an output electrode of a thin-film transistor (TFT), and the other end of the at least two first sub-lines a2 is connected to the first connecting portion a1. A plurality of first vias k1 expose the first connecting portion a1.

[0118] The second segment 14c includes a second connecting portion c1 and at least two second sub-lines c2. The second connecting portion c1 is adjacent to and opposite to the first connecting portion a1. One end of the at least two second sub-lines c2 is connected to the second connecting portion c1, and the other end of the at least two second sub-lines c2 is connected to the scan line 122. A plurality of second vias k2 expose the second connecting portion c1.

[0119] One end of the transition section 14 b is connected to the first connection portion a1 through a first via hole k1 , and the other end of the transition section 14 b is connected to the second connection portion c1 through a second via hole k2 .

[0120] The first segment 14a utilizes at least two first sub-lines a2 spaced apart and connected to the same first connection portion a1, which increases the path for static discharge. Furthermore, even if one first sub-line a2 is damaged, the remaining first sub-line a2 remains operational, improving the stability of signal transmission by the second signal line 14. Furthermore, the use of a strip-type connection reduces the overlap between the first segment 14a and the first signal line 121, compared to a wider, single-line structure for the second signal line. This reduces the risk of shorting between the first segment 14a and the first signal line 121 due to static damage.

[0121] The second segment 14c utilizes at least two second sub-lines c2 spaced apart and connected to the same second connection portion c1, which increases the path for static discharge. Furthermore, even if one second sub-line c2 is damaged by static electricity, the remaining second sub-line c2 remains functional, improving the stability of signal transmission by the second signal line 14. Furthermore, the use of a strip-type connection reduces the overlap between the second segment 14c and the first signal line 121, compared to a wider, single-line second signal line, thereby reducing the risk of shorting between the second segment 14c and the first signal line 121 due to static electricity damage.

[0122] Optionally, the plurality of first via holes k1 are arranged along a direction parallel to the extending direction of the first signal line 121 . The plurality of second via holes k2 are arranged along a direction parallel to the extending direction of the first signal line 121 .

[0123] Optionally, the transition section 14b completely covers the first connection portion a1 and the second connection portion c1, thereby increasing the static electricity release area and reducing the risk of injury from static electricity.

[0124] In one embodiment, the second segment 14c further includes a third connection portion c3, which is connected to a side of the plurality of second sub-lines c2 away from the first connection portion a1. The scan line 122 includes a fourth connection portion 12a and a scan line body 12b, which is connected to a side of the fourth connection portion 12a away from the second signal line 14. The third connection portion c3 and the fourth connection portion 12a are arranged to overlap.

[0125] The second insulating layer 15 is further provided with a plurality of third vias k3 and a plurality of fourth vias k4. The third vias k3 expose the third connection portion c3. The fourth vias k4 expose the fourth connection portion 12a. The drive substrate 100 also includes a bridge wire 16, which is disposed on a side of the second insulating layer 15 away from the substrate 11. One end of the bridge wire 16 is connected to the third connection portion c3 via the third vias k3. The other end of the bridge wire 16 is connected to the fourth connection portion 12a via the fourth vias k4.

[0126] The bridge line 16 uses multiple third vias k3 to connect the third connection part c3, and uses multiple fourth vias k4 to connect the fourth connection part 12a, which can reduce the impedance between the second signal line 14 and the scan line 122, and static electricity can be transmitted through multiple vias, thereby improving the static electricity release path, thereby reducing the risk of the second signal line 14 being damaged by static electricity.

[0127] In addition, the third connection portion c3 and the fourth connection portion 12a are arranged in an overlapping manner. Once the fourth connection portion 12a is damaged by static electricity, the third connection portion c3 and the fourth connection portion 12a are short-circuited. However, since the third connection portion c3 and the fourth connection portion 12a transmit the same signal, even if the two are short-circuited due to static electricity, it will not affect the transmission of the signal. On the contrary, the short-circuiting of the two increases the signal transmission path, reduces the impedance and improves the static electricity release path.

[0128] In one embodiment, in the orthographic projection pattern of the plane where the driving substrate 100 is located, a spike is formed at the portion where the fourth connection portion 12 a overlaps with the third connection portion c3 .

[0129] The spike formed on the fourth connection portion 12a increases the probability of static electricity being released at the spike, reducing the risk of static electricity being released at other locations on the signal line. This increased probability of static electricity being released at the spike increases the probability of shorting the third connection portion c3 and the fourth connection portion 12a, further increasing the signal transmission path, reducing impedance, and improving the static electricity release path.

[0130] An embodiment of the present application provides a display panel, which includes a driving substrate 100 according to any one of the above embodiments.

[0131] Optionally, the display panel may be a liquid crystal panel, an OLED panel, a Mini-LED panel, a Micro-LED panel or other panels.

[0132] The driving substrate of the display panel of this embodiment can be used as an array substrate of a liquid crystal panel, and as a driving backplane of an OLED panel, a Mini-LED panel, a Micro-LED panel, and a QLED panel.

[0133] The structure of the driving substrate in the display panel is similar to or the same as the structure of the driving substrate 100 in any of the above embodiments, and therefore will not be described in detail here.

[0134] The above is a detailed introduction to the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A driving substrate, comprising a pixel driving area and a GOA area located at at least one side of the pixel driving area, the driving substrate comprising: substrate; a metal layer, the metal layer being disposed on the substrate, the metal layer comprising a first signal line and a scan line, the first signal line being located in the GOA region, the scan line being located in the pixel driving region, and an extension direction of the first signal line intersecting with an extension direction of the scan line; a first insulating layer, the first insulating layer covering the metal layer and the substrate; A second signal line, wherein the second signal line is arranged on a side of the first insulating layer away from the substrate, the second signal line is located in the GOA area, a hollow area is provided between two adjacent second signal lines, the second signal line is arranged to cross the first signal line, and one scanning line is correspondingly connected to one second signal line; The metal layer further includes a plurality of electrostatic leads connected to the first signal line. In the orthographic projection pattern of the plane where the drive substrate is located, the electrostatic leads are located in the hollow area, and one end of the electrostatic leads away from the first signal line includes a tip.

2. The driving substrate according to claim 1, wherein: The driving substrate also includes a second insulating layer, and the second signal line includes a first section, a transition section and a second section. The first section and the second section are on the same layer and are disconnected. The second insulating layer covers the first section, the second section and a side of the first insulating layer away from the substrate. The transition section is arranged on a side of the second insulating layer away from the substrate, one end of the transition section is connected to the first section, and the other end of the transition section is connected to the second section.

3. The driving substrate according to claim 2, wherein: The second insulating layer is provided with a plurality of first vias and a plurality of second vias, wherein the plurality of first vias expose the first segment, and the plurality of second vias expose the second segment, one end of the transition segment is connected to the first segment through the first vias, and the other end of the transition segment is connected to the second segment through the second vias.

4. The driving substrate according to claim 3, wherein: The first section includes a first connection portion and at least two first sub-wires, one end of the at least two first sub-wires is connected to an output electrode of a thin film transistor, the other end of the at least two first sub-wires is connected to the first connection portion, and a plurality of the first vias expose the first connection portion; The second section includes a second connection portion and at least two second sub-lines, the second connection portion is adjacent to and opposite to the first connection portion, one end of at least two second sub-lines is connected to the second connection portion, the other end of at least two second sub-lines is connected to the scan line, and a plurality of second vias expose the second connection portion; One end of the transition section is connected to the first connection portion through the first via hole, and the other end of the transition section is connected to the second connection portion through the second via hole.

5. The driving substrate according to claim 4, wherein: The second section further includes a third connection portion, the third connection portion is connected to a side of the plurality of second sub-lines away from the first connection portion, the scan line includes a fourth connection portion and a scan line body, the scan line body is connected to a side of the fourth connection portion away from the second signal line, and the third connection portion and the fourth connection portion are overlapped; The second insulating layer is also provided with a plurality of third vias and a plurality of fourth vias, wherein the third vias expose the third connecting portion, and the fourth vias expose the fourth connecting portion. The driving substrate also includes a bridge wire, which is arranged on a side of the second insulating layer away from the substrate, one end of the bridge wire is connected to the third connecting portion through the third via hole, and the other end of the bridge wire is connected to the fourth connecting portion through the fourth via hole.

6. The driving substrate according to claim 5, wherein: In the orthographic projection pattern of the plane where the driving substrate is located, a spike is formed at a portion where the fourth connection portion overlaps the third connection portion.

7. The driving substrate according to claim 2, wherein: There is a gap between the first section and the second section, and the tip of the electrostatic lead is arranged on one side of the gap and in the extending direction of the gap.

8. The driving substrate according to claim 7, wherein: In the extending direction of the first signal line, the electrostatic lead lines and the second signal lines are alternately arranged.

9. A driving substrate, comprising a pixel driving area and a GOA area located at at least one side of the pixel driving area, the driving substrate comprising: substrate; a metal layer, the metal layer being disposed on the substrate, the metal layer comprising a first signal line and a scan line, the first signal line being located in the GOA region, the scan line being located in the pixel driving region, and an extension direction of the first signal line intersecting with an extension direction of the scan line; a first insulating layer, the first insulating layer covering the metal layer and the substrate; A second signal line, wherein the second signal line is arranged on a side of the first insulating layer away from the substrate, the second signal line is located in the GOA area, a hollow area is provided between two adjacent second signal lines, the second signal line is arranged to cross the first signal line, one scanning line is correspondingly connected to one second signal line, the second signal line comprises a first section, a transfer section and a second section, the first section and the second section are arranged in the same layer and are disconnected, and there is a gap between the first section and the second section; a second insulating layer, wherein the second insulating layer covers the first segment, the second segment, and a side of the first insulating layer away from the substrate, the transition segment is arranged on a side of the second insulating layer away from the substrate, one end of the transition segment is connected to the first segment, and the other end of the transition segment is connected to the second segment; The metal layer further comprises a plurality of first electrostatic leads and at least one second electrostatic lead, wherein the plurality of first electrostatic leads are connected to one of the first signal lines, the second electrostatic lead is connected to a side of the first electrostatic lead away from the first signal line, and the second electrostatic lead is connected to at least two of the first electrostatic leads; In the orthographic projection pattern of the plane where the driving substrate is located, the first electrostatic lead is located in the hollow area, the second electrostatic lead passes through the gap and avoids the first segment and the second segment, the end of the second electrostatic lead away from the first electrostatic lead includes a tip, and the tip of the second electrostatic lead is located in the hollow area.

10. The driving substrate according to claim 9, wherein: The second insulating layer is provided with a plurality of first vias and a plurality of second vias, wherein the plurality of first vias expose the first segment, and the plurality of second vias expose the second segment, one end of the transition segment is connected to the first segment through the first vias, and the other end of the transition segment is connected to the second segment through the second vias.

11. The driving substrate according to claim 10, wherein: The first section includes a first connection portion and at least two first sub-wires, one end of the at least two first sub-wires is connected to an output electrode of a thin film transistor, the other end of the at least two first sub-wires is connected to the first connection portion, and a plurality of the first vias expose the first connection portion; The second section includes a second connection portion and at least two second sub-lines, the second connection portion is adjacent to and opposite to the first connection portion, one end of at least two second sub-lines is connected to the second connection portion, the other end of at least two second sub-lines is connected to the scan line, and a plurality of second vias expose the second connection portion; One end of the transition section is connected to the first connection portion through the first via hole, and the other end of the transition section is connected to the second connection portion through the second via hole.

12. The driving substrate according to claim 11, wherein: The second section further includes a third connection portion, the third connection portion is connected to a side of the plurality of second sub-lines away from the first connection portion, the scan line includes a fourth connection portion and a scan line body, the scan line body is connected to a side of the fourth connection portion away from the second signal line, and the third connection portion and the fourth connection portion are overlapped; The second insulating layer is also provided with a plurality of third vias and a plurality of fourth vias, wherein the third vias expose the third connecting portion, and the fourth vias expose the fourth connecting portion. The driving substrate also includes a bridge wire, which is arranged on a side of the second insulating layer away from the substrate, one end of the bridge wire is connected to the third connecting portion through the third via hole, and the other end of the bridge wire is connected to the fourth connecting portion through the fourth via hole.

13. The driving substrate according to claim 12, wherein: In the orthographic projection pattern of the plane where the driving substrate is located, a spike is formed at a portion where the fourth connection portion overlaps the third connection portion.

14. The driving substrate according to claim 9, wherein: In the extending direction of the first signal line, the electrostatic lead lines and the second signal lines are alternately arranged.

15. A display panel, comprising a driving substrate, the driving substrate comprising a pixel driving area and a GOA area located at at least one side of the pixel driving area, the driving substrate comprising: substrate; a metal layer, the metal layer being disposed on the substrate, the metal layer comprising a first signal line and a scan line, the first signal line being located in the GOA region, the scan line being located in the pixel driving region, and an extension direction of the first signal line intersecting with an extension direction of the scan line; a first insulating layer, the first insulating layer covering the metal layer and the substrate; A second signal line, wherein the second signal line is arranged on a side of the first insulating layer away from the substrate, the second signal line is located in the GOA area, a hollow area is provided between two adjacent second signal lines, the second signal line is arranged to cross the first signal line, and one scanning line is correspondingly connected to one second signal line; The metal layer further includes a plurality of electrostatic leads connected to the first signal line. In the orthographic projection pattern of the plane where the drive substrate is located, the electrostatic leads are located in the hollow area, and one end of the electrostatic leads away from the first signal line includes a tip.

16. The display panel according to claim 15, wherein: The driving substrate also includes a second insulating layer, and the second signal line includes a first section, a transition section and a second section. The first section and the second section are on the same layer and are disconnected. The second insulating layer covers the first section, the second section and a side of the first insulating layer away from the substrate. The transition section is arranged on a side of the second insulating layer away from the substrate, one end of the transition section is connected to the first section, and the other end of the transition section is connected to the second section.

17. The display panel according to claim 16, wherein: The second insulating layer is provided with a plurality of first vias and a plurality of second vias, wherein the plurality of first vias expose the first segment, and the plurality of second vias expose the second segment, one end of the transition segment is connected to the first segment through the first vias, and the other end of the transition segment is connected to the second segment through the second vias.

18. The display panel according to claim 17, wherein: The first section includes a first connection portion and at least two first sub-wires, one end of the at least two first sub-wires is connected to an output electrode of a thin film transistor, the other end of the at least two first sub-wires is connected to the first connection portion, and a plurality of the first vias expose the first connection portion; The second section includes a second connection portion and at least two second sub-lines, the second connection portion is adjacent to and opposite to the first connection portion, one end of at least two second sub-lines is connected to the second connection portion, the other end of at least two second sub-lines is connected to the scan line, and a plurality of second vias expose the second connection portion; One end of the transition section is connected to the first connection portion through the first via hole, and the other end of the transition section is connected to the second connection portion through the second via hole.

19. The display panel according to claim 18, wherein: The second section further includes a third connection portion, the third connection portion is connected to a side of the plurality of second sub-lines away from the first connection portion, the scan line includes a fourth connection portion and a scan line body, the scan line body is connected to a side of the fourth connection portion away from the second signal line, and the third connection portion and the fourth connection portion are overlapped; The second insulating layer is also provided with a plurality of third vias and a plurality of fourth vias, wherein the third vias expose the third connecting portion, and the fourth vias expose the fourth connecting portion. The driving substrate also includes a bridge wire, which is arranged on a side of the second insulating layer away from the substrate, one end of the bridge wire is connected to the third connecting portion through the third via hole, and the other end of the bridge wire is connected to the fourth connecting portion through the fourth via hole.

20. The display panel according to claim 19, wherein: In the orthographic projection pattern of the plane where the driving substrate is located, a spike is formed at a portion where the fourth connection portion overlaps the third connection portion.

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