Driving method for display panel, pixel driving circuit, and display panel

Abstract

Provided are a driving method for a display panel, a pixel driving circuit, and a display panel. The method comprises: dividing a display image into a plurality of display stages that are set in a continuous manner, providing a first control signal for a first sub-frame to an (N-1)th sub-frame, providing a second control signal for an Nth sub-frame, and obtaining pixel data structures in different display stages, wherein the first control signal is a pulse width modulation signal, and the second control signal is a pulse amplitude modulation signal. Thus, display effects are effectively improved.

Description

Display panel driving method, pixel driving circuit and display panel Technical Field

[0001] The present invention relates to the technical field of display panel driving, and in particular to a display panel driving method, a pixel driving circuit, and a display panel. Background Art

[0002] With the development of display panel manufacturing technology, people have put forward higher requirements on the display effects and comprehensive performance of display panels and display devices.

[0003] Currently, the transmittance of transparent light-emitting diode (LED) displays decreases at high pixel densities, making their design increasingly difficult. To improve performance, current LED transparent displays on the market typically employ improvements to the SMD manufacturing process, LED packaging, and control systems of conventional light strip displays on printed circuit boards (PCBs), or employ structural hollowing to enhance transparency. However, as pixel density continues to increase, traditional manufacturing processes and driving methods are no longer sufficient, hindering further improvements in display quality.

[0004] Therefore, it is necessary to propose solutions to the problems in the prior art. SUMMARY OF THE INVENTION

[0005] In summary, in the prior art, traditional manufacturing processes and corresponding driving methods cannot meet the requirements of display panels having high pixel density and good transparency at the same time, which is not conducive to further improving the comprehensive performance of display panels.

[0006] To solve the above problems, embodiments of the present invention provide a display panel driving method, a pixel driving circuit, and a display panel, which effectively improve the problem of unsatisfactory display effects when driving a high-pixel-density display panel in the prior art.

[0007] To solve the above technical problems, an embodiment of the present invention provides a method for driving a display panel, comprising:

[0008] Get a frame of image to be displayed;

[0009] In each frame of an image to be displayed, the image to be displayed is divided into a plurality of display stages that are consecutively arranged, each display stage includes N subframes, where N is an integer greater than or equal to 1;

[0010] In each of the display phases, a first control signal is provided to pixel units corresponding to the 1st to the (N-1)th subframes in the N subframes through a pixel driving circuit of the display panel;

[0011] A second control signal is provided to the pixel unit corresponding to the Nth subframe in the N subframes, and the corresponding pixel data structure in different display stages is obtained and displayed, wherein the number of rows and columns corresponding to the array-arranged pixel data structure in different display stages is different.

[0012] According to an embodiment of the present invention, in the N subframes, the pixel units corresponding to the 1st subframe to the N-1th subframe are low grayscale, and the pixel units corresponding to the Nth subframe are high grayscale;

[0013] The first control signal is a pulse width modulation signal, and the second control signal is a pulse amplitude modulation signal.

[0014] According to an embodiment of the present invention, the pixel unit array is disposed in the display area of ​​the display panel to form an N*M pixel array, and each of the pixel units includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel;

[0015] Wherein, two sub-pixels of one color among the first color sub-pixel, the second color sub-pixel or the third color sub-pixel are provided.

[0016] According to an embodiment of the present invention, in the pixel array, during the pixel unit control process of each frame, the pixel driving circuit sets the number of sub-pixels corresponding to odd and even rows to two and controls them separately.

[0017] According to one embodiment of the present invention, each frame of the displayed image includes a first stage, a second stage, a third stage and a fourth stage that are continuously set, each stage includes 8 subframes, and during the driving process, the first to seventh subframes are pulse width modulated, and the eighth subframe is pulse amplitude modulated.

[0018] According to an embodiment of the present invention, in each stage:

[0019] In the first stage, the pixel driving circuit is controlled to set the data signal value of the first color sub-pixel corresponding to the odd-numbered rows in the pixel array to zero, and the first control signal is provided in the first to seventh sub-frames, and the second control signal is provided in the eighth sub-frame, thereby obtaining a first pixel data structure;

[0020] In the second stage, the pixel driving circuit is controlled so that the data signal values ​​of the first color sub-pixels corresponding to the even-numbered rows in the pixel array are zero, and the data signal values ​​of the sub-pixels corresponding to the first column and the last column are both zero, and the first control signal is provided in the first to seventh sub-frames, and the second control signal is provided in the eighth sub-frame, thereby obtaining a second pixel data structure;

[0021] In the third stage, the pixel driving circuit is controlled so that the data signal values ​​of the first color sub-pixels corresponding to the odd-numbered rows in the pixel array are zero, and the data signal values ​​of the sub-pixels corresponding to the first row and the last row are both zero, and the first control signal is provided in the first to seventh sub-frames, and the second control signal is provided in the eighth sub-frame, thereby obtaining a third pixel data structure;

[0022] In the fourth stage, the pixel driving circuit is regulated and the data signal values ​​of the first color sub-pixels corresponding to the even rows in the pixel array are made zero, and the data signal values ​​of the sub-pixels corresponding to the first row and the last row, the first column and the last column are all zero, and the first control signal is provided from the 1st sub-frame to the 7th sub-frame, and the second control signal is provided from the 8th sub-frame, and a fourth pixel data structure is obtained.

[0023] According to an embodiment of the present invention, in different pixel data structures, each pixel unit includes a virtual pixel, and the virtual pixel is located at the center of the pixel unit.

[0024] According to a second aspect of the embodiments of the present invention, a method for driving a display panel is provided, comprising:

[0025] Get a frame of image to be displayed;

[0026] In each frame of an image to be displayed, the image to be displayed is divided into a plurality of display stages that are consecutively arranged, each display stage includes N subframes, where N is an integer greater than or equal to 1;

[0027] In each of the display phases, a first control signal is provided to pixel units corresponding to the 1st to the (N-1)th subframes in the N subframes through a pixel driving circuit of the display panel;

[0028] A second control signal is provided to the pixel unit corresponding to the Nth subframe in the N subframes, and corresponding pixel data structures in different display stages are obtained and displayed.

[0029] According to an embodiment of the present invention, in the N subframes, the pixel units corresponding to the 1st subframe to the N-1th subframe are low grayscale, and the pixel units corresponding to the Nth subframe are high grayscale;

[0030] The first control signal is a pulse width modulation signal, and the second control signal is a pulse amplitude modulation signal.

[0031] According to an embodiment of the present invention, the pixel unit array is disposed in the display area of ​​the display panel to form an N*M pixel array, and each of the pixel units includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel;

[0032] Wherein, two sub-pixels of one color among the first color sub-pixel, the second color sub-pixel or the third color sub-pixel are provided.

[0033] According to an embodiment of the present invention, in the pixel array, during the pixel unit control process of each frame, the pixel driving circuit sets the number of sub-pixels corresponding to odd and even rows to two and controls them separately.

[0034] According to one embodiment of the present invention, each frame of the displayed image includes a first stage, a second stage, a third stage and a fourth stage that are continuously set, each stage includes 8 subframes, and during the driving process, the first to seventh subframes are pulse width modulated, and the eighth subframe is pulse amplitude modulated.

[0035] According to an embodiment of the present invention, in each stage:

[0036] In the first stage, the pixel driving circuit is controlled to set the data signal value of the first color sub-pixel corresponding to the odd-numbered rows in the pixel array to zero, and the first control signal is provided in the first to seventh sub-frames, and the second control signal is provided in the eighth sub-frame, thereby obtaining a first pixel data structure;

[0037] In the second stage, the pixel driving circuit is controlled so that the data signal values ​​of the first color sub-pixels corresponding to the even-numbered rows in the pixel array are zero, and the data signal values ​​of the sub-pixels corresponding to the first column and the last column are both zero, and the first control signal is provided in the first to seventh sub-frames, and the second control signal is provided in the eighth sub-frame, thereby obtaining a second pixel data structure;

[0038] In the third stage, the pixel driving circuit is controlled so that the data signal values ​​of the first color sub-pixels corresponding to the odd-numbered rows in the pixel array are zero, and the data signal values ​​of the sub-pixels corresponding to the first row and the last row are both zero, and the first control signal is provided in the first to seventh sub-frames, and the second control signal is provided in the eighth sub-frame, thereby obtaining a third pixel data structure;

[0039] In the fourth stage, the pixel driving circuit is regulated and the data signal values ​​of the first color sub-pixels corresponding to the even rows in the pixel array are made zero, and the data signal values ​​of the sub-pixels corresponding to the first row and the last row, the first column and the last column are all zero, and the first control signal is provided from the 1st sub-frame to the 7th sub-frame, and the second control signal is provided from the 8th sub-frame, and a fourth pixel data structure is obtained.

[0040] According to an embodiment of the present invention, in different pixel data structures, each pixel unit includes a virtual pixel, and the virtual pixel is located at the center of the pixel unit.

[0041] According to a third aspect of the embodiments of the present application, a pixel driving circuit is further provided, including:

[0042] a first thin film transistor, wherein a gate electrode of the first thin film transistor is connected to a first scanning signal line, and a source electrode of the first thin film transistor is connected to a data voltage line;

[0043] a second thin film transistor, wherein a gate of the second thin film transistor is connected to a drain of the first thin film transistor, a drain of the second thin film transistor is connected to a high potential voltage of a power supply, and a source of the second thin film transistor is connected to a light emitting diode and one end of the first capacitor;

[0044] a third thin film transistor, wherein a gate of the third thin film transistor is connected to the third scan signal line, a source of the third thin film transistor is connected to the source of the second thin film transistor, and a drain of the third thin film transistor is connected to a reference voltage;

[0045] a fourth thin film transistor, wherein the gate of the fourth thin film transistor is connected to the second scanning signal line, the source of the fourth thin film transistor is connected to the drain of the first thin film transistor and the other end of the first capacitor, and the drain of the fourth thin film transistor is connected to the initial voltage.

[0046] According to an embodiment of the present application, at a low grayscale, the first scan signal line and the third scan signal line are at a high level, the first thin film transistor and the third thin film transistor are turned on, the data voltage is charged into the second thin film transistor and turned on, and then the first scan signal line and the third scan signal line are at a low level, and the first thin film transistor and the third thin film transistor are turned off;

[0047] At a high gray scale, the second scanning signal line is at a low level, the fourth thin film transistor is turned off, the amplitude of the data voltage is adjusted, and the pixel unit displays different gray scales.

[0048] According to an embodiment of the present application, the low grayscale corresponds to a pulse width modulation signal, and the high grayscale corresponds to a pulse amplitude modulation signal. Under the drive of the pulse width modulation signal, the duty cycle corresponding to the charging time of each subframe is controlled to obtain different grayscale values. Beneficial effects

[0049] In summary, the beneficial effects of the embodiments of the present invention are as follows: Compared with the prior art, the embodiments of the present application provide a driving method for a display panel, a pixel driving circuit, and a display panel. During the driving process, in each frame of the displayed image, the displayed image is divided into a plurality of display stages set continuously, each display stage includes N subframes, and the pixel driving circuit of the display panel provides a first control signal to the pixel units corresponding to the 1st subframe to the N-1th subframe in the N subframes, and provides a second control signal to the pixel units corresponding to the Nth subframe in the N subframes, and respectively obtains pixel data structures corresponding to different display stages. Among them, the first control signal is a pulse width modulation signal, and the second control signal is a pulse amplitude modulation signal. In the embodiments of the present application, by controlling different control signals in different subframes and corresponding to different pixel data structures at different times in each subframe, the time intervals between the multiple different pixel data structures are short, thereby achieving a 4-fold pixel display effect under the effect of the visual aftereffect of the human eye, and effectively reducing the number of pixel units of the display panel and the arrangement of the driving circuits, thereby improving the overall performance of the panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a schematic diagram of an arrangement of pixel units provided in an embodiment of the present application;

[0051] FIG2 is a schematic structural diagram of a display device provided in an embodiment of the present application;

[0052] FIG3 is a flowchart corresponding to the driving method provided in an embodiment of the present application;

[0053] 4 to 9 are schematic diagrams of pixel data structures corresponding to pixel units in each subframe provided in an embodiment of the present application;

[0054] FIG10 is a pixel driving circuit provided in an embodiment of the present application;

[0055] FIG11 is a timing diagram corresponding to the pixel driving circuit provided in an embodiment of the present application;

[0056] FIG12 is another timing diagram of the pixel driving circuit provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0057] The following descriptions of the embodiments refer to the accompanying drawings to illustrate specific embodiments in which the present disclosure may be implemented.

[0058] With the continuous development of display panel and device manufacturing technology, people have put forward higher requirements on the performance and display effects of display devices.

[0059] The embodiments of the present application provide a pixel driving method, a driving circuit, and a display panel to ensure that the display panel has a high transparency effect while meeting the requirement of high pixel density, and effectively improve the overall performance of the display panel.

[0060] When a display panel displays an image, a frame refers to one of multiple consecutive display images. A frame is equivalent to a still image. Due to the visual characteristics of the human eye, multiple frames per second are required to maintain a sense of image continuity; otherwise, the display device will experience flicker.

[0061] At the same time, a frame of display image can be divided into multiple display stages that are set continuously as needed. Multiple display stages are performed in sequence, and finally a frame of picture is displayed. Among them, each display stage may include multiple subframes, and a subframe is equivalent to a subfield period. During a subfield period, the pixel unit will maintain light emission for a certain period of time, thereby displaying the brightness level / grayscale corresponding to the light emission period. The longer the pixel unit maintains light emission, the brighter the corresponding display brightness, that is, the higher the grayscale. Therefore, when the pixel unit of the display device displays a frame of image, it actually displays multiple subframes continuously in each display stage, and superimposes the time for each subframe to maintain light emission, that is, superimposes the brightness corresponding to multiple subframes, and finally forms a corresponding display picture in the human eye.

[0062] In order to improve the performance of the display panel in the embodiment of the present application, a transparent substrate, such as a transparent glass substrate, is used when preparing the display panel. The light-emitting diodes and driving circuits corresponding to the plurality of pixel units are arranged on the transparent glass substrate, ultimately forming the LED transparent screen display panel provided in the embodiment of the present application. Because the transparent glass substrate has good light transmittance, most light can directly pass through the areas not blocked by the LEDs and circuits. Therefore, the transparent glass substrate in the embodiment of the present application can effectively improve the transparency of the display panel.

[0063] Specifically, in an embodiment of the present application, when setting the pixel units corresponding to the LEDs in the display panel, the pixel units can be arranged in an array on a transparent glass substrate, such as forming an N*M array structure on the transparent glass substrate, where N and M are both integers and are not specifically limited here.

[0064] As shown in Figure 1, Figure 1 is a schematic diagram of the arrangement of pixel units in the display panel provided in an embodiment of the present application. In the embodiment of the present application, a pixel array with 4 rows and 4 columns is used as an example for description.

[0065] Specifically, during configuration, multiple pixel units 101 are arranged in an array in corresponding row and column directions, ultimately forming a 4*4 array structure as shown in Figure 1. Each pixel unit 101 corresponds to a light-emitting diode. When the display panel is operating normally, the light-emitting diode is controlled to achieve display on the display panel. Each pixel unit 101 includes multiple sub-pixels. Multiple different sub-pixels are encapsulated in the same light-emitting diode to form a pixel unit.

[0066] Specifically, the pixel unit 101 may include a plurality of sub-pixels of different colors. For example, each pixel unit 101 includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The above sub-pixels of different colors may be arranged in a rectangular structure. Optionally, other numbers of sub-pixels of different colors may be provided in each pixel unit 101 and arranged in other array structures. Among them, one sub-pixel of one color among the first color sub-pixel, the second color sub-pixel, or the third color sub-pixel is set to two. If the first color sub-pixel is set to two, the corresponding second color sub-pixel and third color sub-pixel are both set to one, or the sub-pixels of other colors are set to two, which will not be repeated here.

[0067] In the following embodiments, two red sub-pixels 201, one blue sub-pixel 202, and one green sub-pixel 203 are used as examples within each pixel unit 101. The two red sub-pixels 201 are diagonally arranged at the corners of the rectangle. This structure is shown in FIG1 . The first color sub-pixel is the red sub-pixel 201, the second color sub-pixel is the blue sub-pixel 202, and the third color sub-pixel is the green sub-pixel 203. This is not specifically limited here.

[0068] Taking the display panel corresponding to the above pixel structure arrangement as an example, the display panel is driven. Specifically, as shown in Figure 2, Figure 2 is a schematic structural diagram of a display device provided in an embodiment of the present application. The display device includes a display panel 303, a data processing device 301, a gate driver 305, a pixel driver 302, and a plurality of pixel units 101.

[0069] Among them, each light-emitting diode is arranged in each pixel unit 101. When the display device is working normally, the data processing device 301 can receive image data from an external device, such as the RGB value corresponding to the image data, and convert the image data RGB value into data suitable for the pixel driving device 302. Finally, the converted data is transmitted to the pixel unit and the display panel is illuminated for display. Among them, the setting method of each of the above-mentioned functional modules can be set according to the conventional structure and will not be repeated here. In the embodiment of the present application, the display device includes a pixel driving circuit. For example, the pixel driving circuit is set corresponding to each pixel unit 101, and during the light-emitting process, the pixel unit is controlled to achieve different display effects and purposes.

[0070] In the embodiment of the present application, a combination of pulse width modulation (PWM) and pulse amplitude modulation (PAM) driving modes is used to drive the display panel, thereby effectively improving the display effect of the display panel and the device.

[0071] Specifically, as shown in FIG3 , FIG3 is a flowchart corresponding to the driving method provided in an embodiment of the present application. When driving the display, the following steps are included:

[0072] Get a frame of image to be displayed;

[0073] In each frame of an image to be displayed, the image to be displayed is divided into a plurality of display stages that are consecutively arranged, each display stage includes N subframes, where N is an integer greater than or equal to 1;

[0074] In each of the display phases, a first control signal is provided to pixel units corresponding to the 1st to the (N-1)th subframes in the N subframes through a pixel driving circuit of the display panel;

[0075] A second control signal is provided to the pixel unit corresponding to the Nth subframe in the N subframes, and corresponding pixel data structures in different display stages are obtained and displayed.

[0076] In the embodiment of the present application, a frame of image to be displayed may be one of multiple frames of image to be displayed on the display device. Optionally, in the following embodiments, a frame of image to be displayed may be a frame of image to be displayed at the next moment, or may be every frame of image displayed on all display screens on the display device.

[0077] During operation, the image to be displayed actually exists in the form of current data or voltage data corresponding to the image to be displayed. During application, the initial display data of the next frame of the image to be displayed is input into the display driver module through external memory. The display driver module detects and analyzes the initial display data and generates a display drive voltage corresponding to the initial display data based on a reference voltage. The display drive voltage is then input into the pixel drive circuit to drive the display.

[0078] After acquiring a frame of image to be displayed, the image is divided into a plurality of display stages arranged in series. These multiple display stages ultimately constitute a complete frame of image. In the following embodiment, the image to be displayed is divided into four display stages arranged in series. Specifically, the four display stages include a first stage, a second stage, a third stage, and a fourth stage arranged in series.

[0079] At the same time, for each display stage, each display stage includes N subframes, such as the 1st subframe, the 2nd subframe, the 3rd subframe... the Nth subframe. N is an integer greater than or equal to 1. In the embodiment of the present application, each corresponding frame in the 4*4 pixel array can be divided into 8 subframes, and no more specific limitation is made in the embodiment of the present application. And when the pixel unit is at a low grayscale, it is driven by PWM, and when it is at a high grayscale, it is driven by PAM. For example, during the driving process, the 1st to 7th subframes are pulse width modulated, and the amplitude values ​​corresponding to each subframe are the same, but the duty cycle is different. The 8th subframe is pulse amplitude modulated. The four different stages are performed in sequence, and the 8 subframes are repeated 4 times. In this way, each frame of the image to be displayed includes a total of 32 subframes, thereby improving the display effect of the display panel.

[0080] Specifically, during the driving process, within each display phase, the pixel driver circuit provides a first control signal to the pixel units corresponding to subframes 1 through (N-1) of the N subframes. Then, a second control signal is provided to the pixel units corresponding to subframe N of the N subframes. Different pixel data structures corresponding to different display phases are obtained and displayed. Because the intervals between each display phase and subframe are extremely short, the visual afterimage effect causes the display effects of different subframes to visually overlap, resulting in the final display effect.

[0081] In the embodiment of the present application, the first N-1 subframes are all low grayscale, and the Nth subframe is high grayscale display. At the same time, the first control signal is a pulse width modulation signal, and the second control signal is a pulse amplitude modulation signal.

[0082] As shown in Figures 4-9, Figures 4-9 are schematic diagrams of the pixel data structure of the corresponding pixel unit in each subframe provided in the embodiments of the present application. When the pixel unit is displayed, the red, green, and blue sub-pixels in each pixel unit can be combined four times through up, down, left, and right, and each is combined with its adjacent sub-pixels to form a new pixel unit, thereby achieving a repeated combination and mixed color display effect. When it is displayed, the sub-pixels in each independent pixel unit 101 are real pixels. At the center of the pixel unit 101, according to the visual characteristics of the human eye, multiple frames of images need to be played continuously per second to perceive the continuity of the image playback. Otherwise, the display device will be perceived as flickering. When driving the display, because the time interval between each sub-frame is very small, only in the microsecond level, when the displayed information scrolls in a certain direction and in a certain manner, the human eye's short-term visual aftereffect is used to generate a series of moving, physically non-existent virtual pixels between two adjacent pixels, thereby equivalently forming a virtual pixel 40. The virtual pixel 40 emits light at the center of different LEDs, while the real pixel emits light within the same LED. This means the virtual pixel is dispersed, while the real pixel is concentrated. This virtual display technology, through multiplexing of subpixels, enhances the display panel's resolution and achieves optimal image quality.

[0083] 4-9 , in each frame from the 1st to the 7th subframe, as shown in FIG. 4 , at time T0, no light is emitted, and the pixel array corresponding to the pixel unit 101 has a 4-row, 4-column structure. In this pixel array, the subpixels corresponding to different rows are independently controlled, such as the red subpixels 201 in odd and even rows, thereby achieving different display effects. This corresponds to a 4*4 pixel array.

[0084] As shown in FIG5 , and in conjunction with the structure of FIG4 , in the first phase t1 , a driving signal is provided to the pixel unit, and different effects are achieved by controlling the grayscale values ​​of different color sub-pixels. Due to the presence of virtual pixels 40 , there is a corresponding relationship between the distribution of the virtual pixels 40 and the grayscale values ​​of the different sub-pixels.

[0085] Specifically, during the first phase t1, the pixel drive circuit is regulated to cause the corresponding sub-pixels to display different effects. Specifically, the data signal values ​​of the red sub-pixels 201 in odd-numbered rows of the pixel array are set to zero, such as the data signal values ​​of the red sub-pixels 201 in rows 1, 3, and so on. At this point, during display, a first pixel data structure 61 is obtained. This first pixel data structure 61 corresponds to a 4*4 pixel array. Simultaneously, during this first phase t1, in sub-frames 1 through 8, the first control signal (i.e., the PWM control signal) is provided for sub-frames 1 through 7, and the second control signal (i.e., the PAM control signal) is provided for sub-frame 8, resulting in the first pixel data structure 61.

[0086] As shown in FIG6 , during the second phase t2, drive signals are provided to the pixel unit. Similarly, different display effects are achieved by controlling the grayscale values ​​of different color subpixels. Specifically, during the second phase t2, the data signal values ​​of the red subpixels 201 corresponding to even rows in the pixel array are set to zero. Simultaneously, the data signal values ​​of the subpixels corresponding to the first and last columns are also set to zero. Under the above control conditions, a second pixel data structure 62 is obtained; in this case, it corresponds to a 4*3 pixel array. Simultaneously, during the second phase t2, the first through seventh subframes provide the first control signal, i.e., the PWM control signal, and the eighth subframe provides the second control signal, i.e., the PAM control signal, thereby obtaining the second pixel data structure 62. In this embodiment of the present application, in this second pixel data structure 62, except for the subpixels set to 0, the control signals of the drive circuit corresponding to the remaining subpixels are the same as those in the first phase.

[0087] In the embodiment of the present application, when controlling sub-pixels in a pixel array, the sub-pixels corresponding to the odd and even rows are set to two and are controlled separately. For example, the red sub-pixel 201 is controlled separately. Other situations are not described here in detail.

[0088] As shown in FIG7 , during the third phase t3, a drive signal is provided to the pixel unit, and the data signal values ​​of the red subpixels 201 corresponding to the odd-numbered rows of the pixel array are set to zero. Simultaneously, the data signal values ​​of the subpixels in the first and last rows are also set to zero. Under the aforementioned control conditions, a third pixel data structure 64 is obtained; this corresponds to a 3*4 pixel array. Simultaneously, during this third phase t3, during the first through eighth subframes, the first through seventh subframes provide the first control signal, i.e., the PWM control signal, and the eighth subframe provides the second control signal, i.e., the PAM control signal, resulting in a third pixel data structure 64. Similarly, in this third pixel data structure 64, except for the subpixels set to zero, the control signals for the drive circuits corresponding to the remaining subpixels remain the same as in the first phase.

[0089] As shown in FIG8 , during the fourth stage t4, the pixel driving circuit is controlled to set the data signal values ​​of the red subpixels 201 in the even-numbered rows of the pixel array to zero. Simultaneously, the data signal values ​​of the corresponding subpixels in the first and last rows, and the first and last columns, are also set to zero. Under the aforementioned control conditions, a fourth pixel data structure 63 is obtained. This corresponds to a 3*3 pixel array. Simultaneously, during this fourth stage t4, in the first through eighth subframes, the first through seventh subframes provide the first control signal, i.e., the PWM control signal, and the eighth subframe provides the second control signal, i.e., the PAM control signal, resulting in a fourth pixel data structure 63. Similarly, in this fourth pixel data structure 63, except for the subpixels set to zero, the control signals for the driving circuits corresponding to the remaining subpixels remain the same as in the first stage.

[0090] In the embodiments of the present application, different types of pixel data structures can be obtained in the above-mentioned different display stages, and the array arrangement of the pixel data structures in the above-mentioned different display stages corresponds to different numbers of rows and columns. Thus, each subframe display image can be composed of four subfields, and the four subfields correspond to different pixel data structures. As shown in Figure 9, because the time intervals between the first, second, third, and fourth stages and between each subframe are very small, only on the microsecond level, when the human eye observes, it utilizes the residual effect of human vision, and under the influence of the visual effect, ultimately achieves a display effect that is 4 times that of the same real pixels.

[0091] Furthermore, in the embodiment of the present application, when corresponding to an N*M pixel array structure, the displayed image points of the virtual pixel and the real pixel are (2m-1)*(2n-1). Thus, when N and M are large enough, it is approximately equal to 2N*2M, or 4NM, which is four times the number of real pixels. In the embodiment of the present application, different display effects are achieved by adjusting the grayscale values ​​of different sub-pixels, and a display effect of four times is achieved with the same number of pixels.

[0092] As shown in Figure 10, Figure 10 shows a pixel driving circuit provided in an embodiment of the present application. Specifically, the driving circuit is a 4T1C driving circuit. When driving, the pixel driving circuit adopts a PWM driving mode at low grayscale values. At this time, different grayscale values ​​are displayed by controlling the charging time and duty cycle of each subframe, and different pixel data structures are obtained. At high grayscale values, the pixel driving circuit adopts a PAM driving mode. By controlling the amplitude of the data signal value corresponding to each subframe, different grayscales are displayed and the display effect of the panel is improved.

[0093] Specifically, it includes a first thin film transistor T1 , a second thin film transistor T2 , a third thin film transistor T3 , a fourth thin film transistor T4 , a first capacitor C, and a light emitting diode.

[0094] The gate of the first thin film transistor T1 is electrically connected to the first scan signal line scan1, and the source of the first thin film transistor T1 is electrically connected to the data voltage line Vdata;

[0095] The gate of the second thin film transistor T2 is electrically connected to the drain of the first thin film transistor T1. At the same time, the gate is electrically connected to one end of the first capacitor and one end of the light emitting diode. The drain of the second thin film transistor T2 is electrically connected to the power supply high potential voltage OVDD.

[0096] At the same time, the gate of the third thin film transistor T3 is electrically connected to the third scan signal line scan3, the drain of the third thin film transistor T3 is electrically connected to the reference power supply Vref and the DAC, and the source of the third thin film transistor T3 is electrically connected to the first capacitor, one end of the light emitting diode, and the source of the second thin film transistor T2;

[0097] The gate of the fourth thin film transistor T4 is electrically connected to the second scan signal line scan2, the source of the fourth thin film transistor T4 is electrically connected to the drain of the first thin film transistor T1, the other end of the first capacitor C, and the gate of the second thin film transistor T2, and the drain of the fourth thin film transistor T4 is electrically connected to the initial voltage Vini.

[0098] At the same time, the other end of the light emitting diode is connected to a low potential voltage of a power supply, thereby forming the pixel driving circuit provided in the embodiment of the present application.

[0099] As shown in Figure 11, Figure 11 is a timing diagram corresponding to the pixel driving circuit provided in an embodiment of the present application. Combined with the above-mentioned pixel driving circuit and the corresponding timing diagram, when driving, the red sub-pixels in the odd rows and the even rows in the pixel unit provide different control signals. At low grayscale, when scan1 / scan3 is high, the first thin film transistor T1 and the third thin film transistor T3 are turned on. At this time, the Vdata voltage is charged into the gate of the second thin film transistor T2 and controls the turning on of the second thin film transistor T2. Afterwards, scan1 / scan3 is low, the first thin film transistor T1 and the third thin film transistor T3 are turned off, and the level of the second thin film transistor T2 is maintained by the first capacitor C.

[0100] Specifically, if the image needs to be displayed at a high gray scale, pulse amplitude modulation is used, and the control signal of the fourth thin-film transistor T4 is low, the fourth thin-film transistor T4 is turned off, and the width of the data voltage is such as the 8th subframe, and the data voltage of the first 7 subframes is 0. The amplitude of the data voltage is adjusted to display different high gray scales; if the image needs to be displayed at a low gray scale, pulse width modulation is used, the amplitude of the data voltage is such as the first 7 subframes, and the data of the 8th subframe is 0, the control signal of the fourth thin-film transistor T4 is high, and the fourth thin-film transistor T4 is turned on. According to the required low gray scale, the data voltage of the first 7 subframes is controlled, such as being assigned 0 respectively, to control the length of the charging time of the light-emitting diode to achieve different low gray scale displays.

[0101] During the driving process, the charging time can be varied based on the grayscale requirements of each sub-pixel. When the required charging time is reached, the second scanning signal line scan2 is set to a high-level signal, controlling the opening of the fourth thin-film transistor T4 to achieve discharge and end the charging process. In the embodiment of the present application, the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3 primarily implement the control of the PAM driving mode, while the fourth thin-film transistor T4 primarily implements the control of the PWM driving mode.

[0102] As shown in FIG11 , in the first subframe to the seventh subframe, the light emitting diode corresponds to different pulse widths in different subframes through the above adjustment, such as the pulse width from 2 0 , 2 1 , 2 2 , 2 3 , 2 4 , 2 5 , 2 6 , and in the 8th subframe, the pulse width of the light emitting diode is 2 7 , thereby achieving different display effects.

[0103] As shown in FIG12, FIG12 is another timing diagram of the pixel driving circuit provided in an embodiment of the present application. In combination with the timing diagram in FIG11, in an embodiment of the present application, each subframe corresponding to a frame of display image is divided into four display stages, and the four stages t1-t4 correspond to four different pixel data structures, namely the first pixel data structure 61, the second pixel data structure 62, the third pixel data structure 64, and the fourth pixel data structure 63 provided in the embodiment of the present application. In this way, the eight subframes are repeated once in each stage, thereby forming 32 subframes. However, the content of each of the 32 subframes is the same, thereby achieving the desired display effect.

[0104] Furthermore, in the embodiment of the present application, within each display phase, the amplitudes of the first N-1 subframes, such as the 1st to 7th subframes, are the same, but the corresponding widths (duty cycles) are different, with each width corresponding to a grayscale. In the Nth subframe, such as the 8th subframe, the pulse width corresponding to the LED corresponds to the Nth width, thereby adjusting the amplitude to display different grayscale values ​​at high grayscales and achieve different display effects.

[0105] If the hybrid driving method in the embodiment of the present application is adopted, when the frequency is 60 Hz, the blue sub-pixel and the green sub-pixel can achieve a maximum refresh frequency of 1920 Hz, and the red sub-pixel can achieve a maximum refresh frequency of 960 Hz.

[0106] In the embodiments of this application, by adopting different drive methods and combining real and virtual pixels, a four-fold pixel display effect is achieved on a transparent glass substrate. This reduces the number of LED chips and drive circuits, saving costs and simplifying processing while also improving light transmittance. Furthermore, in the embodiments of this application, the distribution of light points under the virtual pixels formed above is also uniform, effectively improving the display quality of the panel.

[0107] Furthermore, in an embodiment of the present application, a display panel and a display device are also provided. When set, the display panel and the display device shown include a substrate, pixel units arrayed on the substrate, and a pixel driving circuit electrically connected to the pixel units. The arrangement and driving method of the above-mentioned pixel units are carried out in accordance with the method in the embodiment of the present application, and the substrate is set as a transparent glass substrate, thereby effectively improving the display effect and overall performance of the panel.

[0108] The display panel and the display device can be applied to any computer, electronic paper, display, notebook computer, digital photo frame, etc. with a high refresh rate effect, and the specific type is not specifically limited.

[0109] To sum up, the above is a detailed introduction to a display panel driving method, a pixel driving circuit and a display panel provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present invention. Although the present invention is disclosed as above in preferred embodiments, the above preferred embodiments are not used to limit the present invention. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is based on the scope defined by the claims.

Claims

1. A method for driving a display panel, comprising the following steps: Get a frame of image to be displayed; In each frame of the image to be displayed, the image to be displayed is divided into a plurality of display stages which are arranged continuously, each of which includes N subframes, wherein: N is an integer greater than or equal to 1; In each of the display stages, a first control signal is provided to pixel units corresponding to the 1st subframe to the N-1th subframe in the N subframes through a pixel driving circuit of the display panel; A second control signal is provided to the pixel unit corresponding to the Nth subframe in the N subframes, and the corresponding pixel data structure in different display stages is obtained and displayed, wherein the number of rows and columns corresponding to the array-arranged pixel data structure in different display stages is different.

2. The driving method according to claim 1, wherein in the N subframes, the pixel units corresponding to the 1st to the N-1th subframes are low grayscale, and the pixel units corresponding to the Nth subframe are high grayscale; in, The first control signal is a pulse width modulation signal, and the second control signal is a pulse amplitude modulation signal.

3. The driving method according to claim 1, wherein the pixel unit array is arranged in the display area of ​​the display panel to form an N*M pixel array, and each of the pixel units includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; in, Two sub-pixels of one color among the first color sub-pixel, the second color sub-pixel, or the third color sub-pixel are provided.

4. The driving method according to claim 3, wherein in the pixel array, during the control of the pixel unit in each frame by the pixel driving circuit, the sub-pixels corresponding to the odd-numbered rows and the even-numbered rows are set to be two and are controlled separately.

5. The driving method according to claim 1, wherein The display stage includes a first stage, a second stage, a third stage and a fourth stage which are arranged in succession, each stage includes 8 subframes, and during the driving process, the first subframe to the seventh subframe are pulse width modulation, and the eighth subframe is pulse amplitude modulation.

6. The driving method according to claim 5, wherein in each phase, In the first stage, the pixel driving circuit is regulated to make the data signal value of the first color sub-pixel corresponding to the odd-numbered rows in the pixel array zero, and the first control signal is provided from the 1st sub-frame to the 7th sub-frame, and the second control signal is provided in the 8th sub-frame, and a first pixel data structure is obtained; In the second stage, the pixel driving circuit is regulated to make the data signal values ​​of the first color sub-pixels corresponding to the even-numbered rows in the pixel array zero, and the data signal values ​​of the sub-pixels corresponding to the first column and the last column are both zero, and the first control signal is provided from the first sub-frame to the seventh sub-frame, and the second control signal is provided in the eighth sub-frame, and a second pixel data structure is obtained; In the third stage, the pixel driving circuit is regulated to make the data signal values ​​of the first color sub-pixels corresponding to the odd-numbered rows in the pixel array zero, and the data signal values ​​of the sub-pixels corresponding to the first row and the last row are both zero, and the first control signal is provided from the 1st sub-frame to the 7th sub-frame, and the second control signal is provided in the 8th sub-frame, and a third pixel data structure is obtained; In the fourth stage, the pixel driving circuit is regulated and the data signal value of the first color sub-pixel corresponding to the even rows in the pixel array is made zero, and the data signal values ​​of the sub-pixels corresponding to the first row and the last row, the first column and the last column are all zero, and the first control signal is provided from the 1st sub-frame to the 7th sub-frame, and the second control signal is provided from the 8th sub-frame, and a fourth pixel data structure is obtained. 7 . The driving method according to claim 6 , wherein in different pixel data structures, each pixel unit includes a virtual pixel, and the virtual pixel is located at a center position of the pixel unit.

8. A method for driving a display panel, comprising the following steps: Get a frame of image to be displayed; In each frame of the image to be displayed, the image to be displayed is divided into a plurality of display stages which are arranged continuously, each of which includes N subframes, wherein: N is an integer greater than or equal to 1; In each of the display stages, a first control signal is provided to pixel units corresponding to the 1st subframe to the N-1th subframe in the N subframes through a pixel driving circuit of the display panel; A second control signal is provided to the pixel unit corresponding to the Nth subframe in the N subframes, and corresponding pixel data structures in different display stages are obtained and displayed.

9. The driving method according to claim 8, wherein in the N subframes, the pixel units corresponding to the 1st to the N-1th subframes are of low grayscale, and the pixel units corresponding to the Nth subframe are of high grayscale; in, The first control signal is a pulse width modulation signal, and the second control signal is a pulse amplitude modulation signal.

10. The driving method according to claim 8, wherein the pixel unit array is disposed in a display area of ​​the display panel to form an N*M pixel array, and each of the pixel units includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; in, Two sub-pixels of one color among the first color sub-pixel, the second color sub-pixel, or the third color sub-pixel are provided.

11. The driving method according to claim 10, wherein in the pixel array, during the control of the pixel unit in each frame by the pixel driving circuit, the sub-pixels corresponding to the odd-numbered rows and the even-numbered rows are set to be two and are controlled separately.

12. The driving method according to claim 8, wherein: The display stage includes a first stage, a second stage, a third stage and a fourth stage which are arranged in succession, each stage includes 8 subframes, and during the driving process, the first subframe to the seventh subframe are pulse width modulation, and the eighth subframe is pulse amplitude modulation.

13. The driving method according to claim 12, wherein in each phase, In the first stage, the pixel driving circuit is regulated to make the data signal value of the first color sub-pixel corresponding to the odd-numbered rows in the pixel array zero, and the first control signal is provided from the 1st sub-frame to the 7th sub-frame, and the second control signal is provided in the 8th sub-frame, and a first pixel data structure is obtained; In the second stage, the pixel driving circuit is regulated to make the data signal values ​​of the first color sub-pixels corresponding to the even-numbered rows in the pixel array zero, and the data signal values ​​of the sub-pixels corresponding to the first column and the last column are both zero, and the first control signal is provided from the first sub-frame to the seventh sub-frame, and the second control signal is provided in the eighth sub-frame, and a second pixel data structure is obtained; In the third stage, the pixel driving circuit is regulated to make the data signal values ​​of the first color sub-pixels corresponding to the odd-numbered rows in the pixel array zero, and the data signal values ​​of the sub-pixels corresponding to the first row and the last row are both zero, and the first control signal is provided from the 1st sub-frame to the 7th sub-frame, and the second control signal is provided in the 8th sub-frame, and a third pixel data structure is obtained; In the fourth stage, the pixel driving circuit is regulated and the data signal value of the first color sub-pixel corresponding to the even rows in the pixel array is made zero, and the data signal values ​​of the sub-pixels corresponding to the first row and the last row, the first column and the last column are all zero, and the first control signal is provided from the 1st sub-frame to the 7th sub-frame, and the second control signal is provided from the 8th sub-frame, and a fourth pixel data structure is obtained. 14 . The driving method according to claim 13 , wherein in different pixel data structures, each pixel unit includes a virtual pixel, and the virtual pixel is located at a center position of the pixel unit.

15. A pixel driving circuit applied to the driving method as claimed in claim 8, comprising: a first thin film transistor, wherein a gate of the first thin film transistor is connected to a first scanning signal line, and a source of the first thin film transistor is connected to a data voltage line; a second thin film transistor, wherein a gate of the second thin film transistor is connected to a drain of the first thin film transistor, a drain of the second thin film transistor is connected to a high potential voltage of a power supply, and a source of the second thin film transistor is connected to a light emitting diode and one end of the first capacitor; a third thin film transistor, wherein a gate of the third thin film transistor is connected to a third scanning signal line, a source of the third thin film transistor is connected to a source of the second thin film transistor, and a drain of the third thin film transistor is connected to a reference voltage; A fourth thin film transistor, wherein the gate of the fourth thin film transistor is connected to the second scanning signal line, the source of the fourth thin film transistor is connected to the drain of the first thin film transistor and the other end of the first capacitor, and the drain of the fourth thin film transistor is connected to the initial voltage.

16. The pixel driving circuit according to claim 15, wherein At low gray scale, the first scanning signal line and the third scanning signal line are at high level, the first thin film transistor and the third thin film transistor are turned on, the data voltage is charged into the second thin film transistor and turned on, then the first scanning signal line and the third scanning signal line are at low level, the first thin film transistor and the third thin film transistor are turned off; At a high gray scale, the second scanning signal line is at a low level, the fourth thin film transistor is turned off, the amplitude of the data voltage is adjusted, and the pixel unit displays different gray scales.

17. The pixel driving circuit according to claim 16, wherein the low grayscale corresponds to a pulse width modulation signal, the high grayscale corresponds to a pulse amplitude modulation signal, and under the drive of the pulse width modulation signal, the duty cycle corresponding to the charging time of each subframe is controlled to obtain different grayscale values.

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