Dynamic memory forming method and dynamic memory

Abstract

The present invention provides a dynamic memory forming method, comprising: on the basis of a first photoetching pattern, etching a first substrate to form silicon pillar structures separated by first trenches; and forming a storage capacitor by taking the silicon pillar structures as a capacitor plate, and forming vertical transfer gate structures above the silicon pillar structures. According to the present invention, the process steps are simple, a high-density trench capacitor can be formed as a storage capacitor, the integration density is high, and the present invention is compatible with an image sensor forming process and has wide applicability. Additionally, according to the solution, a polycrystalline silicon gate and an active area can be used as the connection of a word line and a bit line, thereby breaking through the traditional capacitance density limit.

Description

Method for forming dynamic memory and dynamic memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 29, 2023, with application number 202310786847.6 and invention name “A method for forming a dynamic memory and a dynamic memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a dynamic memory and the dynamic memory. Background Art

[0003] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily uses the amount of charge stored in a capacitor to represent whether a binary byte is 1 or 0. The basic unit of DRAM is very simple, typically a transistor connected in series with a capacitor. The transistor controls the storage or erasure of electrons in the capacitor, thereby controlling the transmission of information. A single DRAM unit can only store one byte of data. An existing DRAM storage unit consists of a memory circuit consisting of a MOS transistor and a capacitor, with the MOS transistor acting as a switch and the capacitor as a storage medium. DRAM capacitors are typically formed in a stacked or trenched manner, offering advantages such as a small footprint, high capacity, and high density. However, their density is affected by metal wiring and has a density limit. As the amount of data input and output by chips increases, information chips require more and more DRAM, but this consumes a large amount of chip area. This, in turn, places higher demands on high-density DRAM designs.

[0004] Summary of the Invention

[0005] The object of the present invention is to provide a method for forming a dynamic memory, comprising:

[0006] Etching the first substrate according to the first photolithographic pattern to form silicon pillar structures separated by first trenches;

[0007] The silicon pillar structure is used as a capacitor plate to form a storage capacitor, and a vertical transfer gate structure is formed above the silicon pillar structure.

[0008] Furthermore, after forming the silicon pillar structures, the method further includes: performing chemical mechanical polishing on the bottom of the first substrate until the silicon pillar structures are electrically isolated from each other.

[0009] Furthermore, a second substrate with high doping concentration is provided. The second substrate is located at the bottom of the first substrate, and the doping type is opposite to that of the silicon pillar structure. When forming the silicon pillar structure, the first substrate is etched to a certain depth so that each silicon pillar structure is electrically isolated from each other to optimize the performance of the storage capacitor.

[0010] Furthermore, at least some of the upper portions of the silicon column structures are connected to each other via a connecting structure to provide support and prevent the silicon column structures from falling over.

[0011] Furthermore, a hard mask layer is formed according to the first photolithography pattern, and the first substrate is etched according to the hard mask layer to form the connection structure, and the connection structure at least includes the hard mask layer or a combination of the hard mask layer and a portion of the first substrate.

[0012] Further, etching the first substrate according to the hard mask layer to form the connection structure includes:

[0013] The first substrate is etched according to the hard mask layer, and the first trench and the silicon pillar structure are formed by adjusting the etching process conditions. At the same time, the hard mask layer or the combination of the hard mask layer and part of the first substrate forms the connection structure.

[0014] Further, etching the first substrate according to the hard mask layer to form the connection structure includes:

[0015] etching the first substrate according to the hard mask layer to form a second trench;

[0016] forming a first dielectric layer on the surface of the second trench;

[0017] etching the first dielectric layer and the first substrate at the bottom of the second trench to form a third trench;

[0018] Isotropic etching is used to widen the third trench on both sides to form the first trench and the silicon pillar structure. At the same time, the first dielectric layer is used to protect the hard mask layer and a portion of the first substrate so as to form the connection structure.

[0019] Further, etching the first substrate according to the hard mask layer to form the connection structure includes:

[0020] etching the first substrate according to the hard mask layer to form a second trench;

[0021] forming a first dielectric layer on the surface of the second trench;

[0022] The bottom of the first dielectric layer and the first substrate are continuously etched, and the first trench and the silicon pillar structure are formed by adjusting the etching process conditions. At the same time, the first dielectric layer is protected so that the hard mask layer and a portion of the first substrate form the connection structure.

[0023] Furthermore, after forming the first trench, the width of the bottom of the first trench is reduced by at least one epitaxial process to increase the capacitance value.

[0024] Furthermore, after the width of the bottom of the first trench is reduced by at least one epitaxial process, the first photolithography pattern is self-alignedly etched again to increase the width of the upper portion of the first trench, so as to optimize subsequent processes.

[0025] Furthermore, forming a vertical transfer gate structure above the silicon pillar structure includes:

[0026] forming a second dielectric layer on the surface of the first trench;

[0027] filling polysilicon in the second dielectric layer to form a polysilicon layer;

[0028] etching the polysilicon layer and the first substrate according to the second photolithography pattern, and controlling the etching selectivity so that the surface of the polysilicon layer is lower than the first substrate to form a fifth trench;

[0029] Filling the fifth trench with a dielectric to form a third dielectric layer, wherein the third dielectric layer forms a shallow trench isolation structure and an active area;

[0030] etching the third dielectric layer on the sidewalls of the active area according to the third photolithographic pattern to expose silicon on the sides of the active area, thereby forming a vertical transfer channel;

[0031] A fourth dielectric layer is formed and filled with polysilicon to form a polysilicon gate.

[0032] Furthermore, the active area is used as a bit line of the dynamic memory.

[0033] Furthermore, the polysilicon gate is used as a word line of the dynamic memory.

[0034] The present invention also provides a dynamic memory formed by adopting the above-mentioned method for forming a dynamic memory.

[0035] This invention proposes a solution that uses simple process steps to form high-density trench capacitors as storage capacitors. This solution offers high integration density and is compatible with image sensor manufacturing processes, making it widely applicable. Furthermore, this solution utilizes polysilicon gates and active areas as connections for word and bit lines, breaking through traditional capacitance density limitations. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments when read with reference to the accompanying drawings.

[0037] FIG1 is a schematic diagram of shape combinations of different photolithographic patterns according to an embodiment of the present invention;

[0038] 2 to 13 are schematic diagrams of the structures of dynamic memories in different embodiments of the present invention.

[0039] In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout different drawings. DETAILED DESCRIPTION

[0040] The present invention aims to provide a method for forming a dynamic memory, which may specifically include the following steps:

[0041] Step S100: etching the first substrate 100 according to the first photolithographic pattern A (as shown in FIG1 ) to form silicon pillar structures 120 separated by first trenches 110 , as shown in FIG2 ;

[0042] Step S200 : Using the silicon pillar structure 120 as a capacitor plate to form a storage capacitor, and forming a vertical transfer gate structure (VTG) above the silicon pillar structure 120 .

[0043] Optionally, in the present invention, to achieve the function of storage capacitors, the silicon pillar structures 120 serving as capacitor plates should be electrically isolated from each other. The present invention is not limited to the specific technical solution for electrically isolating the silicon pillar structures 120. For example, in an optional embodiment, after forming the silicon pillar structures 120, chemical mechanical polishing (CMP) can be performed on the bottom of the first substrate 100 until the silicon pillar structures 120 are electrically isolated from each other, as shown in FIG3. In another optional embodiment, a highly doped second substrate 200 may be provided outside the first substrate 100. As shown in FIG4 , the second substrate 200 is located at the lower portion of the first substrate 100, and the doping type is opposite to that of the silicon pillar structure 120. That is, if the first substrate 100 is N-type doped, the second substrate 200 adopts a highly doped P-type; if the first substrate 100 is P-type doped, the second substrate 200 adopts a highly doped N-type. When the silicon pillar structure 120 is formed in step S100, the first substrate 100 is etched to a certain depth, for example, into the second substrate 200, or close to the interface between the first substrate 100 and the second substrate 200. Due to the different doping types, the silicon pillar structures 120 are electrically isolated from each other to optimize the performance of the storage capacitor.

[0044] In an optional embodiment, the upper portions of at least some of the silicon pillar structures 120 formed in the present invention may be connected to each other via a connecting structure 121 to provide support strength during subsequent processes and prevent the silicon pillar structures 120 from falling over.

[0045] Specifically, in one embodiment, in step S100, when etching to form the silicon pillar structure 120, a hard mask layer 300 can be first formed according to the first photolithography pattern A, and then the first substrate 100 can be etched according to the hard mask layer 300, and the connection structure 121 is formed while forming the silicon pillar structure 120, wherein the connection structure 121 includes at least a partial structure of the hard mask layer 300, or simultaneously includes a combination of the hard mask layer 300 and a portion of the first substrate 100.

[0046] Preferably, the connection structure 121 can be formed according to the following steps:

[0047] Step S111: According to the hard mask layer 300, the first substrate 100 is etched, and the first groove 110 and the silicon pillar structure 120 are formed by adjusting the etching process conditions. At the same time, the hard mask layer 300 or the combination of the hard mask layer 300 and part of the first substrate 100 forms the connection structure 121, as shown in Figure 5 or Figure 6.

[0048] To achieve the connection structure 121, a preferred solution is to directly adjust the process conditions when etching the trenches, such as using isotropic etching, so that the hard mask layer 300 between the silicon pillar structures 120 is retained, as shown in FIG5 . This serves as the connection structure 121 supporting the silicon pillar structures 120. When the support is no longer needed in subsequent process steps, the hard mask layer 300 is also more easily removed. At the same time, a portion of the first substrate 100 beneath the hard mask layer 300 can also be retained, as shown in FIG6 , to serve as a connection support.

[0049] In another optional manner, the connection structure 121 can be formed by the following steps:

[0050] Step S121 : etching the first substrate 100 according to the hard mask layer 300 to form a second trench 130 ;

[0051] Step S122: forming a first dielectric layer 131 on the surface of the second trench 130 , as shown in FIG7 ;

[0052] Step S123: etching the first dielectric layer 131 and the first substrate 100 at the bottom of the second trench 130 to form a third trench 140, as shown in FIG8;

[0053] Step S124: Using isotropic etching, widen the third trench 140 on both sides to form the first trench 110 and the silicon pillar structure 120. At the same time, through the protection of the first dielectric layer 131, the combination of the hard mask layer 300 and a portion of the first substrate 100 forms the connection structure 121, as shown in Figure 9.

[0054] Through the above steps, the hard mask layer 300 and the first substrate 100 thereunder can form the connection structure 121. After the etching process, the first dielectric layer 131 can be removed.

[0055] Alternatively, the third trench 140 may not be formed, and the first dielectric layer 131 and the first substrate 100 at the bottom of the second trench 130 may be directly etched, as follows:

[0056] Step S131 : etching the first substrate 100 according to the hard mask layer 300 to form a second trench 130 ;

[0057] Step S132: forming a first dielectric layer 131 on the surface of the second trench 130;

[0058] Step S133: Continue etching the bottom of the first dielectric layer 131 and the first substrate 100, and by adjusting the etching process conditions, form the first trench 110 and the silicon pillar structure 120. At the same time, through the protection of the first dielectric layer 131, the combination of the hard mask layer 300 and part of the first substrate 100 forms the connecting structure 121.

[0059] Compared with the previous optional implementation, this method has a relatively poor etching effect, but it can also realize the connection structure 121 and provide strength support for the silicon pillar structure 120.

[0060] Preferably, in one embodiment, after forming the first trench 110 , the width of the bottom of the first trench 110 may be reduced through at least one epitaxial process, so that the capacitance value may be increased after the storage capacitor is subsequently formed.

[0061] Furthermore, after the width of the bottom of the first trench 110 is reduced, the first photolithography pattern A (as shown in FIG. 1 ) can be self-aligned and etched again to increase the width of the upper portion of the first trench 110 , thereby optimizing subsequent processes.

[0062] In an optional embodiment, in step S200, a vertical transfer gate structure (VTG) may be formed above the silicon pillar structure 120 by the following steps:

[0063] Step S210: forming a second dielectric layer 111 on the surface of the first trench 110;

[0064] Step S220: filling the second dielectric layer 111 with polysilicon to form a polysilicon layer 112, as shown in FIG10 ;

[0065] Step S230: etching the polysilicon layer 112 and the first substrate 100 according to the second photolithography pattern B (as shown in FIG1 ), and controlling the etching selectivity so that the surface of the polysilicon layer 112 is lower than the first substrate 100, thereby forming a fifth trench 140;

[0066] Step S240: filling the fifth trench 150 with a dielectric to form a third dielectric layer 151 , wherein the third dielectric layer 151 forms a shallow trench isolation (STI) structure and an active area (AA), as shown in FIG11 ;

[0067] Step S250: etching the third dielectric layer 151 on the sidewalls of the active area (AA) according to the third photolithography pattern C (as shown in FIG1 ) to expose the silicon on the side of the active area (AA) to form a vertical transfer channel, as shown in FIG12 ;

[0068] Step S260 : forming a fourth dielectric layer 160 and filling it with polysilicon, and etching according to the fourth photolithography pattern D (as shown in FIG. 1 ) to form a polysilicon gate 170 , as shown in FIG. 13 .

[0069] On the basis of the above process steps, the present invention can also use the active area (AA) as the bit line of the dynamic memory; also optionally, the polysilicon gate 160 can be used as the word line of the dynamic memory.

[0070] On this basis, the present invention further provides a dynamic memory formed by the above-mentioned method for forming a dynamic memory.

[0071] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the wording "a" does not exclude pluralities. Multiple elements stated in a device claim may also be implemented by a single element. Terms such as first and second are used to indicate names and do not imply any particular order.

Claims

1. A method for forming a dynamic memory, characterized in that: include: Etching the first substrate according to the first photolithography pattern to form silicon pillar structures separated by first trenches; The silicon pillar structure is used as a capacitor plate to form a storage capacitor, and a vertical transfer gate structure is formed above the silicon pillar structure.

2. The method for forming a dynamic memory according to claim 1, wherein: After the silicon pillar structures are formed, the method further includes: performing chemical mechanical polishing on the bottom of the first substrate until the silicon pillar structures are electrically isolated from each other.

3. The method for forming a dynamic memory according to claim 1, wherein: A second substrate doped with a high concentration is provided. The second substrate is located at the bottom of the first substrate and has a doping type opposite to that of the silicon pillar structure. When forming the silicon pillar structure, the first substrate is etched to a certain depth so that each silicon pillar structure is electrically isolated from each other to optimize the performance of the storage capacitor.

4. The method for forming a dynamic memory according to claim 1, wherein: At least some of the upper portions of the silicon column structures are connected to each other via a connecting structure to provide support and prevent the silicon column structures from falling over.

5. The method for forming a dynamic memory according to claim 4, wherein: A hard mask layer is formed according to the first photolithography pattern, and the first substrate is etched according to the hard mask layer to form the connection structure, wherein the connection structure at least includes the hard mask layer or a combination of the hard mask layer and a portion of the first substrate.

6. The method for forming a dynamic memory according to claim 5, wherein: The etching the first substrate according to the hard mask layer to form the connection structure comprises: The first substrate is etched according to the hard mask layer, and the first trench and the silicon pillar structure are formed by adjusting the etching process conditions, while the hard mask layer or the combination of the hard mask layer and part of the first substrate forms the connection structure.

7. The method for forming a dynamic memory according to claim 5, wherein: The etching the first substrate according to the hard mask layer to form the connection structure comprises: Etching the first substrate according to the hard mask layer to form a second trench; forming a first dielectric layer on the surface of the second groove; Etching the first dielectric layer and the first substrate at the bottom of the second trench to form a third trench; The third trench is widened on both sides by isotropic etching to form the first trench and the silicon pillar structure. At the same time, the first dielectric layer is used for protection so that the hard mask layer and a part of the first substrate form the connection structure.

8. The method for forming a dynamic memory according to claim 5, wherein: The etching the first substrate according to the hard mask layer to form the connection structure comprises: Etching the first substrate according to the hard mask layer to form a second trench; forming a first dielectric layer on the surface of the second groove; Continue to etch the bottom of the first dielectric layer and the first substrate, and adjust the etching process conditions to form the first trench and the silicon pillar structure. At the same time, the first dielectric layer is protected so that the combination of the hard mask layer and part of the first substrate forms the connection structure.

9. The method for forming a dynamic memory according to claim 1, wherein: After forming the first trench, the width of the bottom of the first trench is reduced by at least one epitaxial process to increase the capacitance value.

10. The method for forming a dynamic memory according to claim 9, wherein: After the width of the bottom of the first trench is reduced by at least one epitaxial process, the first photolithography pattern is self-alignedly etched again to increase the width of the upper portion of the first trench, so as to optimize subsequent processes.

11. The method for forming a dynamic memory according to claim 1, wherein: The forming of a vertical transfer gate structure above the silicon pillar structure comprises: forming a second dielectric layer on the surface of the first trench; Filling polysilicon in the second dielectric layer to form a polysilicon layer; According to the second photolithography pattern, the polysilicon layer and the first substrate are etched, and the surface of the polysilicon layer is made lower than the first substrate by controlling the etching selection ratio, so as to form a fifth trench; Filling the fifth trench with a dielectric to form a third dielectric layer, wherein the third dielectric layer forms a shallow trench isolation structure and an active area; According to the third photolithography pattern, etching the third dielectric layer on the sidewall of the active area to expose the silicon on the side of the active area to form a vertical transfer channel; A fourth dielectric layer is formed and filled with polysilicon to form a polysilicon gate.

12. The method for forming a dynamic memory according to claim 11, wherein: The active area is used as a bit line of the dynamic memory.

13. The method for forming a dynamic memory according to claim 11, wherein: The polysilicon gate is used as a word line of the dynamic memory.

14. A dynamic memory, characterized in that: The dynamic memory is formed by the method for forming the dynamic memory as claimed in claims 1 to 13.

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