Clock synchronization method, and system, assembly and device

Abstract

Provided in the present disclosure are a clock synchronization method, and a system, an assembly and a device. The clock synchronization method which is applied to a slave module comprises: in response to receiving a first message, which is sent by a master module, sending a second message to the master module and starting timing; in response to receiving a third message, which is sent by the master module, stopping timing, wherein the third message is sent by the master module after a first preset duration since the second message is received; dividing the difference between the current timing duration and the first preset duration by 2, so as to obtain a transmission delay between the master module and the slave module; and performing clock synchronization on the master module and the slave module according to the transmission delay. A transmission delay between a master module and a slave module is obtained by means of timing, such that clock correction between the master module and the slave module can be performed.

Description

Clock synchronization method, system, component, and device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202310752783.8 and application date June 26, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present application relates to the field of bus technology, and in particular to a clock synchronization method, system, component, and device. Background Art

[0004] Internal bus interconnect protocols within a system on chip (SOC) include the Advanced eXtensible Interface (AXI) protocol, the I2C (Inter Integrated Circuit) bus, and the I3C (Improved Inter Integrated Circuit). The master die and slave die are connected via a bus. Chiplet technology is becoming increasingly common in SOCs, but the clocks between the chiplets (the master and slaves) are often asynchronous. In addition to data communication, these chiplets also require clock synchronization.

[0005] Summary of the Invention

[0006] The purpose of the present disclosure is to provide a clock synchronization method, system, component, and device, which solve the technical problem of clock asynchrony between a master module and each slave module in the prior art.

[0007] According to one aspect of the present disclosure, a clock synchronization method is provided, which is applied to a slave module of a bus system, comprising:

[0008] In response to receiving the first message sent by the main module, sending a second message to the main module and starting timing;

[0009] In response to receiving a third message sent by the main module, stopping the timing; wherein the third message is sent by the main module at a first preset time interval after receiving the second message;

[0010] Divide the difference between the current timing duration and the first preset duration by 2 to obtain the transmission delay between the master module and the slave module;

[0011] Based on the transmission delay, the clocks of the master module and the slave module are synchronized.

[0012] In some embodiments, in the clock synchronization method, performing clock synchronization on the master module and the slave module based on the transmission delay includes:

[0013] Sending a corresponding fourth message to the main module according to the transmission delay; wherein the fourth message carries the transmission delay;

[0014] Receive a fifth message sent by the main module; wherein the fifth message is generated by the main module according to the transmission delay after receiving the fourth message, and the fifth message carries a second preset duration, and the sum of the second preset duration and the transmission delay is equal to a specified value;

[0015] Restarting the slave clock of the slave module after a second preset time interval after receiving the fifth message sent by the master module;

[0016] The slave clock and the master clock of the master module are restarted at the same time.

[0017] In some embodiments, in the above clock synchronization method, the bus system includes at least two slave modules, and each slave module restarts the corresponding slave clock according to the above method, so that the slave clocks of each slave module are restarted simultaneously.

[0018] In some embodiments, in the above clock synchronization method, the bus system includes at least two slave modules, the designated value corresponding to each slave module is the same, and the fifth message corresponding to each slave module is sent simultaneously by the master module.

[0019] In some embodiments, in the clock synchronization method, before sending the corresponding fourth message to the master module based on the transmission delay, the method further includes:

[0020] Sending a first interrupt message to the main module to trigger the main module to return a sixth message;

[0021] Sending a corresponding fourth message to the main module according to the transmission delay includes:

[0022] In response to receiving the sixth message, a corresponding fourth message is sent to the main module according to the transmission delay.

[0023] In some embodiments, in the clock synchronization method, the method further includes:

[0024] In response to receiving the seventh message sent by the master module, an eighth message is sent to the master module; wherein the eighth message carries the time value of the slave clock when the slave module receives the seventh message, and is used to enable the master module to confirm whether the master clock and the slave clock are synchronized based on the time value of the master clock when it sends the seventh message, the time value of the slave clock when the slave module receives the seventh message, and the transmission delay; or, the eighth message carries the time value of the slave clock when the slave module sends the eighth message, and is used to enable the master module to confirm whether the master clock and the slave clock are synchronized based on the time value of the master clock when it receives the eighth message, the time value of the slave clock when the slave module sends the eighth message, and the transmission delay.

[0025] In some embodiments, in the clock synchronization method, in response to receiving the seventh message sent by the master module, before sending the eighth message to the master module, the method further includes:

[0026] In response to receiving the ninth message sent by the main module, a second interrupt message is sent to the main module to trigger the main module to return the seventh message.

[0027] In some embodiments, in the above clock synchronization method, the bus system includes at least two slave modules, and the time interval between any two slave modules sending the second interrupt message is greater than a third preset time length.

[0028] In some embodiments, in the clock synchronization method, the method further includes:

[0029] Receive the tenth message sent by the master module, and confirm the time value of the slave clock when the slave module receives the tenth message; wherein the tenth message carries the time value of the master clock when the master module sends the tenth message;

[0030] Whether the master clock and the slave clock are synchronized is confirmed based on the time value of the slave clock when the slave module receives the tenth message, the time value of the master clock when the master module sends the tenth message, and the transmission delay.

[0031] According to another aspect of the present disclosure, a clock synchronization method is provided, which is applied to a main module of a bus system, comprising:

[0032] Sending a first message to the slave module to trigger the slave module to start timing and return a second message;

[0033] After receiving the second message, a third message is sent to the slave module at an interval of the first preset time to trigger the slave module to stop timing, so that the slave module divides the difference between the current timing time and the first preset time by 2 to obtain the transmission delay between the master module and the slave module, and then synchronizes the clocks of the master module and the slave module according to the transmission delay.

[0034] In some embodiments, in the clock synchronization method, the method further includes:

[0035] receiving a fourth message sent by the slave module, where the fourth message is generated by the slave module according to the transmission delay and carries the transmission delay;

[0036] Generate a fifth message according to the transmission delay carried by the fourth message; wherein the fifth message carries a second preset duration, and the sum of the second preset duration and the transmission delay is equal to a specified value;

[0037] Sending a fifth message to the slave module, so that the slave module restarts the slave clock of the slave module after a second preset time interval after receiving the fifth message sent by the master module;

[0038] The slave clock and the master clock of the master module are restarted at the same time.

[0039] In some embodiments, in the above clock synchronization method, the bus system includes at least two slave modules, and the master module causes each slave module to restart the corresponding slave clock according to the above method, so that the slave clocks of each slave module are restarted simultaneously.

[0040] In some embodiments, in the above clock synchronization method, the bus system includes at least two slave modules, and the designated values ​​corresponding to the slave modules are the same;

[0041] The fifth messages corresponding to the various slave modules are sent simultaneously by the master module.

[0042] In some embodiments, in the clock synchronization method, before receiving the fourth message sent by the slave module, the method further includes:

[0043] In response to receiving the first interrupt message sent by the slave module, a sixth message is sent to the slave module to trigger the slave module to return a fourth message.

[0044] In some embodiments, in the clock synchronization method, the method further includes:

[0045] Sending a seventh message to the slave module to trigger the slave module to return an eighth message; wherein the eighth message carries the time value of the slave clock when the slave module receives the seventh message; confirming whether the master clock and the slave clock are synchronized based on the time value of the master clock when the master module sends the seventh message, the time value of the slave clock when the slave module receives the seventh message, and the transmission delay; or,

[0046] Send the seventh message to the slave module to trigger the slave module to return the eighth message; wherein the eighth message carries the time value of the slave clock when the slave module sends the eighth message; based on the time value of the master clock when the master module receives the eighth message, the time value of the slave clock when the slave module sends the eighth message, and the transmission delay, confirm whether the master clock and the slave clock are synchronized.

[0047] In some embodiments, in the clock synchronization method, before sending the seventh message to the slave module, the method further includes:

[0048] Sending a ninth message to the slave module to trigger the slave module to return a second interrupt message;

[0049] Send the seventh message to the slave module, including:

[0050] In response to receiving the second interrupt message sent by the slave module, a seventh message is sent to the slave module.

[0051] In some embodiments, in the above clock synchronization method, the bus system includes at least two slave modules, and the time interval between any two slave modules sending the second interrupt message is greater than a third preset time length.

[0052] In some embodiments, in the clock synchronization method, the method further includes:

[0053] A tenth message is sent to the slave module to trigger the slave module to confirm the time value of the slave clock when it receives the tenth message; wherein the tenth message carries the time value of the master clock when the master module sends the tenth message, so that the slave module confirms whether the master clock and the slave clock are synchronized based on the time value of the slave clock when it receives the tenth message, the time value of the master clock when the master module sends the tenth message, and the transmission delay.

[0054] According to another aspect of the present disclosure, there is provided a bus system, comprising:

[0055] bus;

[0056] A slave module configured to implement the clock synchronization method applied to the slave module described in any one of the above embodiments;

[0057] The main module is configured to implement the clock synchronization method applied to the main module described in any of the above embodiments.

[0058] According to another aspect of the present disclosure, an electronic component is provided, comprising the bus system described in any one of the above embodiments.

[0059] According to another aspect of the present disclosure, an electronic device is provided, comprising the electronic component described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] FIG1 is a schematic flow chart of a clock synchronization method (applied to a slave module) provided in one embodiment of the present disclosure;

[0061] FIG2 is a timing diagram of a clock synchronization method provided by an embodiment of the present disclosure;

[0062] FIG3 is a schematic diagram of a connection structure of a bus system provided by an embodiment of the present disclosure;

[0063] FIG4 is a timing diagram of another clock synchronization method provided by an embodiment of the present disclosure;

[0064] FIG5 is a timing diagram of another clock synchronization method provided by an embodiment of the present disclosure;

[0065] FIG6 is a timing diagram of another clock synchronization method provided by an embodiment of the present disclosure;

[0066] FIG7 is a timing diagram of another clock synchronization method provided by an embodiment of the present disclosure;

[0067] FIG8 is a flow chart of a clock synchronization method (applied to a master module) provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0068] Before introducing the embodiments of the present disclosure, it should be noted that:

[0069] Some embodiments of the present disclosure are described as processing flows. Although the various operation steps of the flow may be given sequential step numbers, the operation steps therein may be implemented in parallel, concurrently, or simultaneously.

[0070] In the embodiments of the present disclosure, the terms "first", "second", etc. may be used to describe various features, but these features should not be limited by these terms. These terms are used only to distinguish one feature from another.

[0071] The term “and / or” may be used in embodiments of the present disclosure. “And / or” includes any and all combinations of one or more of the listed associated features.

[0072] It should be understood that when describing the connection relationship or communication relationship between two components, unless it is explicitly stated that the two components are directly connected or directly communicating, the connection or communication between the two components can be understood as direct connection or communication, or as indirect connection or communication through an intermediate component.

[0073] In order to make the technical solutions and advantages of the embodiments of the present disclosure more clearly understood, the exemplary embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present disclosure can be combined with each other unless they conflict.

[0074] The purpose of the present disclosure is to provide a clock synchronization method, system, component, and device, wherein the clock synchronization method applied to a slave module includes sending a second message to the master module and starting timing in response to receiving a first message sent by the master module; stopping timing in response to receiving a third message sent by the master module; wherein the third message is sent by the master module at an interval of a first preset time after receiving the second message; dividing the difference between the current timing time and the first preset time by 2 to obtain the transmission delay between the master module and the slave module; and performing clock synchronization on the master module and the slave module based on the transmission delay.

[0075] In this clock synchronization scheme, the transmission delay between the master module and the slave module is obtained by timing, and the clock between the master module and the slave module can be corrected, thereby achieving clock synchronization between the master module and the slave module.

[0076] An embodiment of the present disclosure provides a clock synchronization method, which is applied to a slave module of a bus system, as shown in FIG1 , and includes:

[0077] Step S110: In response to receiving the first message sent by the main module, sending a second message to the main module and starting timing;

[0078] Step S120: In response to receiving a third message sent by the main module, stop timing; wherein the third message is sent by the main module after receiving the second message at an interval of a first preset time;

[0079] Step S130: Divide the difference between the current timing duration and the first preset duration by 2 to obtain the transmission delay between the master module and the slave module;

[0080] Step S140: performing clock synchronization on the master module and the slave module according to the transmission delay.

[0081] In a bus system, information is transmitted between the master module and the slave module via a bus, which may be an AXI bus, an I2C bus, or an I3C bus.

[0082] The transmission delay test principle is shown in Figure 2. It's understandable that in the timing diagram, T represents the master clock time of the master module, T' represents the slave clock time of the slave module, and Td represents the transmission delay between the master and slave modules. As shown in Figure 2, the master module sends a first message at T0 of the master clock. After receiving the first message, the slave module sends a second message at T'0 of the slave clock and begins timing. The master module receives the second message at T1 of the master clock, separated by a first preset duration, ΔT1, and sends a third message at (T1 + ΔT1) of the master clock. The slave module stops timing after receiving the third message at T'1 of the slave clock. At this point, the timing duration (T'1 - T'0) equals (2*Td + ΔT1). Therefore, the slave module divides the difference between the current timing duration (T'1 - T'0) and the first preset duration, ΔT1, by 2 to obtain the transmission delay Td between the master and slave modules.

[0083] In some embodiments, the first preset time length ΔT1 is not limited in size and can be any value.

[0084] In some embodiments, the master module may carry the first preset time length ΔT1 in the third message and send it to the slave module, or may carry it in other information and send it to the slave module, which is not limited here.

[0085] In some embodiments, the second message is an ACK message. To ensure that the main module has sufficient time to analyze whether the second message is an ACK message or a NACK message upon receiving the second message and confirm whether it is an ACK message before sending the third message, the first preset time duration ΔT1 is preferably greater than the time required for the main module to analyze the second message. In some embodiments, the first preset time duration ΔT1 can be 30 time units (the clock plus 1 is 1 time unit).

[0086] In some embodiments, the main module analyzes whether the second message is an ACK message or a NACK message in the following manner: the second message carries a corresponding valid identifier, 1 indicates that the second message is an ACK message, and 0 indicates that the second message is a NACK message. The correspondence between the valid identifier and the ACK message and the NACK message is recorded in the memory. When the main module receives the second message, the software program of the main module searches the register for corresponding information according to the valid identifier carried by the second message, thereby determining whether the second message is an ACK message or a NACK message.

[0087] The timing function of the slave module is realized by the slave clock, that is, the slave clock is also a timer.

[0088] In some embodiments, when performing clock correction, the master module can send a correction message to the slave module (which carries the time value Tr of the master clock when it sends the correction message). When the slave module receives the correction message, it records the time value T'r of the slave clock when it receives the correction message. Since there is the following relationship between these two time values ​​and the transmission delay Td and the clock deviation offset (the clock deviation between the master clock and the slave clock): T'r = Tr + Td + offset, the slave module can calculate the clock deviation offset, thereby realizing clock correction between the master module and the slave module, and then realizing clock synchronization between the master module and the slave module.

[0089] In other embodiments, when performing clock correction, the slave module can send a correction message to the master module (which carries the time value T'r and transmission delay Td of the slave clock when it sends the correction message). When the master module receives the correction message, it records the time value Tr of the master clock when it receives the correction message. Since there is the following relationship between these two time values ​​and the transmission delay Td and the clock deviation offset (the clock deviation between the master clock and the slave clock): Tr = T'r + Td-offset, the master module can calculate the clock deviation offset, thereby realizing clock correction between the master module and the slave module, and then realizing clock synchronization between the master module and the slave module.

[0090] In other embodiments, when performing clock correction, it is not necessary to calculate the clock offset. Accordingly, step S140 specifically includes:

[0091] Step S142: Sending a corresponding fourth message to the main module according to the transmission delay; wherein the fourth message carries the transmission delay;

[0092] Step S144: receiving a fifth message sent by the main module; wherein the fifth message is generated by the main module according to the transmission delay after receiving the fourth message, and the fifth message carries a second preset duration, and the sum of the second preset duration and the transmission delay is equal to a specified value;

[0093] Step S146: Restarting the slave clock of the slave module after a second preset time interval after receiving the fifth message sent by the master module;

[0094] The slave clock and the master clock of the master module are restarted at the same time.

[0095] Restarting means that the clock starts counting from 0.

[0096] This means that when the slave and master clocks restart simultaneously, the clock offset between them is equal to 0, meaning that clock correction and synchronization are achieved during the restart. This clock synchronization solution eliminates the need to determine the clock offset to achieve clock synchronization, shortening the time required for clock synchronization.

[0097] The way to restart the master clock and the slave clock at the same time is: when the master module sends the fifth message, the master module can determine that the slave clock will restart at a specified time interval (the sum of the second preset time length and the transmission delay) after the master module sends the fifth message. Therefore, the master module can control the master clock to restart at a specified time interval after sending the fifth message, thereby achieving the simultaneous restart of the slave clock and the master clock.

[0098] In some embodiments, the fourth message also carries a restart instruction to further enable the slave module to restart the slave clock of the slave module after a second preset time interval after receiving the fifth message sent by the master module.

[0099] In some embodiments, the bus system includes at least two slave modules. In such a bus system, to synchronize the clocks of the master module and the slave modules, the slave clocks of each slave module need to be restarted simultaneously. The method for restarting the slave clocks of each slave module is the same as that described above and will not be repeated here.

[0100] As shown in FIG3 , the bus system includes three slave modules, namely slave module 0, slave module 1 and slave module 2.

[0101] In some embodiments, in order to achieve simultaneous restart of the slave clocks of each slave module, the specified values ​​corresponding to each slave module are the same, and the fifth messages corresponding to each slave module are sent simultaneously by the master module, thereby achieving that the slave clocks of each slave module are restarted simultaneously at an interval of the specified value (the sum of the second preset time length and the transmission delay) after the master module sends the fifth message.

[0102] It can be understood that, as shown in Figure 2, the time value of the master clock when the master module sends the fifth message is T3, and the above-mentioned specified value is equal to the transmission delay Td plus the second preset time length △T2. When performing clock synchronization, it can be set that when the master module receives the fourth message sent by all slave modules, that is, after obtaining the transmission delay Td corresponding to each slave module, the above-mentioned specified value is set according to the transmission delay Td corresponding to each slave module (the specified value needs to be greater than or equal to the transmission delay Td corresponding to each slave module, preferably greater than the transmission delay Td corresponding to each slave module), and then, at a sending time T3, the master module simultaneously sends the corresponding fifth message to each slave module.

[0103] For example, as shown in Figure 3, the transmission delay corresponding to slave module 0 is 5 time units, the transmission delay corresponding to slave module 1 is 6 time units, and the transmission delay corresponding to slave module 2 is 8 time units. Then the master module can set the specified value to 10 time units, that is, the slave clock is restarted 5 time units (second preset time length) after slave module 0 receives the fifth message, the slave clock is restarted 4 time units (second preset time length) after slave module 1 receives the fifth message, and the slave clock is restarted 2 time units (second preset time length) after slave module 2 receives the fifth message, so that the actual start time (restart time) of the slave clocks of all slave modules is consistent (that is, timing starts from 0 at the same time).

[0104] In some embodiments, as shown in FIG4 , before step S142 , the method further includes:

[0105] A first interrupt message is sent to the main module to trigger the main module to return a sixth message.

[0106] Correspondingly, step S142 includes:

[0107] In response to receiving the sixth message, a corresponding fourth message is sent to the main module according to the transmission delay.

[0108] It can be understood that after the slave module obtains the transmission delay, if the fourth message carrying the transmission delay is directly sent to the master module, it is possible that the master module is not yet ready to receive the transmission delay. Therefore, the preferred method is that after the slave module obtains the transmission delay, it first notifies the master module by interruption, indicating that the slave module has obtained the transmission delay. If the master module is ready to receive the transmission delay, it can send a sixth message to the slave module to read the transmission delay obtained by the slave module. The sixth message is equivalent to a read message.

[0109] In some embodiments, the slave module can be set to wait for a period of time ΔT3 (greater than the time required for the slave module to calculate the transmission delay) after receiving the third message before sending the first interrupt message to the master module, thereby reserving sufficient time for the slave module to calculate the transmission delay. For example, this period of time can be 30 time units.

[0110] In some embodiments, after the master module and the slave module are synchronized, they may be subject to external interference and clock deviation may occur again after a period of time. Therefore, in order to enable the master module to promptly confirm whether the clocks of the master module and the slave module are synchronized, the master module can be configured to send a seventh message to the slave module when it needs to confirm whether the clocks are synchronized, so as to read back the time value of the slave clock, thereby confirming whether the time value of the slave clock has an error. If there is an error, it indicates that clock deviation exists. Specifically, the steps of confirming whether the clocks are synchronized include:

[0111] In response to receiving the seventh message sent by the master module, an eighth message is sent to the master module; wherein the eighth message carries the time value of the slave clock when the slave module receives the seventh message, and is used to enable the master module to confirm whether the master clock and the slave clock are synchronized based on the time value of the master clock when it sends the seventh message, the time value of the slave clock when the slave module receives the seventh message, and the transmission delay; or, the eighth message carries the time value of the slave clock when the slave module sends the eighth message, and is used to enable the master module to confirm whether the master clock and the slave clock are synchronized based on the time value of the master clock when it receives the eighth message, the time value of the slave clock when the slave module sends the eighth message, and the transmission delay.

[0112] It can be understood that, as shown in Figure 5, the first clock synchronization confirmation scheme is: when the master module sends the seventh message, it can record the time value T5 of the master clock when it sends the seventh message, and when the slave module receives the seventh message, it can record the time value T'5 of the slave clock when it receives the seventh message, and then return the time value T'5 of the slave clock when the slave module receives the seventh message to the master module through the eighth message. When the master module receives the eighth message, it confirms whether T'5 is equal to (T5+Td). If so, it means that the master clock and the slave clock are synchronized. Otherwise, it means that the master clock and the slave clock are not synchronized (that is, there is a clock deviation).

[0113] When there is a clock deviation in the slave module, the clock can be resynchronized according to the aforementioned steps S110 to S140. Alternatively, for the slave module with the error, the clock deviation between the master clock and the slave clock can be obtained based on the difference between T'5 and (T5+Td). Then, the master module can send a broadcast command through the bus to instruct the corresponding slave module to perform clock correction. The slave module will adjust the slave clock to be consistent with the master clock based on the clock deviation.

[0114] The second clock synchronization confirmation scheme is: the master module sends the seventh message, triggering the slave module to return the eighth message (which carries the time value T'6 of the slave clock when the slave module sends the eighth message). When the master module receives the eighth message, it records the time value T6 of the master clock when the master module receives the eighth message. When the master module receives the eighth message, it confirms whether T6 is equal to (T'6 + Td). If so, it means that the master clock and the slave clock are synchronized. Otherwise, it means that the master clock and the slave clock are not synchronized (that is, there is a clock deviation).

[0115] Similar to the first clock synchronization confirmation scheme, when there is a clock deviation in the slave module, the clock can be resynchronized according to the aforementioned steps S110 to S140. Alternatively, for the slave module with an error, the clock deviation between the master clock and the slave clock can be obtained based on the difference between T6 and (T'6+Td). Then, the master module can issue a broadcast command through the bus to instruct the corresponding slave module to perform clock correction. The slave module will adjust the slave clock to be consistent with the master clock based on the clock deviation.

[0116] In some embodiments, in response to receiving the seventh message sent by the main module, before sending the eighth message to the main module, the method further includes:

[0117] In response to receiving the ninth message sent by the main module, a second interrupt message is sent to the main module to trigger the main module to return the seventh message.

[0118] It can be understood that when the master module needs to read back the time value of the slave clock to confirm whether there is an error (clock deviation) in the time value of the slave clock, if the master module directly sends the seventh message to the slave module, it is possible that the slave module is not yet ready to be read and return the corresponding time value. Therefore, the preferred method is, as shown in Figure 6, that the master module first sends the ninth message to the slave module to inform the slave module that the master module is going to read data. After the slave module is ready, it informs the master module through an interrupt (second interrupt message), and the master module sends the seventh message after receiving it.

[0119] In some embodiments, in a scenario where the bus system includes at least two slave modules, the time interval between any two slave modules sending the second interrupt message is greater than a third preset duration.

[0120] It can be understood that the master module may send a ninth message to each slave module at the same time to confirm whether there is an error in the time value of the slave clock of each slave module. Setting the time interval between any two slave modules sending the second interrupt message to be greater than the third preset time length can avoid the master module receiving the second interrupt messages sent by two slave modules at the same time, resulting in information omission, and realizing that the master module only receives one second interrupt message at a time.

[0121] The third preset time length needs to be greater than the transmission delay corresponding to each slave module.

[0122] In some embodiments, the third preset duration may be 100 time units.

[0123] For example, in the bus system shown in Figure 3, the slave module 0 can be set to send a second interrupt message to the master module every 100 time units after receiving the ninth message, and then the master module sends a seventh message to read back the time value of the slave clock of the slave module 0 to confirm whether it is synchronized. Similarly, the slave module 1 is set to send a second interrupt message to the master module every 200 time units after receiving the ninth message, and then the master module sends the seventh message to read back the time value of the slave clock of the slave module 1. The slave module 2 is set to send a second interrupt message to the master module every 300 time units after receiving the ninth message, and then the master module sends the seventh message to read back the time value of the slave clock of the slave module 2.

[0124] In some embodiments, a third clock synchronization confirmation scheme is provided: the master module directly sends the time value of the master clock to the slave module, and the slave module determines whether the master clock and the slave clock are synchronized. Specifically, the steps of confirming whether the clocks are synchronized include:

[0125] Receive the tenth message sent by the master module, and confirm the time value of the slave clock when the slave module receives the tenth message; wherein the tenth message carries the time value of the master clock when the master module sends the tenth message;

[0126] Whether the master clock and the slave clock are synchronized is confirmed based on the time value of the slave clock when the slave module receives the tenth message, the time value of the master clock when the master module sends the tenth message, and the transmission delay.

[0127] It can be understood that, as shown in Figure 7, when the master module sends the tenth message, the tenth message carries the time value T7 of the master clock when the master module sends the tenth message. When the slave module receives the tenth message, it can record the time value T'7 of the slave clock when it receives the tenth message, and then confirm whether T'7 is equal to (T7+Td). If so, it means that the master clock and the slave clock are synchronized. Otherwise, it means that the master clock and the slave clock are not synchronized (that is, there is a clock deviation, and the clock deviation is equal to |(T7+Td)-T'7|).

[0128] When there is an error (clock deviation) in the slave module, the error (clock deviation) information can be returned to the master module via an interrupt message, and then the clock can be resynchronized according to the aforementioned steps S110 to S140. Alternatively, for the slave module with an error, the master module can issue a broadcast command via the bus to instruct the corresponding slave module to perform clock correction, and the slave module will adjust the slave clock to be consistent with the master clock based on the clock deviation.

[0129] Based on the same inventive concept, an embodiment of the present disclosure further provides a clock synchronization method, which is applied to a main module of a bus system, as shown in FIG8 , and includes:

[0130] Step S210: Sending a first message to the slave module to trigger the slave module to start timing and return a second message;

[0131] Step S220: After receiving the second message, a third message is sent to the slave module at an interval of the first preset time to trigger the slave module to stop timing, so that the slave module divides the difference between the current timing duration and the first preset duration by 2 to obtain the transmission delay between the master module and the slave module, and then synchronizes the clocks of the master module and the slave module according to the transmission delay.

[0132] In some embodiments, after step S220, the method further includes:

[0133] Step S230: receiving a fourth message sent by the slave module, where the fourth message is generated by the slave module according to the transmission delay and carries the transmission delay;

[0134] Step S240: Generate a fifth message based on the transmission delay carried by the fourth message; wherein the fifth message carries the second preset duration, and the sum of the second preset duration and the transmission delay is equal to a specified value;

[0135] Step S250: sending a fifth message to the slave module, so that the slave module restarts the slave clock of the slave module after a second preset time interval after receiving the fifth message sent by the master module;

[0136] The slave clock and the master clock are restarted at the same time.

[0137] In some embodiments, the bus system includes at least two slave modules, and the master module causes each slave module to restart a corresponding slave clock according to the above method, so that the slave clocks of each slave module are restarted simultaneously.

[0138] In some embodiments, in the above clock synchronization method, the bus system includes at least two slave modules, and the designated values ​​corresponding to the slave modules are the same;

[0139] The fifth messages corresponding to the various slave modules are sent simultaneously by the master module.

[0140] In some embodiments, in the clock synchronization method, before receiving the fourth message sent by the slave module, the method further includes:

[0141] In response to receiving the first interrupt message sent by the slave module, a sixth message is sent to the slave module to trigger the slave module to return a fourth message.

[0142] In some embodiments, in the clock synchronization method, the method further includes:

[0143] Sending a seventh message to the slave module to trigger the slave module to return an eighth message; wherein the eighth message carries the time value of the slave clock when the slave module receives the seventh message; confirming whether the master clock and the slave clock are synchronized based on the time value of the master clock when the master module sends the seventh message, the time value of the slave clock when the slave module receives the seventh message, and the transmission delay; or,

[0144] Send the seventh message to the slave module to trigger the slave module to return the eighth message; wherein the eighth message carries the time value of the slave clock when the slave module sends the eighth message; based on the time value of the master clock when the master module receives the eighth message, the time value of the slave clock when the slave module sends the eighth message, and the transmission delay, confirm whether the master clock and the slave clock are synchronized.

[0145] In some embodiments, in the clock synchronization method, before sending the seventh message to the slave module, the method further includes:

[0146] Sending a ninth message to the slave module to trigger the slave module to return a second interrupt message;

[0147] Send the seventh message to the slave module, including:

[0148] In response to receiving the second interrupt message sent by the slave module, a seventh message is sent to the slave module.

[0149] In some embodiments, in the above clock synchronization method, the bus system includes at least two slave modules, and the time interval between any two slave modules sending the second interrupt message is greater than a third preset time length.

[0150] In some embodiments, in the clock synchronization method, the method further includes:

[0151] A tenth message is sent to the slave module to trigger the slave module to confirm the time value of the slave clock when it receives the tenth message; wherein the tenth message carries the time value of the master clock when the master module sends the tenth message, so that the slave module confirms whether the master clock and the slave clock are synchronized based on the time value of the slave clock when it receives the tenth message, the time value of the master clock when the master module sends the tenth message, and the transmission delay.

[0152] The specific implementation process of the clock synchronization method applied to the master module can refer to the clock synchronization method applied to the slave module described in any of the above embodiments, and will not be repeated here.

[0153] Based on the same inventive concept, an embodiment of the present disclosure further provides a bus system, as shown in FIG3 , comprising a bus, a slave module, and a master module.

[0154] A slave module configured to implement the clock synchronization method applied to the slave module described in any one of the above embodiments;

[0155] The main module is configured to implement the clock synchronization method applied to the main module described in any of the above embodiments.

[0156] The bus system is a processing chip or a system-on-a-chip (SOC) chip that needs to implement read and write operations through the bus.

[0157] Based on the same inventive concept, an embodiment of the present disclosure further provides an electronic component, which includes the bus system described in any of the above embodiments.

[0158] In some usage scenarios, the product form of this electronic component is a graphics card; in other usage scenarios, the product form of this electronic component is a CPU motherboard.

[0159] Based on the same inventive concept, embodiments of the present disclosure further provide an electronic device comprising the aforementioned electronic components. In some usage scenarios, the electronic device is a portable electronic device, such as a smartphone, tablet computer, or VR device; in other usage scenarios, the electronic device is a personal computer, game console, or the like.

[0160] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0161] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A clock synchronization method, applied to a slave module of a bus system, comprising: In response to receiving a first message sent by a main module, sending a second message to the main module and starting timing; In response to receiving a third message sent by the main module, stopping the timing; wherein the third message is sent by the main module at a first preset time interval after receiving the second message; Divide the difference between the current timing duration and the first preset duration by 2 to obtain the transmission delay between the master module and the slave module; The master module and the slave module are clock synchronized according to the transmission delay.

2. The method according to claim 1, performing clock synchronization on the master module and the slave module according to the transmission delay, comprising: According to the transmission delay, sending a corresponding fourth message to the main module; wherein the fourth message carries the transmission delay; Receive a fifth message sent by the main module; wherein the fifth message is generated by the main module according to the transmission delay after receiving the fourth message, the fifth message carries a second preset duration, and the sum of the second preset duration and the transmission delay is equal to a specified value; Restarting the slave clock of the slave module at an interval of the second preset time after receiving the fifth message sent by the master module; The slave clock and the master clock of the master module are restarted simultaneously.

3. The method according to claim 2, wherein the bus system comprises at least two slave modules, and each slave module restarts the corresponding slave clock according to the method according to claim 2, so that the slave clocks of each slave module are restarted simultaneously.

4. The method according to claim 2, wherein the bus system comprises at least two slave modules, the designated value corresponding to each slave module is the same, and the fifth message corresponding to each slave module is sent simultaneously by the master module.

5. The method according to claim 2, before sending the corresponding fourth message to the main module according to the transmission delay, the method further comprises: Sending a first interrupt message to the main module to trigger the main module to return a sixth message; Sending a corresponding fourth message to the main module according to the transmission delay includes: In response to receiving the sixth message, a corresponding fourth message is sent to the main module according to the transmission delay.

6. The method according to claim 1, further comprising: In response to receiving the seventh message sent by the master module, an eighth message is sent to the master module; wherein the eighth message carries the time value of the slave clock when the slave module receives the seventh message, and is used to enable the master module to confirm whether the master clock and the slave clock are synchronized according to the time value of the master clock when it sends the seventh message, the time value of the slave clock when the slave module receives the seventh message, and the transmission delay; or, the eighth message carries the time value of the slave clock when the slave module sends the eighth message, and is used to enable the master module to confirm whether the master clock and the slave clock are synchronized according to the time value of the master clock when it receives the eighth message, the time value of the slave clock when the slave module sends the eighth message, and the transmission delay.

7. The method according to claim 6, in response to receiving the seventh message sent by the main module, before sending the eighth message to the main module, further comprises: In response to receiving the ninth message sent by the main module, a second interrupt message is sent to the main module to trigger the main module to return the seventh message.

8. The method according to claim 7, wherein the bus system comprises at least two slave modules, and the time interval between any two slave modules sending the second interrupt message is greater than a third preset time length.

9. The method according to claim 1, further comprising: Receive the tenth message sent by the master module, and confirm the time value of the slave clock when the slave module receives the tenth message; wherein the tenth message carries the time value of the master clock when the master module sends the tenth message; Whether the master clock and the slave clock are synchronized is confirmed based on the time value of the slave clock when the slave module receives the tenth message, the time value of the master clock when the master module sends the tenth message, and the transmission delay.

10. A clock synchronization method, applied to a main module of a bus system, comprising: Sending a first message to the slave module to trigger the slave module to start timing and return a second message; After receiving the second message, a third message is sent to the slave module at an interval of a first preset time to trigger the slave module to stop timing, so that the slave module divides the difference between the current timing duration and the first preset duration by 2 to obtain the transmission delay between the master module and the slave module, and then synchronizes the clocks of the master module and the slave module according to the transmission delay.

11. The method according to claim 10, further comprising: receiving a fourth message sent by the slave module, wherein the fourth message is generated by the slave module according to the transmission delay and carries the transmission delay; Generate a fifth message according to the transmission delay carried by the fourth message; wherein the fifth message carries a second preset duration, and the sum of the second preset duration and the transmission delay is equal to a specified value; Sending the fifth message to the slave module, so that the slave module restarts the slave clock of the slave module after receiving the fifth message sent by the master module for the second preset time period; The slave clock and the master clock of the master module are restarted simultaneously.

12. The method according to claim 11, wherein the bus system comprises at least two slave modules, and the master module causes each slave module to restart the corresponding slave clock according to the method according to claim 11, so that the slave clocks of each slave module are restarted simultaneously.

13. The method according to claim 11, wherein the bus system comprises at least two slave modules, and the designated values ​​corresponding to the respective slave modules are the same; The fifth messages corresponding to the various slave modules are sent simultaneously by the master module.

14. The method according to claim 11, before receiving the fourth message sent by the slave module, the method further comprises: In response to receiving the first interrupt message sent by the slave module, a sixth message is sent to the slave module to trigger the slave module to return the fourth message.

15. The method according to claim 10, further comprising: Sending a seventh message to the slave module to trigger the slave module to return an eighth message; wherein the eighth message carries the time value of the slave clock when the slave module receives the seventh message; confirming whether the master clock and the slave clock are synchronized according to the time value of the master clock when the master module sends the seventh message, the time value of the slave clock when the slave module receives the seventh message, and the transmission delay; or, Send a seventh message to the slave module to trigger the slave module to return an eighth message; wherein the eighth message carries the time value of the slave clock when the slave module sends the eighth message; based on the time value of the master clock when the master module receives the eighth message, the time value of the slave clock when the slave module sends the eighth message, and the transmission delay, confirm whether the master clock and the slave clock are synchronized.

16. The method according to claim 15, before sending the seventh message to the slave module, further comprising: Sending a ninth message to the slave module to trigger the slave module to return a second interrupt message; Sending a seventh message to the slave module includes: In response to receiving the second interrupt message sent by the slave module, a seventh message is sent to the slave module. 17 . The method according to claim 16 , wherein the bus system comprises at least two slave modules, and the time interval between any two slave modules sending the second interrupt message is greater than a third preset time length.

18. The method according to claim 10, further comprising: Sending a tenth message to the slave module to trigger the slave module to confirm the time value of the slave clock when it receives the tenth message; wherein the tenth message carries the time value of the master clock when the master module sends the tenth message, so that the slave module confirms whether the master clock and the slave clock are synchronized according to the time value of the slave clock when it receives the tenth message, the time value of the master clock when the master module sends the tenth message, and the transmission delay.

19. A bus system comprising: bus; A slave module, configured to implement the clock synchronization method according to any one of claims 1 to 9; A main module is configured to implement the clock synchronization method according to any one of claims 10 to 18.

20. An electronic assembly comprising the bus system according to claim 19.

21. An electronic device comprising the electronic component according to claim 20.

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