Chip test system and chip test method

Abstract

A chip test system and a chip test method. The chip test system comprises: a controller (100) and a pin electronics chip, wherein a driver pin, an active load pin and a comparator pin of the pin electronics chip are respectively connected to different pins of the controller (100); an output pin of the pin electronics chip is used for being connected to a tested pin of a tested chip (200); and a controller (100) is used for sending data of a system-level test (SLT) to the driver pin and the active load pin, and reading a result of the SLT from the comparator pin, the controller (100) is also used for sending data of a final test (FT) to the driver pin and the active load pin, and reading a result of the FT from the comparator pin, and the controller (100) is used for determining, by means of the result of the SLT and the result of the FT, whether the tested chip (200) is up to standard.

Description

Chip testing system and chip testing method

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on June 30, 2023, with application number 202310802611.7 and application name “A Chip Testing System and Chip Testing Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of chip testing, and in particular to a chip testing system and a chip testing method. Background Art

[0003] After chip packaging, testing is required. This typically involves final test (FT) and system-level test (SLT). These tests are used to screen out defective chips or to classify them. FT uses an automatic test equipment (ATE), while SLT uses a system-level motherboard as the testing platform.

[0004] FT test items include: interface function test and electrical performance test, among which the interface function test includes read and write test and communication test, etc.; the electrical performance test includes input and output high and low levels and open and short circuit tests.

[0005] SLT testing items include: interface function testing. SLT testing is closer to actual applications.

[0006] Currently, chip testing requires FT and SLT to be performed separately at two different test stations, and there are a large number of test stations.

[0007] Summary of the Invention

[0008] The embodiments of the present invention provide a chip testing system and a chip testing method, which can complete FT testing and SLT testing in one testing station, thereby reducing the number of testing stations.

[0009] In the first aspect, an embodiment of the present application provides a chip testing system, including: a controller and a pin electronic chip PE; the driver pins, active load pins and comparator pins of the pin electronic chip are respectively connected to different pins of the controller; the output pins of the pin electronic chip are used to connect to the tested pins of the tested chip; the controller is used to send system-level test SLT data to the driver pins and active load pins, and read the results of SLT from the comparator pins; the controller is also used to send final test FT data to the driver pins and active load pins, and read the results of FT from the comparator pins; the controller is used to determine whether the tested chip is qualified based on the results of SLT and FT.

[0010] The chip testing system provided in the embodiment of the present application includes a controller and a PE chip, which is closer to system applications. It does not need to occupy two different test stations and can complete FT testing and SLT testing on the chip under test at the same test station, thereby reducing the number of test stations and effectively reducing testing costs.

[0011] In one possible implementation, the communication bus pin of the pin electronic chip is connected to the communication bus pin of the controller; the controller is also used to send a control signal to the pin electronic chip through the communication bus pin before sending the test data. The control signal is used to set the parameters of the pin electronic chip so that the pin electronic chip cooperates with the test of the tested pin.

[0012] Since the same tested pin needs to be tested for multiple projects, the PE chip needs to be parameterized when testing different projects. Therefore, before the controller sends the test data, the controller is also used to send a control signal to the PE chip through the communication bus SPI pin. The control signal is used to set the parameters of the PE chip so that the pin electronic chip cooperates with the test of the tested pin.

[0013] The following introduces several specific test implementation methods.

[0014] In one possible implementation, the FT includes an open-circuit and short-circuit test; a controller is specifically configured to, when performing an open-circuit and short-circuit test on a pull-up diode of a tested pin, control a signal to set a driver pin of a pin electronic chip to a high level and an active load pin to a current sinking mode, so that an output pin of the pin electronic chip sinks current into the pull-up diode of the tested pin; and a comparator pin is configured to read a test result, and determine whether the pull-up diode of the tested pin is open or short-circuited based on the test result.

[0015] In a possible implementation, the controller is further configured to control a signal to set a reference voltage of a comparator of a pin electronic chip to be high level valid when performing an open circuit or short circuit test on a pull-up diode of a tested pin.

[0016] In one possible implementation, a controller is specifically configured to, when performing an open-circuit or short-circuit test on a pull-down diode of a tested pin, control a signal to set a driver pin of a pin electronic chip to a high level and an active load pin to a current-sourcing mode, so that an output pin of the pin electronic chip sources current from the pull-down diode of the tested pin; and read a test result from a comparator pin to determine whether the pull-down diode of the tested pin is open or short-circuited based on the test result.

[0017] In a possible implementation, the controller is further configured to control a signal to set a reference voltage of a comparator of a pin electronic chip to be active low when performing an open circuit or short circuit test on a pull-down diode of a tested pin.

[0018] In one possible implementation, SLT includes a serial communication test; a controller, specifically used to control a signal to set an active load pin to a current sinking mode when performing a serial communication test on the chip under test; write data to a driver pin, and read data from a comparator pin. When the read data is consistent with the written data, the serial communication test of the chip under test is successful.

[0019] The following describes a chip test system including at least three pin electronic chips as an example, where each pin electronic chip is used to test one pin of the chip under test, and three pin electronic chips correspond to three tested pins. The embodiment of the present application does not specifically limit the number of pin electronic chips included in the chip test system.

[0020] In one possible implementation, the chip under test includes IO pins to be tested and serial bus pins to be tested, and the serial bus pins to be tested include data line pins to be tested and clock line pins to be tested; the chip testing system includes at least three pin electronic chips: a first pin electronic chip, a second pin electronic chip, and a third pin electronic chip;

[0021] The controller includes a data line pin and a clock line pin; the data line pin and the clock line pin of the controller are respectively connected to the driver pin of the first pin electronic chip and the driver pin of the second pin electronic chip; the IO pin of the controller is connected to the driver pin of the third pin electronic chip;

[0022] The output pins of the first-pin electronic chip, the second-pin electronic chip and the third-pin electronic chip are respectively connected to the data line test pin, the clock line test pin and the IO test pin of the chip under test.

[0023] In one possible implementation, a chip under test includes N pins under test, and a chip testing system includes N pin electronic chips; output terminals of the N pin electronic chips are connected to the N pins under test in a one-to-one correspondence; driver pins, active load pins, and comparator pins of the N pin electronic chips are respectively connected to different pins of a controller; and N is an integer greater than or equal to 1. The embodiments of the present application do not specifically limit whether the chip testing system tests one chip under test or multiple chips under test simultaneously.

[0024] The following introduces a situation where a chip testing system can test multiple chips under test, that is, the chip testing system includes many pin electronic chips, one part of which is used to test the first chip under test, and the other part is used to test the second chip under test. It should be understood that three or more chips under test can also be tested at the same time.

[0025] In one possible implementation, a chip testing system includes an M-pin electronic chip, wherein N pin electronic chips among the M pin electronic chips are used to connect to a first chip under test, and MN pin electronic chips among the M pin electronic chips are used to connect to a second chip under test; the driver pins, active load pins, and comparator pins of the M pin electronic chips are respectively connected to different pins of a controller; N is an integer greater than or equal to 1, and M is an integer greater than N.

[0026] In one possible implementation, when N is greater than or equal to 2, the controller is specifically configured to send a low level to the driver pins of the pin electronics chip corresponding to the untested pins of the chip under test, thereby pulling down the levels of the untested pins of the chip under test. In other words, to avoid affecting the test results, the untested pins are disabled, i.e., inoperative.

[0027] One possible implementation further includes a host computer configured to send a test instruction to the controller, the test instruction including at least one of a system-level test instruction and a final test instruction. The host computer can trigger the start and end of the test and perform subsequent operations based on the test results.

[0028] In one possible implementation, the chip testing system includes multiple controllers; each of the multiple controllers is connected to a corresponding pin electronic chip; and a host computer is used to send test instructions to each of the multiple controllers. The embodiment of the present application does not limit the number of controllers, and can be set as needed, that is, the controller and the pin electronic chip can be one-to-one or one-to-many. The embodiment of the present application does not specifically limit the number of controllers included in the chip testing system. For example, if the controller is an SOC, it can include multiple SOCs and can complete the testing of multiple chips under test at the same time.

[0029] One possible implementation involves a system-on-chip (SOC) controller. The SOC includes communication and I / O interfaces, eliminating the need for SOC development and design. Instead, the SOC can directly implement electrical performance tests of the chip under test using software, simplifying chip test system development. For example, for SLT testing, the SOC can call interfaces using C language functions, making test implementation simple.

[0030] An embodiment of the present application also provides a chip testing method, including: sending SLT data to the driver pin and active load pin of a pin electronic chip; the output pin of the pin electronic chip is used to connect to the tested pin of the tested chip; reading the ST result from the comparator pin of the pin electronic chip; sending the final test FT data to the driver pin and active load pin, and reading the FT result from the comparator pin; judging whether the tested chip is qualified based on the ST result and the FT result.

[0031] A possible implementation method, before sending the test data, further includes: sending a control signal to the communication bus pin of the pin electronic chip, the control signal is used to set the parameters of the pin electronic chip so that the pin electronic chip cooperates with the test of the tested pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic diagram of a chip testing system provided in an embodiment of the present application;

[0033] FIG2 is a schematic diagram of another chip testing system provided in an embodiment of the present application;

[0034] FIG3 is a schematic diagram of another chip testing system provided in an embodiment of the present application;

[0035] FIG4 is a schematic diagram of another chip testing system provided in an embodiment of the present application;

[0036] FIG5 is a schematic diagram of another chip testing system provided in an embodiment of the present application;

[0037] FIG6 is a schematic diagram of an O / S test performed by a chip test system according to an embodiment of the present application;

[0038] FIG7 is a schematic diagram of another chip testing system for performing O / S testing according to an embodiment of the present application;

[0039] FIG8 is a flow chart of another chip testing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The embodiments of the present application do not specifically limit the specific type of chip under test. The technical solution provided by the embodiments of the present application can be applied to any chip under test that needs to be tested before leaving the factory. The items that need to be tested on the chip under test include at least one of the items of FT test and SLT test. The chip testing system provided by the embodiments of the present application can complete FT test and SLT test at one test station, without having to perform FT test and SLT test separately at two different test stations, thereby saving test stations.

[0041] In order to enable those skilled in the art to better understand and implement the technical solutions provided by the embodiments of the present application, relevant technical terms are first introduced below.

[0042] Pin electronics (PE) is a specialized chip with three functional modules: 1. Driver, which converts digital signals into outputs and adjusts the signal level to provide the appropriate signal level to the chip under test. 2. Comparator, which receives digital signal inputs, sets high and low levels, and obtains the input signal level of the chip under test. 3. Active load, which provides current sinking and sourcing capabilities, allowing current to be injected into or extracted from the pins of the chip under test.

[0043] The electrical performance test of FT test can include the following items: output high level (VOH, Voltage of Output High Level), output low level (VOL, Voltage of Output Low Level), input high level (VIH, Voltage of Input High Level), input low level (VIL, Voltage of Input Low Level), open circuit and short circuit (O / S, Opens / Shorts).

[0044] The chip testing system provided in the embodiment of the present application does not specifically limit the specific implementation form of the controller. The controller in the chip testing system provided in the embodiment of the present application is not limited to the system on chip (SOC), but can also be other processors such as MCU.

[0045] In the embodiments of the present application, a controller using a SOC is used as an example. Since the SOC can replace the traditional digital vector generator to complete the test, the digital vector generator does not have a mature interface protocol and needs to be developed and designed based on, for example, a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) so that the digital vector generator can test the chip under test. For example, the interface definition of the digital vector generator is completed according to the communication protocol of the chip under test. Therefore, when using the digital vector generator to complete the test of the chip under test, the development of the digital vector generator is relatively difficult. The chip test system provided in the embodiments of the present application can use the controller with a PE chip. For example, it can directly use the existing interfaces of the SOC, including the communication interface and the IO interface, without the need for the development and design of the SOC. The SOC can directly use software to implement the electrical performance test of the chip under test, which can reduce the development difficulty of the chip test system. For example, for SLT testing, the SOC can call the interface using C language functions, making the test implementation very simple.

[0046] SOC usually has functional modules such as conventional bidirectional two-wire serial bus (I2C, Inter-Integrated Circuit), Universal Asynchronous Receiver / Transmitter (UART), general-purpose input / output interface (GPIO, General-purpose input / output), Joint Test Action Group (JTAG), and serial peripheral interface (SPI).

[0047] I2C is a bidirectional, two-wire synchronous serial bus that transmits information between connected devices. It consists of two bidirectional I / O lines: SDA (serial data line) and SCL (serial clock line).

[0048] SPI is a high-speed full-duplex synchronous communication bus with four lines occupying four pins on the chip.

[0049] Both the I2C and SPI of SOC can be used directly when testing the chip under test without the need for development and design.

[0050] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the embodiments of the present application are further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0051] The chip testing system provided in the embodiment of the present application includes a controller and a PE chip, wherein the controller is directly connected to the pins of the PE chip, and the PE chip is connected to the chip under test, and the controller can control the PE chip to complete the FT test and SLT test of the chip under test.

[0052] See Figure 1, which is a schematic diagram of a chip testing system provided in an embodiment of the present application.

[0053] The chip testing system provided in the embodiment of the present application includes: a controller 100 and a pin electronic PE chip;

[0054] The communication bus pins of the PE chip are connected to the communication bus pins of the controller 100. In this embodiment, the communication bus is an SPI bus, that is, the SPI pins of the controller 100 are connected to the SPI pins of the PE chip. The SPI in Figure 1 is only schematic. In actual products, the SPI includes four wires, corresponding to four pins.

[0055] The driver pin D, active load pin I / O and comparator pin Hi / Lo of the pin electronic PE chip are respectively connected to different pins of the controller 100; that is, the D, I / O, Hi and Lo of the PE chip can be connected to four different pins of the controller 100. The embodiment of the present application does not specifically limit the types of the four different pins of the controller 100. For example, they can be pins with certain functions or ordinary IO pins. In Figure 1, the D of the PE chip is connected to the SCL pin of the controller, and I / O, Hi and Lo are respectively connected to the three GPIO pins of the controller 100 as an example. The SCL pin and GPIO pin can be used as both signal input pins and signal output pins.

[0056] For PE chips, D and I / O are signal input pins, and Hi and Lo are signal output pins.

[0057] The output pin of the pin electronic PE chip is used to connect to the tested pin of the tested chip 200; it should be understood that the tested chip 200 may include multiple tested pins. For the convenience of understanding and description, Figure 1 first takes one tested pin of the tested chip 200 as an example for introduction, wherein a GPIO pin of the tested chip 200 is used as the tested pin.

[0058] The controller 100 is also used to send SLT data to the driver pin D and the active load pin I / O, and read the SLT result from the comparator pins Hi and Lo; the controller 100 is also used to send final test FT data to the driver pin and the active load pin, and read the FT result from the comparator pin; and whether the chip under test 200 is qualified is determined by the SLT result and the FT result.

[0059] Since the same tested pin needs to be tested for multiple projects, the PE chip needs to be parameterized when testing different projects. Therefore, before the controller 100 sends the test data, the controller 100 is also used to send a control signal to the PE chip through the communication bus SPI pin. The control signal is used to set the parameters of the PE chip so that the pin electronic chip cooperates with the test of the tested pin.

[0060] It should be understood that when the PE chip is working, it is necessary to initialize the parameters so that the PE chip can complete certain functions when working. The controller 100 can complete the parameter setting of the PE chip through the SPI pin.

[0061] A schematic diagram of the PE chip can be seen in Figure 2. The following describes how the controller sets the parameters of the PE chip via SPI, in conjunction with Figure 2. The SPI pins of the PE chip are not shown in Figure 2. For example, the high level VIH and low level VIL of the driver are set, for example, setting the high level VIH of the driver to 3.3V and the low level VIL to 0V. The high level reference value VOH and low level reference value VOL of the comparator (including the Hi comparator and the Lo comparator) are set, and the operating mode of the active load Load is set to sink current or source current, etc. When the load is sinking current, the VOH and VOL of the comparator are different from when the load is sourcing current. For example, when the load is sinking current, VOH and VOL are set to 1.5V and 0.2V, respectively. When the load is sourcing current, VOH and VOL are set to -0.2V and -1.5V, respectively.

[0062] The controller 100 configures the PE chip through the SPI pins, controls the driver, active load and comparator of the PE chip to work together, and implements relevant parameter testing of the chip under test.

[0063] The communication method between SOC and PE is generally SPI interface, which depends on the interface of PE chip.

[0064] The chip test system provided in the embodiment of the present application can directly complete the SLT test, which is closer to the system application. The controller 100 can receive the test instructions sent by the host computer. In the embodiment of the present application, the host computer is a PC. The PC sends a test instruction to the controller 100. After receiving the control instruction, the controller 100 uses the PE chip to complete the test of the chip under test 200. The test items can complete the test of the FT item and the SLT item. The chip test system provided in the embodiment of the present application includes a controller and a PE chip. It does not need to occupy two different test stations. It can complete the FT test and SLT test of the chip under test at the same test station, thereby reducing the number of test stations and effectively reducing the test cost.

[0065] In addition, the PE chip also has a built-in pin precision measurement unit (PPMU, Per-pin Parameter Measurement Unit). Therefore, the PPMU of the PE chip can also be used to test the pin leakage current of the chip under test.

[0066] The embodiments of the present application do not specifically limit the number of chips under test that can be tested simultaneously by the chip testing system. Multiple chips under test can be tested simultaneously, or only one chip under test can be tested. This can be configured based on actual needs. It should be understood that when the number of chips under test is large, the number of PE chips can be increased. Generally, one PE chip can complete the test of one pin under test. If a chip under test has multiple pins under test that need to be tested, multiple PE chips can be configured. For example, if a chip under test has three pins under test, three PE chips are required.

[0067] The following first introduces the implementation method of the chip testing chip provided in the embodiment of the present application for testing multiple chips under test at the same time.

[0068] See FIG3 , which is a schematic diagram of another chip testing system provided in an embodiment of the present application.

[0069] The chip testing system provided in the embodiment of the present application comprises a chip under test including N pins under test, and the chip testing system comprises N pin electronic chips; the output ends of the N pin electronic chips are connected to the N pins under test in a one-to-one correspondence; the driver pins, active load pins and comparator pins of the N pin electronic chips are respectively connected to different pins of the controller; and N is an integer greater than or equal to 1.

[0070] The chip testing system provided in the embodiment of the present application also includes a host computer; the host computer is used to send test instructions to the control, and the test instructions include system-level test instructions and final test instructions.

[0071] The chip testing system provided in the embodiment of the present application may include multiple controllers, each of which can complete the test of a chip under test, or one controller can complete the test of multiple chips under test at the same time, which is not specifically limited in the embodiment of the present application. For ease of understanding, the following example takes the test of a chip under test completed by one controller as an example. The controller is an SOC as an example, that is, the chip testing system includes a host computer PC, a first controller SOC1 to an Nth controller SOCN, and also includes N PE chips corresponding to each controller, namely PE1, PE2 to PEN. Each chip under test corresponds to N PE chips PE1, PE2 to PEN. N is an integer greater than or equal to 2. In addition, it can also be understood that the number of tested pins of each chip under test can be different, and correspondingly, the number of PE chips corresponding to each controller can be different.

[0072] For example, the first chip under test 201 includes N test pins, each of which is connected to a corresponding PE. For example, the first chip under test 201 includes N test pins, each of which is connected to the output of PE1 and the output of PEN. SOC1 is used to test the first chip under test 201. Similarly, the N test pins of the Nth chip under test 20N are connected to the outputs of the corresponding N PEs, that is, the outputs of PE1 and PE2 are connected to the output of PEN. SOCN is used to test the Nth chip under test 20N.

[0073] The chip testing system provided in this embodiment includes multiple controllers; each of the multiple controllers is connected to multiple pin electronic chips; and a host computer is configured to send test instructions to each of the multiple controllers. It should be understood that each of SOC1 through SOCN can receive test instructions sent by the PC and test the corresponding chip under test according to the test instructions.

[0074] FIG3 is an example of one chip under test corresponding to one controller. The following describes the implementation method of one controller corresponding to multiple chips under test.

[0075] See FIG4 , which is a schematic diagram of another chip testing system provided in an embodiment of the present application.

[0076] The chip testing system provided in this embodiment is introduced by taking the example that the controller can simultaneously complete the test of two chips under test. It should be understood that a controller in the chip testing system provided in the embodiment of the present application can also simultaneously complete the test of more chips under test, such as three chips under test or five chips under test, etc.

[0077] Continuing with the example of a controller using an SOC, the SOC can receive test instructions sent by the PC. The SOC tests the N pins of the first chip under test 201 through PE1, PE2, and PEN. Generally, a chip under test includes multiple pins under test, so N is an integer greater than or equal to 2. Simultaneously, the SOC can also test the M pins of the second chip under test 202 through PEN+1, PEN+2, and PEN+M, where M is an integer greater than or equal to 2. M can be equal to N or different from N, meaning that the number of pins under test on the first chip under test 201 and the number of pins under test on the second chip under test 202 can be equal or different.

[0078] The following describes in detail the process of testing the tested pins of the tested chip with reference to the accompanying drawings.

[0079] See FIG5 , which is a schematic diagram of another chip testing system provided in an embodiment of the present application.

[0080] In the chip testing system provided in the embodiment of the present application, the chip under test 200 includes IO pins to be tested and serial bus pins to be tested, with I2C being an example of the serial bus. The serial bus pins to be tested include data line pins to be tested and clock line pins to be tested, with the data line SDA pin and the clock line SCL pin in Figure 5 being an example; the chip testing system includes at least three pin electronic chips: a first pin electronic chip PE1, a second pin electronic chip PE2, and a third pin electronic chip PE3. In the embodiment of the present application, the chip under test 200 including three test pins is used as an example for introduction, wherein the functional test takes the SDA pin and SCL pin of I2C communication as an example, and the electrical performance test takes the GPIO pin as an example. Each pin under test corresponds to a PE chip, and the three pins under test correspond to PE1, PE2, and PE3, respectively.

[0081] The data line pin and clock line pin of the controller are connected to the driver pin of the first pin electronic chip and the driver pin of the second pin electronic chip respectively; the IO pin of the controller is connected to the driver pin of the third pin electronic chip; that is, the SCL pin of the SOC is connected to the D of the PE1 chip, the SDA pin of the SOC is connected to the D of PE2, and a GPIO pin of the SOC is connected to the D of PE3.

[0082] The output pins of the first pin electronic chip PE1, the second pin electronic chip PE2 and the third pin electronic chip PE3 are respectively connected to the data line test pin (SDA), the clock line test pin (SCL) and the IO test pin (GPIO) of the chip under test 200.

[0083] The SPI pins of PE1, PE2, and PE3 are all connected to the SPI pins of the SOC.

[0084] The I / O, Hi, and Lo pins of PE1 are connected to different GPIO pins of the SOC respectively; the I / O, Hi, and Lo pins of PE2 are connected to different GPIO pins of the SOC respectively; the I / O, Hi, and Lo pins of PE3 are connected to different GPIO pins of the SOC respectively.

[0085] In the chip testing system provided by the embodiment of the present application, when N is greater than or equal to 2, the controller is specifically configured to send a low level to the driver pins of the pin electronic chip corresponding to the untested pins of the chip under test, thereby pulling down the levels of the untested pins of the chip under test. This is to prevent the levels of the untested pins from affecting the levels of the tested pins. For example, if the SOC first tests the SCL pin of the chip under test 200, the levels of the untested SDA pin and the GPIO pin of the chip under test 200 need to be pulled down. The SOC needs to send a low level to the D pins of PE2 and the D pins of PE3 corresponding to the untested SDA pin and GPIO pin of the chip under test 200. Specifically, the SOC's SDA sends a low level to the D pin of PE2, and the SOC's GPIO sends a low level to the D pin of PE3, thereby causing PE2 to output a low level, i.e., pulling down the SDA pin of the chip under test 200. Similarly, PE3 outputs a low level, pulling down the GPIO pin of the chip under test 200.

[0086] FT includes short-circuit and open-circuit tests. Because each pin under test includes both a pull-up diode and a pull-down diode, performing both O / S tests on the pull-up and pull-down diodes is necessary when performing both O / S tests. The O / S test eliminates the need for separate tests; it can detect short, open, or normal operation at once.

[0087] First, the controller performs an O / S test on the pull-up diode of the tested pin of the chip under test. It should be understood that each tested pin of the chip under test needs to undergo an O / S test, for example, the SDA, SCL, and GPIO pins shown in Figure 5 all need to undergo an O / S test.

[0088] See FIG6 , which is a schematic diagram of an O / S test performed by a chip testing system provided in an embodiment of the present application.

[0089] The chip under test 200 includes a pull-up diode D1 and a pull-down diode D2, wherein the anode of D1 is connected to the pin under test, the cathode of D1 is connected to the power supply VDD, the anode of D2 is grounded, and the cathode of D2 is connected to the pin under test.

[0090] The chip testing system provided in the embodiment of the present application, the controller (taking SOC as an example), is specifically used for performing an open-circuit and short-circuit O / S test on the pull-up diode D1 of the tested pin. The control signal is used to set the driver pin of the pin electronic PE chip to a high level and the active load pin to a current injection mode, as shown in Figure 6, so that the output pin of the pin electronic PE chip injects current into the pull-up diode D1 of the tested pin, for example, injecting 100uA current into the pin of the chip under test, 100uA is only an example; the arrow indicates the direction of current, which is injected into D1.

[0091] The SOC reads the test results from the comparator pins and uses them to determine whether the pull-up diode D1 on the tested pin is open or shorted. As shown in Figure 6, since D1's anode is connected to the tested pin, its open or short state directly affects the voltage level on the tested pin. Furthermore, the tested pin is connected to the Hi and Lo inputs of the two comparators. Therefore, the SOC can read the test results from the Hi and Lo outputs and determine whether pull-up diode D1 is functioning properly.

[0092] The controller (SOC) is also used to control signals to set the reference voltage of the comparator in the pin electronics PE chip to active high when performing an open / short circuit O / S test on the pull-up diode D1 of the tested pin. Specifically, the Hi reference voltage is 1.5V, and the Lo reference voltage is 0.2V. The SOC reads the signals at the Hi and Lo outputs of the PE comparator. A signal at the Hi output exceeding 1.5V is considered a high level, and a signal at the Lo output below 0.2V is considered a low level.

[0093] It should be understood that the SOC is controlled by the host computer before the O / S test, receives the test instructions from the host computer, and feeds back the test results to the host computer after the test is completed.

[0094] The following describes how the controller performs O / S testing on the pull-down diode of the tested pin of the tested chip.

[0095] Refer to FIG. 7 , which is a schematic diagram of another chip testing system performing O / S testing according to an embodiment of the present application.

[0096] The chip testing system provided in the embodiment of the present application, the controller (taking SOC as an example), is specifically used for performing an open-circuit and short-circuit O / S test on the pull-down diode D2 of the tested pin. The control signal is used to set the driver pin of the pin electronic chip to a high level and the active load pin to a current-pulling mode, as shown in Figure 7, so that the output pin of the pin electronic PE chip pulls current from the pull-down diode D2 of the tested pin; for example, 100uA current is pulled out to the pin of the chip under test, 100uA is only an example; the arrow indicates the direction of current, which is to pull current out from D2.

[0097] The SOC reads the test results from the comparator pin and uses them to determine whether the pull-down diode D2 of the tested pin is open or short-circuited. As shown in Figure 7, since D2's anode is connected to the tested pin, its open or short-circuit state directly affects the voltage level of the tested pin. Furthermore, the tested pin is connected to the Hi and Lo inputs of the two comparators. Therefore, the SOC can read the test results from the Hi and Lo outputs and determine whether the pull-down diode D2 is functioning properly.

[0098] The controller (SOC) is also used to control signals to set the reference voltage of the comparator in the pin electronics PE chip to active low when performing an open / short circuit O / S test on the pull-down diode D2 of the tested pin. Specifically, the reference voltage for Hi is -0.2V, and the reference voltage for Lo is -1.5V. The SOC reads the signals at the outputs of the Hi and Lo terminals of the PE comparator. A signal at the Hi output exceeding -0.2V is considered a high level, and a signal at the Lo output below -1.5V is considered a low level.

[0099] It should be understood that the SOC is controlled by the host computer before the O / S test, receives the test instructions from the host computer, and feeds back the test results to the host computer after the test is completed.

[0100] The above description takes the O / S test of any one tested pin of the chip under test as an example. The O / S test of other tested pins of the chip under test is performed in the same way and will not be repeated here.

[0101] The following describes how the chip testing system provided in an embodiment of the present application implements communication testing in SLT on the tested pins of the tested chip.

[0102] The controller is specifically used to control the active load pin to the current sinking mode when performing a serial communication test on the chip under test; write data to the driver pin and read data from the comparator pin. When the read data is consistent with the written data, the serial communication test of the chip under test is successful.

[0103] Specifically, the host computer sends a test instruction to the SOC, and the SOC performs a communication function test on the SCL pin and the SDA pin in the I2C of the chip under test.

[0104] The SOC can test both the SCL and SDA pins simultaneously, which requires controlling the PE's driver, active load, and comparator. The SOC sets the active load to current sink mode (simulating a pull-up resistor) and injects 10mA of current into the pin of the chip under test. 10mA is just an example here. The SOC sets the driver's VIH output high level to 3.3V and the VIL output low level to 0V. The SOC sets the comparator's Hi reference voltage to 2.4V (VOH) and the Lo reference voltage to 0.8V (VOL). The SOC sends an I2C write command to write the test data, which can be a specific value, into the internal register of the chip under test, specifically through the PE's driver.

[0105] The SOC sends an I2C read command to read data from the internal register of the chip under test, specifically through the Hi and Lo outputs of the PE comparator. The low level output of Lo must be lower than 0.8V, and the high level output of Hi must be higher than 2.4V to be considered correct. For example, if a high level 1 is written, when reading, the value read from Hi must be higher than 2.4V to be considered successful, otherwise it will fail. In addition, the read value cannot be between 0.8V and 2.4V. If it is between these two values, the chip under test is also considered to have failed the test. The SOC determines whether the data written to the chip under test is consistent with the data read out to determine whether the communication functions of the SCL and SDA pins are normal.

[0106] Moreover, after completing the communication function test of the chip under test, the SOC feeds back the test results to the host computer.

[0107] It should be understood that, to improve test efficiency, the chip testing systems provided in the embodiments of this application generally test multiple chips under test simultaneously. Parallel testing can effectively reduce the total test time and improve test efficiency. For example, the number of chips under test that can be tested simultaneously can be: 2, 4, 8, 16, 32, or 128. The above numbers are only examples, and the number of chips under test can be set according to actual needs.

[0108] Based on the chip testing system provided in the above embodiment, the embodiment of the present application further provides a chip testing method, which is described in detail below with reference to the accompanying drawings.

[0109] See FIG8 , which is a flow chart of a chip testing method provided in an embodiment of the present application.

[0110] The chip testing method provided in the embodiment of the present application includes:

[0111] S801: Sending SLT data to the driver pins and active load pins of the pin electronic chip; the output pins of the pin electronic chip are used to connect to the tested pins of the tested chip; reading the SLT result from the comparator pins of the pin electronic chip; sending FT data to the driver pins and active load pins of the pin electronic chip, and reading the FT result from the comparator pins of the pin electronic chip;

[0112] S802: Determine whether the chip under test is qualified based on the results of SLT and FT.

[0113] The chip testing method provided in the embodiments of the present application is applied to a chip testing system, which includes a controller and a PE chip. The controller is directly connected to the pins of the PE chip, which is connected to the chip under test. The controller can control the PE chip to perform FT testing and SLT testing on the chip under test.

[0114] Since the same tested pin needs to be tested for multiple projects, the PE chip needs to be parameterized when testing different projects. Therefore, before the controller sends the test data, the controller is also used to send a control signal to the PE chip through the communication bus SPI pin. The control signal is used to set the parameters of the PE chip so that the pin electronic chip cooperates with the test of the tested pin.

[0115] The controller in the embodiments of this application is described using a SOC as an example. Since an SOC can replace the digital vector generators in other controllers, such as FPGAs or ASICs, which are more difficult to develop, an SOC can use software to test the electrical performance of the chip under test, thus reducing the difficulty of developing chip test systems. For example, for SLT testing, the SOC can call interfaces using C language functions, simplifying development.

[0116] The above description is only a preferred embodiment of the present application and does not constitute any formal limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A chip testing system, characterized in that: include: Controller and pin electronics chips; The driver pins, active load pins and comparator pins of the pin electronic chip are respectively connected to different pins of the controller; The output pins of the pin electronic chip are used to connect to the tested pins of the tested chip; The controller is used to send data of a system level test SLT to the driver pin and the active load pin, and read the result of the SLT from the comparator pin; The controller is further used to send the final measured FT data to the driver pin and the active load pin, and read the FT result from the comparator pin; The controller is used to determine whether the tested chip is qualified according to the result of the SLT and the result of the FT.

2. The chip testing system according to claim 1, characterized in that: The communication bus pin of the pin electronic chip is connected to the communication bus pin of the controller; The controller is also used to send a control signal to the pin electronic chip through the communication bus pin before sending the test data, and the control signal is used to set the parameters of the pin electronic chip so that the pin electronic chip cooperates with the test of the tested pin.

3. The chip testing system according to claim 2, characterized in that: The FT includes an open circuit and short circuit test; the controller is specifically used to set the driver pin of the pin electronic chip to a high level and the active load pin to a current injection mode when performing an open circuit and short circuit test on the pull-up diode of the tested pin, so that the output pin of the pin electronic chip injects current into the pull-up diode of the tested pin; the test result is read from the comparator pin, and whether the pull-up diode of the tested pin is open or short-circuited is determined by the test result.

4. The chip testing system according to claim 3, characterized in that: The controller is also used for setting the reference voltage of the comparator of the pin electronic chip to be high level valid when the pull-up diode of the tested pin is subjected to an open circuit or short circuit test.

5. The chip testing system according to claim 2 or 3, characterized in that: The controller is specifically used for setting the driver pin of the pin electronic chip to a high level and the active load pin to a current-pulling mode when performing an open-circuit or short-circuit test on the pull-down diode of the tested pin. The control signal is used to set the driver pin of the pin electronic chip to a high level and the active load pin to a current-pulling mode so that the output pin of the pin electronic chip pulls current from the pull-down diode of the tested pin; and reading the test result from the comparator pin to determine whether the pull-down diode of the tested pin is open or short-circuited.

6. The chip testing system according to claim 5, characterized in that: The controller is also used for setting the reference voltage of the comparator of the pin electronic chip to be low level valid when the pull-down diode of the tested pin is subjected to an open circuit or short circuit test.

7. The chip testing system according to claim 2, characterized in that: The SLT includes a serial communication test; the controller is specifically used to set the active load pin to a current sinking mode when performing a serial communication test on the chip under test; write data to the driver pin, and read data from the comparator pin. When the read data is consistent with the written data, the serial communication test of the chip under test is successful.

8. The chip testing system according to claim 7, characterized in that: The chip under test includes IO pins to be tested and serial bus pins to be tested, and the serial bus pins to be tested include data line pins to be tested and clock line pins to be tested; the chip testing system includes at least three pin electronic chips: a first pin electronic chip, a second pin electronic chip and a third pin electronic chip; The controller comprises a data line pin and a clock line pin; the data line pin and the clock line pin of the controller are respectively connected to the driver pin of the first pin electronic chip and the driver pin of the second pin electronic chip; the IO pin of the controller is connected to the driver pin of the third pin electronic chip; The output pins of the first pin electronic chip, the output pins of the second pin electronic chip and the output pins of the third pin electronic chip are respectively connected to the data line test pin, the clock line test pin and the IO test pin of the chip under test.

9. The chip testing system according to any one of claims 1 to 8, characterized in that: The chip under test includes N tested pins, and the chip testing system includes N pin electronic chips; the output ends of the N pin electronic chips are connected to the N tested pins in a one-to-one correspondence; the driver pins, active load pins and comparator pins of the N pin electronic chips are respectively connected to different pins of the controller; N is an integer greater than or equal to 1.

10. A chip testing method, characterized in that: include: Sending SLT data to the driver pin and active load pin of the pin electronic chip; the output pin of the pin electronic chip is used to connect the tested pin of the tested chip; reading the ST result from the comparator pin of the pin electronic chip; Sending final measured FT data to the driver pin and the active load pin, and reading the FT result from the comparator pin; Whether the chip under test is qualified is judged based on the result of the ST and the result of the FT.

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