Sub-pixel structure, display panel and preparation method therefor, and display apparatus

Abstract

Disclosed in the present application are a sub-pixel structure, a display panel and a preparation method therefor, and a display apparatus. The sub-pixel structure comprises: a first sub-part, a second sub-part, a third sub-part, a fourth sub-part and a fifth sub-part, wherein the first sub-part and the second sub-part are arranged in a first direction; the third sub-part, the first sub-part and the fourth sub-part are arranged in sequence in a second direction; the second direction intersects with the first direction; in the first direction, the fifth sub-part and the fourth sub-part are arranged in parallel; in the second direction, the second sub-part and the fifth sub-part are arranged in parallel; and a storage capacitor is arranged in the first sub-part, and drive transistors and switch transistors are arranged in the other sub-parts. The present application optimizes the structure of a sub-pixel, and improves the performance of a display panel.

Description

Sub-pixel structure, display panel and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 26, 2023, with application number 202310771428.5, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, for example, to a sub-pixel structure, a display panel and a method for manufacturing the same, and a display device. Background Art

[0003] Display panels are widely used in all aspects of production and life, including computer monitors, mobile phones, tablets, wearable devices, robot displays, billboards, shopping mall floor indexes, public service terminals, and robotic arm teach pendants. Display panels are composed of thousands of sub-pixels, and the design of these sub-pixels plays a crucial role in determining the panel's high resolution, light transmittance, and leakage current. For example, the complex sub-pixel structure of display panels using self-luminous devices such as organic light-emitting diodes (OLEDs) results in suboptimal performance, and there is room for improvement in the sub-pixel design of related technologies.

[0004] Summary of the Invention

[0005] The present application provides a sub-pixel structure, a display panel and a method for manufacturing the same, and a display device, so as to optimize the structure of the sub-pixel and improve the performance of the display panel.

[0006] The embodiments of this application provide the following technical solutions:

[0007] A sub-pixel structure, comprising: a first sub-section, a second sub-section, a third sub-section, a fourth sub-section, and a fifth sub-section;

[0008] The first sub-section and the second sub-section are arranged along a first direction; the third sub-section, the first sub-section and the fourth sub-section are arranged in sequence along a second direction; the second direction intersects the first direction;

[0009] In the first direction, the fifth sub-section and the fourth sub-section are arranged side by side; in the second direction, the second sub-section and the fifth sub-section are arranged side by side;

[0010] Among them, a storage capacitor is provided in the first sub-section, a driving transistor and at least one switching transistor connected to the control end of the driving transistor are provided in the second sub-section, at least one switching transistor connected to the first electrode of the driving transistor is provided in the third sub-section, at least one switching transistor connected to the storage capacitor is provided in the fourth sub-section, and at least one switching transistor connected to the second electrode of the driving transistor is provided in the fifth sub-section.

[0011] Correspondingly, the present application also provides a display panel, comprising: a plurality of sub-pixel structures as described in any embodiment of the present application.

[0012] Correspondingly, the present application also provides a display device, comprising: a display panel as described in any embodiment of the present application.

[0013] Accordingly, the present application also provides a method for preparing a display panel, comprising:

[0014] The substrate is divided into a plurality of sub-pixel regions, and the sub-pixel regions are divided into a first sub-section, a second sub-section, a third sub-section, a fourth sub-section, and a fifth sub-section; the first sub-section and the second sub-section are arranged along a first direction; the third sub-section, the first sub-section, and the fourth sub-section are arranged in sequence along a second direction; the second direction intersects the first direction; the fifth sub-section and the fourth sub-section are arranged side by side in the first direction; and the second sub-section and the fifth sub-section are arranged side by side in the second direction;

[0015] A storage capacitor is formed in the first sub-section, a driving transistor and at least one switching transistor connected to the control end of the driving transistor are formed in the second sub-section, at least one switching transistor connected to the first electrode of the driving transistor is formed in the third sub-section, at least one switching transistor connected to the storage capacitor is formed in the fourth sub-section, and at least one switching transistor connected to the second electrode of the driving transistor is formed in the fifth sub-section.

[0016] The embodiment of the present application divides the sub-pixel into five sub-sections, and the devices in the five sub-sections are arranged according to the above-set rules, so that the layout of the sub-pixels is compact, which is conducive to reducing the layout space of the sub-pixels and is conducive to the high-density arrangement of the display panel. The storage capacitor is arranged in the first sub-section, and the driving transistor is arranged in the second sub-section, so that the connection between the storage capacitor and the driving transistor does not require a long wire, and thus can be closely connected. In addition, only a storage capacitor is arranged in the first sub-section, so that signal lines such as scanning lines and light-emitting control lines do not need to be arranged in the first sub-section, which can reduce the crosstalk generated by the signal lines to the storage capacitor. In summary, the embodiment of the present application optimizes the structure of the sub-pixel and improves the performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG1 is a schematic diagram of the structure of a sub-pixel provided in an embodiment of the present application;

[0018] FIG2 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0019] FIG3 is a schematic diagram of the structure of another sub-pixel provided in an embodiment of the present application;

[0020] FIG4 is a schematic diagram of the structure of another sub-pixel provided in an embodiment of the present application;

[0021] FIG5 is a schematic diagram of the cross-sectional structure along AA in FIG3 ;

[0022] FIG6 is an enlarged structural diagram of a first sub-unit and a second sub-unit provided in an embodiment of the present application;

[0023] FIG7 is a schematic cross-sectional view of the structure along line BB in FIG6 ;

[0024] FIG8 is a schematic diagram of an equivalent circuit of the driving transistor in FIG6 ;

[0025] FIG9 is an enlarged structural diagram of another first sub-section and a second sub-section provided in an embodiment of the present application;

[0026] FIG10 is a schematic cross-sectional view of the structure along CC in FIG9 ;

[0027] FIG11 is a schematic diagram of an equivalent circuit of the driving transistor in FIG9 ;

[0028] FIG12 is a schematic diagram of the structure of another sub-pixel provided in an embodiment of the present application;

[0029] FIG13 is a cross-sectional schematic diagram of another sub-pixel structure provided in an embodiment of the present application;

[0030] FIG14 is a schematic diagram of a patterned structure of a semiconductor layer provided in an embodiment of the present application;

[0031] FIG15 is a schematic diagram of a patterned structure of a first conductive line layer provided in an embodiment of the present application;

[0032] FIG16 is a schematic diagram of a patterned structure of a second conductive line layer provided in an embodiment of the present application;

[0033] FIG17 is a schematic diagram of a patterned structure of a gate layer provided in an embodiment of the present application;

[0034] FIG18 is a schematic diagram of a patterned structure of a third conductive line layer provided in an embodiment of the present application;

[0035] FIG19 is a schematic diagram of a patterned structure of a first type of via and a second type of via provided in an embodiment of the present application;

[0036] FIG20 is a schematic diagram of a patterned structure of a third type of via and a fourth type of via provided in an embodiment of the present application;

[0037] FIG21 is a schematic diagram of a patterned structure of a fourth conductive line layer provided in an embodiment of the present application;

[0038] FIG22 is a schematic diagram of a patterned structure of a fifth type of via provided in an embodiment of the present application;

[0039] FIG23 is a schematic diagram of a patterned structure of a sixth type of via provided in an embodiment of the present application;

[0040] FIG24 is a schematic cross-sectional view of another sub-pixel structure provided in an embodiment of the present application;

[0041] FIG25 is a schematic diagram of a patterned structure of another semiconductor layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] The present application provides a sub-pixel structure, wherein the sub-pixel provided by the present application redivides its layout area. FIG1 is a schematic diagram of the structure of a sub-pixel provided by the present application. Referring to FIG1 , the sub-pixel structure 10 includes: a first sub-section 11, a second sub-section 12, a third sub-section 13, a fourth sub-section 14, and a fifth sub-section 15.

[0044] With the first subsection 11 as a reference, the first direction X and the second direction Y intersect. For example, the first direction X and the second direction Y are perpendicular. The first subsection 11 and the second subsection 12 are arranged along the first direction X. The third subsection 13, the first subsection 11, and the fourth subsection 14 are arranged in sequence along the second direction Y. In the first direction X, the fifth subsection 15 and the fourth subsection 14 are arranged side by side. In the second direction Y, the second subsection 12 and the fifth subsection 15 are arranged side by side.

[0045] The sub-pixels are composed of pixel circuits, which are composed of devices such as storage capacitors, drive transistors, and switching transistors. The first sub-section 11 includes a storage capacitor, the second sub-section 12 includes a drive transistor and at least one switching transistor connected to the control terminal of the drive transistor, the third sub-section 13 includes at least one switching transistor connected to the first terminal of the drive transistor, the fourth sub-section 14 includes at least one switching transistor connected to the storage capacitor, and the fifth sub-section 15 includes at least one switching transistor connected to the second terminal of the drive transistor.

[0046] The embodiment of the present application divides the sub-pixel into five sub-sections, and the devices in the five sub-sections are arranged according to the above-set rules, so that the layout of the sub-pixels is compact, which is beneficial to reducing the layout space of the sub-pixels and is beneficial to the high-density arrangement of the display panel. The storage capacitor is arranged in the first sub-section 11, and the driving transistor is arranged in the second sub-section 12, so that the connection between the storage capacitor and the driving transistor does not require a long wire, and thus can be tightly connected. In addition, only a storage capacitor is arranged in the first sub-section 11, so that signal lines such as scanning lines and light-emitting control lines do not need to be arranged in the first sub-section 11, which can reduce the crosstalk generated by the signal lines on the storage capacitor; signal lines such as scanning lines and light-emitting control lines do not need to be arranged in the second sub-section 12, which can reduce the crosstalk generated by the signal lines on the driving transistor DT. In summary, the embodiment of the present application optimizes the sub-pixel structure 10 and improves the performance of the display panel.

[0047] Based on the above embodiments, the sub-pixel structure is arranged in different ways according to different types of pixel circuits, which are described in detail below but are not intended to limit the present application.

[0048] FIG2 is a schematic diagram of a pixel circuit according to an embodiment of the present application. Referring to FIG2 , in one embodiment of the present application, the pixel circuit includes, for example, six transistors and a storage capacitor Cst. The connection relationship between the multiple transistors and the storage capacitor Cst is as follows:

[0049] The driving transistor DT is configured to generate a driving current in response to a data signal. Since the driving transistor DT needs to generate the driving current, the size of the driving transistor DT is larger than that of other transistors.

[0050] A first switching transistor T1 has a gate electrically connected to a first scan line S1, a first electrode electrically connected to the gate of a driving transistor DT, and a second electrode electrically connected to the second electrode of the driving transistor DT. The first switching transistor T1 is configured to transmit a data signal from the second electrode of the driving transistor DT to the gate during a data write phase to achieve a threshold compensation function for the driving transistor. Therefore, the first switching transistor T1 can be referred to as a compensation transistor.

[0051] A second switching transistor T2 has a gate electrically connected to the second scan line S2, a first electrode electrically connected to the data line Vdata, and a second electrode electrically connected to the first electrode of the drive transistor DT. The second switching transistor T2 is used to transmit a data signal and write the data signal to the first electrode of the drive transistor DT. Therefore, the second switching transistor T2 can be referred to as a data write transistor.

[0052] A third switching transistor T3 has a gate electrically connected to the first light emission control line EM1, a first electrode electrically connected to the first electrode of the driving transistor DT, and a second electrode electrically connected to the storage capacitor Cst. The second electrode of the third switching transistor T3 is also used to connect to the light emitting device OLED. The third switching transistor T3 acts as a transistor between the driving transistor DT and the light emitting device OLED. The light emitting device OLED can only emit light when the third switching transistor T3 is turned on. Therefore, the third switching transistor T3 can be called a light emission control transistor.

[0053] The fourth switch transistor T4 has a gate electrically connected to the first scan line S1, a first electrode electrically connected to the reference voltage line Vref, and a second electrode electrically connected to the second electrode of the third switch transistor T3. The second electrode of the fourth switch transistor T4 is also used to connect the light-emitting device OLED and the storage capacitor Cst. The fourth switch transistor T4 can transmit a reference voltage signal to the light-emitting device OLED and the storage capacitor Cst, thereby initializing the light-emitting device OLED and the storage capacitor Cst. Therefore, the fourth switch transistor T4 can be called a reset transistor.

[0054] The fifth switch transistor T5 has a gate electrically connected to the second light-emitting control line EM2, a first electrode electrically connected to the power supply line VDD, and a second electrode electrically connected to the second electrode of the drive transistor DT. On the one hand, the fifth switch transistor T5 functions similarly to the third switch transistor T3. During the light-emitting phase, the light-emitting device OLED can only emit light when both the third switch transistor T3 and the fifth switch transistor T5 are turned on. Therefore, the fifth switch transistor T5 can also be referred to as a light-emitting control transistor. On the other hand, during the initialization phase, when the fifth switch transistor T5, the first switch transistor T1, and the fourth switch transistor T4 are all turned on, the storage capacitor Cst can be initialized.

[0055] Based on the structure of the above-mentioned pixel circuit, the embodiment of the present application further provides a specific sub-pixel structure, which is described below but is not intended to limit the present application.

[0056] Figure 3 is a schematic diagram of the structure of another subpixel provided in an embodiment of the present application. In conjunction with Figures 2 and 3, in one embodiment of the present application, a storage capacitor Cst is provided within the first subsection 11; a drive transistor DT and a first switch transistor T1 are provided within the second subsection 12; a second switch transistor T2 and a third switch transistor T3 are provided within the third subsection 13; a fourth switch transistor T4 is provided within the fourth subsection 14; and a fifth switch transistor T5 is provided within the fifth subsection 15. This arrangement in the embodiment of the present application reduces the length of the connecting wires between the transistors, thereby facilitating a compact arrangement of the subpixels.

[0057] In conjunction with Figures 2 and 3 , in one embodiment of the present application, illustratively, the second scan line S2, the first emission control line EM1, the first scan line S1, and the second emission control line EM2 all extend along the first direction X. The second scan line S2 and the first emission control line EM1 are connected to the third subsection 13, the first scan line S1 is connected to the fourth subsection 14, and the second emission control line EM2 is connected to the fifth subsection 15. This arrangement facilitates the second scan line S2 providing the second scan signal to the second switching transistor T2, facilitates the first emission control line EM1 providing the first emission control signal to the third switching transistor T3, facilitates the first scan line S1 providing the first scan signal to the fourth switching transistor T4 and the first switching transistor T1, and facilitates the second emission control line EM2 providing the second emission control signal to the fifth switching transistor T5.

[0058] In conjunction with Figures 2 and 3 , illustratively, in the second direction Y, the second scan line S2, the first emission control line EM1, the first scan line S1, and the second emission control line EM2 are arranged in sequence. In Figure 3 , illustratively, the second scan line S2 is located above the first emission control line EM1, which facilitates positioning the second switch transistor T2 above the third switch transistor T3, thereby facilitating direct connection of the third switch transistor T3 to the storage capacitor Cst. Similarly, the first scan line S1 is located above the second emission control line EM2, which facilitates positioning the fourth switch transistor T4 above the fifth switch transistor T5, thereby facilitating direct connection of the fourth switch transistor T4 to the storage capacitor Cst.

[0059] It should be noted that, in other embodiments, the second scan line S2 may be arranged below the first light emitting control line EM1, or the first scan line S1 may be arranged below the second light emitting control line EM2, which is not limited in this application.

[0060] In conjunction with Figures 2 and 3 , in one embodiment of the present application, illustratively, both the data line Vdata and the power line VDD extend along the second direction Y. The data line Vdata is connected to the third subsection 13, the first subsection 11, and the fourth subsection 14, while the power line VDD is connected to the second subsection 12 and the fifth subsection 15. The third subsection 13 houses a second switching transistor T2. Connecting the data line Vdata to the third subsection 13 facilitates providing a data signal to the second switching transistor T2. Furthermore, since the data line Vdata is a common signal line along the second direction Y, it also needs to be connected to the first subsection 11 and the fourth subsection 14. Similarly, the fifth subsection 15 houses a fifth switching transistor T5. Connecting the power line VDD to the fifth subsection 15 facilitates providing a power signal to the fifth switching transistor T5. Furthermore, since the power line VDD is a common signal line along the second direction Y, it also needs to be connected to the second subsection 12.

[0061] 2 and 3 , in another embodiment of the present application, the reference voltage line Vref illustratively extends along the first direction X and is connected to the fourth sub-section 14. This configuration facilitates the reference voltage line Vref providing a reference voltage signal to the fourth switching transistor T4 located in the fourth sub-section 14.

[0062] FIG4 is a schematic diagram of another sub-pixel structure provided in an embodiment of the present application. Referring to FIG4 , in another embodiment of the present application, the sub-pixel structure 10 illustratively further includes an auxiliary power line VDD1, which extends along a first direction X. The auxiliary power line VDD1 and the power line VDD form a mesh power line. This arrangement in the embodiment of the present application increases the area of ​​the power line VDD, thereby reducing the impedance of the power line VDD and improving the uniformity of the power signal provided by the display panel.

[0063] 2 and 4 , illustratively, the auxiliary power line VDD1 is connected to the fourth sub-section 14 and the fifth sub-section 15. Exemplarily, the auxiliary power line VDD1 is located below the second light emitting control line EM2. This arrangement is conducive to further optimizing the pixel space.

[0064] Continuing with FIG. 4 , based on the above embodiment, the subpixel structure 10 illustratively further includes an auxiliary reference voltage line Vref1. The auxiliary reference voltage line Vref1 extends along the second direction Y. The auxiliary reference voltage line Vref1 and the reference voltage line Vref form a mesh of reference voltage lines. The auxiliary reference voltage line Vref1 illustratively connects to the third sub-section 13, the second sub-section 12, the fifth sub-section 15, and the fourth sub-section 14 to minimize the increase in the spatial size of the subpixel structure 10.

[0065] 2 , based on the above embodiment, illustratively, the power line VDD is a first power line, and the sub-pixel structure further includes a second power line VSS, which is laid in an entire layer.

[0066] In the above embodiment, the subdivision of the transistor and the storage capacitor Cst is described. The film layer arrangement thereof is described below, but this does not limit the present application.

[0067] FIG5 is a schematic cross-sectional view taken along line AA in FIG3 . In conjunction with FIG3 and FIG5 , in one embodiment of the present application, the subpixel structure 10 exemplarily comprises a stacked film structure comprising: a first conductive layer 111, a second conductive layer 112, a semiconductor layer 113, a gate layer 114, and a third conductive layer 115. The two plates of the storage capacitor Cst are disposed on the first conductive layer 111 and the second conductive layer 112, respectively. The active layer, first and second terminals of the driver transistor DT (not shown in FIG5 ), as well as the active layer, first and second terminals of the switching transistors (the second switching transistor T2, the third switching transistor T3, and the first switching transistor T1 are shown in FIG5 ), are disposed on the semiconductor layer 113. The first and second terminals of the driver transistor DT and the first and second terminals of the switching transistors (including the first switching transistor T1 through the fifth switching transistor T5) are conductors formed by heavily doping the semiconductor layer 113. The gate of the driver transistor DT and the gates of the switching transistors (including the first switching transistor T1 through the fifth switching transistor T5) are both disposed on the gate layer 114. The connection jumpers between different film layers are provided in the third conductive layer 115. For example, the connection jumper between the second terminal of the driving transistor DT and the second switching transistor T2 is provided in the third conductive layer 115, the connection jumper between the gate of the driving transistor DT and the first switching transistor T1 is provided in the third conductive layer 115, and the connection jumper between the first switching transistor T1 and the fifth switching transistor T5 is provided in the third conductive layer 115.

[0068] 5 , based on the above embodiment, the third conductive layer 115 is illustratively electrically connected to different film layers through vias. Depending on the depth of the vias, the vias can be divided into first-class vias, second-class vias, third-class vias, and fourth-class vias.

[0069] Exemplarily, the third wire layer 115 is connected to the first wire layer 111 via a first type of via 121. For example, the third wire layer 115 is connected to the lower plate of the capacitor via the first type of via 121. The third wire layer 115 is connected to the second wire layer 112 via a second type of via 122. For example, the third wire layer 115 is connected to the upper plate of the capacitor via the second type of via 122.

[0070] The third wire layer 115 is connected to the semiconductor layer 113 via a third type of via 123. For example, the third wire layer 115 is connected to the first terminal (or second terminal) of the transistor via the third type of via 123. The third wire layer 115 is connected to the gate layer 114 via a fourth type of via (not shown in FIG. 5 ). For example, the third wire layer 115 is connected to the gate of the driving transistor DT via the fourth type of via.

[0071] Among them, the first and second types of via holes are etched at a deeper depth, both of which are deep holes; the third and fourth types of via holes are etched at a shallower depth, both of which are shallow holes.

[0072] Exemplarily, both deep and shallow holes are prepared before the third conductive layer is formed, and the deep and shallow holes are prepared using two separate processes. For example, one mask is used to create the deep holes first, followed by another mask to create the shallow holes. This arrangement in the present embodiment avoids using the same process for both deep and shallow holes, resulting in the shallow holes having larger openings and occupying pixel space.

[0073] Continuing with Figures 3-5 , based on the above embodiments, the driving transistor DT and the switching transistor are illustratively N-type transistors, whose semiconductor materials use metal oxides (e.g., indium gallium zinc oxide, IGZO). Compared with other materials, the use of IGZO as a semiconductor material gives the transistors the advantage of low leakage current, and the transistors can adopt a single-gate transistor structure, which further helps to reduce pixel space and increase the pixel density of the display panel.

[0074] In other embodiments, both the driving transistor DT and the switching transistor are P-type transistors, whose semiconductor material is low-temperature polysilicon (P-Si). To reduce leakage current, the switching transistor can be configured as a horizontal dual-gate structure. The horizontal dual-gate structure is equivalent to two transistors connected in series, which can reduce leakage current.

[0075] FIG6 is an enlarged structural diagram of a first sub-section and a second sub-section provided in an embodiment of the present application, FIG7 is a cross-sectional structural diagram along line BB in FIG6 , and FIG8 is an equivalent circuit diagram of the driving transistor in FIG6 . Referring to FIG6-FIG8 , in one embodiment of the present application, illustratively, the driving transistor DT includes a top gate TG and a bottom gate BG, the bottom gate BG of the driving transistor DT is disposed on the second conductive layer 112, and the top gate TG of the driving transistor DT is disposed on the gate layer 114. The embodiment of the present application utilizes the second conductive layer 112 to set the bottom gate BG of the driving transistor DT, so that the driving transistor DT forms a vertical dual-gate structure. One of the top gate TG and the bottom gate BG serves as a control gate, and the other serves as a gate for adjusting the threshold voltage, which is conducive to providing a more precise control strategy for the driving transistor DT.

[0076] Continuing to refer to Figures 6 to 8, illustratively, the top gate TG of the driving transistor DT is a control gate, and the bottom gate BG of the driving transistor DT is connected to the source S of the driving transistor DT. This arrangement allows the top gate TG to receive a data signal and provide a corresponding driving current under the action of the data signal. Among them, the source S and drain D of the driving transistor DT are symmetrically arranged. In a specific circuit, the end with a lower voltage is used as the source S, and the end with a higher voltage is used as the drain D. In the embodiment of the present application, the first electrode of the driving transistor DT is connected to the second switching transistor T2, and the voltage is lower, which is the source S. Therefore, the bottom gate BG is connected to the source S (i.e., the second switching transistor T2).

[0077] FIG9 is an enlarged structural diagram of another first sub-section and a second sub-section provided in an embodiment of the present application, FIG10 is a cross-sectional structural diagram along CC in FIG9 , and FIG11 is an equivalent circuit diagram of the driving transistor in FIG9 . Referring to FIG9-FIG11 , in another embodiment of the present application, illustratively, the bottom gate BG of the driving transistor DT is a control gate, and the top gate TG of the driving transistor DT is connected to the source S of the driving transistor DT. This arrangement enables the bottom gate BG to receive a data signal and provide a corresponding driving current under the action of the data signal. In an embodiment of the present application, the first electrode of the driving transistor DT is connected to the second switching transistor T2, and the voltage is relatively low, which is the source S. Therefore, the top gate TG is connected to the source S (i.e., the second switching transistor T2).

[0078] Figure 12 is a schematic diagram of the structure of another sub-pixel provided in an embodiment of the present application, and Figure 13 is a schematic cross-sectional diagram of another sub-pixel structure provided in an embodiment of the present application. Referring to Figures 12 and 13, based on the above embodiments, the sub-pixel structure 10 exemplarily further includes a fourth conductive layer 116, which is located on a side of the third conductive layer 115 away from the first conductive layer 111. The fourth conductive layer 116 includes a second auxiliary power line VDD2 and an auxiliary reference voltage line Vref1. The power line VDD, the auxiliary power line VDD1, and the second auxiliary power line VDD2 form a composite mesh of power lines. Exemplarily, the second auxiliary power line VDD2 overlaps the power line VDD. The reference voltage line Vref and the auxiliary reference voltage line Vref1 form a mesh of reference voltage lines. This arrangement in the embodiment of the present application further enhances the uniformity of the power signal and reference voltage signal in the display panel.

[0079] 13 , based on the above embodiment, the sub-pixel structure 10 further includes an anode layer 117, which is located on a side of the fourth wire layer 116 away from the first wire layer 111. The anode layer 117 includes an anode of the light-emitting device.

[0080] Continuing to refer to FIG13 , based on the above embodiment, illustratively, a film layer such as a buffer layer is further provided at the bottom of the first conductive layer 11, and an insulating layer is further provided between the conductive layers. illustratively, the bottom layer is a substrate 131, and the substrate 131 can be, for example, an inorganic film layer such as glass. The first buffer layer 132 is located on the substrate 131, and the first buffer layer 132 can be, for example, an organic material such as polyimide. The second buffer layer 133 is located on the side of the first buffer layer 132 away from the substrate 131, and the second buffer layer 133 can be, for example, an inorganic material such as silicon oxide or silicon nitride. The third buffer layer 134 is located on the side of the second buffer layer 133 away from the substrate 131, and the third buffer layer 134 can be, for example, an organic material such as polyimide. The fourth buffer layer 135 is located on the side of the third buffer layer 134 away from the substrate 131, and the fourth buffer layer 135 can be, for example, an inorganic material such as silicon oxide or silicon nitride. The fifth buffer layer 136 is located on the side of the fourth buffer layer 135 away from the substrate 131. The material of the fifth buffer layer 136 may be, for example, an inorganic material such as aluminum nitride or gallium nitride. The sixth buffer layer 137 is located on the side of the fifth buffer layer 136 away from the substrate 131. The sixth buffer layer 137 may be, for example, an inorganic material such as silicon oxide or silicon nitride. The first insulating layer 141 is located between the first conductive layer 111 and the second conductive layer 112. The first insulating layer 141 may be, for example, an inorganic material such as silicon oxide or silicon nitride. The second insulating layer 142 is located between the second conductive layer 112 and the semiconductor layer 113. The second insulating layer 142 may be, for example, an inorganic material such as silicon oxide or silicon nitride. The third insulating layer 143 is located between the semiconductor layer 113 and the gate layer 114. The third insulating layer 143 may be, for example, an inorganic material such as silicon oxide or silicon nitride. The fourth insulating layer 144 is located between the gate layer 114 and the third conductive layer 115. The fourth insulating layer 144 may be, for example, an inorganic material such as silicon oxide or silicon nitride. A fifth insulating layer 145 is located between the third conductive layer 115 and the fourth conductive layer 116. Fifth insulating layer 145 may be formed of an organic material such as photoresist. A sixth insulating layer 146 is located between the fourth conductive layer 116 and the anode layer 117. Sixth insulating layer 146 may be formed of an organic material such as photoresist. A pixel definition layer 147 is located on the side of the anode layer 117 away from the substrate 131. Pixel definition layer 147 may be formed of an organic material such as photoresist.

[0081] Based on the above embodiments, the embodiments of the present application further illustrate the patterned structure of the film layer, but are not intended to limit the present application.

[0082] FIG14 is a schematic diagram of a patterned structure of a semiconductor layer provided in an embodiment of the present application. Referring to FIG12 and FIG14 , in one embodiment of the present application, illustratively, the semiconductor layer 113 includes:

[0083] The first semiconductor structure 1131 extends along the second direction Y and connects to the third subsection 13, the first subsection 11, and the fourth subsection 14. The first semiconductor structure 1131 is used to form the active layer of the second switching transistor T2, the third switching transistor T3, and the fourth switching transistor T4. After being heavily doped, the first semiconductor structure 1131 is formed into a conductor, thereby forming the source and drain of the second switching transistor T2, the third switching transistor T3, and the fourth switching transistor T4. Exemplarily, the first electrode (source or drain) of the second switch transistor T2 is connected to the data line through a via, the second electrode (drain or source) of the second switch transistor T2 is connected to the first electrode (source or drain) of the third switch transistor T3 through a heavily doped first semiconductor structure 1131, the second electrode of the second switch transistor T2 is also electrically connected to the first electrode (source or drain) of the drive transistor DT through a connecting wire, and the second electrode (drain or source) of the third switch transistor T3 is connected to the second electrode (drain or source) of the fourth switch transistor T4 through the heavily doped first semiconductor structure 1131. The first electrode (source or drain) of the fourth switch transistor T4 is connected to the reference voltage line Vref through a via.

[0084] The second semiconductor structure 1132 is located in the second sub-section 12 and has an inverted G-shape. The long side of the second semiconductor structure 1132 is in the second direction Y. The second semiconductor structure 1132 is used to form the active layer of the driving transistor DT and the first switching transistor T1. After the second semiconductor structure 1132 is heavily doped, a conductor is formed to form the source and drain of the driving transistor DT and the first switching transistor T1. Exemplarily, the first electrode (source or drain) of the driving transistor DT is connected to the second electrode (drain or source) of the second switching transistor T2 via a connecting wire, the second electrode (drain or source) of the driving transistor DT is connected to the second electrode (drain or source) of the first switching transistor T1 via the heavily doped second semiconductor structure 1132, and the first electrode (source or drain) of the first switching transistor T1 is connected to the gate of the driving transistor DT via a connecting wire.

[0085] The third semiconductor structure 1133 is located in the fifth sub-section 15 and extends along the second direction Y. The third semiconductor structure 1133 is used to form the active layer of the fifth switching transistor T5. After being heavily doped, the third semiconductor structure 1133 is formed into a conductor, thereby forming the source and drain of the fifth switching transistor T5. Exemplarily, the first electrode (source or drain) of the fifth switching transistor T5 is connected to the power supply line VDD through a via, and the second electrode (drain or source) of the fifth switching transistor T5 is connected to the second electrode of the driving transistor DT through a connecting line.

[0086] FIG15 is a schematic diagram of a patterned structure of a first conductive layer provided in an embodiment of the present application. Referring to FIG12 and FIG15 , in one embodiment of the present application, illustratively, the first conductive layer 111 includes:

[0087] The first capacitor plate 1111 is located in the first sub-portion 11 , and its vertical projection on the semiconductor layer 113 overlaps with the first semiconductor structure 1131 .

[0088] A reference voltage line Vref extends along the first direction X and is connected to the fourth sub-section 14 to provide a reference voltage to the switching transistor located within the fourth sub-section 14. Exemplarily, the switching transistor located within the fourth sub-section 14 is a fourth switching transistor T4, and the reference voltage line Vref is connected to a first electrode (source or drain) of the fourth switching transistor T4 through a via.

[0089] Auxiliary power line VDD1 extends along the first direction X and connects to the fifth subsection 15, providing a power signal to the switching transistor located within the fifth subsection 15. Exemplarily, the switching transistor located within the fifth subsection 15 is a fifth switching transistor T5. The auxiliary power line VDD1 and the power line VDD located in the third conductive layer 115 form a mesh power line. The fifth switching transistor T5 is connected to the power line VDD through a via, and the auxiliary power line VDD1 is also connected to the power line VDD through a via.

[0090] In other embodiments, the reference voltage line Vref and / or the auxiliary power line VDD1 may be located in the second conductive line layer 112 .

[0091] FIG16 is a schematic diagram of a patterned structure of a second conductive layer provided in an embodiment of the present application. Referring to FIG12 and FIG16 , in one embodiment of the present application, illustratively, the second conductive layer 112 includes:

[0092] The second capacitor plate 1121 is located in the first sub-portion 11 , and its vertical projection on the first conductive layer 111 overlaps with the first capacitor plate 1111 , and the overlapping position constitutes a storage capacitor Cst.

[0093] The bottom gate BG is located in the second sub-portion 12 , and its vertical projection on the semiconductor layer 113 overlaps with the second semiconductor structure 1132 . The overlapping position is defined as the driving transistor DT.

[0094] In the embodiment of the present application, the second conductive line layer 112 is used to set the bottom gate BG of the driving transistor DT, without adding a new film layer or occupying pixel space, thereby ensuring the lightness, thinness and compactness of the display panel.

[0095] FIG17 is a schematic diagram of a patterned structure of a gate layer provided in an embodiment of the present application. Referring to FIG12 and FIG17 , in one embodiment of the present application, the gate layer 114 exemplarily includes:

[0096] The second scan line S2 extends along the first direction X and connects to the third sub-section 13. The vertical projection of the second scan line S2 on the semiconductor layer 113 overlaps with the first semiconductor structure 1131. The overlapping position is defined as a switching transistor located in the third sub-section 13, namely, the second switching transistor T2.

[0097] The first light-emitting control line EM1 extends along the first direction X and is connected to the third sub-section 13; the vertical projection of the first light-emitting control line EM1 on the semiconductor layer 113 overlaps with the first semiconductor structure 1131, and the overlapping position is defined as a switching transistor located in the third sub-section 13, namely, the third switching transistor T3.

[0098] The top gate TG is located in the second sub-portion 12 , and its vertical projection on the semiconductor layer 113 overlaps with the second semiconductor structure 1132 . The overlapping position is defined as the driving transistor DT.

[0099] The first scan line S1 extends along the first direction X in a truncated upward shape, connecting to the fourth sub-section 14 and the second sub-section 12; the vertical projection of the first scan line S1 on the semiconductor layer 113 overlaps with the first semiconductor structure 1131, and the overlapping position is defined as a switching transistor located in the fourth sub-section 14, namely, the fourth switching transistor T4; the vertical projection of the first scan line S1 on the semiconductor layer 113 also overlaps with the second semiconductor structure 1132, and the overlapping position is defined as a switching transistor located in the second sub-section 12, namely, the first switching transistor T1.

[0100] The second light-emitting control line EM2 extends along the first direction X and is connected to the fifth sub-section 15; the vertical projection of the second light-emitting control line EM2 on the semiconductor layer 113 overlaps with the third semiconductor structure 1133, and the overlapping position is defined as a switching transistor located in the fifth sub-section 15, namely, the fifth switching transistor T5.

[0101] In the embodiment of the present application, the transistor is configured as a top-gate transistor. A metal layer can be formed on the semiconductor layer 111, which serves as the gate of the transistor. For IGZO-type semiconductor materials, differential oxygenation can be performed on the semiconductor layer 111 after the gate layer 114 is formed, resulting in differential oxidation between the channel region and the source and drain regions of the semiconductor layer 111, thereby forming a transistor. For LTPS-type semiconductor materials, ion implantation can be performed on the semiconductor layer 111 after the gate layer 114 is formed, thereby forming a transistor.

[0102] FIG18 is a schematic diagram of a patterned structure of a third conductive layer provided in an embodiment of the present application. Referring to FIG12 and FIG18 , in one embodiment of the present application, illustratively, the third conductive layer 115 includes:

[0103] The data line Vdata extends along the second direction Y and connects to the third sub-section 13, providing a data signal to the switching transistor (i.e., the second switching transistor T2) located in the third sub-section 13. The vertical projection of the data line Vdata on the semiconductor layer 113 is located outside the first semiconductor structure 1131. This arrangement helps reduce the overlap area between signal lines, thereby reducing interference between signal lines.

[0104] The power line VDD extends along the second direction Y and connects to the fifth sub-section 15, providing a power signal to the switching transistor (i.e., the fifth switching transistor T5) located in the fifth sub-section 15. The vertical projection of the power line VDD on the semiconductor layer 113 is located outside the third semiconductor structure 1133. This arrangement helps reduce the overlap area between signal lines, thereby reducing interference between signal lines.

[0105] A first crossover 1151 has its two ends located in the second sub-section 12 and the third sub-section 13, respectively. The first crossover 1151 is used to connect the driving transistor DT located in the second sub-section 12 and the switching transistor (i.e., the second switching transistor T2) located in the third sub-section 13. Exemplarily, one end of the first crossover 1151 is connected to the first electrode of the driving transistor DT through a via, and the other end of the first crossover 1151 is connected to the second electrode of the second switching transistor T2 through a via.

[0106] The second crossover 1152 is located in the first subsection 11. The second crossover 1152 is used to connect the switching transistor (i.e., the third switching transistor T3) located in the third subsection 13 and the second electrode plate 1121 of the capacitor located in the first subsection 11. For example, one end of the second crossover 1152 is connected to the second electrode of the third switching transistor T3 through a via, and the other end of the second crossover 1152 is connected to the second electrode plate 1121 of the capacitor through a via. In other embodiments, the two ends of the second crossover 1152 may be located in the first subsection 11 and the third subsection 13, respectively.

[0107] The third crossover 1153 is located in the second sub-section 12 and is used to connect the driving transistor DT, the switching transistor (i.e., the first switching transistor T1), and the first capacitor plate 1111 located in the second sub-section 12. Exemplarily, a portion of the third crossover 1153 is connected to the gate of the driving transistor DT through a via, another portion of the third crossover 1153 is connected to the first electrode of the first switching transistor T1 through a via, and yet another portion of the third crossover 1153 is connected to the first capacitor plate 1111 through a via.

[0108] A fourth crossover 1154 is located in the fifth subsection 15. The fourth crossover 1154 is used to connect the switching transistor (i.e., the first switching transistor T1) located in the second subsection 12 and the switching transistor (i.e., the fifth switching transistor) located in the fifth subsection 15. For example, one end of the fourth crossover 1154 is connected to the second electrode of the first switching transistor T1 through a via, and the other end of the fourth crossover 1154 is connected to the second electrode of the fifth switching transistor T5 through a via. In other embodiments, the ends of the fourth crossover 1154 may be located in the second subsection 12 and the fifth subsection 15, respectively.

[0109] A fifth crossover 1155 is located in the fourth subsection 14 and is used to connect a switching transistor (i.e., the fourth switching transistor T4) located in the fourth subsection 14 to a reference voltage line Vref. Exemplarily, a portion of the fifth crossover 1155 is connected to the first electrode of the fourth switching transistor T4 through a via, and another portion of the fifth crossover 1155 is connected to the reference voltage line Vref through a via.

[0110] FIG19 is a schematic diagram of a patterned structure of a first type of via and a second type of via provided in an embodiment of the present application, and FIG20 is a schematic diagram of a patterned structure of a third type of via and a fourth type of via provided in an embodiment of the present application. Referring to FIG12 and FIG18-FIG20, in one embodiment of the present application, illustratively, a portion of the first cross-line 1151 is connected to the first electrode of the driving transistor DT through the third type of via 1231, and another portion of the first cross-line 1151 is connected to the second electrode of the switching transistor (i.e., the second switching transistor T2) located in the third sub-section 13 through the third type of via 1232. illustratively, another portion of the first cross-line 1151 is connected to the bottom gate BG located in the second sub-section 12 through the second type of via 1222.

[0111] The second crossover 1152 is connected to the second electrode of the switch transistor (ie, the third switch transistor T3 ) in the third subsection 13 through the third type via 1233 , and is connected to the capacitor second plate 1121 through the second type via 1221 .

[0112] The third jumper 1153 is connected to the gate of the driving transistor DT through the fourth type via 1241, the third jumper 1153 is connected to the first electrode of the switching transistor (first switching transistor T1) in the second sub-section 12 through the third type via 1234, and the third jumper 1153 is connected to the first plate 1111 of the capacitor through the first type via 1211.

[0113] One end of the fourth jumper 1154 is connected to the switching transistor located in the second sub-section 12 (i.e., the second electrode of the first switching transistor T1) through the third type via 1235, and the other end of the fourth jumper 1154 is connected to the second electrode of the switching transistor located in the fifth sub-section 15 (i.e., the fifth switching transistor T5) through the third type via 1236.

[0114] The fifth cross-line 1155 is connected to the first electrode of the switch transistor (the fourth switch transistor T4 ) in the fourth sub-section 14 through the third type via 1237 . The fifth cross-line 1155 is connected to the reference voltage line Vref through the first type via 1212 .

[0115] The power line VDD is connected to the auxiliary power line VDD1 in the first wire layer 111 through the first type via 1213 . The power line VDD is connected to the first electrode of the switch transistor (ie, the fifth switch transistor T5 ) in the fifth sub-section 15 through the third type via 1238 .

[0116] The data line Vdata is connected to the first electrode of the switch transistor (ie, the second switch transistor T2 ) in the third sub-section 13 through the third type via 1239 .

[0117] FIG21 is a schematic diagram of a patterned structure of a fourth conductive layer provided in an embodiment of the present application. Referring to FIG12 and FIG21 , in one embodiment of the present application, illustratively, the fourth conductive layer 116 includes:

[0118] The second auxiliary power line VDD2 extends along the second direction Y, and its vertical projection on the semiconductor layer 113 is located outside the third semiconductor structure 1133. Exemplarily, the second auxiliary power line VDD2 overlaps the power line VDD.

[0119] The auxiliary reference voltage line Vref1 extends along the second direction Y and avoids the first sub-portion 11. This configuration is beneficial to avoid the influence of the reference voltage line Vref1 on the storage capacitor Cst.

[0120] Anode jumper 1161 : The anode jumper 1161 is located in the first sub-section 11 and / or the second sub-section 12 . The anode jumper 1161 is used to connect the second capacitor plate 1121 and the anode.

[0121] Figure 22 is a schematic diagram of a patterned structure of a fifth type of via provided in an embodiment of the present application, and Figure 23 is a schematic diagram of a patterned structure of a sixth type of via provided in an embodiment of the present application. Referring to Figures 12 and 21-23, in one embodiment of the present application, the second auxiliary power line VDD2 is connected to the power line VDD located in the third conductor layer 115 via a fifth type of via 1251.

[0122] The auxiliary reference voltage line Vref1 is connected to a fifth crossover 1155 located in the third conductive line layer 115 through a fifth type via 1252 .

[0123] The anode jumper 1161 is connected to the second jumper 1152 located in the third wiring layer 115 through the fifth type via 1253 .

[0124] The anode is connected to the anode jumper 1161 through a sixth type of via 1261 .

[0125] It should be noted that in the above embodiment, the film layer structure of the sub-pixel structure 10 is exemplarily shown to include a first conductive layer 111, a second conductive layer 112, a semiconductor layer 113, a gate layer 114, and a third conductive layer 115. This is not a limitation of the present application, and in other embodiments, the number of film layers of the sub-pixel structure 10 may be further reduced.

[0126] Figure 24 is a schematic cross-sectional view of another sub-pixel structure provided in an embodiment of the present application. Referring to Figure 24, in one embodiment of the present application, illustratively, the film layer structure of the sub-pixel structure 10 includes a first wire layer 111, a semiconductor layer 113, a gate layer 114, and a third wire layer 115. Unlike the aforementioned embodiment, the two plates of the storage capacitor Cst are respectively arranged on the first wire layer 111 and the gate layer 114. That is, the gate layer 114 is reused as the second wire layer 112 in the aforementioned embodiment. This arrangement of the embodiment of the present application is conducive to reducing the number of film layers, thereby facilitating the thinning of the display panel.

[0127] Exemplarily, at least part of the connection lines between the driving transistor DT and the switching transistor, and at least part of the connection lines between the switching transistors are provided in the third conductive line layer 113 .

[0128] Figure 25 is a schematic diagram of another semiconductor layer patterning structure provided in an embodiment of the present application. Referring to Figure 25 , unlike the previous embodiment, the first semiconductor structure 1131 is positioned away from the first sub-section 11. This arrangement prevents the first semiconductor structure 1131 from being located between the first capacitor plate and the second capacitor substrate. For example, the second electrode of the third switching transistor T3 and the second electrode of the fourth switching transistor T4 can be connected by connecting a crossover wire.

[0129] It should be noted that, in the above embodiment, the first direction X and the second direction Y are perpendicular to each other. In other embodiments, the first direction X and the second direction Y may be set to be non-perpendicular as needed.

[0130] An embodiment of the present application further provides a display panel, which includes: a plurality of sub-pixel structures 10 as provided in any embodiment of the present application. The technical principles and effects produced are similar and will not be described in detail.

[0131] The present application also provides a display device, which may be a mobile phone, computer, tablet computer, or wearable device, etc. The display device includes: a display panel provided in any embodiment of the present application, and its technical principles and effects are similar and will not be described in detail.

[0132] The present application also provides a method for manufacturing a display panel. The method is applicable to the display panel provided in any embodiment of the present application and can achieve corresponding beneficial effects. Exemplarily, the method for manufacturing a display panel includes:

[0133] The substrate is divided into a plurality of sub-pixel regions, and the sub-pixel regions are divided into a first sub-section, a second sub-section, a third sub-section, a fourth sub-section, and a fifth sub-section; the first sub-section and the second sub-section are arranged along a first direction; the third sub-section, the first sub-section, and the fourth sub-section are arranged in sequence along a second direction; the second direction intersects the first direction; the fifth sub-section and the fourth sub-section are arranged side by side in the first direction; and the second sub-section and the fifth sub-section are arranged side by side in the second direction;

[0134] A storage capacitor is formed in the first sub-section, a driving transistor and at least one switching transistor connected to the control end of the driving transistor are formed in the second sub-section, at least one switching transistor connected to the first electrode of the driving transistor is formed in the third sub-section, at least one switching transistor connected to the storage capacitor is formed in the fourth sub-section, and at least one switching transistor connected to the second electrode of the driving transistor is formed in the fifth sub-section.

[0135] Exemplarily, a method for preparing the storage capacitor Cst includes the following steps:

[0136] 13 and 15 , a first conductive line layer 111 is formed, and the first conductive line layer 111 is patterned to form a first capacitor plate 1111 ; wherein the first capacitor plate 1111 is located in the first sub-portion 11 .

[0137] Illustratively, the material of first conductive layer 111 includes one or a combination of molybdenum, gold, silver, copper, lithium, sodium, potassium, magnesium, aluminum, and zinc. First conductive layer 111 can be formed using processes such as evaporation and magnetron sputtering, and then patterned using a photolithography and etching process.

[0138] 13 , a first insulating layer 141 is formed on the first conductive line layer 111 .

[0139] For example, the material of the first insulating layer 141 may be an inorganic material such as silicon oxide or silicon nitride, and may be formed by a physical or chemical vapor deposition process.

[0140] 13 and 16 , a second conductive layer 112 is formed on the first insulating layer and patterned to form a second capacitor plate 1121 . The second capacitor plate 1121 overlaps the first capacitor plate to form a storage capacitor Cst.

[0141] Exemplarily, the material of the second conductive layer 112 includes one or a combination of molybdenum, gold, silver, copper, lithium, sodium, potassium, magnesium, aluminum, and zinc. The second conductive layer 112 can be formed by evaporation, magnetron sputtering, or other processes, and then patterned by photolithography and etching.

[0142] Based on the above embodiment, illustratively, a method for preparing a transistor includes:

[0143] 13 , a second insulating layer 142 is formed on the second conductive line layer 112 .

[0144] For example, the material of the second insulating layer 142 may be an inorganic material such as silicon oxide or silicon nitride, and may be formed by a physical or chemical vapor deposition process.

[0145] 13 and 14 , a semiconductor layer 113 is formed on the second insulating layer, and the semiconductor layer 113 is patterned to form a semiconductor structure (including a first semiconductor structure 1131 , a second semiconductor structure 1132 , and a third semiconductor structure 1133 ).

[0146] 13 , a third insulating layer 143 is formed on the semiconductor layer 113 .

[0147] For example, the material of the third insulating layer 143 may be an inorganic material such as silicon oxide or silicon nitride, and may be formed by a physical or chemical vapor deposition process.

[0148] 13 and 17 , a gate layer 114 is formed on the third insulating layer, and the gate layer 114 is patterned to form a driving transistor DT and a gate of a switching transistor; wherein, the intersection of the driving transistor DT and the semiconductor structure constitutes the driving transistor DT, and the intersection of the gate of the switching transistor and the semiconductor structure constitutes the switching transistor.

[0149] Exemplarily, the material of the gate layer 114 includes one or a combination of molybdenum, gold, silver, copper, lithium, sodium, potassium, magnesium, aluminum, and zinc. The gate layer 114 can be formed by evaporation, magnetron sputtering, or the like, and then patterned by photolithography and etching.

[0150] 13 , a fourth insulating layer 144 is formed on the gate layer 114 .

[0151] For example, the fourth insulating layer 144 may be made of an inorganic material such as silicon oxide or silicon nitride, and may be formed by a physical or chemical vapor deposition process.

[0152] 13 and 19 , first-type via holes 121 and second-type via holes 122 are formed at depths corresponding to the positions of the first conductive line layer 111 and the second conductive line layer 112 , respectively.

[0153] Exemplarily, a deep hole etching process is used to form the first type of via holes 121 and the second type of via holes 122 .

[0154] 13 and 20 , a third type of via hole 123 and a fourth type of via hole 124 are formed at depths corresponding to the positions of the semiconductor layer 113 and the gate layer 114 , respectively.

[0155] Exemplarily, the third type via holes 123 and the fourth type via holes 124 are formed by a shallow hole etching process.

[0156] 13 and 18 , a third wire layer 115 is formed on the fourth insulating layer 144 and patterned to form crossovers (including a first crossover 1151 , a second crossover 1152 , a third crossover 1153 , a fourth crossover 1154 and a fifth crossover 1155 ), a data line Vdata and a power line VDD.

[0157] Exemplarily, the material of third conductive layer 115 includes one or a combination of molybdenum, gold, silver, copper, lithium, sodium, potassium, magnesium, aluminum, and zinc. Third conductive layer 115 can be formed using processes such as evaporation and magnetron sputtering, and then patterned using a photolithography-etching process. Third conductive layer 115 can be implanted with vias to electrically connect to other conductive layers.

[0158] Exemplarily, after forming the third conductive line layer 115, the method further includes:

[0159] 13 , a fifth insulating layer 145 is formed on the third conductive line layer 115 .

[0160] For example, the material of the fifth insulating layer 145 may be an organic material such as photoresist, and may be formed by a spin coating process.

[0161] 13 and 22 , a fifth type of via hole 125 is formed at a depth corresponding to the position of the third conductive line layer 115 .

[0162] Exemplarily, the fifth type of via hole 125 is formed by a shallow hole etching process.

[0163] 13 and 21 , a fourth conductive line layer 116 is formed on the fifth insulating layer 145 , and the fourth conductive line layer 116 is patterned to form a second auxiliary power line VDD2 , an auxiliary reference voltage line Vref1 , and an anode jumper 1161 .

[0164] Exemplarily, the material of fourth conductive layer 116 includes one or a combination of molybdenum, gold, silver, copper, lithium, sodium, potassium, magnesium, aluminum, and zinc. Fourth conductive layer 116 can be formed using processes such as evaporation and magnetron sputtering, and then patterned using a photolithography-etching process. Fourth conductive layer 116 can be implanted with vias to electrically connect to third conductive layer 115.

[0165] 13 , a sixth insulating layer 146 is formed on the fourth conductive line layer 116 .

[0166] For example, the sixth insulating layer 146 may be made of an organic material such as photoresist, and may be formed by a spin coating process.

[0167] 13 and 23 , a sixth type of via hole 126 is formed at a depth corresponding to the position of the fourth conductive line layer 116 .

[0168] Exemplarily, the sixth type of via hole 126 is formed by a shallow hole etching process.

[0169] 13 , an anode layer 117 is formed on the sixth insulating layer 146 , and the anode layer 117 is patterned to form an anode.

[0170] Exemplarily, the material of the anode layer includes indium tin oxide (ITO), silver, or a combination of ITO, silver, and ITO (ITO / Ag / ITO).

[0171] After the anode layer 117 is formed, the steps of forming a light-emitting layer and packaging are also included, which will not be described in detail in this application.

[0172] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the multiple steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this application can be achieved. This is not limited herein.

Claims

1. A sub-pixel structure, comprising: a first subsection, a second subsection, a third subsection, a fourth subsection, and a fifth subsection; The first sub-section and the second sub-section are arranged along a first direction; the third sub-section, the first sub-section and the fourth sub-section are arranged in sequence along a second direction; the second direction intersects the first direction; In the first direction, the fifth sub-section and the fourth sub-section are arranged in parallel; in the second direction, the second sub-section and the fifth sub-section are arranged in parallel; Among them, a storage capacitor is provided in the first sub-section, a driving transistor and at least one switching transistor connected to the control end of the driving transistor are provided in the second sub-section, at least one switching transistor connected to the first electrode of the driving transistor is provided in the third sub-section, at least one switching transistor connected to the storage capacitor is provided in the fourth sub-section, and at least one switching transistor connected to the second electrode of the driving transistor is provided in the fifth sub-section.

2. The sub-pixel structure according to claim 1, wherein: The driving transistor and the first switch transistor are provided in the second sub-section, the gate of the first switch transistor is electrically connected to the first scan line, the first electrode of the first switch transistor is electrically connected to the gate of the driving transistor, and the second electrode of the first switch transistor is electrically connected to the second electrode of the driving transistor; A second switch transistor and a third switch transistor are provided in the third sub-section, the gate of the second switch transistor is electrically connected to the second scan line, the first electrode of the second switch transistor is electrically connected to the data line, and the second electrode of the second switch transistor is electrically connected to the first electrode of the drive transistor; the gate of the third switch transistor is electrically connected to the first light-emitting control line, the first electrode of the third switch transistor is electrically connected to the first electrode of the drive transistor, and the second electrode of the third switch transistor is electrically connected to the storage capacitor; A fourth switch transistor is provided in the fourth sub-section, a gate of the fourth switch transistor is electrically connected to the first scan line, a first electrode of the fourth switch transistor is electrically connected to a reference voltage line, and a second electrode of the fourth switch transistor is electrically connected to a second electrode of the third switch transistor; A fifth switch transistor is provided in the fifth sub-section, a gate of the fifth switch transistor is electrically connected to the second light emitting control line, a first electrode of the fifth switch transistor is electrically connected to the power line, and a second electrode of the fifth switch transistor is electrically connected to the second electrode of the driving transistor; The driving transistor, the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor and the fifth switching transistor are oxide transistors respectively.

3. The sub-pixel structure according to claim 2, wherein: The second scan line, the first light emitting control line, the first scan line and the second light emitting control line extend along the first direction respectively; Wherein, the second scan line and the first light-emitting control line are connected to the third sub-section, the first scan line is connected to the fourth sub-section, and the second light-emitting control line is connected to the fifth sub-section; Wherein, in the second direction, the second scan line, the first light emitting control line, the first scan line and the second light emitting control line are arranged in sequence.

4. The sub-pixel structure according to claim 2, wherein: The data line and the power line extend along the second direction respectively, and the data line is connected to the third sub-section, the first sub-section and the fourth sub-section, and the power line is connected to the second sub-section and the fifth sub-section; The sub-pixel structure further includes: an auxiliary power line, the auxiliary power line extending along the first direction, the auxiliary power line and the power line forming a mesh power line; Wherein, the auxiliary power line is connected to the fourth sub-section and the fifth sub-section.

5. The sub-pixel structure according to claim 2, wherein: The reference voltage line extends along the first direction, and the reference voltage line is connected to the fourth sub-section; The sub-pixel structure further includes an auxiliary reference voltage line, the auxiliary reference voltage line extends along the second direction, and the auxiliary reference voltage line and the reference voltage line form a mesh reference voltage line.

6. The sub-pixel structure according to claim 1, wherein: The film layer structure of the sub-pixel structure includes: a first wire layer, a second wire layer, a semiconductor layer, a gate layer and a third wire layer arranged in layers; The two plates of the storage capacitor are respectively arranged on the first wire layer and the second wire layer; The active layer, the first end and the second end of the driving transistor, and the active layer, the first end and the second end of the switching transistor are arranged on the semiconductor layer; wherein the first end and the second end of the driving transistor, and the first end and the second end of the switching transistor are conductors formed by heavily doping the semiconductor layer; The gate of the driving transistor and the gate of the switching transistor are respectively arranged on the gate layer; The connecting wires between different film layers are arranged in the third wire layer.

7. The sub-pixel structure according to claim 6, wherein: The third wire layer is connected to the first wire layer via a first type of via, and the third wire layer is connected to the second wire layer via a second type of via; The third wire layer is connected to the semiconductor layer via a third type of via hole, and the third wire layer is connected to the gate layer via a The fourth type of via connection; The depths of the first type of via holes and the second type of via holes are respectively greater than the depth of the third type of via holes, and the depths of the first type of via holes and the second type of via holes are respectively greater than the depth of the fourth type of via holes.

8. The sub-pixel structure according to claim 6, wherein: The driving transistor comprises a top gate and a bottom gate, the bottom gate of the driving transistor is arranged on the second wire layer, and the top gate of the driving transistor is arranged on the gate layer; Wherein, the top gate of the driving transistor is a control gate, and the bottom gate of the driving transistor is connected to the source of the driving transistor; or, the bottom gate of the driving transistor is a control gate, and the top gate of the driving transistor is connected to the source of the driving transistor; Wherein, the second electrode of the driving transistor is a source electrode.

9. The sub-pixel structure according to claim 6, wherein: The semiconductor layer comprises: a first semiconductor structure, the first semiconductor structure extending along the second direction and connected to the third sub-portion, the first sub-portion and the fourth sub-portion; a second semiconductor structure, the second semiconductor structure is located in the second sub-portion and is in an inverted G-shape; the long side direction of the second semiconductor structure is the second direction; A third semiconductor structure is located in the fifth sub-portion and extends along the second direction.

10. The sub-pixel structure according to claim 9, wherein: The first conductor layer comprises: a first capacitor plate, the first capacitor plate being located in the first sub-portion, and a vertical projection of the first capacitor plate on the semiconductor layer overlapping the first semiconductor structure; a reference voltage line extending along the first direction and connected to the fourth sub-section to provide a reference voltage to the switch transistor in the fourth sub-section; An auxiliary power line extends along the first direction and is connected to the fifth sub-section to provide a power signal to the switch transistor in the fifth sub-section.

11. The sub-pixel structure according to claim 10, wherein: The second conductor layer includes: A second capacitor plate, the second capacitor plate is located in the first sub-portion, and a vertical projection of the second capacitor plate on the first conductor layer overlaps with the first capacitor plate, and the overlapping position constitutes the storage capacitor; A bottom gate is located in the second sub-portion, and a vertical projection of the bottom gate on the semiconductor layer overlaps with the second semiconductor structure, and the overlapping position is defined as the driving transistor.

12. The sub-pixel structure according to claim 11, wherein: The gate layer comprises: a second scan line, the second scan line extending along the first direction and connected to the third sub-section; a vertical projection of the second scan line on the semiconductor layer overlaps with the first semiconductor structure, and the overlapping position is defined as one of the switch transistors located in the third sub-section; A first light-emitting control line, the first light-emitting control line extends along the first direction and is connected to the third sub-section; a vertical projection of the first light-emitting control line on the semiconductor layer overlaps with the first semiconductor structure, and the overlapping position is defined as one of the switch transistors located in the third sub-section; a top gate, the top gate being located in the second sub-portion, and having a vertical projection on the semiconductor layer overlapping with the second semiconductor structure, and the overlapping position is defined as the driving transistor; a first scan line, the first scan line extending along the first direction and connected to the fourth sub-section and the second sub-section; a vertical projection of the first scan line on the semiconductor layer overlaps with the first semiconductor structure, and the overlapping position is defined as one of the switch transistors located in the fourth sub-section; a vertical projection of the first scan line on the semiconductor layer also overlaps with the second semiconductor structure, and the overlapping position is defined as one of the switch transistors located in the second sub-section; A second light-emitting control line, the second light-emitting control line extends along the first direction and is connected to the fifth sub-section; a vertical projection of the second light-emitting control line on the semiconductor layer overlaps with the third semiconductor structure, and the overlapping position is defined as one of the switch transistors located in the fifth sub-section.

13. The sub-pixel structure according to claim 9, wherein: The third conductor layer comprises: a data line extending along the second direction and connected to the third sub-section to provide a data signal to the switch transistor located in the third sub-section; a vertical projection of the data line on the semiconductor layer is located outside the first semiconductor structure; a power line extending along the second direction and connected to the fifth sub-section to provide a power signal to the switch transistor located in the fifth sub-section; a vertical projection of the power line on the semiconductor layer is located outside the third semiconductor structure; A first crossover wire, two ends of which are respectively located in the second sub-section and the third sub-section, and the first crossover wire is used to connect the driving transistor located in the second sub-section and the switching transistor located in the third sub-section; A second crossover wire is located in the first subsection, or two ends of the crossover wire are located in the first subsection and the third subsection respectively, and the second crossover wire is used to connect the switch transistor in the third subsection and the second plate of the capacitor in the first subsection; A third crossover line is located in the second sub-section, and the third crossover line is used to connect the driving transistor located in the second sub-section, The switching transistor and the first plate of the capacitor; a fourth crossover wire, located in the fifth subsection, or having two ends thereof respectively located in the second subsection and the fifth subsection, the fourth crossover wire being used to connect the switch transistor in the second subsection and the switch transistor in the fifth subsection; A fifth cross-line is located in the fourth sub-section, and is used to connect the switch transistor in the fourth sub-section and a reference voltage line.

14. The sub-pixel structure according to claim 13, wherein: One end of the first crossover is connected to the driving transistor through a third type of via, and the other end of the first crossover is connected to the switch transistor located in the third subsection through the third type of via; The second crossover is connected to the switch transistor in the third subsection through the third type of via, and the second crossover is connected to the second plate of the capacitor through the second type of via; The third crossover is connected to the driving transistor through a fourth type of via, the third crossover is connected to the switch transistor in the second sub-section through the third type of via, and the third crossover is connected to the first plate of the capacitor through a first type of via; One end of the fourth crossover is connected to the switch transistor in the second subsection through the third type via, and the other end of the fourth crossover is connected to the switch transistor in the fifth subsection through the third type via; The fifth cross-line is connected to the switch transistor located in the fourth sub-section through the third type of via, and the fifth cross-line is connected to the reference voltage line through the first type of via; The power line is connected to the auxiliary power line located in the first conductor layer through the first type via.

15. The sub-pixel structure according to claim 9, further comprising: a fourth wire layer, the fourth wire layer being located at a side of the third wire layer away from the first wire layer; The fourth conductor layer comprises: a second auxiliary power line, the second auxiliary power line extending along the second direction, and a vertical projection of the second auxiliary power line on the semiconductor layer being located outside the third semiconductor structure; an auxiliary reference voltage line, the auxiliary reference voltage line extending along the second direction and avoiding the first sub-portion; an anode jumper, the anode jumper being located in the first sub-section and / or the second sub-section, and being used to connect the second plate of the capacitor and the anode; Wherein, the second auxiliary power line is connected to the power line located in the third conductor layer through a fifth type via; The auxiliary reference voltage line is connected to a fifth crossover line located in the third conductor layer through the fifth type via hole; The anode jumper is connected to the second jumper located in the third conductor layer through the fifth type via; The anode is connected to the anode jumper through a sixth type via.

16. The sub-pixel structure according to claim 1, wherein: The film layer structure of the sub-pixel structure includes: a first wire layer, a semiconductor layer, a gate layer and a third wire layer arranged in layers; The two plates of the storage capacitor are respectively arranged on the first wire layer and the gate layer; The active layer, the first end and the second end of the driving transistor, and the active layer, the first end and the second end of the switching transistor are arranged on the semiconductor layer; wherein the first end and the second end of the driving transistor, and the first end and the second end of the switching transistor are conductors formed by heavily doping the semiconductor layer; The gate of the driving transistor and the gate of the switching transistor are respectively arranged on the gate layer; At least part of the connection lines between the driving transistor and the switching transistor, and at least part of the connection lines between the switching transistors are arranged in the third conductor layer; Wherein, the semiconductor layer comprises: a first semiconductor structure, the first semiconductor structure extending along the second direction and connected to the third sub-portion and the fourth sub-portion, and the first semiconductor structure avoiding the first sub-portion; a second semiconductor structure, the second semiconductor structure is located in the second sub-portion and is in an inverted G-shape; the long side direction of the second semiconductor structure is the second direction; A third semiconductor structure is located in the fifth sub-portion and extends along the second direction.

17. A display panel, comprising: A plurality of sub-pixel structures as described in any one of claims 1-16.

18. A display device comprising: The display panel as claimed in claim 17.

19. A method for preparing a display panel, comprising: The substrate is divided into a plurality of sub-pixel regions, and the sub-pixel regions are divided into a first sub-section, a second sub-section, a third sub-section, a fourth sub-section and a fifth sub-section; the first sub-section and the second sub-section are arranged along a first direction; the third sub-section, the first sub-section and the fourth sub-section are arranged in sequence along a second direction; the second direction intersects the first direction; in the first direction, the fifth sub-section and the fourth sub-section are arranged in parallel; in the second direction, the second sub-section and the fifth sub-section are arranged in parallel; A storage capacitor is formed in the first sub-section, a driving transistor and at least one switching transistor connected to the control terminal of the driving transistor are formed in the second sub-section, at least one switching transistor connected to the first electrode of the driving transistor is formed in the third sub-section, at least one switching transistor connected to the storage capacitor is formed in the fourth sub-section, and at least one switching transistor connected to the control terminal of the driving transistor is formed in the fifth sub-section. A second electrode of the driving transistor is connected to at least one switching transistor.

20. The method for preparing a display panel according to claim 19, wherein: The preparation method of the storage capacitor comprises: Forming a first conductive line layer, and patterning the first conductive line layer to form a first capacitor electrode; wherein the first capacitor electrode is located in the first sub-section; forming a first insulating layer on the first conductive line layer; Forming a second conductive line layer on the first insulating layer, and patterning the second conductive line layer to form a second capacitor plate; wherein the second capacitor plate overlaps the first capacitor plate to form the storage capacitor; Wherein, the manufacturing method of the driving transistor and the switching transistor includes: forming a second insulating layer on the second conductive line layer; forming a semiconductor layer on the second insulating layer, and patterning the semiconductor layer to form a semiconductor structure; forming a third insulating layer on the semiconductor layer; A gate layer is formed on the third insulating layer, and the gate layer is patterned to form the gates of the driving transistor and the switching transistor; wherein the position where the driving transistor intersects with the semiconductor structure constitutes the driving transistor, and the position where the gate of the switching transistor intersects with the semiconductor structure constitutes the switching transistor; forming a fourth insulating layer on the gate layer; Forming first-type via holes and second-type via holes at depths corresponding to the positions of the first conductive line layer and the second conductive line layer, respectively; Forming a third type of via hole and a fourth type of via hole at depths corresponding to the positions of the semiconductor layer and the gate layer, respectively; A third wire layer is formed on the fourth insulating layer, and the third wire layer is patterned to form a crossover line, a data line and a power line.

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