Pixel drive circuit, display panel, and display device

Abstract

A pixel drive circuit, a display panel, and a display device. The pixel drive circuit comprises: a first pixel driving unit (100) and a second pixel driving unit (200); the first pixel driving unit (100) comprises a first driving transistor (110) and a first light-emitting element (120); the first driving transistor (110) has a first threshold adjustment gate (111) configured to receive a first adjustment signal (R_BSM); the second pixel driving unit (200) comprises a second driving transistor (210) and a second light-emitting element (220); the second driving transistor (210) has a second threshold adjustment gate (211) configured to receive a second adjustment signal (G_BSM); the light-emitting colors of the first light-emitting element (120) and the second light-emitting element (220) are different from each other; and when the first light-emitting element (120) and the second light-emitting element (220) are displayed at a target grayscale, the voltage values of the first adjustment signal (R_BSM) and the second adjustment signal (G_BSM) are different.

Description

Pixel driving circuit, display panel and display device

[0001] This application claims priority to the Chinese patent applications filed with the China Patent Office on June 29, 2023, with application number 202310798701.3, and filed with the China Patent Office on December 4, 2023, with application number 202311686416.9. The entire contents of the above applications are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, for example, to a pixel driving circuit, a display panel and a display device. Background Art

[0003] With the continuous development of display technology, people have higher and higher requirements for display panels, but the performance of display panels needs to be improved.

[0004] Summary of the Invention

[0005] The present application provides a pixel driving circuit, a display panel, and a display device to improve the performance of the display panel.

[0006] The present application provides a pixel driving circuit, which includes:

[0007] a first pixel driving unit, comprising a first driving transistor and a first light-emitting element, wherein the first driving transistor has a first driving current control gate and a first threshold adjustment gate, the first driving current control gate being configured to receive a first data signal, the first threshold adjustment gate being configured to receive a first adjustment signal, and the first driving transistor being configured to drive the first light-emitting element under the control of the first data signal and the first adjustment signal;

[0008] a second pixel driving unit, comprising a second driving transistor and a second light-emitting element, the second driving transistor having a second driving current control gate and a second threshold adjustment gate, the second driving current control gate being configured to receive a second data signal, the second threshold adjustment gate being configured to receive a second adjustment signal, the second driving transistor being configured to drive the second light-emitting element under the control of the second data signal and the second adjustment signal;

[0009] The first light emitting element and the second light emitting element emit different colors. When the first light emitting element and the second light emitting element display a target grayscale, the first adjustment signal and the second adjustment signal have different voltage values.

[0010] The present application also provides a display panel, comprising the pixel driving circuit, the first metal layer, the light-emitting functional layer and the isolation layer described in the above embodiment;

[0011] The first threshold adjustment gate and the second threshold adjustment gate are electrically isolated and disposed in the first metal layer;

[0012] The light-emitting functional layer is provided on one side of the first metal layer, and a portion of the first light-emitting elements and a portion of the second light-emitting elements are provided in the light-emitting functional layer;

[0013] The isolation layer is provided on one side of the first metal layer and is provided to separate the first light emitting element from the second light emitting element, and the isolation layer includes a first gate isolation column and a second gate isolation column;

[0014] The first gate isolation column is coupled to the first threshold adjustment gate and is configured with the first adjustment signal, and the second gate isolation column is coupled to the second threshold adjustment gate and is configured with the second adjustment signal.

[0015] The present application also provides a display panel, comprising:

[0016] a substrate having a first side;

[0017] a driving circuit layer, disposed on the first side, comprising a first driving transistor in a first pixel driving unit, wherein the first driving transistor has a first threshold adjustment gate;

[0018] The isolation layer is disposed on a side of the driving circuit layer away from the substrate, and includes a first gate isolation column coupled to the first threshold adjustment gate and configured with a first adjustment signal.

[0019] The present application also provides a display device, comprising: a display panel as provided in any of the above embodiments.

[0020] In the embodiment of the present application, the driving transistor in the pixel driving unit includes a threshold adjustment gate, so that the voltage of the threshold adjustment gate of the driving transistor can be adjusted, thereby adjusting the threshold voltage of the driving transistor and improving the performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a circuit diagram of a pixel driving circuit provided in an embodiment of the present application;

[0022] FIG2 is a circuit diagram of another pixel driving circuit provided in an embodiment of the present application;

[0023] FIG3 is a circuit diagram of another pixel driving circuit provided in an embodiment of the present application;

[0024] FIG4 is a circuit diagram of another pixel driving circuit provided in an embodiment of the present application;

[0025] FIG5 is a circuit diagram of another pixel driving circuit provided in an embodiment of the present application;

[0026] FIG6 is a circuit diagram of another pixel driving circuit provided in an embodiment of the present application;

[0027] FIG7 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0028] FIG8 is a schematic cross-sectional structural diagram of the first pixel driving unit along line AA in FIG7 ;

[0029] FIG9 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application;

[0030] FIG10 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0031] FIG11 is a schematic cross-sectional view of another display panel provided in an embodiment of the present application;

[0032] FIG12 is a schematic structural diagram of a display panel formed in a portion of steps in a method for manufacturing a display panel according to an embodiment of the present application;

[0033] FIG13 is a schematic structural diagram of a display panel formed in another part of the steps in the method for manufacturing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, in addition to the process, method, system, product or equipment of the series of steps or units shown in the embodiments of the present application, other processes, methods, systems, products and equipment of this series of steps or units not clearly listed may also be included, or other steps or units inherent to these processes, methods, systems, products or equipment.

[0035] The display panel is composed of pixel driving units of different colors. Due to the material differences of the light-emitting elements in the pixel driving units, the pixel efficiency is different, which leads to differences in the black state voltage required for different pixel driving units. This problem can be improved by adjusting the threshold voltage of the driving transistor in the pixel driving unit. In order to meet the display requirements, in some embodiments, the driver chip needs to set the highest data signal (VGMP) it outputs to meet the highest black state voltage in sub-pixels of different colors, and this voltage output range is redundant for other pixel driving units. A high black state voltage will increase the power consumption of the driver chip. Therefore, in some embodiments, the display panel has the problems of high power consumption and low voltage range utilization of the data signal.

[0036] FIG1 is a circuit diagram of a pixel driving circuit provided by an embodiment of the present application. Referring to FIG1 , a pixel driving circuit includes a first pixel driving unit 100 and a second pixel driving unit 200 .

[0037] The first pixel driving unit 100 includes a first driving transistor 110 and a first light-emitting element 120. The first driving transistor 110 has a first driving current control gate 113 and a first threshold adjustment gate 111. The first driving current control gate 113 is configured to receive a first data signal, and the first threshold adjustment gate 111 is configured to receive a first adjustment signal R_BSM. The first driving transistor 110 drives the first light-emitting element 120 under the control of the first data signal and the first adjustment signal R_BSM.

[0038] The second pixel driving unit 200 includes a second driving transistor 210 and a second light-emitting element 220. The second driving transistor 210 has a second driving current control gate 213 and a second threshold adjustment gate 211. The second driving current control gate 213 is configured to receive a second data signal, and the second threshold adjustment gate 211 is configured to receive a second adjustment signal G_BSM. The second driving transistor 210 drives the second light-emitting element 220 under the control of the second data signal and the second adjustment signal G_BSM.

[0039] The first light emitting element 120 and the second light emitting element 220 emit different colors. When the first light emitting element 120 and the second light emitting element 220 display a target grayscale, the voltage values ​​of the first adjustment signal R_BSM and the second adjustment signal G_BSM are different.

[0040] For example, the driving principle of the pixel driving circuit is described by taking the first pixel driving unit 100 as an example. The source of the first driving transistor 110 is connected to the voltage ELVDD, and the drain of the first driving transistor 110 is electrically connected to the first light-emitting element 120. The first driving current control gate 113 of the first driving transistor 110 is written with a first data signal, and the magnitude of the first data signal determines the magnitude of the driving current generated by the first driving transistor 110. Taking the first driving transistor 110 as a P-type transistor as an example, if the voltage of the first data signal is negative, the greater the absolute value of the voltage of the first data signal, the greater the driving current generated by the first driving transistor 110, and the greater the brightness of the first light-emitting element 120; if the voltage of the first data signal is positive, the greater the absolute value of the voltage of the first data signal, the smaller the driving current generated by the first driving transistor 110, and the smaller the brightness of the first light-emitting element 120.

[0041] The range of the first data signal written into the first driving transistor 110 and the magnitude of the driving current generated are also related to the threshold voltage of the first driving transistor 110 itself. The first driving transistor 110 provided in the embodiment of the present application also includes a first threshold adjustment gate 111, which can adjust the magnitude of the threshold voltage of the first driving transistor 110. In practical applications, providing a voltage value to the first threshold adjustment gate 111 of the first driving transistor 110 can enable the threshold voltage of the first driving transistor 110 to reach an ideal state. For example, if the threshold voltage of the first driving transistor 110 needs to be positively biased, a voltage value that makes the threshold voltage positively biased is provided to the first threshold adjustment gate 111; in other embodiments, if the threshold voltage of the first driving transistor 110 needs to be negatively biased, a voltage value that makes the threshold voltage negatively biased is provided to the first threshold adjustment gate 111.

[0042] In the embodiment of the present application, the target grayscale refers to the grayscale corresponding to the light-emitting element in a static state (also referred to as a "standby state"). Accordingly, the voltage configured for the drive current control gate of the light-emitting element in a static state can be referred to as a "black state voltage." Optionally, grayscale 0 can be configured as the target grayscale, and the first light-emitting element 120 and the second light-emitting element 220 do not emit light at grayscale 0. Optionally, other grayscales (such as grayscale 1 or grayscale 2, etc.) can also be configured as the target grayscale.

[0043] Exemplarily, the first light-emitting element 120 is a red light-emitting element R, and the second light-emitting element 220 is a green light-emitting element G. The first driving transistor 110 and the second driving transistor 210 are both P-type transistors. The threshold voltage of a P-type transistor is a negative value. Taking the first pixel driving unit 100 as an example, the lower the voltage written to its first driving current control gate 113 (i.e., the first data voltage corresponding to the first data signal), the greater the driving current generated; and the higher the voltage written to its first driving current control gate 113, the smaller the driving current generated.

[0044] Due to the differences in the performance of the luminescent materials of light-emitting elements of different colors, the efficiency of the pixel driving units of two different colors is different, which leads to differences in the black state voltages required for the pixel driving units of the two different colors. The results of the test of a product in the embodiment of the present application show that, taking the target grayscale as grayscale 0 as an example, for the first pixel driving unit 100, the black state voltage of the first drive current control gate 113 written into the first drive transistor 110 needs to be 6.6V; while for the second pixel driving unit 200, its black state voltage needs to be 6.8V. In order to achieve the black state display of the display panel, the driver chip needs to meet the highest voltage requirement, so the highest data signal output by the driver chip is set to refer to the black state voltage (6.8V) of the second pixel driving unit 200. Such a high voltage output range is redundant for the first light-emitting element 120, which will increase the power consumption of the driver chip.

[0045] The embodiments of the present application adjust the black state voltage of the pixel driver unit by adjusting the voltage of the threshold adjustment gate. For example, by adjusting the voltage of the second adjustment signal G_BSM, the threshold voltage of the second driver transistor 210 is forward-biased, thereby reducing the black state voltage of the second pixel driver unit 200. This is because, during data writing to the driver transistor, when the threshold voltage of the driver transistor is negative, the larger its absolute value, the slower the data writing speed; and when the threshold voltage of the driver transistor is positive, the larger its absolute value, the faster the data writing speed. By adjusting the voltage of the second adjustment signal G_BSM to be different from the first adjustment signal R_BSM and the third adjustment signal B_BSM, the embodiment of the present application can make the threshold voltage of the second driver transistor 210 forward-biased, thereby accelerating the writing speed of the second data signal and facilitating the use of a smaller black state voltage to achieve a black state display of the second light-emitting element 220. Therefore, the embodiments of the present application can make the black state voltages of the first pixel driver unit 100 and the second pixel driver unit 200 tend to be consistent, thereby facilitating reducing the voltage range of the data signal output by the driver chip, improving the utilization rate of the data signal voltage range, and reducing the power consumption of the display panel.

[0046] FIG1 exemplifies the example of a first light-emitting element 120 being a red light-emitting element R and a second light-emitting element 220 being a green light-emitting element G. This is not intended to limit the present application. In other embodiments, the first light-emitting element 210 and the second light-emitting element 220 may be a red light-emitting element R and a blue light-emitting element B, respectively; or the first light-emitting element 210 and the second light-emitting element 220 may be a green light-emitting element G and a blue light-emitting element B, respectively.

[0047] FIG2 is a circuit diagram of another pixel driving circuit provided in an embodiment of the present application. Referring to FIG2 , in another embodiment of the present application, optionally, the first light-emitting element 120 is a red light-emitting element R, and the second light-emitting element 220 is a blue light-emitting element B.

[0048] Exemplarily, the first drive transistor 110 and the second drive transistor 210 are both P-type transistors. The results of a test on a product in an embodiment of the present application show that, taking the target grayscale being configured as grayscale 0 as an example, for the first pixel drive unit 100, the black state voltage of the first drive current control gate 113 written into the first drive transistor 110 needs to be 6.6V; for the second pixel drive unit 200, its black state voltage needs to be 6.4V. In order to achieve black state display of the display panel, the driver chip needs to meet the highest voltage requirement, so the highest data signal output by the driver chip is set to refer to the black state voltage (6.6V) of the first pixel drive unit 100. Such a high voltage output range is redundant for the second light-emitting element 220, which will increase the power consumption of the driver chip.

[0049] The embodiments of the present application can adjust the black-state voltage of the pixel driving unit by adjusting the voltage of the threshold adjustment gate. For example, by adjusting the voltage of the first adjustment signal R_BSM, the threshold voltage of the first driving transistor 110 is forward-biased, which can reduce the black-state voltage of the first pixel driving unit 100, thereby making the black-state voltages of the first pixel driving unit 100 and the second pixel driving unit 200 tend to be consistent, which is beneficial to reducing the voltage range of the data signal output by the driver chip, improving the utilization rate of the voltage range of the data signal, and reducing the power consumption of the display panel.

[0050] FIG3 is a circuit diagram of another pixel driving circuit provided in an embodiment of the present application. Referring to FIG3 , in another embodiment of the present application, optionally, the first light emitting element 120 is a green light emitting element G, and the second light emitting element 220 is a blue light emitting element B.

[0051] Exemplarily, the first drive transistor 110 and the second drive transistor 210 are both P-type transistors. The results of a test on a product in an embodiment of the present application show that, taking the target grayscale as grayscale 0 as an example, for the first pixel drive unit 100, the black state voltage of the first drive current control gate 113 written into the first drive transistor 110 needs to be 6.8V; for the second pixel drive unit 200, its black state voltage needs to be 6.4V. In order to achieve the black state display of the display panel, the driver chip needs to meet the highest voltage requirement, so the highest data signal output by the driver chip is set to refer to the black state voltage (6.8V) of the first pixel drive unit 100. Such a high voltage output range is redundant for the second light-emitting element 220, which will increase the power consumption of the driver chip.

[0052] The embodiments of the present application can adjust the black-state voltage of the pixel driving unit by adjusting the voltage of the threshold adjustment gate. For example, by adjusting the voltage of the first adjustment signal G_BSM, the threshold voltage of the first driving transistor 110 is forward-biased, which can reduce the black-state voltage of the first pixel driving unit 100, thereby making the black-state voltages of the first pixel driving unit 100 and the second pixel driving unit 200 tend to be consistent, which is beneficial to reducing the voltage range of the data signal output by the driver chip, improving the utilization rate of the voltage range of the data signal, and reducing the power consumption of the display panel.

[0053] It can be seen that in the embodiment of the present application, by setting the first driving transistor 110 in the first pixel driving unit 100 to include a first threshold adjustment gate 111, and the second driving transistor 210 in the second pixel driving unit 200 to include a second threshold adjustment gate 211, the voltage of the first threshold adjustment gate 111 of the first driving transistor 110 and the second threshold adjustment gate 211 of the second driving transistor 210 can be adjusted, thereby adjusting the threshold voltage of the first driving transistor 110 and the second driving transistor 210, thereby improving the performance of the display panel.

[0054] FIG4 is a circuit diagram of another pixel driving circuit provided in an embodiment of the present application. Referring to FIG4 , the pixel driving circuit optionally further includes: a third pixel driving unit 300 including a third driving transistor 310 and a third light-emitting element 320. The third driving transistor 310 has a third driving current control gate 314 and a third threshold adjustment gate 311. The third driving current control gate 314 is configured to receive a third data signal, and the third threshold adjustment gate 311 is configured to receive a third adjustment signal B_BSM. The third driving transistor 310 is controlled by the third data signal and the third adjustment signal B_BSM to drive the third light-emitting element 320.

[0055] The first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320 emit different colors. When the first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320 display a target grayscale, the voltage values ​​of at least two of the first adjustment signal R_BSM, the second adjustment signal G_BSM, and the third adjustment signal B_BSM are different. For example, the first adjustment signal R_BSM and the second adjustment signal G_BSM are different, and the third adjustment signal B_BSM is the same as the first adjustment signal R_BSM; for another example, the first adjustment signal R_BSM and the second adjustment signal G_BSM are different, and the third adjustment signal B_BSM is the same as the second adjustment signal G_BSM; for another example, the second adjustment signal G_BSM and the third adjustment signal B_BSM are different, and the first adjustment signal R_BSM and the second adjustment signal G_BSM are the same; for another example, the second adjustment signal G_BSM and the third adjustment signal B_BSM are different, and the first adjustment signal R_BSM and the second adjustment signal G_BSM are the same; for another example, the second adjustment signal G_BSM and the third adjustment signal For example, the first adjustment signal R_BSM and the third adjustment signal B_BSM are different, and the first adjustment signal R_BSM and the third adjustment signal B_BSM are the same; for another example, the first adjustment signal R_BSM and the third adjustment signal B_BSM are different, and the second adjustment signal G_BSM and the first adjustment signal R_BSM are the same; for another example, the first adjustment signal R_BSM and the third adjustment signal B_BSM are different, and the second adjustment signal G_BSM and the third adjustment signal B_BSM are the same; for another example, the first adjustment signal R_BSM, the second adjustment signal G_BSM and the third adjustment signal B_BSM are different from each other.

[0056] In some embodiments, when the first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320 are displayed at a target grayscale, the voltage values ​​of the first data signal, the second data signal, and the third data signal are the same, and the voltage values ​​of at least two of the first adjustment signal R_BSM, the second adjustment signal G_BSM, and the third adjustment signal B_BSM are different.

[0057] For example, the driving principle of the pixel driving circuit is described by taking the first pixel driving unit 100 as an example. The source of the first driving transistor 110 is connected to the voltage ELVDD, and the drain of the first driving transistor 110 is electrically connected to the first light-emitting element 120. The first driving current control gate 113 of the first driving transistor 110 is written with a first data signal, and the magnitude of the first data signal determines the magnitude of the driving current generated by the first driving transistor 110. Taking the first driving transistor 110 as a P-type transistor as an example, if the voltage of the first data signal is negative, the greater the absolute value of the voltage of the first data signal, the greater the driving current generated by the first driving transistor 110, and the greater the brightness of the first light-emitting element 120; if the voltage of the first data signal is positive, the greater the absolute value of the voltage of the first data signal, the smaller the driving current generated by the first driving transistor 110, and the smaller the brightness of the first light-emitting element 120.

[0058] The range of the first data signal written into the first driving transistor 110 and the magnitude of the driving current generated are also related to the threshold voltage of the first driving transistor 110 itself. The first driving transistor 110 provided in the embodiment of the present application also includes a first threshold adjustment gate 111, which can adjust the magnitude of the threshold voltage of the first driving transistor 110. In practical applications, the voltage value provided to the first threshold adjustment gate 111 of the first driving transistor 110 can enable the threshold voltage of the first driving transistor 110 to reach an ideal state. For example, if the threshold voltage of the first driving transistor 110 needs to be positively biased, a voltage value that makes the threshold voltage positively biased is provided to the first threshold adjustment gate 111; in other embodiments, if the threshold voltage of the first driving transistor 110 needs to be negatively biased, a voltage value that makes the threshold voltage negatively biased is provided to the first threshold adjustment gate 111.

[0059] In the embodiment of the present application, the target grayscale refers to the grayscale corresponding to the light-emitting element in a static state (also referred to as a "standby state"). Accordingly, the voltage configured for the drive current control gate of the light-emitting element in a static state can be referred to as a "black state voltage". Optionally, the 0th grayscale can be configured as the target grayscale, and the first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320 do not emit light at the 0th grayscale. Optionally, other grayscales (such as the 1st grayscale or the 2nd grayscale, etc.) can also be configured as the target grayscale.

[0060] Exemplarily, the first light-emitting element 120 is a red light-emitting element R, the second light-emitting element 220 is a green light-emitting element G, and the third light-emitting element 320 is a blue light-emitting element B. The first driving transistor 110, the second driving transistor 210, and the third driving transistor 310 are all P-type transistors. The threshold voltage of the P-type transistor is a negative value. Taking the first pixel driving unit 100 as an example, the lower the voltage written to its first driving current control gate 113 (that is, the first data voltage corresponding to the first data signal), the greater the driving current it generates; the higher the voltage written to its first driving current control gate 113, the smaller the driving current it generates. Due to the differences in the performance of the luminescent materials of light-emitting elements of different colors, the efficiency of the pixel driving units of the three colors is different, which leads to differences in the black state voltages required for the pixel driving units of the three colors. The results of testing a product in accordance with an embodiment of the present application show that, for example, with the target grayscale configured as grayscale 0, for the first pixel driver unit 100, the black-state voltage written to the first drive current control gate 113 of the first driver transistor 110 requires 6.6V; for the second pixel driver unit 200, its black-state voltage requires 6.8V; and for the third pixel driver unit 300, its black-state voltage requires 6.4V. To achieve a black-state display on the display panel, the driver chip must meet the highest voltage requirement. Therefore, the highest data signal output by the driver chip is set to reference the black-state voltage (6.8V) of the second pixel driver unit 200. However, such a high voltage output range is redundant for the first light-emitting element 120 and the third light-emitting element 320, which will increase the power consumption of the driver chip.

[0061] The embodiments of the present application can adjust the black state voltage of the pixel driving unit by adjusting the voltage of the threshold adjustment gate. For example, by adjusting the voltage of the second adjustment signal G_BSM so that the threshold voltage of the second driving transistor 210 is positively biased, the black state voltage of the second pixel driving unit 200 can be reduced. This is because, during the process of writing data to the driving transistor, when the threshold voltage of the driving transistor is negative, the larger its absolute value, the slower the data writing speed; when the threshold voltage of the driving transistor is positive, the larger its absolute value, the faster the data writing speed. The embodiments of the present application adjust the voltage of the second adjustment signal G_BSM to be different from the first adjustment signal R_BSM and the third adjustment signal B_BSM, so that the threshold voltage of the second driving transistor 210 is positively biased, thereby accelerating the writing speed of the second data signal, which is conducive to using a smaller black state voltage to achieve black state display of the second light-emitting element 220. Therefore, the embodiment of the present application can make the black state voltages of the first pixel driving unit 100, the second pixel driving unit 200 and the third pixel driving unit 300 tend to be consistent, which is beneficial to reducing the voltage range of the data signal output by the driving chip, improving the utilization rate of the voltage range of the data signal, and reducing the power consumption of the display panel.

[0062] Figure 5 is a circuit diagram of another pixel driving circuit provided in an embodiment of the present application. Referring to Figure 5, taking the first pixel driving unit 100 as an example, an embodiment of the present application provides a circuit structure. In one embodiment of the present application, optionally, the first pixel driving unit 100 includes a first driving transistor 110, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst. The pixel driving circuit also includes a first scan line providing a first scan signal Scan1, a second scan line providing a second scan signal Scan2, a third scan line providing a third scan signal Scan3, a light emitting control signal line providing a light emitting control signal EM, a reference voltage signal line providing a reference voltage signal Vrefn, and a data line providing a data signal Data.

[0063] The second transistor T2 is a data writing transistor, the third transistor T3 is a threshold compensation transistor, the fourth transistor T4 is a gate initialization transistor, the fifth transistor T5 and the sixth transistor T6 are light emission control transistors, and the seventh transistor T7 is an anode initialization transistor. Exemplarily, the above transistors are all P-type transistors.

[0064] The gate of the second transistor T2 is connected to the second scanning signal Scan2, the first electrode of the second transistor T2 is connected to the source S of the first driving transistor 110, and the second electrode of the second transistor T2 is connected to the data signal Data; the gate of the third transistor T3 is connected to the second scanning signal Scan2, the first electrode of the third transistor T3 is connected to the drain D of the first driving transistor 110, and the second electrode of the third transistor T3 is connected to the first driving current control gate 113 of the first driving transistor 110; the gate of the fourth transistor T4 is connected to the first scanning signal Scan1, the first electrode of the fourth transistor T4 is connected to the first driving current control gate 113 of the first driving transistor 110, and the second electrode of the fourth transistor T4 is connected to the first driving current control gate 113 of the first driving transistor 110. The second electrode is connected to the reference voltage signal Vrefn; the gate of the fifth transistor T5 is connected to the light-emitting control signal EM, the first electrode of the fifth transistor T5 is connected to the source S of the first driving transistor 110, and the second electrode of the fifth transistor T5 is connected to the voltage ELVDD; the gate of the sixth transistor T6 is connected to the light-emitting control signal EM, the first electrode of the sixth transistor T6 is connected to the drain D of the first driving transistor 110, and the second electrode of the sixth transistor T6 is connected to the anode of the first light-emitting element 120; the gate of the seventh transistor T7 is connected to the third scanning signal Scan3, the first electrode of the seventh transistor T7 is connected to the anode of the first light-emitting element 120, and the second electrode of the seventh transistor T7 is connected to the reference voltage signal Vrefn.

[0065] Exemplarily, the driving process of the first pixel driving unit 100 includes a gate initialization phase, a data writing phase, an anode initialization phase, and a light emitting phase.

[0066] During the gate initialization phase, the emission control signal EM, the second scan signal Scan2, and the third scan signal Scan3 are all at a high level, while the first scan signal Scan1 is at a low level. The emission control signal EM turns off the fifth transistor T5 and the sixth transistor T6; the second scan signal Scan2 turns off the second transistor T2 and the third transistor T3; and the third scan signal Scan3 turns off the seventh transistor T7. The first scan signal Scan1 turns on the fourth transistor T4, and the reference voltage signal Vrefn initializes the first drive current control gate 113 of the first drive transistor 110, ensuring that the first drive transistor 110 is in the on state during the data writing phase.

[0067] During the data writing phase, the emission control signal EM, the first scan signal Scan1, and the third scan signal Scan3 are all at a high level, and the second scan signal Scan2 is at a low level. The emission control signal EM controls the fifth transistor T5 and the sixth transistor T6 to be turned off; the first scan signal Scan1 controls the fourth transistor T4 to be turned off; and the third scan signal Scan3 controls the seventh transistor T7 to be turned off. The second scan signal Scan2 controls the second transistor T2 and the third transistor T3 to be turned on, thereby writing the data signal Data into the first drive current control gate 113 of the first drive transistor 110 via the source S and drain D of the first drive transistor 110. Furthermore, the first adjustment signal R_BSM is written into the first threshold adjustment gate 111 of the first drive transistor 110 to adjust the threshold voltage of the first drive transistor 110.

[0068] During the anode initialization phase, the emission control signal EM, the first scan signal Scan1, and the second scan signal Scan2 are all at a high level, while the third scan signal Scan3 is at a low level. The emission control signal EM turns off the fifth and sixth transistors T5 and T6; the first scan signal Scan1 turns off the fourth transistor T4; and the second scan signal Scan2 turns off the second and third transistors T2 and T3. The third scan signal Scan3 turns on the seventh transistor T7, allowing the reference voltage signal Vrefn to initialize the anode of the first light-emitting element 120.

[0069] During the light-emitting phase, the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 are all at a high level. The light-emitting control signal EM is at a low level or exhibits periodic changes, which is not limited in this application. The first scan signal Scan1 controls the fourth transistor T4 to be disconnected; the second scan signal Scan2 controls the second transistor T2 and the third transistor T3 to be disconnected; and the third scan signal Scan3 controls the seventh transistor T7 to be disconnected. When the light-emitting control signal EM controls the fifth transistor T5 and the sixth transistor T6 to be turned on, the first driving transistor 110 generates a driving current, which flows into the anode of the first light-emitting element 120, driving the first light-emitting element 120 to emit light.

[0070] The first adjustment signal R_BSM may be provided continuously throughout the entire driving process, or may be provided during the data writing phase and the light emitting phase, which is not limited in this application.

[0071] Figure 6 is a circuit diagram of another pixel driving circuit provided in an embodiment of the present application. Referring to Figure 6, unlike the aforementioned embodiment, at least two of the first driving transistor 110, the second driving transistor 210, and the third driving transistor 310 are N-type transistors. Optionally, the first driving transistor 110, the second driving transistor 210, and the third driving transistor 310 are all N-type transistors to simplify the preparation process. In contrast to P-type transistors, the threshold voltage of N-type transistors is positive, and the black state voltage of each pixel driving unit is negative. Exemplarily, the first light-emitting element 120 is a red light-emitting element R, the second light-emitting element 220 is a green light-emitting element G, and the third light-emitting element 320 is a blue light-emitting element B. When the first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320 are displayed at the target grayscale, the voltage of the second adjustment signal G_BSM is different from the voltage of the first adjustment signal R_BSM and the third adjustment signal B_BSM, and the voltage difference between the second adjustment signal G_BSM and the voltages of the first adjustment signal R_BSM and the third adjustment signal B_BSM is also relatively large. By adjusting the threshold voltage of the second pixel driving unit 200 to a negative bias, the black state voltage of the second pixel driving unit 200 can be raised. In this way, the black state voltages of the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300 are made consistent, which is beneficial to reducing the voltage range of the data signal output by the driver chip, so that the voltage range utilization of the data signal is maximized, and the power consumption of the display panel is reduced.

[0072] In another embodiment of the present application, optionally, the voltage values ​​of the first adjustment signal R_BSM, the second adjustment signal G_BSM, and the third adjustment signal B_BSM cause the threshold voltages of the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300 to be positively biased. This is because, for N-type driving transistors, due to the process reasons of the driving transistors of indium gallium zinc oxide (IGZO), the fluctuation of the threshold voltage thereof is large, and there is a situation where the threshold voltage is less than zero. In some embodiments, the pixel driving circuit is capable of performing threshold voltage compensation on the N-type driving transistor, but the prerequisite for such compensation is that the threshold voltage of the driving transistor is a positive value. If the threshold voltage of the driving transistor is less than zero, the threshold voltage compensation will not be performed, resulting in the display panel having the problem of uneven display. Therefore, in the embodiment of the present application, the voltage values ​​of the first adjustment signal R_BSM, the second adjustment signal G_BSM, and the third adjustment signal B_BSM are set so that the threshold voltages of the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300 are all positively biased, thereby avoiding the situation where the threshold voltage of the N-type driving transistor is less than zero, thereby ensuring the threshold compensation effect.

[0073] In the aforementioned embodiment, to achieve low power consumption of the display panel, the threshold voltage of the second pixel driving unit 200 needs to be negatively biased; and to ensure that the threshold voltage is greater than zero, the threshold voltage of the pixel driving unit needs to be positively biased. Both the negative and positive biases are relative to the state before threshold voltage adjustment. In practice, when the voltage of the threshold adjustment gate of the driving transistor is fixed, the threshold voltage of the driving transistor is determined accordingly. By selecting an appropriate threshold adjustment gate voltage, it is possible to ensure that the threshold voltage of the driving transistor is greater than zero and adjust the black-state voltage of the pixel driving unit so that the black-state voltages of different pixel driving units are consistent. In some embodiments, when the first light-emitting element 120, the second light-emitting element 220 and the third light-emitting element 320 are displayed at the target gray scale, in order to maximize the voltage range utilization of the data signal (that is, at this time the voltage values ​​of the first data signal, the second data signal and the third data signal are the same), it is necessary to set the voltage values ​​of at least two of the first adjustment signal R_BSM, the second adjustment signal G_BSM and the third adjustment signal B_BSM to be different, which means: the voltage of the first adjustment signal R_BSM can be set to be different from the voltages of the second adjustment signal G_BSM and the third adjustment signal B_BSM; or, the voltage of the second adjustment signal G_BSM can be set to be different from the voltages of the first adjustment signal R_BSM and the third adjustment signal B_BSM; or, the voltage of the third adjustment signal B_BSM can be set to be different from the voltages of the first adjustment signal R_BSM and the second adjustment signal G_BSM. In some other embodiments, when the first light-emitting element 120, the second light-emitting element 220 and the third light-emitting element 320 are displayed at the target gray scale, in order to maximize the voltage range utilization of the data signal (i.e., the voltage values ​​of the first data signal, the second data signal and the third data signal are the same at this time), it is necessary to set the voltage values ​​of the first adjustment signal R_BSM, the second adjustment signal G_BSM and the third adjustment signal B_BSM to be different from each other.

[0074] In the above embodiment, the target grayscale is configured as grayscale 0 for illustration. This is because the voltage corresponding to grayscale 0 determines the maximum voltage value of the data voltage, but this is not a limitation of the present application. In actual applications, the target grayscale can be any grayscale value among all displayed grayscales.

[0075] Continuing with FIG. 2 and FIG. 6 , optionally, the first light-emitting element 120 has a first cathode configured with a first cathode signal R_ELVSS, the second light-emitting element 220 has a second cathode configured with a second cathode signal G_ELVSS, and the third light-emitting element 320 has a third cathode configured with a third cathode signal B_ELVSS. At least two of the first cathode signal R_ELVSS, the second cathode signal G_ELVSS, and the third cathode signal B_ELVSS have different voltage values.

[0076] As can be seen from the above analysis, the performance of luminescent materials of different colors varies, and the light-on voltage, black-state voltage, and other characteristics of light-emitting elements of different colors vary, resulting in different efficiency of the pixel driver units and display panel uniformity issues. The embodiments of the present application compensate for the voltage differences among the first, second, and third light-emitting elements 120, 220, and 320 by setting different voltage values ​​for at least two of the first, second, and third cathode signals R_ELVSS, G_ELVSS, and B_ELVSS. This balances the efficiency of the first, second, and third pixel driver units 100, 200, and 300, thereby improving the uniformity of the display panel.

[0077] Optionally, the voltage of the second cathode signal G_ELVSS is different from the voltages of the first cathode signal R_ELVSS and the third cathode signal B_ELVSS; or, the voltage of the first cathode signal R_ELVSS is different from the voltages of the second cathode signal G_ELVSS and the third cathode signal B_ELVSS; or, the voltage of the third cathode signal B_ELVSS is different from the voltages of the first cathode signal R_ELVSS and the second cathode signal G_ELVSS; or, the voltage values ​​of the first cathode signal R_ELVSS, the second cathode signal G_ELVSS and the third cathode signal B_ELVSS are different from each other.

[0078] In practical applications, the voltages of the first adjustment signal R_BSM, the second adjustment signal G_BSM, and the third adjustment signal B_BSM can be set as needed, and are not limited in this application. For example, they can be determined by performing multiple experiments, or by mathematical modeling or simulation, as long as the black state voltages of the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300 tend to be consistent.

[0079] In summary, in the embodiment of the present application, by setting the luminous colors of the first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320 to be different from each other, when the first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320 are displayed at the target grayscale, the voltage values ​​of at least two of the first adjustment signal R_BSM, the second adjustment signal G_BSM, and the third adjustment signal B_BSM are different, so that the threshold voltages of the first driving transistor 110, the second driving transistor 210, and the third driving transistor 310 can be adjusted, so that the black state voltages of the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300 tend to be consistent, which is beneficial to reducing the voltage range of the data signal output by the driving chip, improving the utilization rate of the voltage range of the data signal, and reducing the power consumption of the display panel.

[0080] The embodiment of the present application further provides a display panel, which includes a pixel driving circuit as provided in any embodiment of the present application, and the technical principles and effects thereof are similar and will not be described in detail.

[0081] Figure 7 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 8 is a schematic diagram of the cross-sectional structure of the first pixel driver unit along line AA in Figure 7. Figure 9 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application. The first pixel driver unit 100 and the second pixel driver unit 200 are configured in the same manner. Figure 8 uses the cross-sectional structure of the first pixel driver unit 100 along line AA as an example for illustration. Referring to Figures 7, 8, and 9, the display panel further includes a first metal layer, a light-emitting functional layer, and an isolation layer.

[0082] The first metal layer 11 , the first threshold adjustment gate 111 and the second threshold adjustment gate 211 (not shown in FIG. 8 ) are electrically isolated and disposed in the first metal layer 11 .

[0083] The light-emitting functional layer is provided on one side of the first metal layer 11 , and a portion of the first light-emitting element 120 and a portion of the second light-emitting element 220 (not shown in FIG. 8 ) are provided in the light-emitting functional layer.

[0084] The isolation layer is disposed on one side of the first metal layer 11 and is configured to separate the first light emitting element 120 from the second light emitting element 220 . The isolation layer includes a first gate isolation column 31 and a second gate isolation column 312 (not shown in FIG. 8 ).

[0085] The first gate isolation pillar 31 is coupled to the first threshold adjustment gate 111 and is configured with the first adjustment signal R_BSM. The second gate isolation pillar 312 is coupled to the second threshold adjustment gate 211 and is configured with the second adjustment signal G_BSM. Exemplarily, the first gate isolation pillar 31 is electrically connected to the first threshold adjustment gate 111 across the membrane layer via a cross-line connection line 16.

[0086] From the foregoing analysis, it can be seen that, based on the structure of the display panel, the embodiment of the present application can, when the first light-emitting element 120 and the second light-emitting element 220 display at the target grayscale, have the same voltage value of the first data signal and the second data signal, and different voltage values ​​of the first adjustment signal R_BSM and the second adjustment signal G_BSM, thereby making the black state voltages of the first pixel driving unit 100 and the second pixel driving unit 200 tend to be consistent, which is beneficial to reducing the voltage range of the data signal output by the driving chip, improving the utilization rate of the voltage range of the data signal, and reducing the power consumption of the display panel.

[0087] In addition, the embodiments of the present application further improve the performance of the driver transistors by improving the structures of the first driver transistor 110 and the second driver transistor 210. For example, the first gate isolation pillar 31 of the isolation layer is used to carry the first adjustment signal R_BSM, which helps reduce the resistance of the first adjustment signal R_BSM during transmission. Similarly, the second threshold adjustment gate 211 is added to the second driver transistor 210, and the second gate isolation pillar 312 of the isolation layer is used to carry the second adjustment signal G_BSM, which helps reduce the resistance of the second adjustment signal G_BSM during transmission.

[0088] Continuing to refer to FIG7 , optionally, the pixel driving circuit further includes a third pixel driving unit 300. Referring to the structure of the first pixel driving unit 100 in FIG8 , the configuration of the third pixel driving unit 300 is similar to that of the first pixel driving unit 100. The third pixel driving unit 300 includes a third driving transistor 310 and a third light-emitting element 320. The third driving transistor 310 has a third driving current control gate 314 and a third threshold adjustment gate 311. The third driving current control gate 314 is configured to receive a third data signal, and the third threshold adjustment gate 311 is configured to receive a third adjustment signal B_BSM. The third driving transistor 310 drives the third light-emitting element 320 under the control of the third data signal and the third adjustment signal B_BSM, wherein: the third threshold adjustment gate 311 and the third light-emitting element 320 are connected. The first threshold adjustment gate 111 is electrically isolated, and the third threshold adjustment gate 311 is electrically isolated from the second threshold adjustment gate 211, and the third threshold adjustment gate 311 is arranged in the first metal layer 11; a portion of the third light-emitting element 320 is arranged in the light-emitting functional layer; the isolation layer is also arranged to isolate the third light-emitting element 320 from the first light-emitting element 120 and the second light-emitting element 220, and the isolation layer includes a third gate isolation column 313, the third gate isolation column 313 is coupled to the third threshold adjustment gate 311, and is configured with a third adjustment signal B_BSM.

[0089] Thus, the embodiments of the present application enable the first, second, and third data signals to have the same voltage value when the first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320 display a target grayscale, and at least two of the first adjustment signal R_BSM, the second adjustment signal G_BSM, and the third adjustment signal B_BSM have different voltage values, thereby making the black state voltages of the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300 tend to be consistent, which is beneficial for reducing the voltage range of the data signal output by the driver chip, improving the utilization rate of the data signal voltage range, and reducing the power consumption of the display panel. In addition, the embodiments of the present application also improve the performance of the driving transistor by improving the structure of the third driving transistor 310. For example, a third threshold adjustment gate 311 is added to the third driving transistor 310, and a third gate isolation column 313 of the isolation layer is used to carry the third adjustment signal B_BSM, which is beneficial for reducing the resistance of the third adjustment signal B_BSM during transmission.

[0090] Such a configuration is beneficial to improving the voltage uniformity of the first adjustment signal R_BSM received by the first pixel driving unit 100, improving the voltage uniformity of the second adjustment signal G_BSM received by the second pixel driving unit 200, and improving the voltage uniformity of the third adjustment signal B_BSM received by the third pixel driving unit 300, thereby improving the display uniformity of the display panel.

[0091] Continuing to refer to Figures 7, 8 and 9, optionally, the display panel also includes a cathode layer 18, which is arranged on the side of the light-emitting functional layer away from the first metal layer 11, and the isolation layer also includes a first cathode isolation column 321, a second cathode isolation column 322 (not shown in Figure 8) and a third cathode isolation column 323 (not shown in Figure 8), wherein: the first light-emitting element 120 has a first cathode 23, the second light-emitting element 220 has a second cathode, and the third light-emitting element 320 has a third cathode, and the first cathode 23, the second cathode and the third cathode are all arranged in the cathode layer 18 and electrically isolated; the first cathode isolation column 321 is coupled to the first cathode 23 and is configured with a first cathode signal, the second cathode isolation column 322 is coupled to the second cathode and is configured with a second cathode signal, and the third cathode isolation column 323 is coupled to the third cathode and is configured with a third cathode signal. Such a setting is conducive to setting the voltage values ​​of at least two of the first cathode signal, the second cathode signal and the third cathode signal to be different, which can compensate for the voltage difference between the first light-emitting element 120, the second light-emitting element 220 and the third light-emitting element 320, thereby balancing the efficiency of the first pixel driving unit 100, the second pixel driving unit 200 and the third pixel driving unit 300, and improving the uniformity of the display panel.

[0092] It should be understood that the functions of the above-mentioned first gate isolation column 31, second gate isolation column 312 and third gate isolation column 313 are to isolate the first light-emitting element 120, the second light-emitting element 220 and the third light-emitting element 320, and carry the corresponding adjustment signal; correspondingly, the functions of the first cathode isolation column 321, the second cathode isolation column 322 and the third cathode isolation column 323 are to isolate the first light-emitting element 120, the second light-emitting element 220 and the third light-emitting element 320, and carry the corresponding cathode signal.

[0093] Optionally, the first gate isolation pillar 31, the second gate isolation pillar 312, the third gate isolation pillar 313, the first cathode isolation pillar 321, the second cathode isolation pillar 322, and the third cathode isolation pillar 323 are an integrated structure. For example, the cross-sectional shape of the integrated structure can be a trapezoid with a larger top and a smaller bottom. This arrangement facilitates the preparation of the isolation pillars. Preferably, the first gate isolation pillar 31, the second gate isolation pillar 312, the third gate isolation pillar 313, the first cathode isolation pillar 321, the second cathode isolation pillar 322, and the third cathode isolation pillar 323 can be prepared using the same process. Optionally, the first gate isolation pillar 31, the second gate isolation pillar 312, the third gate isolation pillar 313, the first cathode isolation pillar 321, the second cathode isolation pillar 322, and the third cathode isolation pillar 323 can also be a layered structure, which is not limited in this application.

[0094] Continuing to refer to FIG. 7 and FIG. 8 , the display panel may optionally further include other film layers, such as an active layer, a second metal layer, a third metal layer, a fourth metal layer, and an anode metal layer. Insulating layers (such as a first insulating layer 41 , a second insulating layer 42 , a third insulating layer 43 , and a fourth insulating layer 44 ) are provided between the film layers.

[0095] Taking the first pixel driving unit 100 as an example, the semiconductor 12 of the first driving transistor 110 is provided in the active layer, and the first driving current control gate 113 is provided in the second metal layer. In this embodiment, the first threshold adjustment gate 111 is located at the bottom of the semiconductor 12, which can also be called the bottom gate; the first driving current control gate 113 is located at the top of the semiconductor 12, which can also be called the top gate. The third metal layer is provided with a capacitor plate 14. For example, the capacitor plate 14 and the first driving current control gate 113 are overlapped to form a storage capacitor. The fourth metal layer is provided with the source and drain 15 of the first driving transistor 110, and the source and drain 15 are electrically connected to the semiconductor 12. The anode metal layer is provided with the anode 21 of the first light-emitting element 120, and the light-emitting functional layer 22 and cathode 23 of the first light-emitting element 120 are also provided on the anode 21. Exemplarily, the anode 21 is electrically connected to the source and drain 15 of the first driving transistor 110 , and the driving current generated by the first driving transistor 110 is transmitted to the anode 21 . Under the action of the voltage of the anode 21 and the voltage of the cathode 23 , the light-emitting functional layer 22 emits light.

[0096] Optionally, the first gate isolation column 31, the second gate isolation column 312 and the third gate isolation column 313, the first cathode isolation column 321, the second cathode isolation column 322 and the third cathode isolation column 323 can be used to realize the whole-surface evaporation of the light-emitting material. For example, taking the first pixel driving unit 100 as an example, after the array film layer provided with the first driving transistor 110 is prepared, an anode metal layer is formed on the array film layer, and patterned to form an anode 21, and the anode 21 is electrically connected to the source and drain 15 of the first driving transistor 110; a seventh insulating layer 52 (i.e., a pixel definition layer) and an isolation layer are prepared on the anode metal layer, and the isolation layer is patterned to form a first gate isolation column 31 and a first cathode isolation column 321 that are larger at the top and smaller at the bottom; the seventh insulating layer 52 (i.e., a pixel definition layer) is patterned, a pixel opening is formed on the anode 21, and the first light-emitting material is evaporated in the pixel opening; and then the first cathode material is evaporated on the first light-emitting material.

[0097] The first light-emitting material and the first cathode material are evaporated in a whole layer. The first light-emitting material and the first cathode material are evaporated in each pixel opening (including the pixel openings corresponding to the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300). Since the shape of the first cathode isolation column 321 is larger at the top and smaller at the bottom, the material evaporated into two adjacent pixel openings is disconnected by the first cathode isolation column 321. At the same time, the edge portion of the cathode 23 is electrically connected to the first cathode isolation column 321. The first light-emitting material and the first cathode material in the pixel openings corresponding to the second pixel driving unit 200 and the third pixel driving unit 300 are removed. At this point, the evaporation of the first light-emitting material and the first cathode material is completed.

[0098] The processes of evaporating the light-emitting material and the cathode material in the pixel openings of the second pixel driving unit 200 and the third pixel driving unit 300 are similar and will not be described in detail.

[0099] Thus, using the display panel provided by the embodiment of the present application, when performing vapor deposition on the light-emitting elements, a full-layer vapor deposition process can be employed, eliminating the need for a fine mask, thereby reducing the manufacturing cost of the display panel. Furthermore, using the embodiment of the present application, no fine mask is required, and thus, the first gate spacer 31 and the first cathode spacer 321 do not need to support the fine mask. Therefore, the size and position of the first gate spacer 31 and the first cathode spacer 321 can be adjusted as needed.

[0100] Continuing to refer to FIG8 , there are various ways to set the insulating layer between the film layers, which are described below but are not intended to limit the present application.

[0101] The material of semiconductor 12 can be amorphous silicon (a-Si), polycrystalline silicon (P-Si), or oxide. For example, if semiconductor 12 is low-temperature polysilicon (LTPS), a P-type driver transistor can be formed; if semiconductor 12 is indium gallium zinc oxide (IGZO), an N-type driver transistor can be formed. Whether it is a P-type driver transistor or an N-type driver transistor, optimization can be achieved by adjusting its threshold and gate voltage.

[0102] In one embodiment, a first insulating layer 41 is optionally provided between the first metal layer 11 and the active layer. The first insulating layer 41 serves as a substrate and is configured to support the film layer thereon. The substrate material can be an organic material, such as polyimide (PI), or an inorganic material, such as glass. For example, the film layer below the first metal layer 11 is also a substrate, that is, the first metal layer 11 is disposed within the substrate film layer.

[0103] In one embodiment, a second insulating layer 42 is optionally provided between the active layer and the second metal layer. The second insulating layer 42 may also be referred to as a gate insulating layer, forming the insulating layer portion of the driving transistor. The material of the second insulating layer 42 may be an inorganic material, such as silicon nitride (SiN) and / or silicon monoxide (SiO).

[0104] In one embodiment, a third insulating layer 43 is optionally provided between the second metal layer and the third metal layer. The third insulating layer 43 may also be referred to as an intermediate insulating layer, forming an intermediate dielectric layer of the capacitor. The material of the third insulating layer 43 may be an inorganic material, such as SiN and / or SiO.

[0105] In one embodiment, optionally, a fourth insulating layer 44 is provided between the third metal layer and the fourth metal layer. The material of the fourth insulating layer may be an inorganic material, such as SiN and / or SiO.

[0106] In one embodiment, optionally, a fifth insulating layer 45 is further provided between the fourth insulating layer 44 and the fourth metal layer. The material of the fifth insulating layer 45 may be an organic material, which can isolate the third metal layer and the fourth metal layer while also playing a certain flattening role.

[0107] In one embodiment, optionally, a sixth insulating layer 51 is provided between the fourth metal layer and the anode metal layer. The sixth insulating layer 51 can flatten the surface of the fourth metal layer while isolating the fourth metal layer and the anode metal layer, which is beneficial to the flatness of the film layer during the subsequent preparation of the light-emitting element and optimizes the light-emitting effect of the light-emitting element.

[0108] In one embodiment, optionally, a seventh insulating layer 52 is further provided on the anode metal layer. The seventh insulating layer 52 may also be referred to as a pixel definition layer, which can define the size of the pixel opening while isolating the anode metal layer and the isolation layer.

[0109] In one embodiment, optionally, an eighth insulating layer 53 is further provided on the isolation layer, and the eighth insulating layer 53 covers the cathode 23 and can isolate the light-emitting element; the eighth insulating layer 53 is also filled between the first gate isolation column 31 and the first cathode isolation column 321, and can isolate the first gate isolation column 31 and the first cathode isolation column 321.

[0110] Due to the shape characteristics of the first gate isolation pillar 31 and the first cathode isolation pillar 321, the space between the first gate isolation pillar 31 and the first cathode isolation pillar 321 is smaller at the top and larger at the bottom. Therefore, the eighth insulating layer 53 may not completely fill this space during deposition. This is permitted. With improved processing, the eighth insulating layer 53 may also completely fill this space. Such situations are within the scope of protection of this application.

[0111] Continuing with FIG8 , in one embodiment of the present application, the first gate isolation pillar 31 and the first cathode isolation pillar 321 are optionally integrally provided. For example, using the first gate isolation pillar 31 as an example, the first gate isolation pillar 31 can be formed by a lift-off process to form a larger top and smaller bottom. For example, a negative photoresist is applied, and then exposed and developed to form an opening at the location of the first gate isolation pillar 31. Metal is then evaporated within the opening, and the remaining photoresist is removed to form the first gate isolation pillar 31 with a larger top and smaller bottom.

[0112] In one embodiment, optionally, a sealing layer 61 and an encapsulation layer 62 are further provided on the eighth insulating layer 53. Exemplarily, the sealing layer 61 is formed by inkjet printing, and the encapsulation layer 62 is formed by chemical vapor deposition.

[0113] Optionally, the pixel driving circuit includes a plurality of first pixel driving units 100, a plurality of second pixel driving units 200, and a plurality of third pixel driving units 300. FIG9 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application. Referring to FIG9 , the first threshold adjustment gates 111 in the plurality of first pixel driving units 100 are coupled via a common first gate isolation column 31, the second threshold adjustment gates 211 in the plurality of second pixel driving units 200 are coupled via a common second gate isolation column 312, and the third threshold adjustment gates 311 in the plurality of third pixel driving units 300 are coupled via a common third gate isolation column 313.

[0114] With this arrangement, the same adjustment voltage can be provided to sub-pixels of the same color, thereby further reducing the number of signal lines while ensuring the display effect of the display panel.

[0115] 9 , optionally, multiple first pixel driving units 100 are arranged into multiple columns, multiple second pixel driving units 200 are arranged into multiple columns, and multiple third pixel driving units 300 are arranged into multiple columns, wherein the first threshold adjustment gates 111 in the first pixel driving units 100 in the same column are coupled via the same first gate isolation column 31, the second threshold adjustment gates 211 in the second pixel driving units 200 in the same column are coupled via the same second gate isolation column 312, and the third threshold adjustment gates 311 in the third pixel driving units 300 in the same column are coupled via the same third gate isolation column 313.

[0116] 9 , optionally, the first cathodes in the plurality of first pixel driving units 100 are coupled via the same first cathode isolation column 321, the second cathodes in the plurality of second pixel driving units 200 are coupled via the same second cathode isolation column 322, and the third cathodes in the plurality of third pixel driving units 300 are coupled via the same third cathode isolation column 323. With this arrangement, the same cathode voltage can be provided to sub-pixels of the same color, thereby further reducing the number of signal lines while ensuring the display quality of the display panel.

[0117] Continuing to refer to Figure 9, optionally, multiple first pixel driving units 100 are arranged into multiple columns, multiple second pixel driving units 200 are arranged into multiple columns, and multiple third pixel driving units 300 are arranged into multiple columns, wherein the first cathodes in the first pixel driving units 100 in the same column are coupled through the same first cathode isolation column 321, the second cathodes in the second pixel driving units 200 in the same column are coupled through the same second cathode isolation column 322, and the third cathodes in the third pixel driving units 300 in the same column are coupled through the same third cathode isolation column 323.

[0118] Continuing to refer to Figures 8 and 9, optionally, the first cathode isolation column 321 surrounds the first pixel driving unit 100, and the first gate isolation column 31 is located on the periphery of the first cathode isolation column 321; the second cathode isolation column 322 surrounds the second pixel driving unit 200, and the second gate isolation column 312 is located on the periphery of the second cathode isolation column 322; the third cathode isolation column 323 surrounds the third pixel driving unit 300, and the third gate isolation column 313 is located on the periphery of the third cathode isolation column 323.

[0119] Optionally, the first gate isolation column 31 is closer to the first pixel driving unit 100 , the second gate isolation column 312 is closer to the second pixel driving unit 200 , and the third gate isolation column 313 is closer to the third pixel driving unit 300 , so as to simplify the wiring.

[0120] In an array, rows and columns are relative concepts. Generally, the vertical direction is considered a column and the horizontal direction is a row. However, at different angles, the vertical and horizontal directions are interchangeable, so rows can also be called columns, and columns can also be called rows.

[0121] FIG10 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Referring to FIG10 , optionally, the display panel has a display area 81 and a frame area (exemplarily, including an upper frame area 82 and a lower frame area 83) arranged adjacent to each other. The pixel driving circuit is located in the display area 81. The display panel includes: a first threshold adjustment bus 711, a second threshold adjustment bus 712, and a third threshold adjustment bus 713. The first threshold adjustment bus 711 is located in the frame area, and the first gate isolation column 31 is coupled to the first threshold adjustment bus 711; the second threshold adjustment bus 712 is located in the frame area, and the second gate isolation column 312 is coupled to the second threshold adjustment bus 712; the third threshold adjustment bus 713 is located in the frame area, and the third gate isolation column 313 is coupled to the third threshold adjustment bus 713. This arrangement further simplifies the wiring of the display panel.

[0122] Optionally, the plurality of first pixel driving units 100 are arranged in multiple columns, the plurality of second pixel driving units 200 are arranged in multiple columns, and the plurality of third pixel driving units 300 are arranged in multiple columns, the columns extending along a first direction X, the first threshold adjustment bus 711, the second threshold adjustment bus 712, and the third threshold adjustment bus 713 extending along a second direction Y, and the first direction X and the second direction Y form an angle. Optionally, the first direction X is perpendicular to the second direction Y.

[0123] Referring to FIG. 10 , the display panel optionally further includes a first cathode bus line 721, a second cathode bus line 722, and a third cathode bus line 723. The first cathode bus line 721 is located in the border region, with the first cathode spacer 321 coupled to the first cathode bus line 721. The second cathode bus line 722 is located in the border region, with the second cathode spacer 322 coupled to the second cathode bus line 722. The third cathode bus line 723 is located in the border region, with the third cathode spacer 323 coupled to the third cathode bus line 723. This arrangement further simplifies the wiring of the display panel.

[0124] Optionally, the plurality of first pixel driving units 100 are arranged in multiple columns, the plurality of second pixel driving units 200 are arranged in multiple columns, and the plurality of third pixel driving units 300 are arranged in multiple columns, the columns extending along a first direction X, the first cathode bus lines 721, the second cathode bus lines 722, and the third cathode bus lines 723 extending along a second direction Y, and the first direction X and the second direction Y form an angle. Optionally, the first direction X is perpendicular to the second direction Y.

[0125] Continuing to refer to FIG10 , in one embodiment of the present application, optionally, the display panel further includes an upper frame area 82 and a lower frame area 83 , wherein the upper frame area 82 is located at the top of the display area 81 , and the lower frame area 83 is located at the bottom of the display area 81 . Both the upper frame area 82 and the lower frame area 83 are provided with a first threshold adjustment bus 711 , which is equivalent to providing voltage from both ends of the first gate isolation column 31 , which is beneficial to improving the uniformity of the voltage signal received by the pixel driving unit. Similarly, both the upper frame area 82 and the lower frame area 83 are provided with a second threshold adjustment bus 712 and a third threshold adjustment bus 713 .

[0126] In another embodiment of the present application, optionally, the first threshold adjustment bus 711 is provided only in the upper border area 82; or, the first threshold adjustment bus 711 is provided only in the lower border area 83. The second threshold adjustment bus 712 is provided only in the upper border area 82; or, the second threshold adjustment bus 712 is provided only in the lower border area 83. The third threshold adjustment bus 713 is provided only in the upper border area 82; or, the third threshold adjustment bus 713 is provided only in the lower border area 83.

[0127] In one embodiment of the present application, optionally, the first threshold adjustment bus 711 , the second threshold adjustment bus 712 , and the third threshold adjustment bus 713 are all disposed on an isolation layer.

[0128] In another embodiment of the present application, the display panel optionally further includes a first gate connection line, a second gate connection line, and a third gate connection line. The first gate connection line is located in the first metal layer 11 of the display area 81, the first threshold adjustment gate 111 is coupled to the first gate connection line, and the first gate connection line is arranged in parallel with the first gate isolation column 31; the second gate connection line is located in the first metal layer 11 of the display area 81, the second threshold adjustment gate 112 is coupled to the second gate connection line, and the second gate connection line is arranged in parallel with the second gate isolation column 312; the third gate connection line is located in the first metal layer 11 of the display area 81, the third threshold adjustment gate 113 is coupled to the third gate connection line, and the third gate connection line is arranged in parallel with the third gate isolation column 313. Among them, since the metal of the first metal layer 11 is thinner and the thickness of the isolation column of the isolation layer is thicker, the impedance of the first gate isolation column 31, the second gate isolation column 312 and the third gate isolation column 313 is relatively small, and the first threshold adjustment gate 111, the second threshold adjustment gate 112 and the third threshold adjustment gate 113 are electrically connected through the first gate isolation column 31, the second gate isolation column 312 and the third gate isolation column 313 respectively, and the uniformity is better. In actual applications, the gate connection line set in the first metal layer 11 is a supplementary solution, which can further improve the uniformity of the display panel.

[0129] Continuing to refer to FIG10 , in one embodiment of the present application, optionally, within the upper frame area 82 , from top to bottom, there are a first threshold adjustment bus 711 , a second threshold adjustment bus 712 , and a third threshold adjustment bus 713 , the first gate isolation column 31 is connected to the first threshold adjustment bus 711 via a crossover wire, and the second gate isolation column 312 is connected to the second threshold adjustment bus 712 via a crossover wire. This arrangement can avoid short circuits between the first gate isolation column 31 and the second threshold adjustment bus 712 and the third threshold adjustment bus 713, and avoid short circuits between the second gate isolation column 312 and the third threshold adjustment bus 713. The third gate isolation column 313 is directly connected to the third threshold adjustment bus 713. This arrangement is conducive to simplifying wiring. Within the lower frame area 83 , the threshold adjustment bus and the gate isolation column are arranged in a similar manner and will not be repeated here.

[0130] Continuing with FIG. 10 , in one embodiment of the present application, optionally, both the upper frame region 82 and the lower frame region 83 are provided with a first cathode bus 721. This arrangement is equivalent to providing voltage from both ends of the first cathode isolation column 321, which helps improve the uniformity of the voltage signal received by the pixel driving unit. Similarly, both the upper frame region 82 and the lower frame region 83 are provided with a second cathode bus 722 and a third cathode bus 723.

[0131] In the above embodiments, the example of a direct electrical connection between the driving transistor and the light-emitting element is used for illustration, which is not a limitation of the present application. In other embodiments, for example, for a pixel driving circuit with a compensation function, a light-emitting control transistor is further provided between the driving transistor and the light-emitting element. Regardless of the form of pixel driving circuit, as long as it is provided with a threshold adjustment gate and the threshold adjustment gate is connected to the gate isolation column, it is within the scope of protection of the present application.

[0132] FIG11 is a schematic diagram of the cross-sectional structure of another display panel provided in an embodiment of the present application. Referring to FIG11 , in another embodiment of the present application, optionally, the first gate isolation column 31 includes at least two sub-film layers, the width of the upper sub-film layer is greater than the width of the lower sub-film layer, and the materials of at least two sub-film layers are different. Exemplarily, the first gate isolation column 31 as shown in FIG12 can be formed by multiple exposure + development + etching processes. The first cathode isolation column 321, the second gate isolation column 312, the third gate isolation column 313, the second cathode isolation column 322 and the third cathode isolation column 323 are arranged in the same manner and prepared in the same manner as the first gate isolation column 31, and are not described in detail.

[0133] Continuing with FIG. 11 , in one embodiment of the present application, the fourth metal layer optionally further includes a crossover connection line 16, which is connected to the first threshold adjustment gate 111 via a via, and the first gate isolation pillar 31 is connected to the crossover connection line 16 via a via. This arrangement facilitates simplifying the etching process for the display panel. When preparing the fourth metal layer, the source and drain electrodes 15 require drilling vias onto the semiconductor 12 of the active layer through an etching process. Simultaneously, vias corresponding to the crossover connection line 16 can be etched onto the first threshold adjustment gate 111 of the first metal layer 11. The crossover connection line 16 can also be formed in the same process as the source and drain electrodes 15. Before forming the first gate isolation pillar 31, vias can be formed in the seventh insulating layer 52 (i.e., the pixel definition layer) and the sixth insulating layer 51 (i.e., the planarization layer) using a photolithography process at locations corresponding to the crossover connection line 16. The first gate isolation pillar 31 is then formed, resulting in a structure in which the first gate isolation pillar 31 is connected to the crossover connection line 16 via a via. The second gate isolation pillar 312 and the third gate isolation pillar 313 are arranged in the same manner and prepared in the same manner as the first gate isolation pillar 31 , and are not described in detail herein.

[0134] In another embodiment of the present application, the first gate isolation pillar 31 is optionally directly connected to the first threshold adjustment gate 111 through a via. For example, before forming the first gate isolation pillar 31, a deep via is formed at the location of the first threshold adjustment gate 111 through a deep hole etching process, and then the first gate isolation pillar 31 is formed. The formed first gate isolation pillar 31 is directly connected to the first threshold adjustment gate 111 through the via. The second gate isolation pillar 312 and the third gate isolation pillar 313 are arranged in the same manner and prepared by the same process as the first gate isolation pillar 31, and are not further described.

[0135] It can be seen from this that, as shown in FIG11 , the method of connecting the first threshold adjustment gate 111 through the cross-line connection line 16 does not require drilling a deep hole, and is easier to implement in terms of process methods.

[0136] The embodiment of the present application further provides a display panel. Referring to FIG8 , the display panel includes:

[0137] A substrate 01 has a first side; a driving circuit layer 02 is arranged on the first side of the substrate 01 and includes a first driving transistor 110 in a first pixel driving unit 100, and the first driving transistor 110 has a first threshold adjustment gate 111; an isolation layer 03 is arranged on a side of the driving circuit layer 02 facing away from the substrate 01, and includes a first gate isolation column 31, which is coupled to the first threshold adjustment gate 111 and is configured with a first adjustment signal R_BSM.

[0138] In the embodiment of the present application, the first driving transistor 110 in the first pixel driving unit 100 includes a first threshold adjustment gate 111. The first threshold adjustment gate 111 is coupled to the first gate isolation column 31 in the isolation layer 03. The first gate isolation column 31 is configured with a first adjustment signal R_BSM, so that the voltage of the first threshold adjustment gate 111 of the first driving transistor 110 can be adjusted, thereby adjusting the threshold voltage of the first driving transistor 110, thereby improving the performance of the display panel.

[0139] Optionally, the driving circuit layer 02 further includes a second driving transistor 210 in the second pixel driving unit 200, the second driving transistor 210 having a second threshold adjustment gate 211. The isolation layer 03 further includes a second gate isolation column 312, which is coupled to the second threshold adjustment gate 211 and configured with a second adjustment signal G_BSM. The configuration of the second driving transistor 210 can refer to the configuration of the first driving transistor 110, and the configuration of the second gate isolation column 312 can refer to the configuration of the first gate isolation column 31, and will not be further described.

[0140] Continuing with FIG8 , optionally, the display panel further includes a light-emitting device layer 04, which is disposed on a side of the driving circuit layer 02 facing away from the substrate 01. The light-emitting device layer 04 includes a first light-emitting element 120 in the first pixel driving unit 100 and a second light-emitting element 220 in the second pixel driving unit 200. The first light-emitting element 120 is coupled to the first driving transistor 110, and the second light-emitting element 220 is coupled to the second driving transistor 210. The first light-emitting element 120 and the second light-emitting element 220 emit different colors. When the first light-emitting element 120 and the second light-emitting element 220 display a target grayscale, the voltage values ​​of the first adjustment signal R_BSM and the second adjustment signal G_BSM are different. As previously described, such a configuration can reduce the power consumption of the display panel and further improve the performance of the display panel.

[0141] Optionally, the driving circuit layer 02 further includes a third driving transistor 310 in the third pixel driving unit 300, and the third driving transistor 310 has a third threshold adjustment gate 311; the isolation layer 03 further includes a third gate isolation column 313, which is coupled to the third threshold adjustment gate 311 and is configured with a third adjustment signal B_BSM. This configuration can adjust the threshold voltage of the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300, respectively, and can compensate for the voltage difference between the first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320, thereby balancing the efficiency of the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300, thereby improving the uniformity and performance of the display panel.

[0142] Optionally, the light-emitting device layer 04 further includes a third light-emitting element 320 in the third pixel driving unit 300, and the third light-emitting element 320 is coupled to the third driving transistor 310. The first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320 emit different colors. When the first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320 are displayed at a target grayscale, at least two of the first adjustment signal R_BSM, the second adjustment signal G_BSM, and the third adjustment signal B_BSM have different voltage values. This configuration makes the voltage adjustment of the pixel driving unit more flexible, further improving the performance of the display panel.

[0143] Optionally, when the first light-emitting element 120, the second light-emitting element 220, and the third light-emitting element 320 are displayed at the target grayscale, the voltage values ​​of the first adjustment signal R_BSM, the second adjustment signal G_BSM, and the third adjustment signal B_BSM are different from each other. This configuration enables the first adjustment signal R_BSM, the second adjustment signal G_BSM, and the third adjustment signal B_BSM to adapt to their corresponding pixel driving units.

[0144] Continuing with FIG8 , the isolation layer 03 optionally further includes a first cathode isolation column 321 . The display panel further includes a light-emitting device layer 04 disposed on a side of the drive circuit layer 02 facing away from the substrate 01 . The light-emitting device layer 04 includes a first light-emitting element 120 in the first pixel driver unit 100 . The first light-emitting element 120 is coupled to the first driver transistor 110 . The first light-emitting element 120 has a first cathode 23 , which is coupled to a first cathode isolation column 321 . The first cathode isolation column 321 is configured with a first cathode signal R_ELVSS . The provision of the first cathode isolation column 321 can, on the one hand, isolate the first cathode 23 of the first light-emitting element 120 from other cathodes, allowing the first cathode 23 of the first light-emitting element 120 to independently provide the first cathode signal R_ELVSS . This can compensate for voltage differences between the first light-emitting element 120 and other light-emitting elements, thereby balancing the efficiency of the first pixel driver unit 100 and other pixel driver units and improving the uniformity of the display panel.

[0145] 8 and 9 , optionally, the first cathode isolation column 321 has a first opening 321A, and a portion of the first light emitting element 120 is located within the first opening 321A. This configuration enables the first light emitting element 120 to be surrounded by the first cathode isolation column 321, achieving cathode isolation.

[0146] Continuing with FIG9 , optionally, the first gate isolation pillars 31 and the first cathode isolation pillars 321 are spaced apart in a second direction Y parallel to the substrate 01 . In the second direction Y, the first gate isolation pillars 31 have a first width d1, and the first cathode isolation pillars 321 have a second width d2, where the first width d1 is smaller than the second width d2. The first gate isolation pillars 31 transmit the first adjustment signal R_BSM required by the first drive transistor 110, while the first cathode isolation pillars 321 transmit the first cathode signal R_ELVSS. Therefore, the first cathode isolation pillars 321 need to withstand a large current. In comparison, the first gate isolation pillars 31 withstand a very small current. Therefore, the first gate isolation pillars 31 can be configured with a smaller width, which facilitates the wiring of the display panel and increases pixel density without compromising the pixel aperture ratio.

[0147] Continuing with FIG9 , the first cathode isolation column 321 optionally includes a first structure 3211 and a second structure 3212 connected to each other. The first structure 3211 encloses a first opening 321A, and the second structure 3212 extends in a first direction X. The first direction X and the second direction Y form an angle, and the second structure 3212 has a second width d2. This arrangement facilitates the first cathode isolation column 321 to connect the first pixel driving units 100 in the first direction X, and also allows the first cathode isolation column 321 to be larger, facilitating the transmission of large currents.

[0148] Optionally, the first direction X is perpendicular to the second direction Y, which is beneficial to the layout design of the display panel. The plane where the first direction X and the second direction Y are located is parallel to the plane where the substrate 01 is located.

[0149] Continuing with FIG9 , optionally, the driving circuit layer 02 further includes a second driving transistor 210 in the second pixel driving unit 200, and the isolation layer 03 further includes a second gate isolation column 312. The second driving transistor 210 includes a second threshold adjustment gate 211. The second gate isolation column 312 is coupled to the second threshold adjustment gate 211 and is configured with a second adjustment signal B_BSM. In a second direction Y parallel to the substrate 01, the first gate isolation column 31 is located between the first cathode isolation column 321 and the second gate isolation column 312. This arrangement allows the first gate isolation column 31 to be located in close proximity to the first driving transistor 110, which helps shorten routing distances and optimize wiring design.

[0150] Continuing with FIG9 , optionally, the light-emitting device layer 04 further includes a second light-emitting element 220 in the second pixel driving unit 200, the second light-emitting element 220 being coupled to the second driving transistor 210, and the isolation layer 03 further including a second cathode isolation column 322. The second light-emitting element 220 has a second cathode coupled to the second cathode isolation column 322, and the second cathode isolation column 322 is configured with a second cathode signal G_ELVSS. In a second direction Y parallel to the substrate 01, the second gate isolation column 312 is located between the first gate isolation column 31 and the second cathode isolation column 322. This arrangement places the second gate isolation column 312 in close proximity to the second driving transistor 210, thereby shortening the routing distance and optimizing the wiring design.

[0151] The first gate isolation column 31 and the second gate isolation column 312 are located as a whole between the first cathode isolation column 321 and the second cathode isolation column 322, and their wiring shape adapts to the pixel arrangement. For example, the wiring shape is serpentine, which can minimize the crowding of pixel openings.

[0152] Optionally, the second cathode isolation column 322 has a second opening, and a portion of the second light emitting element 220 is located in the second opening. This arrangement enables the second light emitting element 220 to be surrounded by the second cathode isolation column 322, thereby achieving cathode isolation.

[0153] Continuing to refer to Figure 9, optionally, the light-emitting device layer 04 also includes a third light-emitting element 320 in the third pixel driving unit 300, and the isolation layer 03 also includes a third cathode isolation column 323, wherein the third light-emitting element 320 has a third cathode, and the third cathode is coupled to the third cathode isolation column 323, and the third cathode isolation column 323 is configured with a third cathode signal B_ELVSS, and in the second direction Y parallel to the substrate 01, the second cathode isolation column 322 is located between the second gate isolation column 321 and the third cathode isolation column 323.

[0154] Optionally, the third cathode isolation column 323 has a third opening, and a portion of the third light emitting element 320 is located within the third opening. This arrangement enables the third light emitting element 320 to be surrounded by the third cathode isolation column 323, thereby achieving cathode isolation.

[0155] Continuing with FIG9 , optionally, the driving circuit layer 02 further includes a third driving transistor 310 in the third pixel driving unit 300, the third driving transistor 310 being coupled to the third light-emitting element 320, and the isolation layer 03 further including a third gate isolation column 313. The third driving transistor 310 includes a third threshold adjustment gate 311, the third gate isolation column 313 being coupled to the third threshold adjustment gate 311 and configured with a third adjustment signal B_BSM, and the third cathode isolation column 323 being located between the second cathode isolation column 322 and the third gate isolation column 313 in a second direction Y parallel to the substrate 01. This arrangement places the third gate isolation column 313 in close proximity to the third driving transistor 310, thereby shortening the routing distance and optimizing the wiring design.

[0156] 9 , along the second direction Y, arranged in sequence are the first cathode isolation pillar 321 , the first gate isolation pillar 31 , the second gate isolation pillar 312 , the second cathode isolation pillar 322 , the third cathode isolation pillar 323 and the third gate isolation pillar 313 , and this arrangement sequence is cyclical.

[0157] For example, referring to FIG. 9 , in some embodiments, the third cathode isolation column 323 includes a third structure (not labeled) and a fourth structure (not labeled) connected to each other, wherein the third structure of the third cathode isolation column 323 encloses a third opening, and the fourth structure of the third cathode isolation column 323 extends in the first direction X. The fourth structure of the third cathode isolation column 323 has a third width d3, and the maximum width of the third structure of the third cathode isolation column 323 is equal to the third width d3.

[0158] The present application also provides a method for manufacturing a display panel. This method is applicable to the display panel provided in any embodiment of the present application and has corresponding effects. Figure 12 is a schematic diagram of the structure of a display panel formed in a part of the steps in the method for manufacturing a display panel provided in an embodiment of the present application, and Figure 13 is a schematic diagram of the structure of a display panel formed in another part of the steps in the method for manufacturing a display panel provided in an embodiment of the present application. Referring to Figures 12 and 13, the method for manufacturing a display panel includes the following steps:

[0159] S110 , sequentially forming a first metal layer 11 , a first insulating layer 41 , an active layer, a second insulating layer 42 and a second metal layer.

[0160] The first and second insulating layers 41 and 42 can be made of inorganic materials, such as SiN and / or SiO, and can be formed using deposition or other processes. The first and second metal layers 11 and 113 are provided with a first drive current control gate 113 and a first threshold adjustment gate 111 of the drive transistor, respectively; the active layer includes the semiconductor 12 of the drive transistor. The first and second metal layers 11 and 113 are made of metal and can be formed using processes such as sputtering or evaporation, followed by patterning to form the first drive current control gate 113 or the first threshold adjustment gate 111.

[0161] S120 , forming a third insulating layer 43 and a third metal layer.

[0162] The material of the third insulating layer 43 can be an inorganic material, such as SiN and / or SiO, and can be formed by a deposition process. The third metal layer is provided with a capacitor plate 14. The material of the third metal layer is metal and can be formed by a sputtering or evaporation process, and then patterned to form the capacitor plate 14.

[0163] S130 , forming a fourth insulating layer 44 and a fourth metal layer.

[0164] The material of the fourth insulating layer 44 can be an inorganic material, such as SiN and / or SiO, and can be formed using a deposition process. Optionally, after forming the fourth insulating layer 44, a fifth insulating layer 45 is formed on the fourth insulating layer 44. The material of the fifth insulating layer 45 can be an organic material, which can isolate the third metal layer and the fourth metal layer while also providing a certain degree of planarization.

[0165] After forming the fourth insulating layer 44 and the fifth insulating layer 45, vias are formed through processes such as photoresist coating, exposure, development, and etching. The fourth metal layer is provided with the source and drain electrodes 15 of the driving transistor. The fourth metal layer is made of metal and can be formed by processes such as sputtering or evaporation. The source and drain electrodes 15 are then patterned to form the source and drain electrodes 15. The source and drain electrodes 15 are connected to the semiconductor 12 through vias.

[0166] Optionally, while forming the via holes corresponding to the source and drain electrodes 15 , via holes corresponding to the cross-line connection lines 16 are also formed; while patterning the source and drain electrodes 15 , the cross-line connection lines 16 are also formed.

[0167] S140 , forming a sixth insulating layer 51 and an anode metal layer.

[0168] The material of the sixth insulating layer 51 can be an organic material. While isolating the fourth metal layer and the anode metal layer, the sixth insulating layer 51 can flatten the surface of the fourth metal layer, which is beneficial to the subsequent preparation of the light-emitting element to make the film layer flat and optimize the light-emitting effect of the light-emitting element.

[0169] After forming the sixth insulating layer 51, an anode opening is formed through processes such as photoresist coating, exposure, development, and etching. The anode metal layer is provided with an anode 21 of the light-emitting element. The anode metal layer is made of metal and can be formed by processes such as sputtering or evaporation. The anode 21 is then patterned to form the anode. The anode 21 is connected to the source and drain electrodes 15 through the anode opening.

[0170] S150 , forming a seventh insulating layer 52 , and forming an isolation layer 03 on the seventh insulating layer 52 .

[0171] The isolation layer 03 includes a first gate isolation column 31 . The first gate isolation column 31 is larger at the top and smaller at the bottom, and the first gate isolation column 31 is conductive. The first gate isolation column 31 and the first threshold adjustment gate 111 are electrically connected across the membrane layer.

[0172] Optionally, the isolation layer 03 further includes a first cathode isolation column 321. The first cathode isolation column 321 is shaped larger at the top and smaller at the bottom, and is conductive. The first gate isolation column 31 is shaped larger at the top and smaller at the bottom, and the first gate isolation column 31 and the first cathode isolation column 321 are manufactured using the same process.

[0173] Optionally, the first gate isolation column 31 is integrally provided, and the first cathode isolation column 321 is integrally provided. Exemplarily, the first gate isolation column 31 and the first cathode isolation column 321, which are larger at the top and smaller at the bottom, can be formed by a lift-off process. Exemplarily, negative photoresist is applied, and then exposure and development are performed to form openings at the positions of the first gate isolation column 31 and the first cathode isolation column 321. Metal is then evaporated within the openings, and the remaining photoresist is removed to form the first gate isolation column 31 and the first cathode isolation column 321, which are larger at the top and smaller at the bottom.

[0174] S160 , forming an opening on the seventh insulating layer 52 to expose the anode 21 .

[0175] Exemplarily, an opening exposing the anode 21 is formed by processes such as photoresist coating+exposure+development+etching, and the opening defines the size of the pixel opening.

[0176] S170 , forming the light-emitting functional layer 22 and the cathode 23 of the light-emitting element on the anode 21 .

[0177] The light-emitting functional layer 22 and the cathode 23 can be evaporated as a whole layer. The light-emitting functional layer 22 and the cathode 23 of adjacent light-emitting elements are separated by the first cathode isolation column 321 , and the cathode 23 of the light-emitting element is connected to the first cathode isolation column 321 .

[0178] Illustratively, the entire light-emitting functional layer 22 and cathode layer 18 of the red pixel driving unit are evaporated, and the red light-emitting functional layer 22 and cathode layer 18 are evaporated in each pixel opening. Since the shape of the first cathode isolation column 321 is larger at the top and smaller at the bottom, the material evaporated into the two adjacent pixel openings is disconnected by the first cathode isolation column 321. At the same time, the edge portion of the cathode 23 is electrically connected to the first cathode isolation column 321; the light-emitting functional layer 22 and cathode layer 18 outside the red pixel opening are removed.

[0179] The light-emitting functional layer 22 and cathode layer 18 of the green pixel driving unit are evaporated on the entire layer, and the green light-emitting functional layer 22 and cathode layer 18 are evaporated in each pixel opening. Since the red light-emitting functional layer 22 and cathode layer 18 have been evaporated in the red pixel opening, the green light-emitting functional layer 22 and cathode layer 18 are stacked on the red light-emitting functional layer 22 and cathode layer 18 in the red pixel opening; the green light-emitting functional layer 22 and cathode layer 18 outside the green pixel opening are removed.

[0180] The light-emitting functional layer 22 and cathode layer 18 of the blue pixel driving unit are evaporated on the entire layer, and the blue light-emitting functional layer 22 and cathode layer 18 are evaporated in each pixel opening. Since the red light-emitting functional layer 22 and cathode layer 18 have been evaporated in the red pixel opening, and the green light-emitting functional layer 22 and cathode layer 18 have been evaporated in the green pixel opening, the blue light-emitting functional layer 22 and cathode layer 18 are stacked on the red light-emitting functional layer 22 and cathode layer 18 in the red pixel opening; in the green pixel opening, the blue light-emitting functional layer 22 and cathode layer 18 are stacked on the green light-emitting functional layer 22 and cathode layer 18; the blue light-emitting functional layer 22 and cathode layer 18 outside the blue pixel opening are removed.

[0181] Thus, the red pixel driving unit, the green pixel driving unit and the blue pixel driving unit can be formed without using a fine mask.

[0182] S180 , forming an eighth insulating layer 53 , a sealing layer 61 and an encapsulation layer 62 on the cathode 23 .

[0183] In the embodiments of the display panel, specific descriptions of the preparation methods and processes are given for different display panel structures. These preparation methods and processes can all be considered as the preparation methods of the display panels provided in the embodiments of the present application, and repeated content will not be repeated here.

[0184] An embodiment of the present application also provides a display device, which can be a mobile phone, computer, tablet computer, television, wearable device, etc. The display device includes the display panel provided by any embodiment of the present application. Its technical principles and effects are similar and will not be repeated here.

Claims

1. A pixel driving circuit, comprising: A first pixel driving unit, comprising a first driving transistor and a first light emitting element, wherein the first driving transistor has a first driving current control gate and a first threshold adjustment gate, wherein the first driving current control gate is configured to receive a first data signal, and the first threshold adjustment gate is configured to receive a first adjustment signal, and the first driving transistor is configured to drive the first light emitting element under the control of the first data signal and the first adjustment signal; a second pixel driving unit, comprising a second driving transistor and a second light emitting element, wherein the second driving transistor has a second driving current control gate and a second threshold adjustment gate, wherein the second driving current control gate is configured to receive a second data signal, and the second threshold adjustment gate is configured to receive a second adjustment signal, and the second driving transistor is configured to be controlled by the second data signal and the second adjustment signal to drive the second light emitting element; The first light emitting element and the second light emitting element emit different colors, and when the first light emitting element and the second light emitting element are displayed at a target grayscale, the first adjustment signal and the second adjustment signal have different voltage values.

2. The pixel driving circuit according to claim 1, further comprising: a third pixel driving unit, comprising a third driving transistor and a third light emitting element, wherein the third driving transistor has a third driving current control gate and a third threshold adjustment gate, wherein the third driving current control gate is configured to receive a third data signal, wherein the third threshold adjustment gate is configured to receive a third adjustment signal, and wherein the third driving transistor is configured to be controlled by the third data signal and the third adjustment signal to drive the third light emitting element; The light-emitting colors of the first light-emitting element, the second light-emitting element and the third light-emitting element are different from each other, and when the first light-emitting element, the second light-emitting element and the third light-emitting element are displayed at a target gray scale, the voltage values ​​of at least two of the first adjustment signal, the second adjustment signal and the third adjustment signal are different; or the voltage values ​​of the first adjustment signal, the second adjustment signal and the third adjustment signal are different from each other.

3. The pixel driving circuit according to claim 2, wherein: The target grayscale is the 0th grayscale, the first light-emitting element, the second light-emitting element and the third light-emitting element do not emit light at the 0th grayscale, and / or, when the first light-emitting element, the second light-emitting element and the third light-emitting element are displayed at the target grayscale, the voltage values ​​of the first data signal, the second data signal and the third data signal are the same.

4. The pixel driving circuit according to claim 1, wherein: The first light emitting element has a first cathode, which is configured with a first cathode signal; the second light emitting element has a second cathode, which is configured with a second cathode signal; wherein the voltage values ​​of the first cathode signal and the second cathode signal are different.

5. The pixel driving circuit according to claim 4, wherein: The pixel driving circuit further includes a third pixel driving unit, the third pixel driving unit includes a third light emitting element, the first light emitting element, the second light emitting element and the third light emitting element emit different colors, the third light emitting element has a third cathode, and the third cathode is configured with a third cathode signal; The voltage values ​​of at least two of the first cathode signal, the second cathode signal and the third cathode signal are different; or the voltage values ​​of the first cathode signal, the second cathode signal and the third cathode signal are different from each other.

6. A display panel, comprising the pixel driving circuit according to any one of claims 1 to 5, a first metal layer, a light-emitting functional layer and an isolation layer; The first threshold adjustment gate and the second threshold adjustment gate are electrically isolated and disposed in the first metal layer; The light-emitting functional layer is disposed on one side of the first metal layer, and a portion of the first light-emitting elements and a portion of the second light-emitting elements are disposed in the light-emitting functional layer; The isolation layer is disposed on one side of the first metal layer and is configured to isolate the first light-emitting element from the second light-emitting element, and the isolation layer at least includes a first gate isolation column and a second gate isolation column; in, The first gate isolation column is coupled to the first threshold adjustment gate and is configured with the first adjustment signal, and the second gate isolation column is coupled to the second threshold adjustment gate and is configured with the second adjustment signal.

7. The display panel according to claim 6, wherein: The pixel driving circuit further includes a third pixel driving unit, the third pixel driving unit includes a third driving transistor and a third light emitting element, the third driving transistor has a third driving current control gate and a third threshold adjustment gate, the third driving current control gate is configured to receive a third data signal, the third threshold adjustment gate is configured to receive a third adjustment signal, and the third driving transistor is configured to be controlled by the third data signal and the third adjustment signal to drive the third light emitting element; wherein the third threshold adjustment gate is electrically isolated from the first threshold adjustment gate, and the third threshold adjustment gate is electrically isolated from the second threshold adjustment gate, and the third threshold adjustment gate is disposed in the first metal layer; A portion of the third light-emitting element is disposed in the light-emitting functional layer; The isolation layer is further configured to isolate the third light emitting element from the first light emitting element, and the isolation layer is further configured to isolate the third light emitting element from the second light emitting element. The system further includes a third gate isolation column, wherein the third gate isolation column is coupled to the third threshold adjustment gate and is configured with the third adjustment signal.

8. The display panel according to claim 6, further comprising a cathode layer, wherein the cathode layer is disposed on a side of the light-emitting functional layer away from the first metal layer, and the isolation layer further comprises a first cathode isolation column and a second cathode isolation column; in, The first light emitting element has a first cathode, the second light emitting element has a second cathode, the first cathode and the second cathode are electrically isolated and disposed in the cathode layer; The first cathode isolation column is coupled to the first cathode and is configured with a first cathode signal, and the second cathode isolation column is coupled to the second cathode and is configured with a second cathode signal; The voltage values ​​of the first cathode signal and the second cathode signal are different; The pixel driving circuit further includes a third pixel driving unit, and the third pixel driving unit includes a third light emitting element; The isolation layer further includes a third cathode isolation column, the third light emitting element has a third cathode, the third cathode is disposed in the cathode layer, the third cathode is electrically isolated from the first cathode, and the third cathode is electrically isolated from the second cathode, the third cathode isolation column is coupled to the third cathode, and is configured with a third cathode signal; At least two of the first cathode signal, the second cathode signal and the third cathode signal have different voltage values; or, the first cathode signal, the second cathode signal and the third cathode signal have different voltage values.

9. The display panel according to claim 6, wherein: The pixel driving circuit includes a plurality of the first pixel driving units and a plurality of the second pixel driving units; In which, the first threshold adjustment gates in the multiple first pixel driving units are coupled through the same first gate isolation column, the second threshold adjustment gates in the multiple second pixel driving units are coupled through the same second gate isolation column, and / or the isolation layer also includes a first cathode isolation column and a second cathode isolation column, the first light-emitting element has a first cathode, the second light-emitting element has a second cathode, the first cathodes in the multiple first pixel driving units are coupled through the same first cathode isolation column, and the second cathodes in the multiple second pixel driving units are coupled through the same second cathode isolation column.

10. The display panel according to claim 7, wherein: The pixel driving circuit includes a plurality of first pixel driving units, a plurality of second pixel driving units and a plurality of third pixel driving units; The first threshold adjustment gates in the plurality of first pixel driving units are coupled via the same first gate isolation column, and the second threshold adjustment gates in the plurality of second pixel driving units are coupled via the same first gate isolation column. The first threshold adjustment gates in the first pixel driving units of the same column are coupled through the same second gate isolation column, and the third threshold adjustment gates in the plurality of third pixel driving units are coupled through the same third gate isolation column; or, the plurality of first pixel driving units are arranged in multiple columns, the plurality of second pixel driving units are arranged in multiple columns, and the plurality of third pixel driving units are arranged in multiple columns, wherein the first threshold adjustment gates in the first pixel driving units in the same column are coupled through the same first gate isolation column, the second threshold adjustment gates in the second pixel driving units in the same column are coupled through the same second gate isolation column, and the third threshold adjustment gates in the third pixel driving units in the same column are coupled through the same third gate isolation column.

11. The display panel according to claim 8, wherein: The pixel driving circuit includes a plurality of first pixel driving units, a plurality of second pixel driving units and a plurality of third pixel driving units, wherein the third pixel driving unit includes a third light emitting element, wherein the third light emitting element has a third cathode, wherein the third cathode is disposed in the cathode layer, wherein the third cathode is electrically isolated from the first cathode, and wherein the third cathode is electrically isolated from the second cathode, wherein the isolation layer further includes a third cathode isolation column, wherein the third cathode isolation column is coupled to the third cathode and is configured with a third cathode signal; wherein, the first cathodes in the plurality of first pixel driving units are coupled through the same first cathode isolation column, the second cathodes in the plurality of second pixel driving units are coupled through the same second cathode isolation column, and the third cathodes in the plurality of third pixel driving units are coupled through the same third cathode isolation column; or, the plurality of first pixel driving units are arranged in multiple columns, the plurality of second pixel driving units are arranged in multiple columns, and the plurality of third pixel driving units are arranged in multiple columns, wherein the first cathodes in the first pixel driving units in the same column are coupled through the same first cathode isolation column, the second cathodes in the second pixel driving units in the same column are coupled through the same second cathode isolation column, and the third cathodes in the third pixel driving units in the same column are coupled through the same third cathode isolation column.

12. The display panel according to claim 6, wherein the display panel comprises a display area and a frame area which are adjacent to each other, the pixel driving circuit is located in the display area, and the display panel comprises: A first threshold adjustment bus is located in the border area, and the first gate isolation column is coupled to the first threshold adjustment bus; A second threshold adjustment bus is located in the border area, and the second gate isolation column is coupled to the second threshold adjustment bus; The pixel driving circuit further includes a third pixel driving unit, the third pixel driving unit includes a third driving transistor and a third light emitting element, the third driving transistor has a third driving current control gate and a third threshold adjustment gate, the third driving current control gate is configured to receive a third data signal, the third threshold adjustment gate is configured to receive a third adjustment signal, and the third driving transistor is configured to be controlled by the third data signal and the third adjustment signal to drive the third light emitting element. element; Wherein, the isolation layer further includes a third gate isolation column, the third gate isolation column is coupled to the third threshold adjustment gate and is configured with the third adjustment signal; The display panel further includes a third threshold adjustment bus located in the frame area, and the third gate isolation column is coupled to the third threshold adjustment bus.

13. The display panel according to claim 12, wherein: The pixel driving circuit comprises a plurality of first pixel driving units, a plurality of second pixel driving units and a plurality of third pixel driving units; the plurality of first pixel driving units are arranged into a plurality of columns, the plurality of second pixel driving units are arranged into a plurality of columns, the plurality of third pixel driving units are arranged into a plurality of columns, the columns extend along a first direction, and the first threshold adjustment bus, the second threshold adjustment bus and the third threshold adjustment bus extend along a second direction; The first direction and the second direction have an angle or the first direction is perpendicular to the second direction.

14. The display panel according to claim 13, wherein: The isolation layer also includes a first cathode isolation column, a second cathode isolation column and a third cathode isolation column; The display panel further comprises: a cathode layer, which is arranged on a side of the light-emitting functional layer away from the first metal layer; wherein the first light-emitting element has a first cathode, the second light-emitting element has a second cathode, the third light-emitting element has a third cathode, the first cathode, the second cathode and the third cathode are electrically isolated and arranged in the cathode layer, the first cathode isolation column is coupled to the first cathode, the second cathode isolation column is coupled to the second cathode, and the third cathode isolation column is coupled to the third cathode; A first cathode bus line is located in the frame area, and the first cathode isolation column is coupled to the first cathode bus line; A second cathode bus line is located in the frame area, and the second cathode isolation column is coupled to the second cathode bus line; A third cathode bus line is located in the frame area, and the third cathode isolation column is coupled to the third cathode bus line; The first cathode bus line, the second cathode bus line, and the third cathode bus line extend along the second direction.

15. A display panel, comprising: a substrate having a first side; A driving circuit layer, disposed on the first side, comprising at least a first driving transistor in a first pixel driving unit, wherein the first driving transistor has a first threshold adjustment gate; The isolation layer is disposed on a side of the driving circuit layer away from the substrate, and includes at least a first gate isolation column, the first gate isolation column is coupled to the first threshold adjustment gate, and is configured with a first adjustment signal.

16. The display panel according to claim 15, wherein: The driving circuit layer further includes a second driving transistor in a second pixel driving unit, wherein the second driving transistor has a second threshold adjustment gate; The isolation layer further includes a second gate isolation column, the second gate isolation column is coupled to the second threshold adjustment gate and is configured with a second adjustment signal; The display panel further comprises a light emitting device layer, which is arranged on a side of the driving circuit layer away from the substrate, and the light emitting device layer comprises a first light emitting element in the first pixel driving unit and a second light emitting element in the second pixel driving unit, wherein the first light emitting element is coupled to the first driving transistor, and the second light emitting element is coupled to the second driving transistor; The first light emitting element and the second light emitting element emit different colors, and when the first light emitting element and the second light emitting element are displayed at a target grayscale, the first adjustment signal and the second adjustment signal have different voltage values; The driving circuit layer further includes a third driving transistor in a third pixel driving unit, wherein the third driving transistor has a third threshold adjustment gate; The isolation layer further includes a third gate isolation column, the third gate isolation column is coupled to the third threshold adjustment gate and is configured with a third adjustment signal; The light emitting device layer further comprises a third light emitting element in the third pixel driving unit, wherein the third light emitting element is coupled to the third driving transistor; The light-emitting colors of the first light-emitting element, the second light-emitting element and the third light-emitting element are different from each other, and when the first light-emitting element, the second light-emitting element and the third light-emitting element are displayed at a target gray scale, the voltage values ​​of at least two of the first adjustment signal, the second adjustment signal and the third adjustment signal are different; or the voltage values ​​of the first adjustment signal, the second adjustment signal and the third adjustment signal are different from each other.

17. The display panel according to claim 15, wherein: The isolation layer also includes a first cathode isolation column; The display panel further includes: A light-emitting device layer is arranged on a side of the driving circuit layer away from the substrate, wherein the light-emitting device layer includes a first light-emitting element in the first pixel driving unit, wherein the first light-emitting element is coupled to the first driving transistor; wherein the first light-emitting element has a first cathode, and the first cathode is connected to the first driving transistor. The first cathode isolation column is coupled, and the first cathode isolation column is configured with a first cathode signal; The first cathode isolation column has a first opening, and a portion of the first light emitting element is located in the first opening; The first gate isolation column and the first cathode isolation column are arranged at intervals in a second direction parallel to the substrate, and in the second direction, the first gate isolation column has a first width, and the first cathode isolation column has a second width, and the first width is smaller than the second width; The first cathode isolation column includes a first structure and a second structure connected to each other; wherein the first structure encloses the first opening, the second structure extends in a first direction, the first direction and the second direction have an angle or the first direction is perpendicular to the second direction, and the second structure has the second width.

18. The display panel according to claim 17, wherein: The driving circuit layer further includes a second driving transistor in a second pixel driving unit, and the isolation layer further includes a second gate isolation column; wherein the second driving transistor has a second threshold adjustment gate, the second gate isolation column is coupled to the second threshold adjustment gate and is configured with a second adjustment signal, and in a second direction parallel to the substrate, the first gate isolation column is located between the first cathode isolation column and the second gate isolation column; The light-emitting device layer further includes a second light-emitting element in the second pixel driving unit, the second light-emitting element is coupled to the second driving transistor, the isolation layer further includes a second cathode isolation column, wherein the second light-emitting element has a second cathode, the second cathode is coupled to the second cathode isolation column, the second cathode isolation column is configured with a second cathode signal, and in a second direction parallel to the substrate, the second gate isolation column is located between the first gate isolation column and the second cathode isolation column; The second cathode isolation column has a second opening, and a portion of the second light emitting element is located in the second opening.

19. The display panel according to claim 18, wherein: The light emitting device layer further includes a third light emitting element in a third pixel driving unit, and the isolation layer further includes a third cathode isolation column; The third light emitting element has a third cathode, the third cathode is coupled to the third cathode isolation column, the third cathode isolation column is configured with a third cathode signal, and in a second direction parallel to the substrate, the second cathode isolation column is located between the second gate isolation column and the third cathode isolation column; The third cathode isolation column has a third opening, and a portion of the third light emitting element is located in the third opening; The driving circuit layer also includes a third driving transistor in the third pixel driving unit, and the third driving transistor is coupled to the third light-emitting element. The isolation layer also includes a third gate isolation column, wherein the third driving transistor has a third threshold adjustment gate, and the third gate isolation column is coupled to the third threshold adjustment gate and is configured with a third adjustment signal. In a second direction parallel to the substrate, the third cathode isolation column is located between the second cathode isolation column and the third gate isolation column.

20. A display device, comprising: The display panel according to any one of claims 6 to 14; or, A display panel as claimed in any one of claims 15 to 19.

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