Semiconductor device, manufacturing method therefor, and electronic apparatus

Abstract

A semiconductor device, a manufacturing method therefor, and an electronic apparatus, relating to, but not limited to, the technical field of storage. The manufacturing method for the semiconductor device comprises: forming a first metal silicide thin film on a first silicon substrate (71); forming a second metal silicide thin film on a second silicon substrate (101); using a flip-chip bonding mode to bond the first metal silicide thin film of the first silicon substrate (71) with the second metal silicide thin film of the second silicon substrate (101), such that the first metal silicide thin film and the second metal silicide thin film form a metal silicide layer (78); using an etching process to etch the metal silicide layer (78) so as to form linear bit lines (13); and making the first silicon substrate (71) form semiconductor columns (50). The present disclosure solves the problems of circuit breaking of the bit lines (13), poor contact between the bit lines (13) and the semiconductor columns (50), etc., and ensures the uniformity of the heights of the semiconductor columns (50).

Description

Semiconductor device, manufacturing method thereof, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 26, 2023, with application number 202310753427.8 and invention name “A semiconductor device, its manufacturing method, and electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of storage technology, and specifically to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0003] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared with static memory, DRAM memory has the advantages of simpler structure, lower manufacturing cost and higher capacity density. With the development of technology, the application of DRAM memory is becoming more and more extensive.

[0004] In the fabrication process of semiconductor devices containing vertical channel transistors (VCTs), such as DRAMs, the bit lines need to be buried beneath the channels, requiring atomic layer deposition, etching, and high-temperature annealing. Furthermore, during material preparation, trenches must be dug in the substrate and then deposited within the trenches. This complex fabrication process also makes the resulting bit lines prone to short circuits, severely impacting the performance of the semiconductor device.

[0005] Summary of the Invention

[0006] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0007] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0008] forming a first metal silicide thin film on a first silicon substrate;

[0009] forming a second metal silicide thin film on the second silicon substrate;

[0010] bonding the first metal silicide film on the first silicon substrate to the second metal silicide film on the second silicon substrate by flip-chip bonding, so that the first metal silicide film and the second metal silicide film form a metal silicide layer;

[0011] etching the metal silicide layer to form linear bit lines through an etching process;

[0012] The first silicon substrate is formed into a semiconductor pillar.

[0013] In an exemplary embodiment, forming a first metal silicide thin film on the first silicon substrate includes:

[0014] depositing a first metal thin film on the first silicon substrate;

[0015] forming a first metal silicide thin film on the first silicon substrate through an annealing process;

[0016] The surface of the first metal silicide film is planarized by a chemical mechanical polishing process.

[0017] In an exemplary embodiment, the first metal thin film includes at least one of a transition metal and a transition metal alloy.

[0018] In an exemplary embodiment, forming a second metal silicide thin film on the second silicon substrate includes:

[0019] depositing a second metal film on the second silicon substrate;

[0020] forming a second metal silicide thin film on the second silicon substrate through an annealing process;

[0021] The surface of the second metal silicide film is planarized by a chemical mechanical polishing process.

[0022] In an exemplary embodiment, the second metal thin film includes at least one of a transition metal and a transition metal alloy.

[0023] In an exemplary embodiment, the first metal silicide thin film and the second metal silicide thin film are made of the same material.

[0024] In an exemplary embodiment, etching the metal silicide layer to form a linear bit line includes:

[0025] Through an etching process, grooves are formed in the first silicon substrate and the metal silicide layer, and the metal silicide layer is etched to form a plurality of linear bit lines. The grooves are arranged between adjacent bit lines, and the grooves extend from the surface of the first silicon substrate away from the second silicon substrate to the second silicon substrate.

[0026] In an exemplary embodiment, after forming the semiconductor pillar on the first silicon substrate, the method further includes:

[0027] Using an etching process to expose the sidewalls of the semiconductor pillar;

[0028] forming a gate insulating layer on the sidewall of the semiconductor column by an atomic deposition process;

[0029] A gate electrode is formed on the gate insulating layer by adopting an atomic deposition process. The gate electrode and the gate insulating layer are arranged around the sidewall of the semiconductor column.

[0030] In a second aspect, an embodiment of the present disclosure further provides a semiconductor device, comprising a memory cell arranged on a substrate, the memory cell comprising a bit line arranged on the substrate, a semiconductor column arranged on a side of the bit line away from the substrate, the semiconductor column comprising a first electrode, a channel and a second electrode arranged in sequence along a direction away from the substrate, the first electrode being electrically connected to the bit line; the bit line comprising a first metal silicide layer and a second metal silicide layer, the first metal silicide layer and the second metal silicide layer being bonded.

[0031] In an exemplary embodiment, the first metal silicide layer and the second metal silicide layer are made of the same material and are connected into one body.

[0032] In an exemplary embodiment, the bit line is linear and includes a bottom surface close to the substrate and a top surface away from the substrate. Both the bottom surface and the top surface are flat surfaces in the extending direction of the bit line.

[0033] In an exemplary embodiment, the memory cell further includes a gate insulating layer and a gate electrode, and the gate electrode and the gate insulating layer are disposed around a sidewall of the channel of the semiconductor pillar.

[0034] In a third aspect, an embodiment of the present disclosure further provides an electronic device comprising the aforementioned semiconductor device.

[0035] The manufacturing method of the semiconductor device in the embodiment of the present application adopts a flip chip bonding method to bond the metal silicide films on two silicon substrates to form a metal silicide layer. Subsequently, through an etching process, the metal silicide layer is formed into a bit line, so that the bit line has a uniform and tight internal structure, solves the problems of bit line disconnection and poor contact between the bit line and the semiconductor pillar, and ensures the uniformity of the height of multiple semiconductor pillars formed on the silicon substrate.

[0036] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0037] Summary of the Figures

[0038] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0039] FIG1 is a schematic diagram of a planar structure of a semiconductor device according to an embodiment of the present application;

[0040] FIG2 is a schematic diagram of a cross-sectional structure of a semiconductor device according to an embodiment of the present application;

[0041] FIG3 is a second schematic cross-sectional structural diagram of a semiconductor device according to an embodiment of the present application;

[0042] FIG4 a is a schematic diagram of a semiconductor device after forming a first doping layer and a second doping layer during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0043] FIG4 b is a schematic diagram of a semiconductor device after a metal silicide layer is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0044] FIG4 c is a schematic diagram of a metal silicide layer and a substrate after bonding during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0045] 5a is a schematic cross-sectional view in the second direction after a semiconductor pillar is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0046] 5 b is a schematic cross-sectional view in a first direction after a semiconductor pillar is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0047] 6 is a schematic cross-sectional view in a second direction after a second insulating film is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0048] 7a is a schematic cross-sectional view in the second direction after a third insulating film is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0049] 7 b is a schematic cross-sectional view in the first direction after a third insulating film is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0050] 8a is a schematic cross-sectional view in the second direction after the second electrode is exposed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0051] 8 b is a schematic cross-sectional view in the first direction after the second electrode is exposed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0052] 9a is a schematic cross-sectional view in a second direction after a second barrier layer is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0053] 9 b is a schematic cross-sectional view in the first direction after the second barrier layer is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0054] FIG10 a is a schematic cross-sectional view in the second direction after the channel is exposed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0055] FIG10 b is a schematic cross-sectional view in the first direction after the channel is exposed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0056] 11a is a schematic cross-sectional view in the second direction after a gate insulating layer is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0057] FIG11 b is a schematic cross-sectional view in a first direction after a gate insulating layer is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0058] 12a is a schematic cross-sectional view in the second direction after a gate electrode is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0059] 12 b is a schematic cross-sectional view in the first direction after a gate electrode is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application.

[0060] Details

[0061] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0062] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0063] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0064] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0065] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0066] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (also called a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (also called a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0067] In this specification, the first electrode referred to below may be a drain electrode and the second electrode may be a source electrode, or alternatively, the first electrode may be a source electrode and the second electrode may be a drain electrode. In practical applications, whether the first electrode or the second electrode is the source electrode and the drain electrode is related to the direction of current flow; generally, current flows from the source electrode to the drain electrode. The functions of "source electrode" and "drain electrode" are sometimes interchangeable when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchangeable.

[0068] In this specification, "electrically connected" includes components connected together via an element having some electrical function, such as a physical connection or a signal connection. There are no particular limitations on the "element having some electrical function" as long as it allows electrical signals to be transmitted between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0069] In this specification, the terms "parallel" or "perpendicular" refer to approximately parallel or perpendicular lines within a margin of error. "Parallel" refers to a state where the angle formed by two straight lines is between -10° and 10°, and thus also includes a state where the angle is between -5° and 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is between 80° and 100°, and thus also includes a state where the angle is between 85° and 95°.

[0070] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0071] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0072] An embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0073] forming a first metal silicide thin film on a first silicon substrate;

[0074] forming a second metal silicide thin film on the second silicon substrate;

[0075] bonding the first metal silicide film on the first silicon substrate to the second metal silicide film on the second silicon substrate by flip-chip bonding, so that the first metal silicide film and the second metal silicide film form a metal silicide layer;

[0076] etching the metal silicide layer to form linear bit lines through an etching process;

[0077] The first silicon substrate is formed into a semiconductor pillar.

[0078] In an exemplary embodiment, forming a first metal silicide thin film on the first silicon substrate includes:

[0079] depositing a first metal thin film on the first silicon substrate;

[0080] forming a first metal silicide thin film on the first silicon substrate through an annealing process;

[0081] The surface of the first metal silicide film is planarized by a chemical mechanical polishing process.

[0082] In an exemplary embodiment, the first metal thin film includes at least one of a transition metal and a transition metal alloy.

[0083] In an exemplary embodiment, forming a second metal silicide thin film on the second silicon substrate includes:

[0084] depositing a second metal film on the second silicon substrate;

[0085] forming a second metal silicide thin film on the second silicon substrate through an annealing process;

[0086] The surface of the second metal silicide film is planarized by a chemical mechanical polishing process.

[0087] In an exemplary embodiment, the second metal thin film includes at least one of a transition metal and a transition metal alloy.

[0088] In an exemplary embodiment, the first metal silicide thin film and the second metal silicide thin film are made of the same material.

[0089] The solution of this embodiment is illustrated below through some examples.

[0090] Figure 1 is a schematic diagram of the planar structure of a semiconductor device according to an embodiment of the present application. In an exemplary embodiment, as shown in Figure 1, the semiconductor device according to an embodiment of the present application includes a plurality of memory cells 11 disposed on a substrate and spaced apart from each other. Memory cells 11 include word lines 12 disposed on the substrate and extending along a first direction D1, bit lines 13 extending along a second direction D2, semiconductor pillars 14 extending perpendicular to the substrate, and gate electrodes, each insulated from a channel surrounding semiconductor pillars 14, electrically connected to word lines 12.

[0091] In an exemplary embodiment, as shown in FIG1 , a plurality of mutually spaced memory cells 11 are spaced apart and arranged along a first direction D1 to form a memory cell row, a word line 12 is electrically connected to the gate electrodes of all the memory cells 11 in a memory cell row, and all the memory cells 11 in a memory cell row can share one word line 12.

[0092] In an exemplary embodiment, as shown in FIG1 , a plurality of mutually spaced memory cells 11 are spaced apart and arranged along a second direction D2 to form a memory cell column, a bit line 13 is electrically connected to the semiconductor pillars 14 of all the memory cells 11 in a memory cell column, and all the memory cells 11 in a memory cell column can share one bit line 13.

[0093] In an exemplary embodiment, the material of the bit line 13 may be a metal silicide, such as titanium silicon compound, cobalt silicon compound, or platinum nickel silicon compound.

[0094] In the semiconductor device of the embodiment of the present application, the bit line 13 is made of metal silicide, which can form an ohmic contact with the electrode of the semiconductor column 14, reduce the contact resistance of the bit line 13, and solve the problem of poor contact between the bit line and the electrode of the semiconductor column 14.

[0095] In an exemplary embodiment, the metal silicide includes transition metal ions. For example, the transition metal ions include at least one of titanium ions, cobalt ions, platinum ions, and nickel ions.

[0096] In an exemplary embodiment, the orthographic projection of the semiconductor pillar 14 on the substrate may have various shapes, for example, regular or irregular shapes such as circle, ellipse, rectangle, diamond, triangle, pentagon, hexagon, etc.

[0097] The semiconductor device of the embodiment of the present application may be a vertical channel transistor. The semiconductor device of the embodiment of the present application may be used as a read transistor and / or a write transistor in a dynamic random access memory (DRAM), thereby reducing the memory area and improving the storage density.

[0098] In some embodiments, the semiconductor device of the embodiment of the present application may also be other storage structures in which the bit line is buried in the channel close to the substrate side, and the embodiment of the present application will not be described in detail here.

[0099] Figure 2 is a schematic cross-sectional structural diagram of a semiconductor device according to an embodiment of the present application, and Figure 3 is a schematic cross-sectional structural diagram of a semiconductor device according to an embodiment of the present application. Figure 2 may be a schematic cross-sectional diagram taken along the a-a' direction in Figure 1, and Figure 3 may be a schematic cross-sectional diagram taken along the c-c' direction in Figure 1. In an exemplary embodiment, as shown in Figures 2 and 3, a memory cell 11 includes a bit line 13 disposed on a second silicon substrate 101 perpendicular to the substrate, and a semiconductor pillar 50 disposed on a side of the bit line 13 away from the second silicon substrate 101. The semiconductor pillar 50 includes a first electrode 51, a channel 52, and a second electrode 53, disposed sequentially along the direction away from the substrate. The channel 52 is located between the first electrode 51 and the second electrode 53, and both the first electrode 51 and the second electrode 53 are electrically connected to the channel 52. The first electrode 51 is located on the side of the channel 52 closer to the second silicon substrate 101 and is electrically connected to the bit line 13. The second electrode 53 is located on the side of the channel 52 away from the second silicon substrate 101.

[0100] In an exemplary embodiment, the bit line 13 includes a first metal silicide layer and a second metal silicide layer, wherein the second metal silicide layer is located on a side of the first metal silicide layer close to the second silicon substrate 101. The first metal silicide layer and the second metal silicide layer are bonded.

[0101] In an exemplary embodiment, the first metal silicide layer and the second metal silicide layer may be made of the same material and connected as one body.

[0102] In exemplary embodiments, the first metal silicide layer and the second metal silicide layer may be made of different materials.

[0103] In an exemplary embodiment, the bit line 13 is linear, and includes a bottom surface located close to the second silicon substrate 101 and a top surface located away from the second silicon substrate 101 . Both the bottom surface and the top surface are flat surfaces in the extension direction of the bit line 13 .

[0104] The bit line of the semiconductor device in the embodiment of the present application is first formed by forming a first metal silicide film on a first silicon substrate and a second metal silicide film on a second silicon substrate. Subsequently, the first metal silicide film and the second metal silicide film are bonded to each other by a flip chip bonding method to form a metal silicide layer. Finally, the metal silicide layer is formed into the bit line, and the bit line is transferred between the bottom of the semiconductor column and the surface of the second silicon substrate, so that the top and bottom surfaces of the bit line 13 are flat and the interior is uniform and tight, thereby ensuring the electrical performance of the bit line 13.

[0105] In an exemplary embodiment, as shown in Figures 2 and 3, the memory cell 11 further includes a gate electrode 30, which is disposed around the outside of the channel 52. The gate electrode 30 extends on the sidewalls of the channel 52 to form a ring-shaped conductive layer extending in a direction perpendicular to the second silicon substrate 101. A gate insulating layer 31 is disposed between the gate electrode 30 and the channel 52, separating and insulating the gate electrode 30 from the channel 52.

[0106] In an exemplary embodiment, gate insulating layer 31 may be made of a material with a wide bandgap and a high dielectric constant, or a material suitable for making very small devices, such as hafnium dioxide. Gate insulating layer 31 may be made of a single layer of dielectric material, such as an oxide or nitride, or may be made of multiple layers of dielectric material, such as a combination of oxide and nitride.

[0107] In an exemplary embodiment, as shown in FIG. 2 and FIG. 3 , the gate electrode 30 is insulated from the first electrode 51 , the second electrode 53 , and the bit line 13 .

[0108] In an exemplary embodiment, as shown in Figures 2 and 3, the gate electrode 30 is disposed opposite the channel 52, and the gate electrode 30 does not cover the first electrode 51 and the second electrode 53. The gate electrode 30 may surround part or all of the channel 52 to form a ring-gate structure. For example, the gate electrode 30 may be ring-shaped, and the gate electrode 30 surrounds the four sides of the channel 52.

[0109] In an exemplary embodiment, the gate electrode 30 may be made of metal, for example, conductive metals such as tin and tungsten.

[0110] The gate-all-around structure of the transistor in the embodiment of the present application has strong gate control, can increase the area of ​​the channel region, and can improve the retention time. In addition, the gate-all-around structure can reduce the area of ​​the semiconductor device.

[0111] In an exemplary embodiment, as shown in FIG2 and FIG3 , the semiconductor device further includes a first isolation layer 81. The first isolation layer 81 is disposed on a side of the semiconductor pillar 50 away from the substrate and contacts the second electrode 53 of the semiconductor pillar 50. The orthographic projection of the first isolation layer 81 on the substrate covers the orthographic projection of the semiconductor pillar 50 on the substrate. The first isolation layer 81 is used to isolate the surface of the second electrode 53 of the semiconductor pillar 50 to prevent it from affecting the semiconductor pillar 50 during the formation of the gate electrode 30. The material of the first isolation layer 81 can be an inorganic material. For example, the material of the first isolation layer 81 can be silicon dioxide.

[0112] In an exemplary embodiment, as shown in FIG2 and FIG3 , the semiconductor device further includes a second isolation layer 82. The second isolation layer 82 is disposed around the sidewalls of the second electrode 53 of the semiconductor pillar 50. The second isolation layer 82 is used to isolate the sidewalls of the second electrode 53 of the semiconductor pillar 50 to prevent the semiconductor pillar 50 from being affected during the formation of the gate electrode 30. The material of the second isolation layer 82 can be an inorganic material. For example, the material of the second isolation layer 82 can be silicon dioxide.

[0113] In an exemplary embodiment, as shown in FIG2 , a first trench 61 is provided between semiconductor pillars 50 of adjacent memory cells in the second direction D2. The first trench 61 extends along the first direction D1. The first trench 61 extends perpendicularly to the second silicon substrate 101 to the bit line 13. The bottom wall of the first trench 61 is the surface of the bit line 13 facing away from the substrate. The first direction D1 intersects the second direction D2. For example, the first direction D1 is perpendicular to the second direction D2.

[0114] In an exemplary embodiment, as shown in FIG2 , the semiconductor device further includes a first insulating layer 21 and a second insulating layer 22. Both the first insulating layer 21 and the second insulating layer 22 are disposed in the first trench 61. In the second direction D2, the first insulating layer 21 is located between the gate electrodes 30 of adjacent memory cells 11, isolating the gate electrodes 30 of adjacent memory cells 11 and insulating the gate electrodes 30 and the second electrode 53 of adjacent memory cells 11 from each other. In a direction perpendicular to the substrate, the second insulating layer 22 is located between the gate electrode 30 of a memory cell 11 and the bit line 13 of that memory cell 11, isolating the gate electrode 30 from the bit line 13 and insulating the gate electrode 30 from the bit line 13. The first insulating layer 21 and the second insulating layer 22 can be made of an inorganic material.

[0115] In an exemplary embodiment, as shown in FIG2 , the semiconductor device further includes a third insulating layer 23. The third insulating layer 23 is disposed on a side of the first insulating layer 21 away from the substrate, and is located between first isolation layers 81 on adjacent memory cells 11. The third insulating layer 23 may be made of an inorganic material.

[0116] In an exemplary embodiment, as shown in FIG3 , a second trench 62 is provided between the semiconductor pillars 50 of adjacent memory cells in a first direction D1. The second trench 62 extends along a second direction D2. The second trench 62 extends perpendicularly to the second silicon substrate 101 to the second silicon substrate 101. The bottom wall of the second trench 62 is the surface of the second silicon substrate 101. The gate electrode 30 and the gate insulating layer 31 are provided in the second trench 62.

[0117] In an exemplary embodiment, the second trench 62 is used to form the bit line 13 ; the first trench 61 and the second trench 62 are used to form the semiconductor pillar 50 .

[0118] In an exemplary embodiment, as shown in FIG3 , the second insulating layer 22 is located in the second trench 62. In the first direction D1, the second insulating layer 22 is located between the bit lines 13 of adjacent memory cells 11, isolating the bit lines 13 of adjacent memory cells 11 and insulating the bit lines 13 of adjacent memory cells 11 from each other and the first electrode 51. In a direction perpendicular to the substrate, the second insulating layer 22 is located between the gate electrode 30 and the second silicon substrate 101.

[0119] In an exemplary embodiment, as shown in FIG3 , a portion of the third insulating layer 23 near the substrate is located in the second trench 62 and disposed on a side of the gate electrode 30 away from the substrate. A portion of the third insulating layer 23 away from the substrate is located above the second trench 62 and disposed between the first isolation layers 81 on adjacent memory cells 11.

[0120] In an exemplary embodiment, as shown in FIG. 2 and FIG. 3 , the semiconductor device further includes a covering layer 90 . The covering layer 90 is located on a side of the semiconductor pillar 50 and the third insulating layer 23 away from the substrate. The covering layer 90 may cover one or more semiconductor pillars 50 to protect the semiconductor pillars 50 .

[0121] The technical solution of this embodiment will be further illustrated below using the fabrication process of the semiconductor device of this embodiment. The "patterning process" referred to in this embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a well-established fabrication process in the relevant art. The "photolithography process" referred to in this embodiment includes film coating, mask exposure, and development, and is a well-established fabrication process in the relevant art. Deposition can be performed using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can use known coating processes; and etching can use known methods, without specific limitations here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin layer of a material deposited on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire fabrication process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire fabrication process, the "thin film" before patterning is referred to as a "thin film," and the "layer" after patterning is referred to as a "layer." A "layer" after patterning or photolithography contains at least one "pattern."

[0122] In an exemplary embodiment, the semiconductor device includes a memory cell arranged on a substrate, the memory cell includes a bit line and a semiconductor column arranged in sequence along a direction away from the substrate, the semiconductor column includes a first electrode, a channel and a second electrode arranged in sequence along a direction away from the substrate, and the first electrode is electrically connected to the bit line.

[0123] In an exemplary embodiment, a process for manufacturing the semiconductor device may include:

[0124] S101) A first silicon substrate 71 is provided. Ion implantation is performed to perform P-type doping (B-doping) and N-type doping (P-doping) at different depths within the first silicon substrate 71. Subsequently, a heat treatment is performed to repair the lattice. The P-type doped regions of the first silicon substrate 71 form a first doped layer 72, and the N-type doped regions form a second doped layer 73. The second doped layer 73 is interconnected with the first doped layer 72, as shown in FIG4a. The first silicon substrate 71 is used to subsequently form semiconductor pillars, the first doped layer 72 is used to subsequently form channels, and the second doped layer 73 is used to subsequently form a first electrode.

[0125] S102) Forming a first metal silicide film 77 on the second doped layer 73 of the first silicon substrate 71, as shown in FIG4b. The first metal silicide film 77 is used for subsequent formation of bit lines.

[0126] In one exemplary embodiment, forming the first metal silicide film 77 includes:

[0127] depositing a first metal thin film on the first silicon substrate;

[0128] forming a first metal silicide thin film on the first silicon substrate through an annealing process;

[0129] The surface of the first metal silicide film is planarized by a chemical mechanical polishing process.

[0130] The first metal film includes at least one of a transition metal and a transition metal alloy. For example, the transition metal includes at least one of titanium and cobalt, and the transition metal alloy includes a platinum-nickel alloy.

[0131] S103) Provide a second silicon substrate 101. Form a second metal silicide film on the second silicon substrate 101. The second silicon substrate 101 is used as a substrate in the subsequent process, and the second metal silicide film is used to form a bit line in the subsequent process.

[0132] In one exemplary embodiment, forming a second metal silicide film on the second silicon substrate 101 includes:

[0133] depositing a second metal film on the second silicon substrate 101;

[0134] forming a second metal silicide thin film on the second silicon substrate through an annealing process;

[0135] The surface of the second metal silicide film is planarized by a chemical mechanical polishing process.

[0136] The second metal film includes at least one of a transition metal and a transition metal alloy. For example, the transition metal includes at least one of titanium and cobalt, and the transition metal alloy includes a platinum-nickel alloy.

[0137] In an exemplary embodiment, the first metal silicide film and the second metal silicide film are made of the same material. For example, the first metal silicide film and the second metal silicide film are both made of titanium silicon compound.

[0138] Subsequently, the first metal silicide film of the first silicon substrate 71 is bonded to the second metal silicide film of the second silicon substrate 101 by flip-chip bonding; the first metal silicide film and the second metal silicide film form a metal silicide layer 78, with the second silicon substrate 101 serving as a base.

[0139] Subsequently, the portion of the first silicon substrate 71 away from the first doping layer 72 is N-type doped (doped with P), so that the N-type doped region in the first silicon substrate 71 forms a third doping layer 74, as shown in FIG4c. The third doping layer 74 is used to subsequently form the second electrode.

[0140] S104) Forming a semiconductor pillar. Forming the semiconductor pillar includes: etching the first doped layer 72, the second doped layer 73, the third doped layer 74, and the metal silicide layer 78 of the first silicon substrate 71 on the substrate having the aforementioned pattern through an etching process. Second trenches 62 are formed in the first doped layer 72, the second doped layer 73, the third doped layer 74, and the metal silicide layer 78, so that the metal silicide layer 78 is etched to form a plurality of linear bit lines 13; each bit line 13 extends along the second direction D2, and the plurality of bit lines 13 are arranged at intervals along the first direction D1, with second trenches 62 provided between adjacent bit lines 13; the second trenches 62 extend along the second direction D2, and the second trenches 62 extend to the second silicon substrate 101, and the bottom wall of the second trench 62 is the surface of the second silicon substrate 101;

[0141] Subsequently, the first insulating film 91 is filled in the second trench 62. A portion of the first insulating film 91 fills the second trench 62, and a portion of the first insulating film 91 is located on the surface of the semiconductor pillar 50 away from the second silicon substrate 101.

[0142] Subsequently, a first trench 61 is formed in the first doped layer 72, the second doped layer 73, and the third doped layer 74. The first trench 61 extends along a first direction D1 and reaches the bit line 13. The bottom wall of the first trench 61 is the surface of the bit line 13 on the side away from the substrate. The first trench 61 and the second trench 62 form the first silicon substrate 71 into a semiconductor pillar 50. Specifically, the first trench 61 and the second trench 62 form the third doped layer 74 into the second electrode 53, the first doped layer 72 into the channel 52, and the second doped layer 73 into the first electrode 51. The second electrode 53, the channel 52, and the first electrode 51 form the semiconductor pillar 50, as shown in Figures 5a and 5b.

[0143] S105) On the substrate having the aforementioned pattern, a second insulating film 92 is formed on the sidewalls of the first trench 61 using an atomic deposition process, as shown in FIG6 .

[0144] S106) On the substrate having the aforementioned pattern, a chemical deposition process is used to form a third insulating film 93 on the side of the semiconductor pillar 50 away from the second silicon substrate 101, with a portion of the third insulating film 93 filling the first trench 61, and a portion of the third insulating film 93 covering the first insulating film 91 on one or more semiconductor pillars 50, as well as the first insulating film 91 in the second trench 62, as shown in Figures 7a and 7b.

[0145] S107) On the substrate having the aforementioned pattern, a grinding process is used to remove a portion of the third insulating film 93 away from the second silicon substrate 101 and the first insulating film 91 on the semiconductor pillar 50, so that the surface of the second electrode 53 of the semiconductor pillar 50 is exposed; then, an etching process is used to etch away a portion of the second insulating film 92 and a portion of the first insulating film 91 in the second trench 62, so that the side wall of the second electrode 53 of the semiconductor pillar 50 is exposed; the retained third insulating film 93 forms a first insulating layer 21, as shown in Figures 8a and 8b.

[0146] S108) On the substrate having the aforementioned pattern, a second isolation layer 82 is formed on the exposed sidewalls of the second electrode 53 using an atomic deposition process. The second isolation layer 82 is disposed around the sidewalls of the second electrode 53, as shown in FIG9a and FIG9b.

[0147] S109) On the substrate having the aforementioned pattern, an etching process is used to remove a portion of the second insulating film 92 and a portion of the first insulating film 91 to form a cavity 110 surrounding the sidewalls of the channel 52. The cavity 110 exposes the sidewalls of the channel 52 of the semiconductor pillar 50, so that the retained first insulating film 91 and the retained second insulating film 92 form a second insulating layer 22, as shown in Figures 10a and 10b.

[0148] FIG11a is a schematic cross-sectional view taken along the second direction after a gate insulating layer is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application; FIG11b is a schematic cross-sectional view taken along the first direction after a gate insulating layer is formed during the manufacturing process of the semiconductor device according to an embodiment of the present application;

[0149] S110) On the substrate having the aforementioned pattern, an atomic deposition process is used to form a gate insulating layer 31 on the exposed sidewalls of the channel 52, and the gate insulating layer 31 is arranged around the sidewalls of the channel 52; a first isolation layer 81 is formed on the surface of the second electrode 53 of the semiconductor pillar 50 away from the second silicon substrate 101, as shown in Figures 11a and 11b.

[0150] S111) On the substrate having the aforementioned pattern, a gate electrode 30 is formed on the gate insulating layer 31 using an atomic deposition process. The gate electrode 30 is disposed around the sidewall of the channel 52 through the gate insulating layer 31, as shown in FIG. 12a and FIG. 12b.

[0151] S112) On the substrate having the aforementioned pattern, a third insulating layer 23 is formed on the side of the first insulating layer 21 away from the substrate and on the side of the gate electrode 30 away from the substrate; subsequently, a covering layer 90 is formed on the side of the first isolation layer 81 away from the substrate and on the side of the third insulating layer 23 away from the substrate on the semiconductor pillar 50, as shown in Figures 2 and 3.

[0152] The manufacturing method of the semiconductor device of the present application has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost and high yield rate.

[0153] The manufacturing method of the semiconductor device in the embodiment of the present application adopts a flip chip bonding method to bond the metal silicide films on two silicon substrates to form a metal silicide layer. Subsequently, through an etching process, the metal silicide layer is formed into a bit line, so that the bit line has a uniform and tight internal structure, solves the problems of bit line disconnection and poor contact between the bit line and the semiconductor pillar, and ensures the uniformity of the height of multiple semiconductor pillars formed on the silicon substrate.

[0154] The embodiment of the present application further provides an electronic device, comprising any of the semiconductor devices described above. The embodiment of the present application does not impose any particular limitation on the specific form of the electronic device.

[0155] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to general designs. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, may be combined with each other to obtain new embodiments.

[0156] It should be understood by those skilled in the art that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a first metal silicide film on a first silicon substrate; forming a second metal silicide film on a second silicon substrate; Using a flip chip bonding method, bonding the first metal silicide film on the first silicon substrate to the second metal silicide film on the second silicon substrate, so that the first metal silicide film and the second metal silicide film form a metal silicide layer; The metal silicide layer is etched to form a linear bit line by an etching process; The first silicon substrate is formed into a semiconductor pillar.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming a first metal silicide film on the first silicon substrate comprises: depositing a first metal film on the first silicon substrate; forming a first metal silicide film on the first silicon substrate through an annealing process; The surface of the first metal silicide film is planarized by a chemical mechanical polishing process.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The first metal film includes at least one of a transition metal and a transition metal alloy.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming a second metal silicide film on the second silicon substrate, comprising: depositing a second metal film on the second silicon substrate; forming a second metal silicide film on the second silicon substrate through an annealing process; The surface of the second metal silicide film is planarized by a chemical mechanical polishing process.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The second metal film includes at least one of a transition metal and a transition metal alloy.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein: The first metal silicide film and the second metal silicide film are made of the same material.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein: The metal silicide layer is etched to form a linear bit line, comprising: Through an etching process, grooves are formed in the first silicon substrate and the metal silicide layer, and the metal silicide layer is etched to form a plurality of linear bit lines, wherein the grooves are arranged between adjacent bit lines, and the grooves extend from a surface of the first silicon substrate away from a side of the second silicon substrate to the second silicon substrate.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein: After forming the first silicon substrate into a semiconductor column, the method further includes: Using an etching process to expose the sidewalls of the semiconductor pillar; Using an atomic deposition process, forming a gate insulating layer on the sidewall of the semiconductor column; A gate electrode is formed on the gate insulating layer by adopting an atomic deposition process, and the gate electrode and the gate insulating layer are arranged around the side wall of the semiconductor column.

9. A semiconductor device, comprising a memory cell disposed on a substrate, the memory cell comprising a bit line disposed on the substrate, a semiconductor column disposed on a side of the bit line away from the substrate, the semiconductor column comprising a first electrode, a channel, and a second electrode sequentially disposed in a direction away from the substrate, the first electrode being electrically connected to the bit line; the bit line comprising a first metal silicide layer and a second metal silicide layer, the first metal silicide layer and the second metal silicide layer being bonded.

10. The semiconductor device according to claim 9, wherein The first metal silicide layer and the second metal silicide layer are made of the same material and are connected into one.

11. The semiconductor device according to claim 9, wherein: The bit line is linear and includes a bottom surface located at a side close to the substrate and a top surface located at a side away from the substrate. Both the bottom surface and the top surface are flat surfaces in the extension direction of the bit line.

12. The semiconductor device according to claim 9, wherein The memory cell further includes a gate insulating layer and a gate electrode, wherein the gate electrode and the gate insulating layer are arranged around the sidewall of the channel of the semiconductor column.

13. An electronic device comprising the semiconductor device according to any one of claims 9 to 12.

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