Charging and discharging circuit, and related apparatus

Abstract

Provided in the embodiments of the present application are a charging and discharging circuit, and a related apparatus. The circuit comprises a first battery, an NMOS module comprising one or more NMOSs, a second battery, and a control unit, wherein the control unit is used for controlling the NMOS module to be linearly turned on when a device is powered on and the voltage difference value of the batteries is greater than a first threshold value; the control unit is further used for controlling the NMOS module to be turned on when the device is powered on and the voltage difference value is less than or equal to the first threshold value; the control unit comprises a voltage stabilization module which is used for stabilizing the voltage of a control end of the NMOS module, a first module, and a voltage division module which is used for performing voltage division processing on a voltage that is outputted from the first module; and the first module is used for performing boosting processing on the voltage of the first battery when the device is powered on, and providing the voltage for the control end of the NMOS module. When the voltage difference between batteries is large, a linear conduction resistance value of an NMOS module on a path from the batteries to a charging chip is relatively large, so as to balance the voltages of the batteries, thereby improving the safety of the batteries. Since a first module has a boosting function, the use of a power supply with a relatively large voltage is reduced.

Description

Charging and discharging circuits and related devices

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on June 27, 2023, with application number 202310769348.6 and application name “Charging and Discharging Circuits and Related Devices”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of terminal technology, and in particular to charging and discharging circuits and related devices. Background Art

[0003] With the development and progress of society, mobile phones, tablet computers and other terminal devices have become an indispensable part of people's lives. Terminal devices are usually equipped with batteries to facilitate user use.

[0004] Currently, terminal devices use a solution of multiple batteries to increase the charging speed of the terminal devices. For example, the terminal devices can use a parallel charging and parallel discharging method to achieve fast charging of the terminal devices.

[0005] However, in this method, there may be a large voltage difference between the batteries, resulting in mutual charging, which in turn causes battery safety problems.

[0006] Summary of the Invention

[0007] The present invention provides a charge-discharge circuit and related devices for use in the field of terminal technology. When the battery voltage difference is large, the linear conduction resistance of the NMOS module in the path from the battery to the charging chip is large, thereby balancing the battery voltage and improving battery safety. The first module has a boost function, reducing the need for higher voltage power supplies.

[0008] In a first aspect, an embodiment of the present application proposes a charge and discharge circuit. The charge and discharge circuit includes: a first battery, a second battery, an NMOS module and a control unit; the NMOS module includes one or more NMOSs, and the NMOS module is controlled by the control unit; the control unit is used to control the NMOS module to be in a linear conduction state when the terminal device is turned on and the voltage difference between the first battery and the second battery is greater than a first threshold value, so as to reduce the voltage difference between the first battery and the second battery; wherein, when the NMOS module is in a linear conduction state, one or more NMOSs in the NMOS module operate in a linear region; the control unit is also used to control the NMOS module to be in a conduction state when the terminal device is turned on and the voltage difference between the first battery and the second battery is less than or equal to the first threshold value;

[0009] The control unit includes: a first module with a boosting function, a first voltage divider module, a second voltage divider module and a voltage stabilizing module; the other end of the first module is connected to one end of the first voltage divider module, and the other end of the first voltage divider module is connected to the control end of the NMOS module; one end of the second voltage divider module is connected to the other end of the first voltage divider module, and the other end of the second voltage divider module is grounded, one end of the voltage stabilizing module is connected to the control end of the NMOS module, and the other end of the voltage stabilizing module is grounded; the first module is used to boost the input voltage when the terminal device is turned on, and provide voltage for the control end of the NMOS module; the first voltage divider module and the second voltage divider module are used to divide the voltage output by the first module when the terminal device is turned on, so that the NMOS module is in a linear conduction state or a conduction state; the voltage stabilizing module is used to stabilize the voltage of the gate control end of the NMOS module.

[0010] In this way, when the voltage difference between the first and second batteries is large, the NMOS module in the path from the second battery to the charging chip has a higher linear conduction resistance, balancing the battery voltages and improving battery safety. The first module's voltage boost function reduces the need for higher-voltage power supplies and reduces power consumption. Compared to PMOS, NMOS modules are smaller and less expensive.

[0011] Optionally, the first voltage divider module includes: a first resistor R1, the second voltage divider module includes: a second resistor R2 and a switch tube M1, and the voltage stabilizing module includes a capacitor C1; the first module is connected to one end of R1, and the other end of R1 is connected to the control end of the NMOS module; one end of R2 is connected to the other end of R1, and the other end of R2 is connected to the drain of M1; the source of M1 is grounded, one end of C1 is connected to the control end of the NMOS module, and the other end of C1 is grounded; when the voltage difference between the first battery and the second battery is greater than a first threshold value, the switch tube M1 is used to alternate between on and off, so that the NMOS module is in a linear on state; when the voltage difference between the first battery and the second battery is less than or equal to the first threshold value, the switch tube M1 is used to be continuously turned on, so that the NMOS module is in an on state.

[0012] In this way, voltage division is achieved through two resistors and a switch tube, and the state of the NMOS module is adjusted. The work flow is simple and easy to implement.

[0013] Optionally, the first module includes: a voltage adjustment module; the input end of the voltage adjustment module is connected to the first battery, and the output end of the voltage adjustment module is connected to the first voltage divider module; the voltage adjustment module is used to boost the voltage output by the first battery so that the NMOS in the NMOS module is in a linear conduction state or a conduction state.

[0014] In this way, the voltage of the first battery is used for voltage boosting, and no other power supply is needed, thereby reducing power consumption.

[0015] Optionally, the first module also includes: a control logic and a feedback module; the control logic is used to adjust the voltage output by the voltage adjustment module based on the voltage at the input end of the voltage adjustment module and the error between the first voltage and the voltage at the control end of the NMOS module; the first voltage is a preset voltage at the control end of the NMOS module; the feedback module is used to feed back the error between the preset voltage and the voltage at the control end of the NMOS module to the control logic; the preset voltage is the voltage at the control end of the NMOS module in a preset power-on scenario.

[0016] In this way, the output voltage of the first module can be adjusted in real time based on the voltage at the control end of the NMOS module, and the voltage at the control end of the NMOS module can be accurately controlled to be more stable.

[0017] Optionally, the second voltage divider module also includes: a switching tube M2; the source of M2 is grounded, and the drain of M2 is connected to the gate of M1; M2 is used to alternate between on and off when the terminal device is turned on and the voltage difference between the first battery and the second battery is greater than a first threshold, so that M2 alternates between off and on; M2 is also used to turn off when the terminal device is turned on and the voltage difference between the first battery and the second battery is less than or equal to the first threshold, so that M2 is turned on.

[0018] In this way, when the device is turned off, the voltage at the gate of M2 is low, and M2 is turned off, which is relatively simple to implement.

[0019] Optionally, the second voltage divider module further includes a second interface and a third resistor R3, and the third resistor is located between the gate of M1 and the second interface; the second interface is used to provide voltage to the gate of M1.

[0020] In this way, the situation where the second interface is directly grounded can be reduced.

[0021] Optionally, the control unit further includes a fourth resistor R4 and a third interface, the fourth resistor is located between the third interface and the gate of M2; the third interface is used to provide voltage to the gate of M2; the fourth resistor is used to protect the switch tube M2.

[0022] In this way, the situation in which the switch tube M2 is damaged due to excessive voltage output by the third interface can be reduced.

[0023] Optionally, the control module is further configured to control the NMOS module to be in an off state when the terminal device is turned off, so that the second battery does not supply power.

[0024] In this way, when the terminal device is turned off, the second device is not powered.

[0025] Optionally, the NMOS module includes a switch tube U1 and a switch tube U2; the source of U1 is connected to the first battery, the source of U2 is connected to the second battery, the drain of U1 is connected to the drain of U2, the gate of U1 is connected to the gate of U2, and the gate of U1 is connected to the control unit.

[0026] It is understandable that when a high-power NMOS transistor is used in the charge and discharge circuit, using only one NMOS transistor may cause the first battery and the second battery to be turned on through the parasitic diode on the high-power NMOS transistor. To prevent the first battery and the second battery from being turned on through the parasitic diode, two high-power NMOS transistors can be used to implement the above-mentioned charge and discharge circuit, and the sources of the two NMOS transistors are coupled, or the drains are coupled.

[0027] Optionally, when the terminal device is shut down, the first module outputs a voltage V1 that satisfies the following equation: V1 × resistance of the second voltage divider ÷ (resistance of the first voltage divider + resistance of the second voltage divider) ≤ (threshold voltage of U2 + discharge cut-off voltage of the second battery). The discharge cut-off voltage is the lowest voltage at which the second battery does not operate externally, or can be understood as the lowest operating voltage at which the battery is no longer suitable for discharge during discharge.

[0028] It can be understood that V1×the resistance value of the second voltage dividing unit÷(the resistance value of the first voltage dividing unit+the resistance value of the second voltage dividing unit) corresponds to the third value below.

[0029] In some embodiments, V1×resistance of R2÷(resistance of R1+resistance of R2)≤(threshold voltage of U2+discharge cut-off voltage of the second battery).

[0030] In this way, U2 can remain off when the terminal device is turned off.

[0031] Optionally, the NMOS module includes a switch tube U3; the gate of U3 is connected to the control unit, the source of U3 is connected to the second battery, the drain of U3 is connected to the first battery, and the drain of U3 is also used to connect to the charging chip to charge the first battery and / or the second battery.

[0032] In this way, one NMOS realizes voltage balancing of the first battery and the second battery. The structure is simple, easy to implement, small in size, and occupies a small area.

[0033] Optionally, the charging and discharging circuit also includes: a charging chip, which is connected to the NMOS module; the charging chip is used to charge the first battery and / or the second battery; when the NMOS module includes U1 and U2, the charging chip is connected to the drain of U1; when the NMOS module includes U3, the charging chip is connected to the drain of U3.

[0034] In some embodiments, the first module is an existing module of the terminal device, and there is no need to add a module with a boost function, which saves circuit area and cost. For example, the first module can be a PMU module used as a driver, etc.

[0035] In a second aspect, embodiments of the present application provide a terminal device, which may also be referred to as a terminal, user equipment (UE), mobile station (MS), mobile terminal (MT), etc. The terminal device may be a mobile phone, a smart TV, a wearable device, a tablet computer (Pad), a computer with wireless transceiver functions, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0036] The terminal device includes: a load, and any one of the charge-discharge circuits of the first aspect, wherein the charge-discharge circuit is used to supply power to the load.

[0037] In a third aspect, an embodiment of the present application provides a chip, which includes any charging and discharging circuit of the first aspect.

[0038] It should be understood that the second to third aspects of this application correspond to the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a schematic diagram of the structure of a charge and discharge circuit in a possible design;

[0040] FIG2 is a schematic structural diagram of a charge and discharge circuit provided in an embodiment of the present application;

[0041] FIG3 is a schematic structural diagram of an NMOS module provided in an embodiment of the present application;

[0042] FIG4 is a schematic structural diagram of a control unit according to an embodiment of the present application;

[0043] FIG5A is a schematic diagram of current direction of a control unit according to an embodiment of the present application;

[0044] FIG5B is a schematic diagram of a waveform of a voltage signal of a second interface according to an embodiment of the present application;

[0045] FIG5C is a schematic diagram of the current direction of a control unit according to an embodiment of the present application;

[0046] FIG5D is a schematic diagram of the current direction of a control unit according to an embodiment of the present application;

[0047] FIG6 is a schematic structural diagram of a control unit according to an embodiment of the present application;

[0048] FIG7 is a schematic structural diagram of an NMOS module provided in an embodiment of the present application;

[0049] FIG8 is a schematic structural diagram of a first module provided in an embodiment of the present application;

[0050] FIG9 is a schematic structural diagram of a terminal device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] To facilitate understanding of the embodiments of the present application, some of the terms involved in the present application are first briefly explained.

[0052] 1. Other terms

[0053] In the embodiments of this application, terms such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the terms "first chip" and "second chip" are used solely to distinguish between different chips and do not define their order. Those skilled in the art will understand that terms such as "first" and "second" do not define the quantity or execution order, and do not necessarily define differences.

[0054] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0055] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, a--c, bc, or abc, where a, b, c can be single or multiple.

[0056] 2. Terminal equipment

[0057] The terminal device of the embodiment of the present application may also be any form of electronic device. For example, the electronic device may include a handheld device, a vehicle-mounted device, etc. For example, some electronic devices include: mobile phones, tablet computers, PDAs, laptop computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving cars, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, terminal devices in 5G networks or future evolved public land mobile communication networks. The terminal equipment in the network (PLMN), etc., is not limited to this in the embodiments of the present application.

[0058] As an example and not a limitation, in the embodiments of the present application, the electronic device may also be a wearable device. Wearable devices may also be referred to as wearable smart devices, which are a general term for wearable devices that are intelligently designed and developed using wearable technology for daily wear, such as glasses, gloves, watches, clothing, and shoes. A wearable device is a portable device that is worn directly on the body or integrated into the user's clothes or accessories. Wearable devices are not only hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are fully functional, large in size, and can achieve complete or partial functions without relying on smartphones, such as smart watches or smart glasses, as well as those that only focus on a certain type of application function and need to be used in conjunction with other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0059] In addition, in the embodiments of the present application, the electronic device can also be a terminal device in the Internet of Things (IoT) system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network of human-machine interconnection and object-to-object interconnection.

[0060] The electronic devices in the embodiments of the present application may also be referred to as: terminal equipment, user equipment (UE), mobile station (MS), mobile terminal (MT), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent or user device, etc.

[0061] In the embodiments of the present application, the electronic device or each network device includes a hardware layer, an operating system layer running on the hardware layer, and an application layer running on the operating system layer. The hardware layer includes hardware such as a central processing unit (CPU), a memory management unit (MMU), and memory (also known as main memory). The operating system can be any one or more computer operating systems that implement business processing through processes, such as the Linux operating system, the Unix operating system, the Android operating system, the iOS operating system, or the Windows operating system. The application layer includes applications such as browsers, address books, word processing software, and instant messaging software.

[0062] Terminal devices are usually equipped with batteries for user convenience. However, the battery of terminal devices is consumed quickly and the charging frequency is high.

[0063] Some terminal devices use multiple batteries connected in parallel to increase charging speed. However, when multiple batteries are connected in parallel, current may flow into each other, leading to battery safety issues and low battery reliability.

[0064] For example, Figure 1 is a schematic diagram of a possible charging and discharging circuit design. As shown in Figure 1, the circuit includes a charging chip 101, battery 102, battery 2 103, and a load 104. Charging chip 101 is connected to battery 102, which is connected in parallel to battery 103. Both battery 102 and battery 2 103 are coupled to load 103 via charging chip 101.

[0065] The charging chip 101 is used to charge the battery 1 102 and the battery 2 103. In some possible scenarios, the charging chip 101 is connected to a power adapter, which can convert AC power into DC power to charge the battery 1 102 and the battery 2 103.

[0066] Battery 1 102 and battery 2 103 are used to supply power to a load 104 .

[0067] The load 104 may be a processor, a memory, a communication interface, etc., or a power management integrated circuit (PMIC), or a system on chip (SoC), etc. The embodiment of the present application does not limit the specific structure of the load 104.

[0068] It should be noted that in the circuit shown in Figure 1, Battery 1 102 and Battery 2 103 are directly connected. If the voltage difference between Battery 1 102 and Battery 2 103 is too large, Battery 1 102 and Battery 2 103 may directly conduct, resulting in excessive current flow between Battery 1 102 and Battery 2 103, potentially damaging components in the circuit. If the current flow between Battery 1 102 and Battery 2 103 exceeds the current capacity of the batteries, this may damage the batteries.

[0069] In view of this, an embodiment of the present application provides a charge and discharge circuit that isolates parallel-connected batteries through NMOS to reduce direct conduction between batteries.

[0070] For example, Figure 2 is a schematic diagram of the structure of a charge and discharge circuit provided in an embodiment of the present application. As shown in Figure 2, the charge and discharge circuit includes: a charging chip 201, a first battery 202, a second battery 203, a load 204, an NMOS module 205 and a control unit 206.

[0071] The charging chip 201 is used to charge the first battery 202 and the second battery 203. In some possible scenarios, the charging chip 201 is connected to a power adapter, which can convert AC power into DC power to charge the first battery 202 and the second battery 203.

[0072] The first battery 202 and the second battery 203 are used to power the load 204. The discharge cut-off voltage of the first battery 202 is greater than or equal to the discharge cut-off voltage of the second battery. The discharge cut-off voltage is the lowest operating voltage value at which the battery is no longer suitable for further discharge during discharge.

[0073] It is understood that the discharge cut-off voltage is the load voltage of the battery at the end of discharge, as specified by the manufacturer. The manufacturer's specified discharge cut-off voltage may vary depending on the battery type, discharge conditions, battery capacity requirements, and battery life requirements. This is not limited in the present embodiment.

[0074] The load 204 may be a processor, a memory, a communication interface, etc., or a power management integrated circuit (PMIC), or a system on a chip (SoC), etc. The embodiment of the present application does not limit the specific structure of the load 204.

[0075] The NMOS module 205 is configured to control the NMOS module to be in a linear conduction state when the voltage difference between the first battery and the second battery is greater than a first threshold value, so as to reduce the voltage difference between the first battery and the second battery.

[0076] In the embodiment of the present application, the first threshold value can be set based on the safe range of the voltage difference between the first battery and the second battery. The embodiment of the present application does not limit the specific value of the first threshold value. The threshold voltage in the embodiment of the present application can also be referred to as the turn-on voltage, the conduction threshold voltage, etc.

[0077] A first end of the NMOS module 205 is connected to the first battery, a second end of the NMOS module 205 is connected to the second battery, and a third end of the NMOS module 205 is connected to the control unit.

[0078] In some embodiments, the NMOS module 205 includes an NMOS. The source of the NMOS is connected to the second battery, the drain of the NMOS is connected to the first battery, and the gate of the NMOS is connected to the control unit. The specific control method is similar to the following and is not described in detail here.

[0079] In some other embodiments, the NMOS module 205 includes two NMOSs.

[0080] For example, FIG3 is a schematic diagram of the structure of an NMOS module 205 provided in an embodiment of the present application. As shown in FIG3 , the NMOS module 205 includes a first NMOS transistor U1 and a second NMOS transistor U2. The source of U1 is connected to the first battery 202, the source of U2 is connected to the second battery 203, the drain of U1 is connected to the drain of U2, and the gates of U1 and U2 are both connected to the control unit 206.

[0081] It is understood that when the absolute value of the voltage difference between the first battery and the second battery is greater than or equal to the first threshold, U1 and U2 both operate in the linear region to balance the voltages of the first and second batteries. When the voltage difference between the first battery and the second battery is less than the first threshold, U1 and U2 are both turned on. When the terminal device is turned off, U1 and U2 are both turned off.

[0082] It is understandable that the embodiment of the present application uses NMOS to control the connection between the first battery 202 and the second battery 203. Compared with PMOS, NMOS occupies a smaller area, which is conducive to the miniaturization of terminal equipment.

[0083] Based on the above embodiment, the NMOS module 205 further includes a fifth resistor R5. One end of the fifth resistor R5 is connected to the first battery 202, and the other end of the fifth resistor R5 is connected to the second battery 203. The fifth resistor R5 can perform low-current hardware balancing on the first battery and the second battery when the terminal device is in the off state.

[0084] The control unit 206 is configured to control the NMOS module 205 to disconnect the first battery from the second battery when detecting that the voltage difference between the first battery and the second battery is greater than a first threshold.

[0085] In the embodiment of the present application, the first threshold value may be 200 mV, or 100 mV, or any other value. The embodiment of the present application does not limit the specific value of the first threshold value.

[0086] For example, Figure 4 is a schematic diagram of the structure of a control unit according to an embodiment of the present application. As shown in Figure 4 , the control unit includes: a first module 401 , a first voltage dividing module 402 , a second voltage dividing module 403 and a voltage stabilizing module 404 .

[0087] The other end of the first module 401 is connected to one end of the first voltage divider module 402, and the other end of the first voltage divider module 401 is connected to the control end of the NMOS module; one end of the second voltage divider module 403 is connected to the other end of the first voltage divider module 402, and the second voltage divider module 403 is grounded; one end of the voltage stabilizing module 404 is connected to the control end of the NMOS module, and the other end of the voltage stabilizing module 404 is grounded;

[0088] The first module 401 is used to boost the voltage of the first battery when the terminal device is turned on, so as to provide voltage for the control terminal of the NMOS module.

[0089] In some embodiments, the first module 401 is further configured to not process the voltage output by the first battery when the terminal device is powered on, so that the NMOS in the NMOS module is in an off state.

[0090] The first voltage dividing module 402 and the second voltage dividing module 403 are used to divide the voltage output by the first module when the terminal device is turned on, so that the NMOS module is in a linear conduction state or a conduction state.

[0091] The voltage stabilizing module 404 is used to stabilize the voltage at the control terminal of the NMOS module.

[0092] In this way, when the voltage difference is large, the parallel batteries are isolated by the NMOS module, reducing direct conduction between the batteries. In addition, the control unit in the circuit shown in Figure 4 includes a module with a boost function, requiring a lower power supply voltage, which can reduce the use of higher voltage power supplies and reduce the power consumption of the terminal device.

[0093] Exemplarily, as shown in FIG4 , the first voltage dividing module 402 includes a first resistor R1 , the second voltage dividing module 403 includes a second resistor R2 and a switch tube M1 , and the voltage stabilizing module 404 includes a capacitor C1 .

[0094] The first module 401 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the NMOS module 205 (for example, the gate of U1); one end of the second resistor R2 is connected to the other end of the first resistor R1, and the other end of the second resistor R2 is connected to the drain of the switch tube M1; the gate of the switch tube M1 is connected to the second interface 402, the source of the switch tube M1 is grounded, one end of the capacitor C1 is connected to the NMOS module 205 (for example, the gate of U1), and the other end of the capacitor C1 is grounded.

[0095] When the voltage difference between the first battery and the second battery is greater than a first threshold, the switch tube M1 is used to alternate between on and off, so that the NMOS module is in a linear on state;

[0096] When the voltage difference between the first battery and the second battery is less than or equal to the first threshold, the switch tube M1 is further configured to be continuously turned on, so that the NMOS module is in a conducting state.

[0097] In some embodiments, the gate of the switch M1 is connected to the second interface 405. The second interface 405 is configured to output a waveform alternating between high and low levels when the absolute value of the difference between the voltage of the first battery 202 and the voltage of the second battery 203 is greater than or equal to a first threshold, thereby placing the NMOS transistors in the NMOS module in a linear conduction state. The second interface 402 is further configured to output a low level when the absolute value of the difference between the voltage of the first battery 202 and the voltage of the second battery 203 is less than the first threshold, thereby placing the NMOS transistors in the NMOS module in a conduction state.

[0098] The second interface 402 may be an input / output interface (I / O interface), for example, a general purpose input / output (GPIO) interface. The GPIO interface may be an interface on a system IO power supply. The present embodiment of the application does not limit the specific module corresponding to the second interface.

[0099] The first resistor R1 and the second resistor R2 are used to divide the voltage output by the first module when M1 is turned on, so that the NMOS in the NMOS module is in a linear on state or an off state.

[0100] In some embodiments, the first module can output a voltage of 7V-8.5V, the resistance of the first resistor R1 is 510K, the resistance of the second module R2 is 200K, the capacitance of the capacitor C1 is 100nF, the threshold voltage of U1 is 1V, the threshold voltage of U2 is 1V, and the threshold voltage of M1 is 1V.

[0101] The switch tube M1 is configured to alternately turn on and off when the absolute value of the voltage difference between the first battery and the second battery is greater than or equal to a first threshold. The switch tube M1 is configured to turn on when the absolute value of the voltage difference between the first battery and the second battery is less than the first threshold. The switch tube M1 is also configured to turn on when the terminal device is powered off.

[0102] The capacitor C1 is used to perform alternating charge and discharge when the absolute value of the voltage difference between the first battery and the second battery is greater than or equal to a first threshold, so as to stabilize the voltage of the control terminal of the NMOS module.

[0103] The embodiment of the present application does not limit the specific structures of the first module 401 , the first voltage dividing module 402 , the second voltage dividing module 403 and the voltage stabilizing module 404 .

[0104] The control flow of the circuit shown in FIG. 4 is described below with reference to FIG. 5A to FIG. 5D .

[0105] When the terminal device is in the shutdown state, the second interface 402 continuously outputs a high level, the difference between the voltage at the gate of the switch tube M1 and the voltage at the source of the switch tube M1 is greater than or equal to the threshold voltage of the switch tube M1, and the switch tube M1 is in the on state.

[0106] When the terminal device is in the off state, the first module 401 does not perform a voltage boost process, and the output voltage is the second value. The second value is the same as the voltage Vbatt1 of the first battery. The first resistor R1 and the second resistor R2 divide the voltage at the first module 401, and the voltage conducted by the first module 401 to the gate of U1 is a third value. The voltage value of the third value is equal to Vbatt1*R2 / (R1+R2). The third value is less than the second value Vbatt1.

[0107] The first module 401 charges the capacitor C1 via the first resistor R1. The voltage of the fully charged capacitor C1 is equal to the third value. The voltage at the gate of U1 is the voltage output by the first module after the boost process, i.e., the first value. The voltage at the source of U1 is the voltage Vbatt1 of the first battery 202. If the difference between the voltage at the gate of U1 and the voltage at the source of U1 is less than or equal to the threshold voltage of U1, U1 is in the off state.

[0108] Adaptively, the voltage at the gate of U1 is a third value, which is smaller than the voltage Vbatt1 of the first battery 202 .

[0109] It can be understood that, as shown in Figure 5A, the voltage at the source of U1 is the voltage Vbatt1 of the first battery 202; the voltage at the gate of U1 is a second value, which is less than Vbatt1, and the difference between the voltage at the gate of U1 and the voltage at the source of U1 is less than the threshold voltage of U1, and U1 is in the off state.

[0110] In the embodiment of the present application, in the shutdown state, U1 is turned off, which can reduce direct conduction between the first and second batteries. When the voltage difference between the first and second batteries is too large, direct conduction between the two batteries can be reduced, thereby reducing damage to components in the path between the two batteries. When the voltage difference between the first and second batteries is too large, the current in the path is reduced from exceeding the battery's own charge and discharge current value, thereby reducing battery damage.

[0111] In the embodiment of the present application, the third value is less than the sum of Vbatt2 and the threshold voltage, and the third value is less than Vbatt1. In this way, under different circumstances, U2 is in the off state.

[0112] In some embodiments, the third value is the same as the discharge cut-off voltage of the second battery. Thus, in different situations, U2 is in the off state.

[0113] Specifically, in possible situation one, the second battery 203 is in working state, and the voltage of the second battery 203 is greater than the discharge cut-off voltage, then the voltage at the source of U2 is the voltage Vbatt2 of the second battery 203; the voltage at the gate of U2 is the same as the voltage at the gate of U1, which is the third value, the third value is Vbatt1*R2 / (R1+R2), and the third value is less than Vbatt1.

[0114] In the embodiment of the present application, the third value is less than the sum of the discharge cut-off voltage of the second battery and the threshold voltage of U2. In this way, the difference between the voltage at the gate of U2 and the voltage at the source of U2 is less than the threshold voltage of U2, and U2 is in the off state.

[0115] In possible scenario two, the second battery 203 is in an overdischarged state, and the voltage of the second battery 203 is less than the discharge cutoff voltage. The second battery 203 does not output voltage to the charging chip 201. The fifth resistor R5 can conduct electricity between the first battery 202 and the second battery 203. The voltage at the source of the second NMOS U2 is the voltage Vbatt1 of the first battery 202. The voltage at the gate of U2 is a second value; the difference between the voltage at the gate of U2 and the voltage at the source of U2 is less than the threshold voltage of U2, and U2 is in the off state.

[0116] The over-discharge state can be understood as a state of no power, or can be understood as the voltage of the second battery being lower than the discharge cut-off voltage.

[0117] In possible case three, the voltage of the second battery 203 is equal to the discharge cut-off voltage. The difference between the voltage at the gate of U2 and the voltage at the source of U2 is zero, which is less than the threshold voltage of U2, and U2 is in the off state.

[0118] For example, the discharge cut-off voltage of the second battery is 2.5V and the voltage of the first battery 202 is 4.5V. If the voltage of the second battery is greater than 2.5V, the voltage at the source of U2 is greater than 2.5V. The voltage at the gate of U2 is 2.5V. At this time, U2 is in the off state; if the voltage of the second battery is less than 2.5V, the voltage at the source of U2 is the voltage of the first battery 202, that is, 4.5V. The voltage at the gate of U2 is 2.5V. At this time, U2 is in the off state; if the voltage of the second battery is 2.5V, the voltage at the source of U2 is 2.5V. The voltage at the gate of U2 is 2.5V. At this time, U2 is in the off state.

[0119] In this way, when the device is off, both U1 and U2 are turned off, reducing direct conduction between the first and second batteries. This can also reduce direct conduction between the two batteries when the voltage difference between them is too large, thereby minimizing damage to components in the path between the two batteries. This also reduces the current in the path from exceeding the battery's inherent charge and discharge current when the voltage difference between the first and second batteries is too large, minimizing damage to the batteries.

[0120] It is understandable that when the terminal device is powered on, the states of the first battery and the second battery are divided into two situations: a large pressure difference scenario and a small pressure difference scenario. Adaptively, each of the two scenarios has a corresponding control process.

[0121] In scenarios with large voltage differences, the second interface 402 outputs a waveform that alternates between high and low levels (as shown in FIG5B ), and capacitor C1 alternately charges and discharges, causing U1 to operate in the linear region and be in a linear conduction state. This causes the voltage of the first battery 202 and the voltage of the second battery 203 to continuously approach each other, and the absolute value of the difference between the two gradually decreases. In scenarios with small voltage differences, the second interface continuously outputs a low level, and U1 is in a conducting state, allowing the battery and mobile terminal to operate normally.

[0122] Specifically, when the terminal device is powered on, the first module boosts the voltage output by the first battery to a first value. The first value is greater than the voltage Vbatt1 output by the first battery. The voltage output by the first module 401 is transmitted to the gate of U1 via the first resistor R1.

[0123] When the second interface 402 outputs a low level, the difference between the voltage at the gate of the switch tube M1 and the voltage at the source of the switch tube M1 is zero, which is less than the threshold voltage of the switch tube M1, and the switch tube M1 is in the off state (as shown in FIG5C).

[0124] It is understood that when the switch M1 is in the off state, the first resistor R1 and the second resistor R2 have no voltage dividing function, and the first module 401 charges the capacitor C1. The voltage at the gate of U1 is the voltage of the capacitor C1. The voltage at the source of U1 is the voltage Vbatt1 of the first battery 202.

[0125] When the difference between the voltage of capacitor C1 and the voltage Vbatt1 of the first battery 202 is greater than the threshold voltage of U1, U1 is turned on; when the difference between the voltage of capacitor C1 and the voltage Vbatt1 of the first battery 202 is less than or equal to the threshold voltage of U1, U1 is turned off. Alternatively, it can be understood that whether U1 is in the on state or the off state depends on the voltage of capacitor C1.

[0126] It can be understood that the voltage at the source of U2 is the voltage of the second battery, Vbatt2. The voltage at the gate of U2 is the same as the voltage at the gate of U1, both of which are the voltage of capacitor C1. Similarly, whether U2 is in the on state or the off state depends on the voltage of capacitor C1.

[0127] When the second interface 402 outputs a high level, the difference between the voltage at the gate of the switch tube M1 and the voltage at the source of the switch tube M1 is greater than or equal to the threshold voltage of the switch tube M1, and the switch tube M1 is turned on.

[0128] The first module 401 boosts the voltage output by the first battery, and the resulting voltage is a first value. The first resistor R1 and the second resistor R2 divide the voltage output by the first module 401. The voltage transmitted from the first module 401 to the gate of U1 is a fourth value, which is less than the first value.

[0129] If the difference between the voltage at the gate of U1 and the voltage at the source of U1 is less than U1's threshold voltage, U1 is in the off state. The voltage at the source of U2 is the voltage of the second battery, Vbatt2. The voltage at the gate of U2 is the same as the voltage at the gate of U1, both being the voltage of capacitor C1. If the difference between the voltage at the gate of U2 and the voltage at the source of U2 is less than U2's threshold voltage, U2 is in the off state.

[0130] It is understood that when the switch M1 is turned on, the capacitor C1 can discharge through the second resistor R2 and the switch M1. The voltage at the gate of U1 is equal to the voltage of the capacitor C1, and the voltage of the capacitor C1 is less than the voltage at the first module 401 (as shown in FIG5D).

[0131] It should be noted that during the charging and discharging process of the capacitor C1, the voltage fluctuation of the capacitor C1 is slow (i.e., the change of the voltage of the capacitor C1 is not strong). The charging and discharging process of the capacitor C1 stabilizes the voltage of the capacitor C1. After the capacitor C1 stabilizes, the capacitor C1 has a voltage value.

[0132] During the charging and discharging process of the capacitor C1, the voltage of the capacitor C1 continuously increases, and the voltage of the gate G of the MOS transistor U1 and the voltage of the gate G of the MOS transistor U2 also continuously increases (because the voltage of the gate G of the MOS transistor U1 and the voltage of the gate G of the MOS transistor U2 are both the voltage of the capacitor C1), so that U1 and U2 are both in a linear conduction state; thereby, the voltage of the first battery and the voltage of the second battery continuously approach each other, and thus the absolute value of the difference between the voltage of the first battery and the voltage of the second battery gradually decreases.

[0133] In the scenario where the voltage difference is small, the second interface 402 continuously outputs a low level. The difference between the voltage at the gate of the switch M1 and the voltage at the source of the switch M1 is zero, which is less than the threshold voltage of the switch M1, and the switch M1 is in the off state.

[0134] When the terminal device is powered on, the first module boosts the voltage output by the first battery to a first value. The first value is greater than the voltage Vbatt1 output by the first battery. The voltage output by the first module 401 is transmitted to the gate of U1 via the first resistor R1.

[0135] It is understood that when switch M1 is in the off state, first resistor R1 and second resistor R2 have no voltage divider function, and first module 401 charges capacitor C1. The voltage of capacitor C1 after full charge is equal to the first value. The voltage at the gate of U1 is the first value; the voltage at the source of U1 is the voltage Vbatt1 of the first battery 202 (as shown in Figure 5C).

[0136] The difference between the voltage at the gate of U1 and the voltage at the source of U1 is greater than the threshold voltage of U1, and U1 is in the on state.

[0137] The voltage at the source of U2 is the voltage Vbatt2 of the second battery 203. The difference between the voltage at the gate of U2 and the voltage at the source of U2 is greater than the threshold voltage of U2, and U2 is in the on state.

[0138] In the circuit shown in FIG4 , when the voltage difference is large, U1 and U2 are both in a linear conduction state to balance the voltage of the first battery and the voltage of the second battery. When the voltage difference is small, U1 and U2 are both turned on, allowing the first battery, the second battery, the load, etc. to operate normally.

[0139] In summary, the circuit shown in Figure 4 isolates parallel batteries through NMOS transistors when a voltage difference is large, reducing direct conduction between batteries. Furthermore, the source of switch M1 is grounded. When switch M1 is on, the voltage at the gate is low, requiring a low power supply voltage, making implementation easier. The control unit in the circuit shown in Figure 4 requires a low power supply voltage, reducing the need for higher-voltage power supplies and lowering power consumption in terminal devices.

[0140] For example, Figure 6 is a schematic diagram of the structure of another control unit according to an embodiment of the present application. As shown in Figure 6 , the control unit includes: a first module 601 , a first voltage dividing module 602 , a second voltage dividing module 603 and a voltage stabilizing module 604 .

[0141] The structures and functions of the first voltage dividing module 602 , the second voltage dividing module 603 and the voltage stabilizing module 604 can be referred to the above corresponding descriptions and will not be repeated here.

[0142] As shown in FIG6 , the first voltage dividing module 602 includes a first resistor R1 , the second voltage dividing module 603 includes a second resistor R2 , a switch tube M1 and a switch tube M2 , and the voltage stabilizing module 604 includes a capacitor C1 .

[0143] One end of the first resistor R1 is connected to the first module 401, and the other end of the first resistor R1 is connected to the gate of U1; one end of the second resistor R2 is connected to the other end of the first resistor R1, and the other end of the second resistor R2 is connected to the drain of the switch tube M1; the gate of the switch tube M1 is connected to the drain of the switch tube M2, the source of the switch tube M1 is grounded, the gate of the switch tube M2 is connected to the third interface 403, and the source of the switch tube M2 is grounded; one end of the capacitor C1 is connected to the gate of U1, and the other end of the capacitor C1 is grounded.

[0144] The functions of the first module 601 , the first resistor R1 , the second resistor R2 , and the capacitor C1 can be referred to the corresponding description above and will not be repeated here.

[0145] In some embodiments, the second voltage divider module 603 further includes a second interface 605 for supplying power to the gate of M1 and a second interface 602 for outputting a continuous high-level signal to the gate of M1.

[0146] In some embodiments, the second voltage divider module 603 further includes a third interface 606 configured to output a high-low alternating signal to control M2 to alternately turn on and off when the absolute value of the difference between the voltage of the first battery 202 and the voltage of the second battery 203 is greater than or equal to a first threshold. In this manner, M2 is alternately turned on and off, which in turn causes M1 to alternately turn on and off, and capacitor C1 to alternately charge and discharge, thereby placing the NMOS in the NMOS module in a linear conduction state.

[0147] The third interface 606 is further configured to output a high-level signal when the absolute value of the difference between the voltage of the first battery 202 and the voltage of the second battery 203 is less than a first threshold, thereby controlling M1 to be turned off via M2. Thus, when M1 is turned off via M2, the first module supplies power to the capacitor C1, causing the NMOS in the NMOS module to be in a conductive state.

[0148] The third interface 606 is further configured to output a low-level signal when the terminal device is turned off, so as to control M1 to be turned on through M2, so that the NMOS in the NMOS module is in the off state.

[0149] The following describes the working process of the control unit in the circuit shown in FIG6 in combination with different states of the terminal device.

[0150] When the terminal device is in the shutdown state, the third interface 606 has no output, a low level, the difference between the voltage at the gate of the switch tube M2 and the voltage at the source of the switch tube M2 is less than the threshold voltage of the switch tube M2, and the switch tube M2 is in the off state.

[0151] The second interface 605 outputs a high level, the difference between the voltage at the gate of the switch tube M1 and the voltage at the source of the switch tube M1 is greater than or equal to the threshold voltage of the switch tube M2, and the switch tube M1 is in the on state.

[0152] When the terminal device is in the off state, the first module 401 does not operate and the output voltage is the second value. The first resistor R1 and the second resistor R2 divide the voltage at the first module 401, and the voltage transmitted from the first module 401 to the gate of U1 is a third value. The third value is smaller than the second value.

[0153] The first module 401 charges the capacitor C1 via the first resistor R1. The voltage of the fully charged capacitor C1 is equal to the third value. The voltage at the gate of U1 is the first value; the voltage at the source of U1 is the voltage Vbatt1 of the first battery 202. The difference between the voltage at the gate of U1 and the voltage at the source of U1 is less than or equal to the threshold voltage of U1, and U1 is in the off state.

[0154] In the embodiment of the present application, in the shutdown state, U1 is turned off, which can reduce direct conduction between the first and second batteries. When the voltage difference between the first and second batteries is too large, direct conduction between the two batteries can be reduced, thereby reducing damage to components in the path between the two batteries. When the voltage difference between the first and second batteries is too large, the current in the path is reduced from exceeding the battery's own charge and discharge current value, thereby reducing battery damage.

[0155] In some embodiments, the third value is the same as the discharge cut-off voltage of the second battery. Thus, in different situations, U2 is in the off state.

[0156] Specifically, in possible situation one, the second battery 203 is in working state, and the voltage of the second battery 203 is greater than the discharge cut-off voltage, then the voltage at the source of U2 is the voltage Vbatt2 of the second battery 203; the voltage at the gate of U2 is the same as the voltage at the gate of U1, which is the third value and is less than Vbatt1.

[0157] The difference between the voltage at the gate of U2 and the voltage at the source of U2 is less than the threshold voltage of U2, and U2 is in the off state.

[0158] In possible scenario two, the second battery 203 is in an over-discharge state, and the voltage of the second battery 203 is less than the discharge cut-off voltage. The protection board corresponding to the second battery 203 is turned off, and the second battery 203 does not output a voltage. The fifth resistor R5 can conduct electricity between the first battery 202 and the second battery 203, and the voltage at the source of the second NMOS U2 is the voltage Vbatt1 of the first battery 202. The voltage at the gate of U2 is a second value; the difference between the voltage at the gate of U2 and the voltage at the source of U2 is less than the threshold voltage of U2, and U2 is in the off state.

[0159] The over-discharge state can be understood as a state of no power, or can be understood as being lower than the discharge cut-off voltage, etc.

[0160] In possible case three, the voltage of the second battery 203 is equal to the discharge cut-off voltage. The difference between the voltage at the gate of U2 and the voltage at the source of U2 is zero, which is less than the threshold voltage of U2, and U2 is in the off state.

[0161] Take the case where the discharge cut-off voltage is 2.5V and the voltage of the first battery 202 is 4.5V as an example. If the voltage of the second battery is greater than 2.5V, the voltage at the source of U2 is greater than 2.5V. The voltage at the gate of U2 is 2.5V. At this time, U2 is in the off state; if the voltage of the second battery is less than 2.5V, the voltage at the source of U2 is the voltage of the first battery 202, that is, 4.5V. The voltage at the gate of U2 is 2.5V. At this time, U2 is in the off state; if the voltage of the second battery is 2.5V, the voltage at the source of U2 is 2.5V. The voltage at the gate of U2 is 2.5V. At this time, U2 is in the off state.

[0162] In this way, when the device is off, both U1 and U2 are turned off, reducing direct conduction between the first and second batteries. This can also reduce direct conduction between the two batteries when the voltage difference between them is too large, thereby minimizing damage to components in the path between the two batteries. This also reduces the current in the path from exceeding the battery's inherent charge and discharge current when the voltage difference between the first and second batteries is too large, minimizing damage to the batteries.

[0163] It is understandable that when the terminal device is powered on, the states of the first battery and the second battery are divided into two situations: a large pressure difference scenario and a small pressure difference scenario. Adaptively, each of the two scenarios has a corresponding control process.

[0164] In a scenario with a large voltage difference, the third interface 606 outputs a waveform that alternates between high and low levels, and the second interface continuously outputs a high level. Based on the on / off control of the switch tube M2, the switch tube M1 is turned on or off, thereby controlling the alternating charging and discharging of the capacitor C1, so that U1 operates in the linear region and is in a linear conduction state, so that the voltage of the first battery 202 and the voltage of the second battery 203 are continuously approaching, and the absolute value of the difference between the two gradually decreases.

[0165] In a scenario where the voltage difference is small, the third interface continuously outputs a low level, the second interface continuously outputs a high level, and U1 is in the on state, allowing the battery and the mobile terminal to work normally.

[0166] Specifically, when the terminal device is powered on, the first module boosts the voltage output by the first battery to a first value. The first value is greater than the voltage Vbatt1 output by the first battery. The voltage output by the first module 401 is transmitted to the gate of U1 via the first resistor R1.

[0167] When the third interface outputs a high level, the difference between the voltage at the gate of switch M2 and the voltage at the source of switch M2 is greater than the threshold voltage of M2, and switch M2 is in the on state. Since switch M2 is on and the source of switch M2 is grounded, the gate voltage of switch M1 is zero. The difference between the voltage at the gate of switch M1 and the voltage at the source of switch M1 is zero, which is less than the threshold voltage of switch M1, and switch M1 is in the off state.

[0168] It is understood that when the switch M1 is in the off state, the first resistor R1 and the second resistor R2 have no voltage dividing function, and the first module 601 charges the capacitor C1. The voltage at the gate of U1 is the voltage of the capacitor C1. The voltage at the source of U1 is the voltage Vbatt1 of the first battery 202.

[0169] When the difference between the voltage of capacitor C1 and the voltage Vbatt1 of the first battery 202 is greater than the threshold voltage of U1, U1 is turned on; when the difference between the voltage of capacitor C1 and the voltage Vbatt1 of the first battery 202 is less than or equal to the threshold voltage of U1, U1 is turned off. Alternatively, it can be understood that whether U1 is in the on state or the off state depends on the voltage of capacitor C1.

[0170] It can be understood that the voltage at the source of U2 is the voltage of the second battery, Vbatt2. The voltage at the gate of U2 is the same as the voltage at the gate of U1, both of which are the voltage of capacitor C1. Similarly, whether U2 is in the on state or the off state depends on the voltage of capacitor C1.

[0171] When the third interface outputs a low level, the difference between the voltage at the gate of the switch tube M2 and the voltage at the source of the switch tube M2 is smaller than the threshold voltage of M2, and the switch tube M2 is in the off state.

[0172] Since the switch M2 is turned off, the voltage output by the second interface 402 is transmitted to the gate of the switch M1. The difference between the voltage at the gate of the switch M1 and the voltage at the source of the switch M1 is greater than or equal to the threshold voltage of the switch M1, and the switch M1 is turned on.

[0173] The first module 401 boosts the voltage output by the first battery, and the resulting voltage is a first value. The first resistor R1 and the second resistor R2 divide the voltage output by the first module 601. The voltage transmitted from the first module 401 to the gate of U1 is a fourth value, which is less than the first value.

[0174] If the difference between the voltage at the gate of U1 and the voltage at the source of U1 is less than U1's threshold voltage, U1 is in the off state. The voltage at the source of U2 is the voltage of the second battery, Vbatt2. The voltage at the gate of U2 is the same as the voltage at the gate of U1, both being the voltage of capacitor C1. If the difference between the voltage at the gate of U2 and the voltage at the source of U2 is less than U2's threshold voltage, U2 is in the off state.

[0175] It is understandable that when the switch M1 is turned on, the capacitor C1 can discharge through the second resistor R2 and the switch M1. The voltage at the gate of U1 is equal to the voltage of the capacitor C1, and the voltage of the capacitor C1 is less than the voltage at the first module 401.

[0176] It should be noted that during the charging and discharging process of the capacitor C1, the voltage fluctuation of the capacitor C1 is slow (i.e., the change of the voltage of the capacitor C1 is not strong). The charging and discharging process of the capacitor C1 stabilizes the voltage of the capacitor C1. After the capacitor C1 stabilizes, the capacitor C1 has a voltage value.

[0177] During the charging and discharging process of capacitor C1, the voltage of capacitor C1 continues to increase, and the voltage at the gate of U1 and the voltage at the gate of U2 also continue to increase (because the voltage at the gate of U1 and the voltage at the gate of U2 are both the voltage of capacitor C1), so that U1 and U2 are both in a linear conduction state; thereby, the voltage of the first battery and the voltage of the second battery continue to approach each other, so that the absolute value of the difference between the output voltage and the output voltage of v2 gradually decreases.

[0178] In scenarios where the voltage difference is small, the third interface 606 continuously outputs a high level. The difference between the voltage at the gate of switch M2 and the voltage at the source of switch M2 is greater than the threshold voltage of M2, and switch M2 is in the on state. Since switch M2 is on and the source of switch M2 is grounded, the gate voltage of switch M1 is 0. The difference between the voltage at the gate of switch M1 and the voltage at the source of switch M1 is zero, which is less than the threshold voltage of switch M1, and switch M1 is in the off state.

[0179] The voltage at the source of U2 is the voltage Vbatt2 of the second battery 203. The difference between the voltage at the gate of U2 and the voltage at the source of U2 is greater than the threshold voltage of U2, and U2 is in the on state.

[0180] When the voltage difference is large, U1 and U2 are both in a linear conduction state to balance the voltage of the first battery and the voltage of the second battery; when the voltage difference is small, U1 and U2 are both turned on, so that the first battery, the second battery, the load, etc. can operate normally.

[0181] In summary, the circuit shown in Figure 6 isolates parallel batteries through NMOS transistors when a voltage difference is large, reducing direct conduction between batteries. Furthermore, the source of switch M1 is grounded. When switch M1 is on, the voltage at the gate is low, requiring a low power supply voltage, making implementation easier. The control unit in the circuit shown in Figure 6 requires a low power supply voltage, reducing the need for higher-voltage power supplies and lowering power consumption in terminal devices.

[0182] It is understandable that in the control unit shown in Figure 4, different voltage signals from the second interface control the on / off switching of M1. The second interface needs to output a high level in the off state, and after powering on, it outputs alternating high and low levels when the voltage difference between the first and second batteries is large, and outputs a low level when the voltage difference between the first and second batteries is small. The need to output a high level in the off state is relatively difficult to implement. Compared to the control unit shown in Figure 4, the control unit shown in Figure 6 adds an interface and a switch tube M2. In this way, the second interface is a constantly powered interface, and the on / off switching of M1 and M2 is controlled by different voltage signals from the third interface. The third interface outputs a low level in the off state, and after powering on, it outputs alternating high and low levels when the voltage difference is large, and a high level when the voltage difference is small. In this way, the second interface outputs a fixed, low voltage, and the third interface outputs a low voltage in the off state, which is relatively simple to implement.

[0183] In the embodiment shown in FIG6 , the third interface 606 may be an interface on a GPIO (or referred to as a “pin”).

[0184] The second interface 605 can be used to power a chip in a terminal device. The chip can be a power management chip or any other type of chip, etc., and this embodiment of the application is not limited to this. Exemplarily, the second interface can be an interface for powering the IO of the power management chip. Exemplarily, the system's LDO includes two interfaces, one interface for inputting battery voltage and the other interface for outputting 1.8V voltage to power the IO of the system's power management chip.

[0185] Based on the embodiment shown in FIG6 , the control unit further includes a third resistor R3. The third resistor R3 is used to protect the second interface 605. The third resistor R3 is located between the second interface 402 and the gate of the switch tube M1.

[0186] Exemplarily, as shown in FIG6 , one end of the third resistor R3 is connected to the second interface 402 , and the other end of the third resistor R3 is connected to the drain of the switch tube M2 .

[0187] In this way, the situation where the second interface 605 is directly grounded can be reduced.

[0188] Based on the embodiment shown in FIG6 , the control unit further includes a fourth resistor R4 . The fourth resistor R4 is used to protect the switch tube M2 . The fourth resistor R3 is located between the third interface 403 and the gate of the switch tube M2 .

[0189] For example, as shown in FIG7 , one end of the fourth resistor R3 is connected to the third interface 403 , and the other end of the fourth resistor R4 is connected to the gate of the switch tube M2 .

[0190] In this way, the situation where the switch tube M2 is damaged due to excessive voltage output by the third interface 606 can be reduced.

[0191] Based on the above embodiment, the NMOS module 205 further includes a fifth resistor R5. One end of the fifth resistor R5 is connected to the first battery 202, and the other end of the fifth resistor R5 is connected to the second battery 203. The fifth resistor R5 can perform low-current hardware balancing on the first battery and the second battery when the terminal device is in the off state.

[0192] The above workflow illustrates the control process of the control unit using an NMOS module including two NMOS transistors as an example. In some embodiments, the NMOS module includes one NMOS transistor. Exemplarily, as shown in FIG7 , the NMOS module 205 includes a third NMOS transistor U3. The drain (D) of U3 is connected to the first battery 202, the source (S) of U3 is connected to the second battery 203, and the gate (G) of U3 is connected to the control unit 206.

[0193] It is understood that when the absolute value of the voltage difference between the first battery and the second battery is greater than or equal to the first threshold, U3 operates in the linear region. When the voltage difference between the first battery and the second battery is less than the first threshold, U3 is turned on. When the terminal device is turned off, U3 is turned off.

[0194] When the NMOS module includes an NMOS transistor U3, the control flow of the control unit can refer to the above description of U2 and will not be repeated here.

[0195] In the embodiments shown in Figures 2-7 above, the first module outputs a first voltage value when powered off and a second voltage value when powered on. For example, Figure 8 is a schematic diagram of the structure of a first module provided in an embodiment of the present application. As shown in Figure 8, the first module includes: control logic 801, a voltage adjustment module 802, and a feedback module 803.

[0196] The control logic 801 is used to adjust the voltage output by the voltage adjustment module 802 based on the voltage input by the voltage adjustment module 802 and the error between the preset voltage and the voltage at the control terminal of the NMOS module. The preset voltage is the voltage at the control terminal of the NMOS module in a preset startup scenario.

[0197] The voltage adjustment module 802 is used to boost the voltage input to the first module (the voltage output by the first battery) so that the NMOS in the NMOS module is in a linear conduction state or a conduction state.

[0198] As shown in FIG8 , the voltage adjustment module 802 includes a switch A1 , a switch A2 , and an inductor.

[0199] When the terminal device is turned on, switch A1 is turned on, and switch A2 is turned on and off alternately. When switch A2 is turned on, the voltage input by the first module (the voltage of the first battery) flows through inductor L1 and switch A2. During this process, the current on the inductor increases linearly at a certain ratio, and the inductor stores energy. When switch A2 is turned off, due to the current retention characteristic of the inductor, the current flowing through the inductor slowly changes from the value at the time of charging to 0. Inductor L1 charges capacitor C1, the voltage difference across capacitor C1 increases, and the voltage output by voltage adjustment module 802 is greater than the voltage input by voltage adjustment module 802.

[0200] When the terminal device is turned off, the switch tube A1 is turned on and the switch tube A2 is turned off.

[0201] The feedback module 803 is configured to feed back the error between the preset voltage and the voltage at the third terminal of the NMOS module to the control logic 803 .

[0202] As shown in FIG8 , the feedback module 803 includes an error amplifier and a comparator, which are used to obtain the error between the preset voltage and the voltage at the third electrode of the NMOS module.

[0203] It is understandable that the first module continuously outputs a fixed voltage in the power-on state. The first module can be an existing module in the terminal device, for example, a module used as a driver (power management unit, PMU), etc., and the embodiment of the present application is not limited to this.

[0204] In this way, there is no need to add a module with a boost function, saving circuit area and cost.

[0205] The above embodiment uses two batteries connected in parallel as an example. If the terminal device uses three or more batteries connected in parallel, the NMOS module in the above circuit and the control unit for controlling the NMOS module are included between any two batteries. This embodiment of the application does not limit the number of batteries connected in parallel in the terminal device.

[0206] An embodiment of the present application provides a terminal device, which includes: a processor and a memory; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory, so that the terminal device executes the above method.

[0207] For example, FIG9 is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application. As shown in FIG9, the terminal device includes: the terminal device may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0208] It should be understood that the structures illustrated in the embodiments of the present invention do not constitute specific limitations on the terminal device. In other embodiments of the present application, the terminal device may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0209] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0210] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0211] Processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 110. If processor 110 needs to use the same instruction or data again, it can directly retrieve it from the memory. This avoids duplicate accesses, reduces processor 110 latency, and thus improves system efficiency.

[0212] In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0213] It is understood that the interface connection relationship between the modules illustrated in the embodiment of the present invention is only a schematic illustration and does not constitute a structural limitation on the terminal device. In other embodiments of the present application, the terminal device may also adopt a different interface connection method from the above embodiment, or a combination of multiple interface connection methods.

[0214] The charging management module 140 is configured to receive charging input from a charger. The charger can be either a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 can receive charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 can receive wireless charging input via a wireless charging coil in the terminal device. While charging the battery 142, the charging management module 140 can also power the electronic device through the power management module 141.

[0215] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and provides power to the processor 110, the internal memory 121, the display 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

[0216] It will be appreciated that the battery in the charge-discharge circuit in the above embodiment corresponds to battery 142 in FIG. 9 . The terminal device includes at least two batteries 142 . The charging interface corresponds to USB interface 130 . The power management module 141 includes the charge-discharge circuit shown in the above embodiment. In some embodiments, the power management module 141 is located in the processor.

[0217] The terminal device implements display functionality through a GPU, display screen 194, and an application processor. The GPU is a microprocessor for image processing that connects display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0218] Display screen 194 is used to display images, videos, etc. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-oLed, or a quantum dot light-emitting diode (QLED). In some embodiments, the terminal device can include one or N display screens 194, where N is a positive integer greater than 1.

[0219] The terminal device can realize the shooting function through the ISP, camera 193, video codec, GPU, display 194 and application processor.

[0220] The ISP processes data fed back by camera 193. For example, when taking a photo, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, which is then passed to the ISP for processing and transformed into a visible image. The ISP can also perform algorithmic optimization on image noise, brightness, and skin tone. It can also optimize parameters such as exposure and color temperature of the captured scene. In some embodiments, the ISP can be located within camera 193.

[0221] Camera 193 is used to capture still images or videos. In some embodiments, the terminal device may include one or N cameras 193, where N is a positive integer greater than 1. The types of the multiple cameras 193 can vary. For example, camera 193 may include a camera for capturing color images or a time-of-flight camera. In the embodiments of the present application, a camera can be understood as a camera. Cameras include: the AO camera, time-of-flight camera, etc. in the embodiments of the present application.

[0222] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the terminal device. The external memory card communicates with the processor 110 via the external memory interface 120 to implement data storage functions. For example, files such as music and videos can be stored on the external memory card.

[0223] The internal memory 121 can be used to store computer executable program codes, which include instructions. The internal memory 121 can include a program storage area and a data storage area.

[0224] The terminal device can implement audio functions such as music playback and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0225] Keys 190 include a power button, a volume button, and other buttons. Keys 190 can be mechanical or touch-sensitive. The terminal device can receive key inputs and generate key signal inputs related to user settings and function control of the terminal device. Indicator 192 can be an indicator light that can be used to indicate charging status, battery level changes, messages, missed calls, notifications, and the like.

[0226] In addition, on top of the above components, the device also runs an operating system, such as the iOS operating system, the Android operating system, or the Windows operating system. Applications can be installed and run on the operating system.

[0227] The software system of the terminal device can adopt a layered architecture, event-driven architecture, micro-kernel architecture, microservice architecture, or cloud architecture, etc., which will not be described here.

[0228] An embodiment of the present application provides a terminal device, which includes a load and the charge-discharge circuit provided in the above embodiment, wherein the charge-discharge circuit is used to supply power to the load.

[0229] An embodiment of the present application provides a chip, which includes the charge-discharge circuit provided in the above embodiment.

[0230] The present embodiment provides a chip. The chip includes a processor configured to invoke a computer program stored in a memory to execute the technical solution of the above embodiment. The implementation principles and technical effects are similar to those of the above-mentioned related embodiments and will not be further described here.

[0231] The embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the above-mentioned method is implemented. The methods described in the above embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted on a computer-readable medium. Computer-readable media can include computer storage media and communication media, and can also include any medium that can transfer a computer program from one place to another. The storage medium can be any target medium that can be accessed by a computer.

[0232] In one possible implementation, computer-readable media may include RAM, ROM, compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium designed to carry or store the desired program code in the form of instructions or data structures and accessible by a computer. Moreover, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave are used to transmit software from a website, server or other remote source, the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwave are included in the definition of medium. Disk and optical disk as used herein include optical disk, laser disk, optical disk, digital versatile disk (DVD), floppy disk and Blu-ray disk, where disks generally reproduce data magnetically, while optical disks reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0233] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed, the computer executes the above method.

[0234] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application.It should be understood that each flow process and / or box in the flow chart and / or block diagram and the combination of the flow process and / or box in the flow chart and / or block diagram can be realized by computer program instructions.These computer program instructions can be provided to the processing unit of general-purpose computer, special-purpose computer, embedded processing machine or other programmable device to produce a machine, so that the instruction executed by the processing unit of computer or other programmable data processing device produces the device for realizing the function specified in one flow chart flow or multiple flows and / or one block or multiple blocks of block diagram.

[0235] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0236] The above specific implementation methods further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of the present invention should be included in the scope of protection of the present invention.

Claims

1. A charging and discharging circuit, characterized in that: Applied to terminal equipment, the charging and discharging circuit includes: a first battery, a second battery, an NMOS module and a control unit; the NMOS module includes one or more NMOSs, and the NMOS module is controlled by the control unit; The control unit is used to control the NMOS module to be in a linear conduction state when the terminal device is turned on and the voltage difference between the first battery and the second battery is greater than a first threshold value, so as to reduce the voltage difference between the first battery and the second battery; Wherein, when the NMOS module is in the linear conduction state, one or more NMOS in the NMOS module operates in the linear region; The control unit is further configured to control the NMOS module to be in the on state when the terminal device is turned on and the difference between the voltage of the first battery and the voltage of the second battery is less than or equal to the first threshold; The control unit comprises: a first module with a voltage boosting function, a first voltage dividing module, a second voltage dividing module and a voltage stabilizing module; The other end of the first module is connected to one end of the first voltage divider module, and the other end of the first voltage divider module is connected to the control end of the NMOS module; one end of the second voltage divider module is connected to the other end of the first voltage divider module, and the other end of the second voltage divider module is grounded; one end of the voltage stabilizing module is connected to the control end of the NMOS module, and the other end of the voltage stabilizing module is grounded; The first module is used to boost the input voltage when the terminal device is turned on, so as to provide voltage for the control end of the NMOS module; The first voltage dividing module and the second voltage dividing module are used to divide the voltage output by the first module when the terminal device is turned on, so that the NMOS module is in the linear conduction state or the conduction state; The voltage stabilizing module is used to stabilize the voltage of the control end of the NMOS module.

2. The charge and discharge circuit according to claim 1, characterized in that: The first voltage dividing module includes: a first resistor R1, the second voltage dividing module includes: a second resistor R2 and a switch tube M1, and the voltage stabilizing module includes a capacitor C1; The first module is connected to one end of the R1, and the other end of the R1 is connected to the control end of the NMOS module; one end of the R2 is connected to the other end of the R1, and the other end of the R2 is connected to the drain of the M1; the source of the M1 is grounded, one end of the C1 is connected to the control end of the NMOS module, and the other end of the C1 is grounded; When the voltage difference between the first battery and the second battery is greater than the first threshold, the M1 is used to alternate between on and off, so that the NMOS module is in the linear on state; When the voltage difference between the first battery and the second battery is less than or equal to the first threshold, the switch tube M1 is used to be continuously turned on, so that the NMOS module is in the on state.

3. The charge and discharge circuit according to claim 1 or 2, characterized in that: The first module includes: a voltage adjustment module; an input end of the voltage adjustment module is connected to the first battery, and an output end of the voltage adjustment module is connected to the first voltage dividing module; The voltage adjustment module is used to boost the voltage output by the first battery so that the NMOS in the NMOS module is in a linear conduction state or a conduction state.

4. The charge and discharge circuit according to claim 3, characterized in that: The first module also includes: a control logic and feedback module; The control logic is used to adjust the voltage output by the voltage adjustment module based on the voltage at the input end of the voltage adjustment module and the error between the first voltage and the voltage at the control end of the NMOS module; the first voltage is a preset voltage at the control end of the NMOS module; The feedback module is used to feed back to the control logic the error between a preset voltage and a voltage at the control end of the NMOS module, wherein the preset voltage is the voltage at the control end of the NMOS module in a preset startup scenario.

5. The charge and discharge circuit according to any one of claims 1 to 4, characterized in that: The second voltage dividing module further includes: a switch tube M2; the source of the M2 is grounded, and the drain of the M2 is connected to the gate of the M1; The M2 is used to alternate between being turned on and off when the terminal device is turned on and the voltage difference between the first battery and the second battery is greater than the first threshold, so that the M2 alternates between being turned off and on; The M2 is also used to turn off when the terminal device is turned on and the voltage difference between the first battery and the second battery is less than or equal to the first threshold, so that the M2 is turned on.

6. The charge and discharge circuit according to claim 5, characterized in that: The second voltage dividing module further includes a second interface and a third resistor R3, and the third resistor is located between the gate of M1 and the second interface; The second interface is used to provide a voltage to the gate of M1.

7. The charge and discharge circuit according to claim 5 or 6, characterized in that: The control unit further includes a fourth resistor R4 and a third interface, wherein the fourth resistor is located between the third interface and the gate of M2; The third interface is used to provide a voltage to the gate of M2; The fourth resistor is used to protect the M2.

8. The charge and discharge circuit according to any one of claims 1 to 7, characterized in that: The control module is further configured to control the NMOS module to be in an off state when the terminal device is turned off, so that the second battery does not supply power.

9. The charge and discharge circuit according to any one of claims 1 to 8, characterized in that: The NMOS module includes a switch tube U1 and a switch tube U2; The source of U1 is connected to the first battery, the source of U2 is connected to the second battery, the drain of U1 is connected to the drain of U2, the gate of U1 is connected to the gate of U2, and the gate of U1 is connected to the control unit.

10. The charge and discharge circuit according to claim 9, characterized in that: When the terminal device is turned off, the output voltage V1 of the first module satisfies: the V1×resistance of the second voltage divider unit÷(resistance of the first voltage divider unit+resistance of the second voltage divider unit)≤(threshold voltage of U2+discharge cut-off voltage of the second battery).

11. The charge and discharge circuit according to any one of claims 1 to 8, characterized in that: The NMOS module includes a switch tube U3; The gate of U3 is connected to the control unit, the source of U3 is connected to the second battery, and the drain of U3 is connected to the first battery.

12. The charge and discharge circuit according to any one of claims 1 to 11, characterized in that: The charging and discharging circuit further includes: a charging chip, wherein the charging chip is connected to the NMOS module; The charging chip is used to charge the first battery and / or the second battery; When the NMOS module includes U1 and U2, the charging chip is connected to the drain of U1; When the NMOS module includes U3, the charging chip is connected to the drain of U3.

13. A terminal device, characterized in that: include: A load, and a charging and discharging circuit as described in any one of claims 1 to 12, wherein the charging and discharging circuit is used to supply power to the load.

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