Semiconductor device

Abstract

The present application discloses a semiconductor device. The semiconductor device comprises: a base body; a drift layer; first trenches, wherein spaced trenches comprise two sub-trench portions spaced apart in a first direction, and the sub-trench portions comprise a plurality of gate trench groups and a plurality of dummy gate trenches; second trenches, wherein the second trenches are arranged between the two sub-trench portions at intervals in the first direction; first connecting trenches, wherein one of the two first connecting trenches connects the ends of one side of the plurality of second trenches in the first direction, the other one of the two first connecting trenches connects the ends of the other side of the plurality of second trenches in the first direction, and the first connecting trenches are connected to the ends of the dummy gate trenches adjacent to the second trenches; and second connecting trenches, wherein the second connecting trenches connect the ends of gate trenches among the gate trench groups adjacent to the second trenches. Therefore, an insulated gate bipolar transistor region and a fast recovery diode region can be prevented from interfering with each other in the process, respective performance of the two regions is ensured, and the current-carrying capacity of the semiconductor device can also be improved.

Description

semiconductor devices Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device. Background Art

[0002] A reverse-conducting insulated gate bipolar transistor (IGBT) is a device that integrates an IGBT and a freewheeling diode (or an IGBT and a fast recovery diode) on a single chip. Typically, when preparing a reverse-conducting IGBT in the industry, the IGBT and the fast recovery diode are integrated into the active region of the device, with the two devices sharing a common terminal, thereby achieving the purpose of integrating a fast recovery diode onto the IGBT.

[0003] In the related art, since the insulated gate bipolar transistor and the fast recovery diode share the active area of ​​the device, the fast recovery diode in this method occupies part of the active area of ​​the insulated gate bipolar transistor. When designing the device, in order to make the device achieve the target on-state voltage drop, the effective area of ​​the device is the sum of the effective area of ​​the insulated gate bipolar transistor and the effective area of ​​the fast recovery diode. Therefore, the total area of ​​the reverse conducting insulated gate bipolar transistor with the same current specification will be larger than the total area of ​​a single insulated gate bipolar transistor, resulting in a larger area of ​​the reverse conducting insulated gate bipolar transistor. In this way, the number of chips that can be produced on a wafer of the same size is smaller, resulting in a higher production cost of the reverse conducting insulated gate bipolar transistor.

[0004] Summary of the Invention

[0005] In a first aspect, the present application discloses a semiconductor device, comprising:

[0006] a drift layer of a first conductivity type;

[0007] a well region of a second conductivity type, the well region being disposed in the drift layer, and an upper surface of the well region constituting at least a portion of an upper surface of the drift layer;

[0008] a field stop layer, the field stop layer being disposed on a lower surface of the drift layer;

[0009] A collector layer of the second conductivity type is provided on the lower surface of the field stop layer. An emitter layer of the first conductivity type is provided in the collector layer. The semiconductor device has an active area. The emitter layer and the active area are staggered.

[0010] In the second aspect, the present application provides a semiconductor device, comprising: a drift layer of a first conductive type; a groove portion, the groove portion extending downward from the upper surface of the drift layer, the groove portion extending in a first direction and being multiple, the multiple groove portions being spaced apart in a second direction and forming a gate trench group and a dummy gate trench group, the gate trench group and the dummy gate trench group being alternately arranged in the second direction; a field stop layer of a first conductive type, the field stop layer being arranged on the lower surface of the drift layer; a collector layer of a second conductive type, the collector layer being arranged on the lower surface of the field stop layer, a first emitter layer of a first conductive type being arranged in the collector layer, the first emitter layer corresponding to the dummy gate trench group above and below.

[0011] In a third aspect, the present application provides a semiconductor device comprising: a drift layer of a first conductivity type; a field stop layer of a first conductivity type, the field stop layer being arranged on a lower surface of the drift layer; a collector layer of a second conductivity type, the collector layer being arranged on a lower surface of the field stop layer; a first emitter layer of a first conductivity type, the first emitter layer being arranged on a lower surface of the field stop layer, the collector layer being circumferentially arranged on an outer side of the first emitter layer; a ring layer of a second conductivity type, the ring layer being arranged in the drift layer, the upper surface of the ring layer constituting at least a portion of the upper surface of the drift layer, the ring layer corresponding to a junction of the collector layer and the first emitter layer, and a plurality of groove portions being arranged in the ring layer; a well layer of a second conductivity type, the well layer being arranged in the drift layer, the upper surface of the well layer constituting at least a portion of the upper surface of the drift layer, the well layer being arranged on both sides of the ring layer and at least partially corresponding to the collector layer and the first emitter layer, and a portion of the well layer corresponding to the collector layer being provided with a plurality of groove portions.

[0012] In a fourth aspect, the present application provides a fast recovery diode, comprising: a substrate of a first conductivity type; a drift layer of the first conductivity type, the drift layer comprising a first concentration doping layer, a second concentration doping layer and a third concentration doping layer, the first concentration doping layer being arranged on the substrate, the second concentration doping layer being arranged on a side of the first concentration doping layer away from the substrate, the third concentration doping layer being arranged on a side of the second concentration doping layer away from the substrate, the doping concentration of the second concentration doping layer being not greater than the doping concentration of the first concentration doping layer and being less than the doping concentration of the third concentration doping layer, the doping concentration of the first concentration doping layer gradually decreasing in a direction away from the substrate; an anode layer of the second conductivity type, the anode layer being arranged on a side of the third concentration doping layer facing away from the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a schematic diagram of a semiconductor device according to some embodiments of the present application;

[0014] FIG2 is a partial cross-sectional view taken along the A1-A1 direction in FIG1 ;

[0015] FIG3 is a partial cross-sectional view of other embodiments along the A1-A1 direction in FIG1 ;

[0016] FIG4 is a partial cross-sectional view of some embodiments along the A1-A1 direction in FIG1 ;

[0017] FIG5 is a schematic diagram of a semiconductor device according to some other embodiments of the present application;

[0018] FIG6 is a schematic diagram of a semiconductor device in some embodiments;

[0019] FIG7 is a schematic diagram of a semiconductor device in some embodiments;

[0020] FIG8 is a partial cross-sectional view taken along the A2-A2 direction in FIG5 or the A3-A3 direction in FIG6;

[0021] FIG9 is a schematic diagram of area B1 in FIG6 ;

[0022] FIG10 is a schematic diagram of the B2 area in FIG7 or the B3 area in FIG5;

[0023] FIG11 is a schematic diagram of a semiconductor device according to some embodiments of the present application from another perspective;

[0024] FIG12 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application;

[0025] FIG13 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present application;

[0026] FIG14 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present application;

[0027] FIG15 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present application;

[0028] FIG16 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present application;

[0029] FIG17 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present application;

[0030] FIG18 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present application;

[0031] FIG19 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present application;

[0032] FIG20 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present application;

[0033] FIG21 is a schematic diagram of a semiconductor device according to some embodiments of the present application;

[0034] FIG22 is a schematic diagram of a semiconductor device from another perspective according to some embodiments of the present application;

[0035] FIG23 is a schematic diagram of a semiconductor device from another perspective according to some other embodiments of the present application;

[0036] FIG24 a is a schematic diagram of a semiconductor device according to some embodiments of the present application from another perspective;

[0037] FIG24 b is a schematic diagram showing the relationship between emitter voltage and current of a semiconductor device according to some embodiments of the present application;

[0038] FIG25 is a schematic diagram of a semiconductor device according to some embodiments of the present application;

[0039] FIG26 is a partial schematic diagram of a semiconductor device according to some embodiments of the present application;

[0040] FIG27 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present application;

[0041] FIG28 is a cross-sectional view of structure 1 according to some embodiments of the present application;

[0042] FIG29 is a cross-sectional view of structure 2 according to some embodiments of the present application;

[0043] FIG30 is a cross-sectional view of structure 3 according to some embodiments of the present application;

[0044] FIG31 is a cross-sectional view of structure 4 according to some embodiments of the present application;

[0045] FIG32 is a schematic diagram of a semiconductor device according to some embodiments of the present application;

[0046] FIG33 is a partial cross-sectional view of a semiconductor device along line AA according to some embodiments of the present application;

[0047] FIG34 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application;

[0048] FIG35 is a cross-sectional view of structure 1 according to some embodiments of the present application;

[0049] FIG36 is a cross-sectional view of structure 2 according to some embodiments of the present application;

[0050] FIG37 is a cross-sectional view of structure 3 according to some embodiments of the present application;

[0051] FIG38 is a cross-sectional view of structure 4 according to some embodiments of the present application;

[0052] FIG39 is a cross-sectional view of structure 5 according to some embodiments of the present application;

[0053] FIG40 is a cross-sectional view of structure 6 according to some embodiments of the present application;

[0054] FIG41 is a cross-sectional view of structure 7 according to some embodiments of the present application;

[0055] FIG42 is a schematic structural diagram of a fast recovery diode according to some embodiments of the present application;

[0056] FIG43 is a linear diagram of the doping concentration of a fast recovery diode according to some embodiments of the present application;

[0057] FIG44 is a linear diagram of the doping concentration of a fast recovery diode according to another embodiment of the present application;

[0058] FIG45 is a linear diagram of the electric field strength of a fast recovery diode according to some embodiments of the present application;

[0059] FIG46 is a linear diagram of the electric field strength of a fast recovery diode according to another embodiment of the present application;

[0060] FIG47 is a schematic diagram of the structure of a substrate and a drift layer during the fabrication of a fast recovery diode according to some embodiments of the present application;

[0061] FIG48 is a schematic structural diagram of a substrate, a drift layer, and an anode layer according to some embodiments of the present application;

[0062] FIG49 is a schematic structural diagram of a substrate, a drift layer, an anode layer, and an anode metal layer according to some embodiments of the present application;

[0063] Figure 50 is a schematic diagram of the overall structure of a fast recovery diode according to some embodiments of the present application. DETAILED DESCRIPTION

[0064] The following will be combined with the accompanying drawings to clearly and completely describe some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, rather than all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0065] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0066] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0067] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean a fixed connection, a removable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediary. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The embodiments disclosed herein are not necessarily limited to the contents herein.

[0068] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0069] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0070] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0071] In semiconductor devices, a reverse-conducting insulated-gate bipolar transistor (IGBT) refers to an IGBT and a freewheeling diode or fast-recovery diode integrated on a single chip. Generally speaking, the industry typically integrates IGBTs and fast-recovery diodes into the chip's cell region using a lumped or distributed approach, with the two sharing terminals. This creates a highly integrated reverse-conducting IGBT, eliminating the need to connect the two discrete devices, the IGBT and fast-recovery diode, through packaging.

[0072] In related technologies, because the insulated-gate bipolar transistor (IGBT) and the fast-recovery diode (FRD) share the same device cell area, in order to achieve the theoretical performance of the IGBT, the chip design requires increasing the cell area to accommodate the FRD region. Therefore, as the chip area increases, the number of chips that can be produced on a wafer of the same size decreases, resulting in a certain cost compromise.

[0073] In the semiconductor device 100 proposed in the present application, an emitter layer is provided at a position of the collector layer corresponding to the transition region, which not only enables the semiconductor device to be reverse-conducted, but also improves the area utilization of the semiconductor device and prevents the overall area of ​​the semiconductor device from increasing. Thus, while achieving reverse conduction of the semiconductor device, the effective area of ​​the semiconductor device can be increased and the size of the semiconductor device can be reduced.

[0074] The following describes a semiconductor device 100 according to some embodiments of the present application with reference to FIG1-10. The semiconductor device 100 is, for example, a reverse-conducting insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In this application, the first conductivity type is N-type, and the second conductivity type is P-type.

[0075] As shown in Figures 2 and 8, the semiconductor device 100 according to the present application may mainly include: a drift layer 1 of a first conductive type, which is a basic component of the semiconductor device 100 of the present application, and the drift layer 1 of the first conductive type may provide an installation basis for at least some other components of the semiconductor device 100.

[0076] The semiconductor device 100 of the present application may further include a gate pad 2 , which is disposed on the upper surface of the drift layer 1 .

[0077] The semiconductor device 100 of the present application may further include a well region 101 of the second conductivity type. The well region 101 is disposed in the drift layer 1, and its upper surface constitutes at least a portion of the upper surface of the drift layer 1. Specifically, the well region 101 of the second conductivity type is disposed on at least a portion of the upper surface of the drift layer 1. This can serve as a main junction to optimize the terminal electric field distribution, thereby improving the voltage resistance of the semiconductor device 100. At least a portion of the well region 101 can also be disposed on the upper surface of the drift layer 1. The gate pad 2 can also be disposed above the well region 101, such that the well region 101 is located below the gate pad 2.

[0078] The semiconductor device 100 of the present application may further include a field stop layer 3 , which is disposed on the lower surface of the drift layer 1 .

[0079] The semiconductor device 100 of the present application may further include a dielectric layer 9 , which is disposed on the upper surface of the well region 101 to prevent the well region 101 from being in contact and electrically connected to the gate pad 2 , thereby ensuring the reliability of the semiconductor device 100 .

[0080] The semiconductor device 100 of the present application may further include a collector layer 4. The semiconductor device 100 has an insulated gate bipolar transistor region, and the collector layer 4 is located in the insulated gate bipolar transistor region of the semiconductor device 100. By disposing the gate pad 2 on the upper surface of the dielectric layer 9, the field stop layer 3 on the lower surface of the drift layer 1, and the collector layer 4 on the lower surface of the drift layer 1, the basic structure of the semiconductor structure can be formed, ensuring the normal operation of the semiconductor device 100.

[0081] The semiconductor device 100 of the present application may further include an emitter layer 5, which is located within the collector layer 4, such that at least a portion of the collector layer 4 is provided with the emitter layer 5. The emitter layer 5 is located in the fast recovery diode region of the semiconductor device 100, and the emitter layer 5 corresponds to the gate pad 2 above and below. Specifically, the conductivity type of the collector layer 4 is the second conductivity type, the conductivity type of the emitter layer 5 in the collector layer 4 is the first conductivity type, and the emitter layer 5 is partially provided below the collector layer 4 corresponding to the gate pad 2. The emitter layer 5 and the portion of the well region 101 corresponding to the portion below the gate pad 2 can form a PN junction, and the well region 101 corresponding to the portion above the emitter layer 5 can serve as the collector of the fast recovery diode. In this way, a fast recovery diode structure can be formed in the region of the semiconductor device 100 corresponding to the gate pad 2 to achieve reverse conduction of the semiconductor device 100.

[0082] The well region 101 is at least partially disposed on the upper surface of the drift layer 1 and below the gate pad 2 , and may correspond to the emitter layer 5 in the fast recovery diode structure to form a current flow path of the fast recovery diode.

[0083] In related art, the insulated gate bipolar transistor (IGBT) and fast recovery diode (FRD) in a reverse-conducting insulated gate bipolar transistor (IGBT) are integrated into the active region of a semiconductor device. When the semiconductor device is forward-conducting, driven by a gate voltage, the emitter layer of the first conductivity type in the IGBT device injects electrons into the first conductivity type drift region through the channel, while the collector region of the second conductivity type on the back of the semiconductor device injects holes upward, forming a conductive path from top to bottom. During reverse conduction, the integrated FRD region within the semiconductor device begins to operate. The well region of the second conductivity type on the front side acts as the anode of the FRD to inject holes into the drift region, while the emitter layer of the second conductivity type on the back side acts as the cathode to inject electrons into the drift region, thereby integrating the IGBT region and the FRD region within the same semiconductor device. However, the FRD region requires a portion of the active region of the semiconductor device. Assuming the proportion of the effective gate trench within the IGBT region remains unchanged, the saturation current of the IGBT decreases, requiring the area of ​​the active region of the semiconductor device to be supplemented, which increases the overall size of the semiconductor device. In addition, the increase in the area of ​​the active region of the semiconductor device may lead to an increase in the heat generated during operation of the IGBT, thereby reducing the reliability of the IGBT.

[0084] In some embodiments of the present application, the emitter layer 5 structure constituting the fast recovery diode is disposed in the portion of the collector layer 4 of the semiconductor device 100 corresponding to the gate pad 2. This allows the fast recovery diode structure to be disposed in the pad region 12, allowing the emitter layer 5 to be offset from the active region 6 of the semiconductor device 100. This not only enables reverse conduction of the semiconductor device 100, but also reduces the number of structures disposed in the active region 6 of the semiconductor device 100, thereby reducing the area of ​​the active region 6 of the semiconductor device 100, thereby improving the integration of the semiconductor device 100. It should also be noted that a second contact hole 1102 can be provided on the upper surface of the gate pad 2 to optimize heat distribution on the gate metal 15.

[0085] This arrangement allows more semiconductor devices 100 to be produced on wafers of the same size, thereby improving wafer utilization and reducing the production cost of the semiconductor devices 100. Taking a 30A current-spec semiconductor device 100 as an example, by integrating the fast recovery diode below the gate pad 2, approximately 27% of the area can be saved. Taking an 8-inch wafer as an example, the number of semiconductor devices 100 that can be produced per wafer increases from 2,778 to 3,771, significantly improving the production efficiency and wafer utilization of the semiconductor devices 100 and reducing the production cost of the semiconductor devices 100.

[0086] Furthermore, while ensuring that the theoretical performance of the insulated gate bipolar transistor meets requirements, the area of ​​the active region 6 of the semiconductor device 100 can be reduced, thereby reducing the overall area of ​​the semiconductor device 100. This can reduce the heat generated by the insulated gate bipolar transistor during operation, thereby reducing the power consumption of the semiconductor device 100 and improving the reliability of the semiconductor device 100. The emitter layer 5 is disposed below the gate pad 2 of the semiconductor device 100. The emitter layer 5 and the well region 101 below the gate pad 2 can form a PN junction. The well region 101 corresponding to the emitter layer 5 above the emitter layer 5 can serve as the collector of the fast recovery diode, forming a fast recovery diode structure. Except for the portion of the well region 101 above the drift layer 1 corresponding to the portion below the gate pad 2, which can serve as the collector of the fast recovery diode, the remaining portion of the well region 101 serves as the main junction to optimize the terminal electric field distribution. This arrangement not only ensures that the withstand voltage capability of the semiconductor device 100 is not affected, but also integrates the well region 101 into the fast recovery diode region, improving chip integration, reducing the overall chip area, and thus reducing costs.

[0087] Therefore, by setting the emitter layer 5 below the collector layer 4 corresponding to the gate pad 2, not only can the semiconductor device 100 be reverse-conducted, but the integration of the semiconductor device 100 can also be improved. Therefore, while achieving reverse conduction of the semiconductor device 100, the saturation current of the insulated gate bipolar transistor structure can be guaranteed without increasing the area of ​​the active region 6. Compared with reverse-conducting insulated gate bipolar transistor devices of the same specifications, the semiconductor device 100 of the present application has an advantage in area size.

[0088] Furthermore, in other embodiments, the semiconductor device 100 of some embodiments of the present application may further include a transition region that is offset from the active region 6, and the emitter layer 5 may further be disposed opposite the transition region of the semiconductor device 100. This allows the emitter layer 5 to be offset from the active region 6 of the semiconductor device 100. This may also reduce the area of ​​the active region 6 of the semiconductor device 100.

[0089] As shown in Figures 2 and 3 , the width of the well region 101 in the first direction is W1, and the width of the emitter layer 5 in the first direction is W2. W1 and W2 satisfy the relationship: W1>W2. The width of the well region 101 in the first direction is set to be greater than the width of the emitter layer 5 in the first direction. This setting can ensure the reliability of the reverse flow of current in the fast recovery diode, thereby ensuring the reliability of the reverse conduction of the semiconductor device 100. In some embodiments, the width of the well region 101 in the first direction is equal to the width of the emitter layer 5 in the first direction, which can also achieve reverse conduction of the semiconductor device 100. It should also be noted that the width of the emitter layer 5 in the first direction of the fast recovery diode region in the semiconductor device 100 needs to be set according to the specifications of the fast recovery diode in the reverse conducting insulated gate bipolar transistor device.

[0090] In some embodiments, as shown in FIG3 , the cross-section of the emitter layer 5 in the vertical direction is in the shape of a continuous long strip in the first direction. Specifically, the cross-section of the emitter layer 5 in the vertical direction is configured as a continuous long strip on the first square. The width of the well region 101 in the first direction is sufficient to accommodate the placement of the emitter layer 5 of the fast recovery diode structure in the portion of the collector layer 4 corresponding to the gate pad 2. This provides a sufficiently large placement space for the emitter layer 5, so that the fast recovery diode structure meets the actual requirements and design goals of the semiconductor device 100.

[0091] In some embodiments, as shown in FIG4 , the emitter layer 5 includes a plurality of emitter portions 501 in a vertical cross-section. The plurality of emitter portions 501 are spaced apart in the first direction, and the sum of the widths of the plurality of emitter portions 501 in the first direction is W2. Specifically, the emitter layer 5 of the fast recovery diode in the semiconductor device 100 may also be composed of a plurality of emitter portions 501. The width of the well region 101 in the first direction is sufficient to accommodate the emitter layer 5 of the fast recovery diode structure disposed in the portion of the collector layer 4 corresponding to the gate pad 2. This provides a sufficiently large space for the emitter layer 5 to ensure that the fast recovery diode structure meets the actual requirements and design objectives of the semiconductor device 100. It should also be noted that in some embodiments, the sum of the widths of the plurality of emitter portions 501 in the vertical cross-section in the first direction does not exceed the width of the well region 101 in the first direction, to ensure that the plurality of emitter portions 501 correspond to the well region 101 in the vertical direction.

[0092] In some embodiments, the widths of the multiple emitters 501 in the first direction are all the same. This not only ensures that the fast recovery diode structure meets the actual requirements and design goals of the semiconductor device 100, but also simplifies the fabrication process of the fast recovery diode structure, thereby improving the production convenience of the semiconductor device 100. In some embodiments, the widths of the multiple emitters 501 in the first direction are not all the same. This arrangement can improve the convenience of disposing the emitter layer 5, which is of great significance for insulated gate bipolar transistors operating at high frequencies. Specifically, some emitters 501 can have different widths, while some emitters 501 can have the same width.

[0093] In some embodiments, the emitter layer 5 is at least one of a square, a rounded rectangle, a circle, a small ellipse, and a hexagon when viewed from above. Specifically, by setting the emitter layer 5 to at least one of a square, a rounded rectangle, a circle, a small ellipse, and a hexagon when viewed from above, the emitter layer 5 in the fast recovery diode can be configured into different shapes based on the actual needs and design objectives of the semiconductor device 100, thereby being suitable for semiconductor devices 100 of different specifications and improving the reliability of the semiconductor device 100. It should also be noted that the top view is a view perpendicular to the vertical direction in Figure 1.

[0094] In some embodiments, when viewed from above, the emitter layer 5 is formed by a combination of at least two of a plurality of small squares, small circles, small ovals, and small rounded rectangles. Specifically, by setting the top-view shape of the emitter layer 5 to be a combination of at least two of a plurality of small squares, small circles, small ovals, and small rounded rectangles, the emitter layer 5 in the fast recovery diode can be configured to have different shapes and sizes according to the actual needs and design objectives of the semiconductor device 100, thereby being suitable for semiconductor devices 100 of different specifications and facilitating improved reliability of the semiconductor device 100. It should also be noted that the top-view perspective is a perspective perpendicular to the vertical plane in FIG. 1 .

[0095] In some embodiments, when viewed from above, the emitter layer 5 is at least one of a square, a rounded rectangle, and a circle, and the emitter layer 5 is a combination of at least two of a plurality of small squares, small circles, small ellipses, and small rounded rectangles. Specifically, by setting the top view shape of the emitter layer 5 to at least one of a square, a rounded rectangle, and a circle, and a combination of at least two of a plurality of small squares, small circles, small ellipses, and small rounded rectangles, the emitter layer 5 in the fast recovery diode can be set to different shapes and sizes according to the actual needs and design goals of the semiconductor device 100, so as to be suitable for semiconductor devices 100 of different specifications, which is beneficial to improving the reliability of the semiconductor device 100. It should also be noted that the top view is the view perpendicular to the straight-face direction in Figure 1

[0096] As shown in Figures 3 and 4 , the drift layer 1 is provided with a plurality of trench portions 7 spaced apart in a first direction in a portion corresponding to the active region 6 of the semiconductor device 100. The distance between two adjacent trench portions 7 in the first direction is L1. The distance between one of the plurality of trench portions 7 adjacent to the well region 101 in the first direction and the well region 101 is W3, where W3 and L1 satisfy the relationship: W3 ≥ L1. Specifically, the drift layer 1 is provided with a trench portion 7 in a portion corresponding to the active region 6 of the semiconductor device 100. The trench portion 7 is used to form the gate of the semiconductor device 100. There are multiple trench portions 7, and the number of trench portions 7 can be set according to the specifications of the semiconductor device 100. The plurality of trench portions 7 are spaced apart in the first direction to ensure the independence of the plurality of trench portions 7, thereby ensuring the reliability of the semiconductor device 100.

[0097] In some embodiments, the area of ​​the active region 6 of the semiconductor device 100 is only used to set up the insulated gate bipolar transistor structure. This can reduce the area of ​​the active region 6, increase the density of the effective trench, and further increase the current density of the insulated gate bipolar transistor, thereby reducing the conduction voltage drop of the semiconductor device 100, which is beneficial to reducing the switching loss of the semiconductor device 100.

[0098] In some embodiments, the spacing distance between two adjacent groove portions 7 in the first direction does not exceed the distance from the groove portion 7 to the well region 101 in the first direction adjacent to the well region 101. Such a setting can provide a setting space for the transition region 14 in the semiconductor device 100, so that the transition region 14 transitions to the active region 6 and the terminal region 13 of the semiconductor device 100, thereby ensuring the reliability of the semiconductor device 100.

[0099] In some embodiments, as shown in conjunction with FIG. 1 and FIG. 5 , the drift layer 1 is provided with a trench portion 7 , which extends in the second direction. There are multiple trench portions 7 , and the multiple trench portions 7 are spaced apart in the first direction. Specifically, the multiple trench portions 7 provided in the drift layer 1 can extend in the second direction, and the multiple trench portions 7 can be spaced apart in the first direction to accommodate the structural configuration of semiconductor devices 100 of different specifications, thereby ensuring that the fast recovery diode structure meets the actual needs and design objectives of the semiconductor device 100 .

[0100] In some embodiments, as shown in FIG6 and FIG7 , a plurality of trench portions 7 extend in a first direction, and the plurality of trench portions 7 are spaced apart in a second direction. Specifically, the plurality of trench portions 7 provided in the drift layer 1 can extend in the first direction, and the plurality of trench portions 7 can be spaced apart in the second direction to accommodate the structural configuration of semiconductor devices 100 of different specifications, thereby enabling the fast recovery diode structure to meet the actual needs and design objectives of the semiconductor device 100.

[0101] In some embodiments, as shown in conjunction with FIG1 and FIG6 , the gate pad 2 is located on one side of the drift layer 1 in the second direction, and the gate pad 2 is symmetrically arranged about the center line extending in the second direction of the drift layer 1. Specifically, by arranging the gate pad 2 on one side of the drift layer 1 in the second direction and symmetrically arranging the gate pad 2 about the center line extending in the second direction of the drift layer 1, the structural configuration of semiconductor devices 100 of different specifications can be satisfied while ensuring the structural and functional reliability of the semiconductor device 100. This allows the fast recovery diode structure to be freely arranged at the position corresponding to the gate pad 2 in the semiconductor device 100, thereby ensuring that the configuration of the fast recovery diode meets the actual needs and design objectives of the semiconductor device 100.

[0102] In some embodiments, as shown in Figures 5 and 7, the gate pad 2 is located on one side of the drift layer 1 in the second direction, and the gate pad 2 is located at one end of the drift layer 1 in the first direction. Such a configuration can save the area of ​​the semiconductor device 100 while ensuring the structural reliability and functional reliability of the semiconductor device 100. In this way, the structural settings of semiconductor devices 100 of different specifications can be met, and the fast recovery diode structure can be freely set at the position corresponding to the gate pad 2 in the semiconductor device 100, so that the setting of the fast recovery diode can meet the actual needs and design goals of the semiconductor device 100.

[0103] As shown in Figures 2, 8, and 11, an emitter metal 1001 is further provided on the upper surface of the dielectric layer 9. A first contact hole 1101 is provided on the dielectric layer 9. At least a portion of the emitter metal 1001 passes through the first contact hole 1101 and contacts the well region 101. Specifically, the emitter metal 1001 on the upper surface of the dielectric layer 9 can serve as the emitter of the insulated gate bipolar transistor region, forming the basic structure of the insulated gate bipolar transistor region in the semiconductor, ensuring the normal operation of the semiconductor device 100. The first contact hole 1101 is formed on the dielectric layer 9 by etching, and the first contact hole 1101 can be used to electrically connect the emitter metal 1001 and the well region 101. When depositing metal to form the emitter metal 1001, at least a portion of the emitter metal 1001 is penetrated by a first contact hole 1101 for electrical connection to the well region 101, thereby enabling electrical conduction of the fast recovery diode in the semiconductor device 100. At this time, the emitter layer 5 in the fast recovery diode region forms a PN junction with the corresponding portion of the well region 101 below the gate pad 2. This portion of the well region 101 can serve as the collector in the fast recovery diode.

[0104] In some embodiments, the first contact hole 1101 is in the shape of a continuous long strip, which can facilitate the electrical contact between the emitter metal 1001 and the polysilicon field plate 8, and can increase the contact area between the emitter metal 1001 and the polysilicon field plate 8, thereby ensuring the circuit reliability of the semiconductor device 100.

[0105] In some embodiments, as shown in FIG9 , the first contact holes 1101 are multiple rectangular, and the multiple first contact holes 1101 are spaced apart in the first direction. Specifically, the first contact holes 1101 can also be multiple rectangular, and the multiple rectangular first contact holes 1101 are spaced apart in the first direction, so that the emitter metal 1001 is in contact and electrically connected to the polysilicon field plate 8 at multiple spaced locations in the first direction, so as to be suitable for electrically conducting fast recovery diodes of different specifications and sizes, thereby ensuring the reliability of the semiconductor device 100.

[0106] As shown in Figures 2, 8, 9, and 10, the trench portion 7 includes a gate trench portion 701 and a dummy gate trench portion 702, with at least one dummy gate trench portion 702 disposed between two adjacent gate trench portions 701. Specifically, disposing at least one dummy gate trench portion 702 between two adjacent gate trench portions 701 not only ensures the structural reliability of the insulated gate bipolar transistor region in the semiconductor device 100, but also controls the short-circuit performance of the semiconductor device 100, thereby ensuring the reliability of the semiconductor device 100. The first contact hole 1101 is located between two adjacent gate trench portions 701 and is spaced apart from the dummy gate trench portion 702 in the second direction; and / or, the first contact hole 1101 is spaced apart from the gate trench portion 701 in the second direction.

[0107] 10 . In some embodiments, the first contact hole 1101 is located between two adjacent gate trenches 701 and is spaced apart from the dummy gate trench 702 in the second direction. In some embodiments, the first contact hole 1101 is spaced apart from the gate trench 701 in the first direction.

[0108] In some embodiments, at least a portion of the first contact hole 1101 is located between two adjacent gate trenches 701 and is spaced apart from the dummy gate trench 702 in the second direction. At least a portion of the first contact hole 1101 is spaced apart from the gate trench 701 in the first direction. This arrangement allows the first contact holes 1101 to be freely arranged on the semiconductor device 100 to meet the structural configuration of semiconductor devices 100 of different specifications, and allows the fast recovery diode structure to meet the actual needs and design goals of the semiconductor device 100.

[0109] 8 and 9 , the structure of the insulated gate bipolar transistor region in the semiconductor device 100 further includes an emitter region 17 of the first conductivity type.

[0110] The structure of the insulated gate bipolar transistor region in the semiconductor device 100 further includes a base region 18 of the second conductivity type. The base region 18 of the second conductivity type is disposed on one side of the emitter region 17 of the first conductivity type.

[0111] The structure of the insulated gate bipolar transistor region in the semiconductor device 100 further includes a carrier storage layer.

[0112] The structure of the IGBT region in the semiconductor device 100 further includes a collector metal layer 1002 . The collector metal layer 1002 is located at the bottom of the semiconductor device 100 .

[0113] The structure of the insulated gate bipolar transistor region in the semiconductor device 100 further includes a gate.

[0114] The emitter region 17 , the base region 18 , the carrier storage layer and the collector metal layer 1002 cooperate to form an insulated gate bipolar transistor region in the semiconductor device 100 .

[0115] The IGBT region in the semiconductor device 100 may be composed of multiple regions, wherein the structure of the IGBT region in the semiconductor device 100 further includes an active region 6 .

[0116] The structure of the IGBT region in the semiconductor device 100 further includes a transition region 14 . The transition region 14 is located on one side of the active region 6 and is connected to the active region 6 .

[0117] The structure of the IGBT region in the semiconductor device 100 further includes a pad region 12 . The pad region 12 is located on a side of the transition region 14 facing away from the active region 6 .

[0118] The structure of the IGBT region in the semiconductor device 100 further includes a termination region 13 . The termination region 13 is located on a side of the pad region 12 facing away from the transition region 14 .

[0119] The termination region 13 includes a field stop ring 1302. It also includes a field limiting ring 1303, which is located on one side of the field stop ring 1302. The termination region 13 also includes a metal field plate. The termination region 13 also includes structures such as a polysilicon field plate 8, which can be positioned above the field limiting ring 1303. These structures are sequentially arranged in the termination region 13 at a predetermined distance to improve the withstand voltage capability of the insulated gate bipolar transistor and ensure the stability of the semiconductor device 100.

[0120] In some embodiments, the pad region 12 includes a gate metal 15, which is used to connect to external wires and serves as the focal point of a gate runner 16 to control the gate of the insulated gate bipolar transistor device. A dummy gate trench 702 may or may not be provided in the transition region 14, and no first conductivity type emitter region 17 or second conductivity type contact layer is provided in the transition region 14.

[0121] In conjunction with FIG. 12 to FIG. 20 , the following describes a method for manufacturing a semiconductor device 100 according to some embodiments of the present application:

[0122] Providing a semiconductor substrate of the first conductivity type, which is structure 1;

[0123] On the basis of structure 1, after taking certain protective measures, a well region 101 of the second conductivity type is implanted into the terminal region 13 to form structure 2;

[0124] On the basis of structure 2, a field oxide layer 1301 is grown to obtain structure 3;

[0125] On the basis of structure three, the groove portion 7 is etched, and processes such as rounding of the groove portion 7 and growth of a gate oxide layer are completed to obtain structure four;

[0126] On the basis of structure four, polysilicon is grown to obtain structure five;

[0127] On the basis of structure five, the emitter region 17 of the first conductivity type, the carrier storage layer, the contact layer of the second conductivity type and other structures are implanted to obtain structure six;

[0128] On the basis of structure six, a dielectric layer 9 is grown to obtain structure seven;

[0129] On the basis of structure seven, the dielectric layer 9 is etched to obtain structure eight;

[0130] On the basis of structure eight, emitter metal 1001 is deposited to obtain structure nine;

[0131] On the basis of structure nine, a field stop layer 3 and a collector layer 4 of the second conductivity type are formed on the back surface of the semiconductor device 100 to obtain structure ten;

[0132] On the basis of the structure 10, an emitter layer 5 of the first conductivity type is formed in the region of the collector layer 4 corresponding to the gate pad 2 to form the structure 11;

[0133] On the basis of the structure 11, a collector metal layer 1002 is deposited on the back side of the semiconductor device 100 to finally form the structure of an insulated gate bipolar transistor device.

[0134] A reverse-conducting insulated gate bipolar transistor (IGBT) is a device that integrates an IGBT and a freewheeling diode (or an IGBT and a fast recovery diode) on a single chip. Typically, when preparing a reverse-conducting IGBT in the industry, the IGBT and the fast recovery diode are integrated into the active region of the device, with the two devices sharing a common terminal, thereby achieving the purpose of integrating a fast recovery diode onto the IGBT.

[0135] In the related art, since the insulated gate bipolar transistor and the fast recovery diode share the active area of ​​the device, the fast recovery diode in this method occupies part of the active area of ​​the insulated gate bipolar transistor. When designing the device, in order to make the device achieve the target on-state voltage drop, the effective area of ​​the device is the sum of the effective area of ​​the insulated gate bipolar transistor and the effective area of ​​the fast recovery diode. Therefore, the total area of ​​the reverse conducting insulated gate bipolar transistor with the same current specification will be larger than the total area of ​​a single insulated gate bipolar transistor.

[0136] In the semiconductor device 200 proposed in some embodiments of the present application, an emitter layer is set at a position of the collector layer corresponding to the transition zone, which not only enables the semiconductor device to be reverse-conducted, but also improves the area utilization of the semiconductor device and prevents the overall area of ​​the semiconductor device from increasing. Therefore, while achieving reverse conduction of the semiconductor device, the effective area of ​​the semiconductor device can be increased and the size of the semiconductor device can be reduced.

[0137] The following describes a semiconductor device 200 according to some embodiments of the present application with reference to Figures 21-24b. The semiconductor device 200 is, for example, a reverse-conducting insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In this application, the first conductivity type is N-type and the second conductivity type is P-type.

[0138] As shown in FIG. 21 , the semiconductor device 200 according to the present application may primarily include a first conductivity type drift layer 204 located within the semiconductor device 200. The semiconductor device 200 includes an active region 201 and a transition region 202. The active region 201 and the transition region 202 may be two connected regions or two unconnected regions on the semiconductor device 200. The drift layer 204 includes a portion corresponding to the transition region 202.

[0139] The semiconductor device 200 of the present application may further include a well region 205 of the second conductivity type, wherein the well region 205 is arranged in a portion of the drift layer 204 corresponding to the transition region 202 of the semiconductor device 200 , and an upper surface of the well region 205 constitutes a portion of an upper surface of the drift layer 204 .

[0140] The semiconductor device 200 of the present application may further include a field stop layer 206 , which is disposed on a lower surface of the drift layer 204 .

[0141] The semiconductor device 200 of the present application may further include a collector layer 207 of the second conductivity type, and the collector layer 207 is disposed on the lower surface of the field stop layer 206 .

[0142] Specifically, a drift layer 204 of the first conductivity type, a well region 205 of the second conductivity type, a field stop layer 206 and a collector layer 207 of the second conductivity type are arranged in the semiconductor device 200, and the field stop layer 206 is arranged on the lower surface of the drift layer 204, and the collector layer 207 is arranged on the lower surface of the field stop layer 206. In this way, the basic structure of the semiconductor structure can be formed to ensure the normal operation of the semiconductor device 200.

[0143] The semiconductor device 200 of the present application may further include an emitter layer 208. The emitter layer 208 of the first conductivity type is disposed within the collector layer 207. The emitter layer 208 is located in a portion of the collector layer 207 corresponding to the terminal region 203. Specifically, the collector layer 207 has the second conductivity type, the emitter layer 208 in the collector layer 207 has the first conductivity type, and the emitter layer 208 is disposed in a portion of the collector layer 207 corresponding to the transition region 202. This allows the emitter layer 208 of the first conductivity type in the collector layer 207, the drift layer 204 of the first conductivity type, and the well region 205 of the second conductivity type in the transition region 202 to form a reverse conducting structure in the semiconductor device 200, thereby achieving reverse conduction of the semiconductor device 200.

[0144] In the related art, the insulated gate bipolar transistor 215 and the fast recovery diode 214 in the reverse-conducting insulated gate bipolar transistor are integrated into the active region 201 of the semiconductor device 200. When the semiconductor device 200 is forward-conducting, driven by the gate voltage, the first conductivity type emitter layer 208 in the insulated gate bipolar transistor 215 injects electrons into the first conductivity type drift region through the channel 209, and the second conductivity type collector region on the back of the semiconductor device 200 injects holes upward, forming a conductive path from top to bottom. During reverse conduction, the fast recovery diode 214 integrated in the semiconductor device 200 begins to operate. The second conductivity type well region 205 on the front side acts as the anode of the fast recovery diode 214 to inject holes into the drift region, and the second conductivity type emitter layer 208 on the back side acts as the cathode to inject electrons into the drift region, thereby integrating the insulated gate bipolar transistor 215 and the fast recovery diode 214 in the same semiconductor device 200. However, the fast recovery diode 214 occupies a portion of the active region 201 of the semiconductor device 200. To achieve the desired on-state voltage drop of the insulated gate bipolar transistor 215, the area of ​​the active region 201 of the semiconductor device 200 must be increased, which increases the overall size of the semiconductor device 200. Furthermore, the increased area of ​​the active region 201 of the semiconductor device 200 increases the heat generated by the insulated gate bipolar transistor 215 during operation, thereby reducing the reliability of the insulated gate bipolar transistor 215.

[0145] In some embodiments of the present application, the emitter layer 208 structure constituting the fast recovery diode 214 is disposed in the portion of the collector layer 207 in the semiconductor device 200 corresponding to the transition region 202. In this way, the fast recovery diode 214 structure can be disposed in the transition region 202, which not only enables reverse conduction of the semiconductor device 200 but also reduces the number of structures disposed in the active region 201 of the semiconductor device 200. This allows the area of ​​the active region 201 to be used as much as possible for disposing the insulated gate bipolar transistor 215 structure, thereby improving the area utilization of the active region 201 and enhancing the area effectiveness of the semiconductor device 200.

[0146] In addition, while ensuring that the theoretical performance of the insulated gate bipolar transistor 215 meets the requirements, the area of ​​the active region 201 of the semiconductor device 200 can be reduced, so that the heat generated by the insulated gate bipolar transistor 215 during operation is reduced, and the power consumption of the semiconductor device 200 is reduced, thereby reducing the overall area of ​​the semiconductor device 200 and improving the reliability of the semiconductor device 200.

[0147] Therefore, by setting the emitter layer 208 at the position of the collector layer 207 corresponding to the transition zone 202, not only can the semiconductor device 200 be reverse-conducted, but also the area utilization of the semiconductor device 200 can be improved, and the overall area of ​​the semiconductor device 200 can be prevented from increasing. Therefore, while achieving reverse conduction of the semiconductor device 200, the effective area of ​​the semiconductor device 200 can be increased and the size of the semiconductor device 200 can be reduced.

[0148] As shown in FIG21 , the well region 205 and the emitter layer 208 correspond to each other in the vertical direction. Specifically, the well region 205 of the second conductivity type corresponds to the emitter layer 208 of the first conductivity type in the vertical direction. A drift region of the first conductivity type is disposed between the well region 205 and the emitter layer 208. The doping concentrations of the well region 205 and the emitter layer 208 are both greater than the doping concentration of the drift layer 204. Therefore, the structure of the portion of the semiconductor device 200 where the well region 205 is located, from top to bottom, is the P+ well region 205, the N- drift layer 204, and the N+ emitter layer 208. P+ indicates that the impurity concentration in the well region 205 of the second conductivity type is heavily doped, N- indicates that the impurity concentration in the drift layer 204 of the first conductivity type is lightly doped, and N+ indicates that the impurity concentration in the emitter layer 208 of the first conductivity type is heavily doped. With such configuration, the well region 205 , the drift region and the emitter layer 208 can form a PIN junction in the fast recovery diode 214 structure, achieving a higher withstand voltage, thereby facilitating reverse conduction in the semiconductor device 200 .

[0149] In some embodiments, as shown in conjunction with FIG. 21 and FIG. 22 , the emitter layer 208 is circumferentially disposed within the transition region 202. This arrangement can increase the area occupied by the emitter layer 208 within the transition region 202 and adjust the reverse conduction performance of the semiconductor device 200. In some embodiments, the transition region 202 occupies a relatively large and concentrated proportion of the area of ​​the semiconductor device 200, and the area where the emitter layer 208 can be disposed within the transition region 202 is relatively large. This increases the adjustability of the emitter layer 208 within the transition region 202. By adjusting the position and area of ​​the emitter layer 208 within the transition region 202, it is possible to avoid affecting the short-circuit performance of the semiconductor device 200, thereby ensuring the reliability of the semiconductor device 200.

[0150] In some embodiments, as shown in FIG. 22 , the termination region 203 of the semiconductor device 200 is circumferentially disposed outside the active region 201 of the semiconductor device 200, with the termination region 203 spaced apart from the active region 201. The transition region 202 is circumferentially disposed outside the active region 201 and located between the active region 201 and the termination region 203. The emitter layer 208 is circumferentially disposed outside the active region 201. Specifically, considering that the electric field strength in the termination region 203 of the semiconductor device 200 is relatively strong and the voltage per unit length is relatively high, voltage breakdown is more likely to occur there. By providing the termination structure 213 in the termination region 203, the electric field distribution in the termination region 203 can be optimized, thereby improving the withstand voltage capability of the termination region 203. The circumferential arrangement of the termination region 203 outside the active region 201 of the semiconductor device 200 can ensure the withstand voltage reliability of the termination region 203 of the semiconductor device 200.

[0151] In some embodiments, the termination region 203 and the active region 201 are spaced apart, allowing the transition region 202 to be disposed between the termination region 203 and the active region 201. The transition region 202 needs to connect the termination region 203 and the active region 201. Furthermore, for the insulated gate bipolar transistor 215 device, a gate electrical connection region is designed in the transition region 202. Therefore, the width of the transition region 202 is generally relatively wide, which facilitates the placement of the emitter layer 208 of the fast recovery diode 214 in some embodiments of the present application. Furthermore, the well region 205 in the transition region 202 is connected to the main junction, which ensures the voltage resistance of the transition region 202 and thus the reliability of the semiconductor device 200.

[0152] In some embodiments, the transition region 202 is circumferentially disposed outside the active region 201 to ensure the reliability of the transition between the terminal region 203 and the active region 201, thereby ensuring the reliability of the semiconductor device 200. The emitter layer 208 is circumferentially disposed outside the active region 201 to form a fast recovery diode 214 structure within the transition region 202, thereby achieving reverse conduction of the semiconductor device 200. Compared to the active region 201, the transition region 202 provides a larger space for the emitter layer 208. This not only effectively utilizes the space in the active region 201, which is conducive to reducing the size of the semiconductor device 200, but also increases the adjustable space of the fast recovery diode 214 device while ensuring the electrical performance of the semiconductor device 200.

[0153] In some embodiments, as shown in conjunction with FIG22 , the emitter layer 208 is spaced apart from the active region 201. Specifically, in some embodiments of the present application, the insulated gate bipolar transistor 215 structure is disposed in the active region 201. By spacing the emitter layer 208 apart from the active region 201, the fast recovery diode 214 and the insulated gate bipolar transistor 215 can be integrated and spaced apart in the semiconductor device 200. In this way, in the semiconductor device 200, the on-state voltage drop of the fast recovery diode 214 and the on-state voltage drop of the insulated gate bipolar transistor 215 can be guaranteed, thereby ensuring the reliability of the semiconductor device 200.

[0154] In some embodiments, as shown in FIG. 21 , the emitter layer 208 is spaced apart from the termination region 203. Specifically, a termination structure 213 is disposed within the termination region 203. The termination structure 213 can improve the voltage resistance of the termination region 203 in the semiconductor device 200, thereby preventing voltage breakdown in the termination region 203 and improving the voltage resistance of the semiconductor device 200. Spaced apart from the emitter layer 208, the voltage resistance of the termination region 203 can be ensured, thereby ensuring the voltage resistance of the semiconductor device 200.

[0155] In some embodiments, as shown in conjunction with FIG. 21 and FIG. 23 , multiple emitter layers 208 are provided, and the multiple emitter layers 208 are spaced apart in the transition region 202. Specifically, in some embodiments, a single emitter layer 208 having a larger area can be split into multiple emitter layers 208 having smaller areas. The multiple emitter layers 208 can be spaced apart in the transition region 202. The transition region 202 occupies a larger area in the semiconductor device 200, providing greater adjustment space for the emitter layer 208, allowing the multiple emitter layers 208 to be configured according to the specifications of the fast recovery diode 214 device. Furthermore, by splitting a single emitter layer 208 into multiple emitter layers 208 having smaller areas, a single fast recovery diode 214 device integrated in the semiconductor device 200 can be dispersed into multiple fast recovery diodes 214 devices having smaller areas. This prevents current concentration in the fast recovery diodes 214 devices within the semiconductor device 200, which could affect the short-circuit performance of the semiconductor device 200, thereby ensuring the reliability of the semiconductor device 200.

[0156] As shown in Figure 23, the terminal region 203 of the semiconductor device 200 is circumferentially arranged outside the active region 201 of the semiconductor device 200, and the terminal region 203 is spaced apart from the active region 201. The transition region 202 is circumferentially arranged outside the active region 201 and is located between the active region 201 and the terminal region 203. Multiple emitter layers 208 are circumferentially spaced apart in the transition region 202.

[0157] Specifically, considering that the electric field strength in the terminal area 203 of the semiconductor device 200 is relatively strong and the voltage per unit length is relatively large, it is relatively easy for voltage breakdown to occur there. By setting a terminal structure 213 in the terminal area 203, the electric field distribution in the terminal area 203 can be optimized and the voltage resistance of the terminal area 203 can be improved. The terminal area 203 is circumferentially arranged on the outside of the active area 201 of the semiconductor device 200, which can ensure the voltage resistance reliability of the terminal area 203 of the semiconductor device 200.

[0158] In some embodiments, the termination region 203 and the active region 201 are spaced apart, allowing the transition region 202 to be disposed between the termination region 203 and the active region 201. The transition region 202 needs to connect the termination region 203 and the active region 201. Furthermore, for the insulated gate bipolar transistor 215 device, a gate electrical connection region is designed in the transition region 202. Therefore, the width of the transition region 202 is generally relatively wide, which facilitates the placement of the emitter layer 208 of the fast recovery diode 214 in some embodiments of the present application. Furthermore, the well region 205 in the transition region 202 is connected to the main junction, which ensures the voltage resistance of the transition region 202 and thus the reliability of the semiconductor device 200.

[0159] In some embodiments, multiple emitter layers 208 are circumferentially spaced apart in the transition region 202, so that the fast recovery diode 214 structure in the semiconductor device 200 can be dispersed in the transition region 202. This not only meets the specification setting requirements of the fast recovery diode 214 device, but also prevents current concentration on the fast recovery diode 214 structure from affecting the short-circuit performance of the semiconductor device 200, thereby ensuring the reliability of the semiconductor device 200.

[0160] In some embodiments, as shown in conjunction with FIG23 , the emitter layer 208 is spaced apart from the active region 201. Specifically, in some embodiments of the present application, the insulated gate bipolar transistor 215 structure is disposed in the active region 201. By spacing the emitter layer 208 apart from the active region 201, the fast recovery diode 214 and the insulated gate bipolar transistor 215 can be integrated and spaced apart in the semiconductor device 200. In this way, in the semiconductor device 200, the on-state voltage drop of the fast recovery diode 214 and the on-state voltage drop of the insulated gate bipolar transistor 215 can be guaranteed, thereby ensuring the reliability of the semiconductor device 200.

[0161] In some embodiments, as shown in FIG. 23 , the emitter layer 208 is spaced apart from the termination region 203. Specifically, a termination structure 213 is provided within the termination region 203. The termination structure 213 can improve the voltage resistance of the termination region 203 in the semiconductor device 200, thereby preventing voltage breakdown in the termination region 203 and improving the voltage resistance of the semiconductor device 200. Spaced apart from the emitter layer 208, the voltage resistance of the termination region 203 can be ensured, thereby ensuring the voltage resistance of the semiconductor device 200.

[0162] In some embodiments, the doping concentration of the emitter layer 208 is greater than the doping concentration of the drift layer 204. Specifically, in some embodiments, electrons need to be injected into the portion of the collector layer 207 corresponding to the well region 205 to form the emitter layer 208. The electron concentration of the emitter layer 208 must be greater than the doping concentration of the drift layer 204. This ensures that the emitter layer 208 has sufficient electrons for current injection, allowing the emitter layer 208 to output a sufficiently large current, thereby ensuring normal operation of the semiconductor device 200.

[0163] In some embodiments, as shown in conjunction with FIG. 21 and FIG. 24 a , transition region 202 is connected to active region 201. A metal electrode 210 is located above transition region 202, and metal electrode 210 is connected to emitter metal 211 disposed above the front surface of active region 201, forming the basic structure of a semiconductor structure and ensuring the normal operation of semiconductor device 200. Emitter layer 208 is disposed below well region 205, forming a fast recovery diode 214 and ensuring the normal electrical performance of semiconductor device 200 without affecting the withstand voltage and reliability of semiconductor device 200.

[0164] In some embodiments, the transition region 202 includes a gate bus 212 region, where the metal is not connected to the emitter metal 211 of the active region 201. However, the gate bus 212 occupies a relatively small area of ​​the transition region 202, and due to the inherent characteristics of the semiconductor device 200, the carrier path does not completely correspond to the position of the metal electrode 210 in the semiconductor device 200. Therefore, even if the emitter layer 208 on the back side of the semiconductor device 200 partially aligns with the gate bus 212, reverse conduction can still be achieved in the semiconductor device 200. Simulation experiments have confirmed the feasibility of achieving reverse conduction in the semiconductor device 200 when the emitter layer 208 on the back side of the semiconductor device 200 partially aligns with the gate bus 212. The figure below shows the simulation results of the on-state voltage drop of the fast recovery diode 214 in the semiconductor device 200 when the emitter layer 208 on the back side of the semiconductor device 200 partially aligns with the gate bus 212.

[0165] RC-IGBT (reverse conducting-Insulated Gate Bipolar Transistor) integrates IGBT (Insulated Gate Bipolar Transistor) and FRD (Fast Recovery Diode) into the same chip, making it have both forward and reverse conduction characteristics. It has many advantages such as small size, high power density, low cost and high reliability.

[0166] In related technologies, IGBTs and FRDs are often integrated into the device's cell area, with the two devices sharing terminals to achieve integration. However, since the IGBT and FRD share the device's cell area, this approach suffers from the disadvantage of sacrificing a portion of the IGBT's cell area. During device design, to achieve the theoretical performance of the IGBT, the device's cell area must be increased. This results in an increase in the overall area of ​​the RC-IGBT, reduced heat dissipation performance, and increased costs.

[0167] In the semiconductor device 300 proposed in some embodiments of the present application, by making the first emitter layer correspond to the dummy gate trench group in the upper and lower directions, the dummy gate area can be fully utilized, and there is no need to set up a second semiconductor device type area separately. Therefore, under the premise of ensuring that the semiconductor device has both forward conduction and reverse conduction characteristics and the short-circuit capability of the semiconductor device, the dummy gate area can also be used as the second semiconductor device type area, thereby reducing the area of ​​the semiconductor device, improving the working performance of the semiconductor device, and reducing the production cost of the semiconductor device.

[0168] The following describes a semiconductor device 300 according to some embodiments of the present application with reference to Figures 25-31. The semiconductor device 300 may be an RC-IGBT, wherein the first semiconductor device type region 3011 may be an IGBT region, and the second semiconductor device type region 3012 may be an FRD region. In the following description, N and P represent the conductivity type of the semiconductor. In this application, the first conductivity type is assumed to be N-type, and the second conductivity type is assumed to be P-type.

[0169] 25-27 , the semiconductor device 300 according to the present application may mainly include: a drift layer 310 of a first conductive type, the drift layer 310 being the basic component of the semiconductor device 300 of the present application, and the drift layer 310 may provide an installation basis for at least some other components of the semiconductor device 300 .

[0170] The semiconductor device 300 of the present application may further include a second conductivity type well layer 315 , which is located on an upper surface of the drift layer 310 , such that the second conductivity type well layer 315 is located above the drift layer 310 .

[0171] The semiconductor device 300 of the present application may further include a first emitter layer 313 of the first conductivity type, where the first emitter layer 313 of the first conductivity type is located in the well layer 315 .

[0172] The semiconductor device 300 of the present application may further include a dielectric layer 317 , which is located above the first emitter layer 313 .

[0173] The semiconductor device 300 of the present application may further include an emitter metal layer 318 . The emitter metal layer 318 is located above the dielectric layer 317 .

[0174] The semiconductor device 300 of the present application may further include a field stop layer 311 of the first conductivity type, and the field stop layer 311 is disposed on the lower surface of the drift layer 310 .

[0175] The semiconductor device of the present application may further include a collector layer 312 of the second conductivity type, and the collector layer 312 is disposed on the lower surface of the field stop layer 311 .

[0176] The semiconductor device of the present application may further include a collector metal layer 314 . The collector metal layer 314 is located at the bottom of the semiconductor device 300 , ie, below the second conductivity type collector layer 312 and the first conductivity type first emitter layer 313 .

[0177] Among them, the dielectric layer 317 can protect the well layer 315 and reduce the risk of damage to the semiconductor device 300. By opening a contact hole 3171 on the dielectric layer 317, the contact hole 3171 is located above the well layer 315, and the contact hole 3171 is located between two adjacent groove portions 320, so that the contact hole 3171 extends in the second direction, and the second emitter layer 316 is at least partially located below the contact hole 3171, so that the emitter metal layer 318 can contact the second emitter layer 316 through the contact hole 3171.

[0178] In some embodiments, the semiconductor device 300 includes an active region 301 . The active region 301 of the semiconductor device 300 may be used to dispose some components of the semiconductor device 300 .

[0179] The semiconductor device 300 further includes a termination region 302. The termination region 320 is disposed outside the active region 301. A first emitter layer 313 is disposed within the collector layer 312. The region corresponding to the collector layer 312 in the vertical direction is the first semiconductor device type region 3011, and the region corresponding to the first emitter layer 313 in the vertical direction is the second semiconductor device type region 3012. In other words, the active region 301 of the semiconductor device 300 may include the first semiconductor device type region 3011. The active region 301 of the semiconductor device 300 may also include the second semiconductor device type region 3012. The emitter metal layer 318 can not only serve as the emitter lead-in terminal of the first semiconductor device type region 3011, but also serve as the anode lead-in terminal of the second semiconductor device type region 3012. The collector metal layer 314 can not only serve as the collector lead-in terminal of the first semiconductor device type region 3011, but also serve as the cathode lead-in terminal of the second semiconductor device type region 3012. In this way, the first semiconductor device type region 3011 can realize forward conduction of the semiconductor device 300, and the second semiconductor device type region 3012 can realize reverse conduction of the semiconductor device 300, so that the semiconductor device 300 has both forward conduction and reverse conduction characteristics.

[0180] As shown in Figures 25 and 26, the semiconductor device 300 may further include a groove portion 320, which extends downward from the upper surface of the drift layer 310. The groove portion 320 is extended in the first direction and is multiple. The multiple groove portions 320 are spaced apart in the second direction and form a gate trench group 321 and a dummy gate trench group 322. The gate trench group 321 and the dummy gate trench group 322 are alternately arranged in the second direction.

[0181] Specifically, the gate trench group 321 includes at least one gate trench portion 3211, and the dummy gate trench group 322 includes at least one dummy gate trench portion 3221. Both the gate trench portion 3211 and the dummy gate trench portion 3221 are provided with an oxide insulating layer 323 and deposited with polysilicon 324. A gate can be formed in the gate trench portion 3211, and second emitter layers 316 are provided on both sides of the gate trench portion 3211 in the second direction. The gate trench portion 3211 has a conductive channel and current flow capability, ensuring normal operation of the first semiconductor device type region 3011 and even the semiconductor device 300. However, the dummy gate trench portion 3221 does not have the second emitter layer 316 on both sides of the second direction. The dummy gate trench portion 3221 does not have a conductive channel and current flow capability. The dummy gate trench portion 3221 can be connected to the emitter, reducing Miller capacitance and current density, thereby improving the short-circuit capability of the semiconductor device 300.

[0182] In addition, by alternating the gate trench group 321 and the dummy gate trench group 322 in the second direction, the uniformity of the circuit distribution of the semiconductor device 300 can be improved, and the thermal distribution and anti-interference ability of the circuit can be improved. The specific number of dummy gate trench portions 3221 in the dummy gate trench group 322 and the specific number of gate trench portions 3211 in the gate trench group 321 can be set according to the specific short-circuit requirements of the semiconductor device 300, and are not specifically limited here.

[0183] In some embodiments, the first emitter layer 313 is vertically aligned with the dummy gate trench group 322. Specifically, the region vertically aligned with the dummy gate trench group 322 is a dummy gate region 3014. Compared to the related art in which the second semiconductor device type region 3012 and the dummy gate region 3014 are separately provided, by vertically aligning the first emitter layer 313 with the dummy gate trench group 322, the area of ​​the dummy gate region 3014 can be fully utilized, eliminating the need to separately provide the second semiconductor device type region 3012. Thus, while ensuring that the semiconductor device 300 has both forward and reverse conduction characteristics and short-circuit capability, the dummy gate region 3014 can also be used as the second semiconductor device type region 3012. This can reduce the area of ​​the semiconductor device 300, improve the operating performance of the semiconductor device 300, and reduce the production cost of the semiconductor device 300.

[0184] Therefore, by making the first emitter layer 313 correspond to the dummy gate trench group 322 in the upper and lower directions, the dummy gate region 3014 can be fully utilized without having to separately set up the second semiconductor device type region 3012, so that the dummy gate region 3014 can also be used as the second semiconductor device type region 3012, thereby reducing the area of ​​the semiconductor device 300, improving the working performance of the semiconductor device 300, and reducing the production cost of the semiconductor device 300.

[0185] 25-27 , there are multiple first emitter layers 313 and multiple dummy gate trench groups 322, and the multiple first emitter layers 313 are disposed corresponding to the multiple dummy gate trench groups 322. Specifically, by disposing the first emitter layers 313 corresponding to the multiple dummy gate trench groups 322, not only can the area of ​​the dummy gate region 3014 be fully utilized, thereby reducing the area of ​​the semiconductor device 300 in some embodiments, but also the multiple first emitter layers 313 can be more evenly distributed within the semiconductor device 300, thereby improving the operating performance of the semiconductor device 300.

[0186] In some embodiments, the first emitter layer 313 is extended in the first direction. Specifically, by extending the first emitter layer 313 in the first direction, the first emitter layer 313 can be easily arranged in the semiconductor device 300 while ensuring the current specifications of the second semiconductor device type region 3012. This can simplify the workflow of the second semiconductor device type region 3012 and even the semiconductor device 300, thereby improving production efficiency.

[0187] In some embodiments, as shown in conjunction with Figures 25-27 , the first emitter layer 313 includes a plurality of sub-emitter portions 3131, which are spaced apart in the first direction. Specifically, by having the first emitter layer 313 include a plurality of sub-emitter portions 3131, and by having the plurality of sub-emitter portions 3131 spaced apart in the first direction, the distribution of the plurality of sub-emitter portions 3131 in the semiconductor device 300 can be made more uniform and reasonable, thereby optimizing the operating performance of the second semiconductor device type region 3012 and, therefore, the semiconductor device 300.

[0188] It should be noted that the length and spacing of the multiple sub-emitter portions 3131 in the first direction are related to the current specification of the second semiconductor device type region 3012. The greater the rated current, the larger the total area of ​​the first emitter layer 313. That is, the longer the sub-emitter portion 3131, the smaller the spacing between two adjacent sub-emitter portions 3131. When the spacing between two adjacent sub-emitter portions 3131 is zero, the first emitter layer 313 extends in the first direction. In actual manufacturing, the first emitter layer 313 can be selectively extended in the first direction, or the first emitter layer 313 can be configured to include multiple sub-emitter portions 3131 spaced apart in the first direction, depending on the actual application scenario.

[0189] As shown in Figures 25-27 , the projection of the dummy gate trench group 322 on the lower surface of the drift layer 310 overlaps the projection of the first emitter layer 313 on the lower surface of the drift layer 310. Specifically, the region to which the gate trench group 321 corresponds in the vertical direction is the gate region 3013. To ensure normal operation of the first semiconductor device type region 3011, the gate trench group 321 should correspond in the vertical direction to the collector layer 312, not the first emitter layer 313. That is, the collector layer 312 should be located in the gate region 3013, and the first emitter layer 313 should be located in the dummy gate region 3014. By making the projection of the dummy gate trench group 322 on the lower surface of the drift layer 310 cover the projection of the first emitter layer 313 on the lower surface of the drift layer 310, it can be ensured that the first emitter layer 313 only corresponds to the dummy gate trench group 322 in the upper and lower directions, thereby preventing the first emitter layer 313 from entering the gate area 3013 and avoiding affecting the first semiconductor device type area 3011, thereby ensuring the working performance of the first semiconductor device type area 3011 and ensuring the normal operation of the semiconductor device 300.

[0190] 26 , the length of the first emitter layer 313 in the first direction is smaller than the length of the dummy gate trench group 322 in the first direction. Specifically, by setting the length of the first emitter layer 313 in the first direction to be smaller than the length of the dummy gate trench group 322 in the first direction, the first emitter layer 313 is prevented from protruding beyond both ends of the dummy gate trench group 322 in the first direction, which would cause the first emitter layer 313 to enter the gate region 3013 in the first direction and affect the first semiconductor device type region 3011. This ensures the operating performance of the first semiconductor device type region 3011 and the normal operation of the semiconductor device 300.

[0191] In some embodiments, as shown in FIG26 , the width of the first emitter layer 313 in the second direction is equal to the width of the dummy gate trench group 322 in the second direction. Specifically, the width of the first emitter layer 313 in the second direction can be equal to the width of the dummy gate trench group 322 in the second direction. This fully utilizes the area of ​​the dummy gate trench group 322 in the second direction, thereby effectively utilizing the area of ​​the semiconductor device 300, improving the performance of the semiconductor device 300, and reducing the cost.

[0192] In some embodiments, the width of the first emitter layer 313 in the second direction is smaller than the width of the dummy gate trench group 322 in the second direction. Specifically, the width of the first emitter layer 313 in the second direction can be set to be smaller than the width of the dummy gate trench group 322 in the second direction. This can further prevent the first emitter layer 313 from protruding from the end of the dummy gate trench group 322 in the second direction in the second direction, and prevent the first emitter layer 313 from entering the gate region 3013 in the second direction and affecting the first semiconductor device type region 3011. This can ensure the operating performance of the first semiconductor device type region 3011 and the normal operation of the semiconductor device 300.

[0193] In some embodiments, the dummy gate trench group 322 may include a dummy gate trench portion 3221, the width of the first emitter layer 313 in the second direction is less than the width of the dummy gate trench portion 3221 in the second direction, or the width of the first emitter layer 313 in the second direction is equal to the width of the dummy gate trench portion 3221 in the second direction.

[0194] Specifically, when the dummy gate trench group 322 includes only one dummy gate trench portion 3221, the dummy gate trench portion 3221 and the gate trench group 321 are spaced apart from each other, and the width of the dummy gate trench group 322 in the second direction is the width of a gate trench portion 3211 in the second direction. At this time, the width of the first emitter layer 313 in the second direction can be set to be smaller than the width of a dummy gate trench portion 3221 in the second direction, or the width of the first emitter layer 313 in the second direction can be set to be equal to the width of a dummy gate trench portion 3221 in the second direction. In this way, each first emitter layer 313 can fall in the dummy gate region 3014 corresponding to each dummy gate trench portion 3221, thereby preventing the first emitter layer 313 from entering the gate region 3013 in the second direction, thereby ensuring the respective performance of the second semiconductor device type region 3012 and the first semiconductor device type region 3011.

[0195] In some embodiments, in combination with Figure 26, the dummy gate trench group 322 may include at least two dummy gate trench portions 3221 spaced apart in the second direction, the width of the first emitter layer 313 in the second direction is D1, the sum of the widths of the at least two dummy gate trench portions 3221 in the second direction is D2, and the sum of the spacing distances of the at least two dummy gate trench portions 3221 in the second direction is D3, and D1, D2 and D3 satisfy the relationship: D1≤D2+D3.

[0196] Specifically, when the dummy gate trench group 322 includes at least two dummy gate trench portions 3221 spaced apart in the second direction, at least two dummy gate trench portions 3221 are spaced apart from the gate trench group 321, and the width of the dummy gate trench group 322 in the second direction can be understood as the sum of the widths of the at least two dummy gate trench portions 3221 in the second direction plus the sum of the spacing distances of the at least two dummy gate trench portions 3221 in the second direction. At this time, the width of the first emitter layer 313 in the second direction can be set to be no greater than the sum of the sum of the widths of the at least two dummy gate trench portions 3221 in the second direction and the sum of the spacing distances of the at least two dummy gate trench portions 3221 in the second direction. In this way, each first emitter layer 313 can fall within each dummy gate region 3014, avoiding the first emitter layer 313 from entering the gate region 3013 in the second direction, and ensuring the respective performance of the second semiconductor device type region 3012 and the first semiconductor device type region 3011, thereby ensuring the normal operation of the semiconductor device 300.

[0197] The following describes an example of a method for manufacturing a semiconductor device 300 with reference to FIG. 27 to FIG. 31 . The semiconductor device 300 is an RC-IGBT.

[0198] As shown in Figure 28, an N-substrate material is provided as a drift layer 310. Structure 1 is formed.

[0199] As shown in FIG29 , based on Structure 1, a groove portion 320 is etched, and an oxidized insulating layer 323 and polysilicon 324 are sequentially grown in the groove portion 320 , and then the polysilicon 324 is etched, thereby forming Structure 2.

[0200] As shown in FIG30 , based on structure 2, a P well layer 315 is formed by implantation, an N+ second emitter layer 316 is implanted into the well layer 315 and annealed, and then a dielectric layer 317 is deposited on top to form structure 3.

[0201] As shown in FIG31 , based on Structure 3, contact holes 3171 are etched, and metal sputtering is performed to prepare an emitter metal layer 318. Thus, Structure 4 is formed.

[0202] As shown in FIG31 , based on structure 4, the N+ field stop layer 311 is implanted, the P+ collector layer 312 is implanted, the FRD region N+ first emitter layer 313 is implanted, laser annealing is performed, and metal sputtering is performed to prepare the collector metal layer 314. Finally, the semiconductor device 300 is formed.

[0203] It should be noted that other structures and operations of the semiconductor device 300 according to some embodiments of the present application are well known to those skilled in the art and will not be described in detail here.

[0204] RC-IGBT (reverse conducting-Insulated Gate Bipolar Transistor) integrates IGBT (Insulated Gate Bipolar Transistor) and FRD (Fast Recovery Diode) into the same chip, making it have both forward and reverse conduction characteristics. It has many advantages such as small size, high power density, low cost and high reliability.

[0205] In related technologies, the FRD region and the IGBT region often have the same trench and contact hole design. On the one hand, the trench occupies a certain area of ​​the FRD region, which reduces the effective PN junction area and increases the forward voltage drop. On the other hand, the FRD region uses the same process flow as the IGBT region, and its barrier voltage drop is large, which makes its forward voltage drop relatively large.

[0206] In the semiconductor device 400 proposed in some embodiments of the present application, the ring layer is made to correspond to the junction of the collector layer and the first emitter layer, a plurality of groove portions are provided in the ring layer, the well layer is provided on both sides of the ring layer and at least partially corresponds to the collector layer and the first emitter layer, and a plurality of groove portions are provided in the portion of the well layer corresponding to the collector layer. In this way, while ensuring the voltage resistance of the semiconductor device, the conduction voltage drop in the second semiconductor device type region is improved, thereby improving the working performance of the semiconductor device.

[0207] The following describes a semiconductor device 400 according to some embodiments of the present application with reference to FIG32-FIG41. The semiconductor device 400 may employ a method for manufacturing the semiconductor device 400. The semiconductor device 400 may be an RC-IGBT, the first semiconductor device type region 4011 may be an IGBT region, and the second semiconductor device type region 4012 may be an FRD region. In the following description, N and P represent the conductivity type of the semiconductor. In this application, the first conductivity type is set to N-type and the second conductivity type is set to P-type for the purpose of illustration.

[0208] As shown in Figures 32 and 33, the semiconductor device 400 according to the present application may mainly include: a drift layer 410 of the first conductive type, the drift layer 410 is the basic component of the semiconductor device 400 of the present application, and the drift layer 410 can provide an installation basis for at least part of other components of the semiconductor device 400.

[0209] The semiconductor device 400 of the present application may further include a second conductive type ring layer 431, which is arranged in the drift layer 410. The upper surface of the ring layer 431 constitutes at least part of the upper surface of the drift layer 410, so that at least part of the ring layer 431 is also located on the upper surface of the drift layer 410.

[0210] The semiconductor device 400 of the present application may further include a well layer 430 of the second conductivity type, which is also located in the drift layer 410. The upper surface of the well layer 430 constitutes at least a portion of the upper surface of the drift layer 410, so that at least a portion of the well layer 430 is also located on the upper surface of the drift layer 410. A field stop layer 420 of the first conductivity type, a collector layer 421 of the second conductivity type, a first emitter layer 422 of the first conductivity type, a ring layer 431 of the second conductivity type, and the well layer 430 of the second conductivity type are provided.

[0211] The semiconductor device 400 of the present application may further include a first emitter layer 422 of the first conductivity type, where the first emitter layer 422 of the first conductivity type is located in the well layer 430 .

[0212] The semiconductor device 400 of the present application may further include a dielectric layer 433 , and the dielectric layer 433 is located above the first emitter layer 422 .

[0213] The semiconductor device 400 of the present application may further include an emitter metal layer 435 . The emitter metal layer 435 is located above the dielectric layer 433 .

[0214] The semiconductor device 400 of the present application may further include a first conductivity type field stop layer 420 located on a lower surface of the first conductivity type drift layer 410 , and a first conductivity type first emitter layer 422 located on a lower surface of the field stop layer 420 .

[0215] The semiconductor device 400 of the present application may further include a collector layer 421 of the second conductivity type. The collector layer 421 of the second conductivity type is located on the lower surface of the field stop layer 420 .

[0216] The semiconductor device 400 of the present application may further include a collector metal layer 423 . The collector metal layer 423 is located at the bottom of the semiconductor device 400 , specifically below the first emitter layer 422 of the first conductivity type and the collector layer 421 of the second conductivity type.

[0217] The semiconductor device 400 is provided with an active region 401 . The active region 401 of the semiconductor device 400 may be used to dispose some components of the semiconductor device 400 .

[0218] The semiconductor device 400 is further provided with a termination region 402, which surrounds the outside of the active region 401. The collector layer 421 is circumferentially arranged outside the first emitter layer 422. The region corresponding to the collector layer 421 in the vertical direction is the first semiconductor device type region 4011, and the region corresponding to the first emitter layer 422 in the vertical direction is the second semiconductor device type region 4012. In other words, the active region 401 of the semiconductor device 400 may include the first semiconductor device type region 4011. The active area 401 of the semiconductor device 400 can also include a second semiconductor device type region 4012. The emitter metal layer 435 can not only serve as the emitter lead-in terminal of the first semiconductor device type region 4011, but also serve as the anode lead-in terminal of the second semiconductor device type region 4012. The collector metal layer 423 can not only serve as the collector lead-in terminal of the first semiconductor device type region 4011, but also serve as the cathode lead-in terminal of the second semiconductor device type region 4012. In this way, the first semiconductor device type region 4011 can realize forward conduction of the semiconductor device 400, and the second semiconductor device type region 4012 can realize reverse conduction of the semiconductor device 400, so that the semiconductor device 400 has both forward conduction and reverse conduction characteristics.

[0219] As shown in Figure 33, the ring layer 431 corresponds to the junction of the collector layer 421 and the first emitter layer 422, and a plurality of groove portions 440 are provided in the ring layer 431. The well layer 430 is provided on both sides of the ring layer 431 and at least partially corresponds to the collector layer 421 and the first emitter layer 422. A plurality of groove portions 440 are provided in the portion of the well layer 430 corresponding to the collector layer 421.

[0220] Specifically, the ring layer 431 corresponds to the junction of the collector layer 421 and the first emitter layer 422, that is, the ring layer 431 is provided at the junction of the first semiconductor device type region 4011 and the second semiconductor device type region 4012, and the well layer 430 is provided on both sides of the ring layer 431, and the well layer 430 at least partially corresponds to the collector layer 421 and the first emitter layer 422, that is, the first semiconductor device type region 4011 and the second semiconductor device type region 4012 are both provided with the well layer 430.

[0221] By setting multiple groove portions 440 in the ring layer 431 and setting multiple groove portions 440 in the portion of the well layer 430 corresponding to the collector layer 421, that is, the groove portion 440 is set in the first semiconductor device type region 4011, and the groove portion 440 is not set in the second semiconductor device type region 4012. In this way, on the one hand, the oxide insulation layer 441 and the polysilicon 442 can be deposited in sequence in the groove portion 440, and a gate is formed at the groove portion 440 to ensure the normal operation of the first semiconductor device type region 4011. On the other hand, the groove portion 440 at the second semiconductor device type region 4012 can be eliminated, so that the second semiconductor device type region 4012 is only a planar PN junction, thereby effectively increasing the effective area of ​​the PN junction and reducing the forward conduction voltage drop of the second semiconductor device type region 4012. In this way, the working performance of the semiconductor device 400 can be improved.

[0222] In some embodiments, since the groove portion 440 at the second semiconductor device type region 4012 is canceled, the width of the second semiconductor type dopant required to be injected into the first semiconductor device type region 4011 is much larger than the width of the second semiconductor type dopant required to be injected into the second semiconductor device type region 4012. If the same implantation dose and annealing conditions are used, the junction depth and doping concentration at the junction of the first semiconductor device type region 4011 and the second semiconductor device type region 4012 will be smaller than the junction depth and doping concentration of the first semiconductor device type region 4011, resulting in problems with the withstand voltage of the semiconductor device 400. By respectively setting the ring layer 431 and the well layer 430, the junction depth and doping concentration at the junction of the first semiconductor device type region 4011 and the second semiconductor device type region 4012 can be increased, ensuring that the junction depth and doping concentration of the first semiconductor device type region 4011 and the second semiconductor device type region 4012 are the same, ensuring that the withstand voltage of the first semiconductor device type region 4011 and the second semiconductor device type region 4012 are the same, and ensuring the withstand voltage capability of the semiconductor device 400.

[0223] Therefore, by making the ring layer 431 correspond to the junction of the collector layer 421 and the first emitter layer 422, a plurality of groove portions 440 are provided in the ring layer 431, and the well layer 430 is provided on both sides of the ring layer 431 and at least partially corresponds to the collector layer 421 and the first emitter layer 422. A plurality of groove portions 440 are provided in the portion of the well layer 430 corresponding to the collector layer 421. In this way, while ensuring the voltage resistance of the semiconductor device 400, the on-state voltage drop of the second semiconductor device type region 4012 can be improved, thereby improving the working performance of the semiconductor device 400.

[0224] 33 , the depth of the well layer 430 in the vertical direction is less than the depth of the ring layer 431. Specifically, by setting the depth of the well layer 430 in the vertical direction to be less than the depth of the ring layer 431 in the vertical direction, in some embodiments, the junction depth and doping concentration at the junction of the first semiconductor device type region 4011 and the second semiconductor device type region 4012 can be ensured to be the same as the junction depth and doping concentration of the first semiconductor device type region 4011, thereby ensuring the voltage withstand capability of the second semiconductor device type region 4012 and, therefore, the semiconductor device 400.

[0225] 33 , the vertical depth of the groove portion 440 is greater than the vertical depth of the well layer 430 , and the vertical depth of the groove portion 440 is less than the vertical depth of the ring layer 431 .

[0226] Specifically, by setting the depth of the groove portion 440 in the up and down directions to be greater than the depth of the well layer 430 in the up and down directions, the groove portion 440 in the first semiconductor device type region 4011 located in the well layer 430 can penetrate the well layer 430 and reach the drift layer 410, thereby ensuring the normal operation of the first semiconductor device 400.

[0227] In some embodiments, the depth of the groove portion 440 in the up-down direction is set to be smaller than the depth of the ring layer 431 in the up-down direction, so that the ring layer 431 can surround the groove portion 440 located at the junction of the first semiconductor device type region 4011 and the second semiconductor device type region 4012, thereby ensuring that the junction depth and doping concentration at the junction of the first semiconductor device type region 4011 and the second semiconductor device type region 4012 are the same as the junction depth and doping concentration of the first semiconductor device type region 4011, ensuring that the withstand voltage of the first semiconductor device type region 4011 and the second semiconductor device type region 4012 are the same, and ensuring the working performance of the semiconductor device 400.

[0228] As shown in FIG33 , the cross section of the ring layer 431 in the vertical direction is arc-shaped, and the cross section of the well layer 430 in the vertical direction is rectangular.

[0229] Specifically, by making the cross-section of the well layer 430 in the upper and lower directions rectangular, the lower surface of the well layer 430 is parallel to the upper surface of the drift layer 410, so that the well layer 430 of the second semiconductor device type region 4012 can be evenly distributed and have the same depth as the first semiconductor device type region 4011, thereby ensuring the working performance of the second semiconductor device type region 4012 and ensuring that the junction depth and doping concentration in the middle of the first direction of the first semiconductor device type region 4011 and the middle of the first direction of the second semiconductor device type region 4012 are the same.

[0230] In some embodiments, by making the cross-section of the ring layer 431 in the upper and lower directions arc-shaped, the lower surface of the ring layer 431 is arc-shaped, so that the ring layer 431 can surround the groove portion 440 located at the junction of the first semiconductor device type region 4011 and the second semiconductor device type region 4012, thereby ensuring that the junction depth and doping concentration at the junction of the first semiconductor device type region 4011 and the second semiconductor device type region 4012 are the same as the junction depth and doping concentration of the first semiconductor device type region 4011.

[0231] In this way, the withstand voltages of the first semiconductor device type region 4011 and the second semiconductor device type region 4012 can be made the same, thereby ensuring the withstand voltage capability of the semiconductor device 400 and the operating performance of the semiconductor device 400 .

[0232] As shown in Figure 33, a second emitter layer 432 is provided on both sides of the groove portion 440, and a dielectric layer 433 is provided on the upper surfaces of the ring layer 431 and the well layer 430. The dielectric layer 433 has a first contact hole 4331 between the two adjacent groove portions 440, and a second contact hole 4332 is provided in the portion of the dielectric layer 433 corresponding to the first emitter layer 422. An emitter metal layer 435 is provided on the upper surface of the dielectric layer 433, at least a portion of the emitter metal layer 435 passes through the first contact hole 4331 and is electrically connected to the second emitter layer 432, at least a portion of the emitter metal layer 435 passes through the second contact hole 4332 and is electrically connected to the portion of the well layer 430 located in the middle of the ring layer 431, and multiple groove portions 440 are spaced apart in the first direction, and the length of the second contact hole 4332 in the first direction is greater than the length of the first contact hole 4331 in the first direction.

[0233] Specifically, by disposing the dielectric layer 433 on the upper surfaces of the ring layer 431 and the well layer 430 , the dielectric layer 433 can protect the well layer 430 , thereby reducing the risk of damage to the semiconductor device 400 .

[0234] By arranging a second emitter layer 432 on both sides of the groove portion 440, a first contact hole 4331 is opened in the dielectric layer 433 between two adjacent groove portions 440, so that at least a portion of the emitter metal layer 435 can pass through the first contact hole 4331 and be electrically connected to the second emitter layer 432, thereby ensuring the normal operation of the first semiconductor device type region 4011.

[0235] In some embodiments, a second contact hole 4332 is opened in a portion of the dielectric layer 433 corresponding to the first emitter layer 422 so that the length of the second contact hole 4332 in the first direction is greater than the length of the first contact hole 4331 in the first direction. The second contact hole 4332 directly corresponds to the second semiconductor device type region 4012. This is different from setting multiple first contact holes 4331 in the first semiconductor device type region 4011, where only one second contact hole 4332 is set in the second semiconductor device type region 4012. At least a portion of the emitter metal layer 435 passes through the second contact hole 4332 and is electrically connected to the portion of the well layer 430 located in the middle of the ring layer 431, that is, the emitter metal layer 435 is in contact with the well layer 430 of the second semiconductor device type region 4012, thereby ensuring the normal operation of the second semiconductor device type region 4012.

[0236] As shown in FIG33 , a barrier metal layer 434 is provided on the surface of the dielectric layer 433. The barrier metal layer 434 is located between the dielectric layer 433 and the emitter metal layer 435. A third contact hole 4341 is formed in the portion of the barrier metal layer 434 corresponding to the second contact hole 4332. At least a portion of the emitter metal layer 435 is penetrated by the third contact hole 4341 and the second contact hole 4332. The barrier metal layer 434 is electrically connected to the portion of the well layer 430 located in the middle of the ring layer 431.

[0237] Specifically, considering that the width of the first contact hole 4331 on the dielectric layer 433 is relatively small, in order to facilitate the setting of the emitter metal layer 435 and ensure the contact between the emitter metal layer 435 and the second emitter layer 432, a barrier metal layer 434 can be set on the surface of the dielectric layer 433, and then the emitter metal layer 435 is deposited. In this way, the barrier metal layer 434 is located between the dielectric layer 433 and the emitter metal layer 435, thereby ensuring the normal extraction of current and ensuring the normal operation of the first semiconductor device type region 4011 and even the semiconductor device 400.

[0238] In some embodiments, taking into account the large width of the second contact hole 4332, under the premise of not affecting the electrical connection between the emitter metal layer 435 and the portion of the well layer 430 located in the middle of the ring layer 431, a third contact hole 4341 is opened in the portion of the barrier metal layer 434 corresponding to the second contact hole 4332. In this way, the barrier metal layer 434 in the second semiconductor device type region 4012 can be eliminated, so that at least a portion of the emitter metal layer 435 can pass through the third contact hole 4341 and the second contact hole 4332, and be directly electrically connected to the portion of the well layer 430 located in the middle of the ring layer 431, thereby reducing the contact resistance, reducing the forward conduction voltage drop of the second semiconductor device type region 4012, and improving the working performance of the second semiconductor device type region 4012 and even the semiconductor device 400.

[0239] As shown in Figure 34, the manufacturing method of the semiconductor device 400 according to the present application may mainly include the following steps: preparing a drift layer 410; injecting a second conductive type ring layer 431 into the drift layer 410, and annealing the ring layer 431; etching a groove portion 440 in the drift layer 410, and setting an oxidized insulating layer 441 on the upper surface of the drift layer 410; injecting a second conductive type well layer 430 into the drift layer 410, and annealing the well layer 430, wherein the well layer 430 is located on both sides of the ring layer 431.

[0240] Specifically, when manufacturing the semiconductor device 400, a drift layer 410 of the first conductivity type is provided. A ring layer 431 of the second conductivity type can be first implanted into the drift layer 410, and the ring layer 431 is annealed. The ring layer 431 is located at the junction of the first semiconductor device type region 4011 and the second semiconductor device type region 4012. Then, a groove portion 440 is etched only in the drift layer 410 corresponding to the first semiconductor device type region 4011, and an oxidized insulating layer 441 is provided on the upper surface of the drift layer 410. Then, a well layer 430 of the second conductivity type is implanted into the drift layer 410, and the well layer 430 is annealed so that the upper surfaces of the well layer 430 and the ring layer 431 together constitute the upper surface of the drift layer 410.

[0241] In this way, the trench portion 440 in the second semiconductor device type region 4012 can be eliminated, thereby increasing the effective area of ​​the PN junction of the second semiconductor device type region 4012 and reducing the forward conduction voltage drop of the second semiconductor device type region 4012 .

[0242] In addition, since the injection dose and annealing time of the ring layer 431 are greater than the injection dose and annealing time of the well layer 430, by first injecting the ring layer 431 and then injecting the well layer 430, the junction depth and doping concentration of the first semiconductor device type region 4011 and the second semiconductor device type region 4012 can be guaranteed to be the same, and the withstand voltage of the first semiconductor device type region 4011 and the second semiconductor device type region 4012 can be guaranteed to be the same, thereby ensuring the withstand voltage capability of the semiconductor device 400.

[0243] As shown in Figure 34, after the step of injecting a second conductive type well layer 430 into the drift layer 410 and annealing the well layer 430, wherein the well layer 430 is located on both sides of the ring layer 431, the manufacturing method of the semiconductor device 400 may further include: injecting a second emitter layer 432 into the drift layer 410; arranging a dielectric layer 433 on the upper surface of the oxidized insulating layer 441; and opening a first contact hole 4331 in the dielectric layer 433 between two adjacent groove portions 440, and opening a second contact hole 4332 in the dielectric layer 433 corresponding to the well layer 430 located in the middle of the ring layer 431, wherein the length of the second contact hole 4332 in the first direction is greater than the length of the first contact hole 4331 in the first direction.

[0244] Specifically, after a well layer 430 of the second conductivity type is implanted into the drift layer 410 and the well layer 430 is annealed, a second emitter layer 432 can be implanted into both sides of the groove portion 440 in the drift layer 410, and then a dielectric layer 433 is provided on the surface of the oxidized insulating layer 441. The dielectric layer 433 covers the well layer 430, the ring layer 431, the second emitter layer 432 and the oxidized insulating layer 441. Then, a first contact hole 4331 and a second contact hole 4332 are correspondingly opened in the dielectric layer 433, wherein the first contact hole 4331 corresponds to the area between two adjacent groove portions 440, that is, the second emitter layer 432 can be exposed through the first contact hole 4331, and the second contact hole 4332 can correspond to the portion of the well layer 430 located in the middle of the ring layer 431, that is, the well layer 430 corresponding to the second semiconductor device type region 4012 can be exposed through the second contact hole 4332.

[0245] It can be understood that the width of the well layer 430 corresponding to the second semiconductor device type region 4012 is much larger than the width between two adjacent groove portions 440 , so the length of the second contact hole 4332 in the first direction is much larger than the length of the first contact hole 4331 in the first direction.

[0246] In some embodiments, as shown in FIG34 , a first contact hole 4331 is opened in the dielectric layer 433 between two adjacent groove portions 440, and a second contact hole 4332 is opened in the dielectric layer 433 corresponding to the portion of the well layer 430 located in the middle of the ring layer 431, wherein the length of the second contact hole 4332 in the first direction is greater than the length of the first contact hole 4331 in the first direction. Then, the manufacturing method of the semiconductor device 400 may further include: providing a barrier metal layer 434 on the upper surface of the dielectric layer 433, on the sidewalls of the dielectric layer 433 corresponding to the first contact hole 4331 and the second contact hole 4332, and on the upper surfaces of the ring layer 431 and the well layer 430; and etching portions of the barrier metal layer 434 corresponding to the second contact hole 4332 and the opposite side walls of the groove portions 440 on both sides of the second contact hole 4332 to etch a third contact hole 4341.

[0247] Specifically, after a first contact hole 4331 is opened between two adjacent groove portions 440 corresponding to the dielectric layer 433 and a second contact hole 4332 is opened in the middle portion of the ring layer 431 corresponding to the well layer 430 of the dielectric layer 433, a barrier metal layer 434 can be set on the upper surface of the dielectric layer 433, the side walls of the first contact hole 4331 and the second contact hole 4332 corresponding to the dielectric layer 433, and the upper surfaces of the ring layer 431 and the well layer 430, and the second contact hole 4332 and the opposite side walls of the groove portions 440 on both sides of the second contact hole 4332 are etched, so that a third contact hole 4341 can be etched.

[0248] On the one hand, the barrier metal layer 434 of the first semiconductor device type region 4011 still exists, so that the barrier metal layer 434 can be in contact with the second emitter layer 432, which facilitates the electrical connection between the later emitter metal layer 435 and the second emitter layer 432, thereby ensuring the normal operation of the first semiconductor device type region 4011. On the other hand, the barrier metal layer 434 of the second semiconductor device type region 4012 can be cancelled, which facilitates the direct electrical connection between the later emitter metal layer 435 and the well layer 430 of the second semiconductor device type region 4012, thereby reducing the conduction voltage drop of the second semiconductor device type region 4012.

[0249] 34 , after etching the barrier metal layer 434 corresponding to the second contact hole 4332 and the opposite side walls of the trench portion 440 on both sides of the second contact hole 4332 to form the third contact hole 4341, the method for manufacturing the semiconductor device 400 may further include: providing an emitter metal layer 435 on the upper surface of the barrier metal layer 434, wherein at least a portion of the emitter metal layer 435 passes through the first contact hole 4331 and is electrically connected to the second emitter layer 432; At least a portion of the emitter metal layer 435 passes through the third contact hole 4341 and the second contact hole 4332 and is electrically connected to the portion of the well layer 430 located in the middle of the ring layer 431; a field stop layer 420 is provided on the lower surface of the drift layer 410; a collector layer 421 of a second conductive type is provided on the lower surface of the field stop layer 420; a first emitter layer 422 is provided at a position of the collector layer 421 corresponding to the middle of the ring layer 431; and a collector metal layer 423 is provided on the lower surface of the collector layer 421.

[0250] Specifically, after etching the barrier metal layer 434 corresponding to the second contact hole 4332 and the opposite side walls of the groove portion 440 on both sides of the second contact hole 4332 to etch the third contact hole 4341, an emitter metal layer 435 can be firstly provided on the upper surface of the barrier metal layer 434, so that at least a portion of the emitter metal layer 435 passes through the first contact hole 4331 and contacts the second emitter layer 432, and at least a portion of the emitter metal layer 435 can pass through the third contact hole 4341 and the third contact hole 4341. The second contact hole 4332 is connected to the well layer 430, and then a field stop layer 420 is set on the lower surface of the drift layer 410, and a collector layer 421 of a second conductive type can be set on the lower surface of the field stop layer 420, and a first emitter layer 422 is set at a position in the middle of the collector layer 421 corresponding to the ring layer 431. Finally, a collector metal layer 423 is set on the lower surfaces of the collector layer 421 and the first emitter layer 422, and the collector metal layer 423 is electrically connected to the collector layer 421 and the first emitter layer 422.

[0251] In this way, a semiconductor device 400 can be manufactured, including a first semiconductor device type region 4011 and a second semiconductor device type region 4012 , and having a lower on-state voltage drop and better voltage resistance.

[0252] The following describes an example of a method for manufacturing a semiconductor device 400 with reference to FIG. 33 and FIG. 35 to FIG. 41 . The semiconductor device 400 is an RC-IGBT.

[0253] 35 , an N-substrate material is provided as a drift layer 410. Structure 1 is formed.

[0254] As shown in FIG36 , based on structure 1, a P-type ring layer 431 is implanted and annealed to form structure 2.

[0255] As shown in FIG37 , based on Structure 2, a groove portion 440 is etched, and an oxidized insulating layer 441 and polysilicon 442 are sequentially grown in the groove portion 440 , and then the polysilicon 442 is etched, thereby forming Structure 3.

[0256] As shown in FIG38 , based on Structure 3, a P-type well layer 430 is implanted and annealed to form Structure 4.

[0257] As shown in FIG39 , based on Structure 4, an N+ second emitter layer 432 is implanted and annealed, and then a dielectric layer 433 is deposited thereon to form Structure 5.

[0258] As shown in FIG40 , based on Structure 5 , a first contact hole 4331 and a second contact hole 4332 are etched on the dielectric layer 433 , and then a Ti or TiN barrier metal layer 434 is deposited on the dielectric layer 433 , thereby forming Structure 6 .

[0259] As shown in FIG41 , based on Structure 6, a third contact hole 4341 is etched on the barrier metal layer 434 to ensure that the FRD region is free of the barrier metal layer 434. Thus, Structure 7 is formed.

[0260] As shown in FIG33 , based on structure 7, metal sputtering is performed to form an emitter metal layer 435. Then, the N+ field stop layer 420 is implanted, the P+ collector layer 421 is implanted, the FRD region N+ first emitter layer 422 is implanted, laser annealing is performed, and metal sputtering is performed to form a collector metal layer 423. Finally, a semiconductor device 400 is formed.

[0261] It should be noted that other structures and operations of the semiconductor device 400 according to some embodiments of the present application are well known to those skilled in the art and will not be described in detail here.

[0262] The fast recovery diode in the related art usually includes a substrate, a drift layer and an anode layer, and the doping concentration of the drift layer will greatly affect the voltage resistance and reverse recovery softness of the fast recovery diode. However, due to the unreasonable structural setting of the fast recovery diode in the related art, the doping concentration of the drift layer of some fast recovery diodes is too low. During the reverse recovery process, when the voltage across the two ends of the fast recovery diode reaches the bus voltage, the width of the depletion region widens too large, resulting in a small number of residual carriers on the side of the drift layer close to the substrate, and current interruption is prone to occur. The doping concentration of the drift layer of other fast recovery diodes is too high, the width of the depletion region widens too small, the residual carriers in the drift layer are too many, the reverse current shows soft recovery, but the electric field gradient becomes larger during reverse voltage resistance, and the electric field peak becomes larger, which leads to a significant decrease in the reverse voltage resistance of the fast recovery diode.

[0263] Some embodiments of the present application propose that in a fast recovery diode 500, the doping concentration of the second concentration-doped layer is not greater than the doping concentration of the first concentration-doped layer and is less than the doping concentration of the third concentration-doped layer. That is, the concentration of the third concentration-doped layer can be larger, that is, the doping concentration of the side of the drift layer close to the anode layer can be larger. In this way, the carrier concentration of the side of the drift layer close to the anode layer during forward conduction can be reduced, thereby effectively reducing the peak current of reverse recovery.

[0264] As shown in Figures 42 to 50, a fast recovery diode 500 according to some embodiments of the present application includes a substrate 5100 of a first conductivity type, which is a basic component of the fast recovery diode 500 of the present application and can provide a mounting base for at least some other components of the semiconductor device 500. A drift layer 5200 of a first conductivity type and an anode layer 5300 of a second conductivity type are also included.

[0265] The fast recovery diode 500 of the present application further includes a drift layer 5200. The drift layer 5200 includes a first-concentration doped layer 5210, which is disposed on a substrate 5100. The drift layer 5200 further includes a second-concentration doped layer 5220, which is disposed on a side of the first-concentration doped layer 5210 away from the substrate. The drift layer 5200 further includes a third-concentration doped layer 5230, which is disposed on a side of the second-concentration doped layer 5220 away from the substrate. The doping concentration of the second-concentration doped layer 5220 is no greater than the doping concentration of the first-concentration doped layer 5210 and less than the doping concentration of the third-concentration doped layer 5230. The doping concentration of the first-concentration doped layer 5210 gradually decreases as it moves away from the substrate 5100.

[0266] The fast recovery diode 500 of the present application further includes an anode layer 5300 . The anode layer 5300 is disposed on a side of the third concentration-doped layer 5230 facing away from the substrate 5100 .

[0267] The substrate 5100 may be formed by arsenic doping, the drift layer 5200 may be composed of a phosphorus doped silicon epitaxial layer, and the anode layer 5300 may be formed by boron ion implantation.

[0268] According to some embodiments of the fast recovery diode 500 of the present application, the drift layer 5200 is set as a first concentration doping layer 5210, a second concentration doping layer 5220 and a third concentration doping layer 5230, and the first concentration doping layer 5210 is set on the substrate 5100, the second concentration doping layer 5220 is set on the side of the first concentration doping layer 5210 away from the substrate, and the third concentration doping layer 5230 is set on the side of the second concentration doping layer 5220 away from the substrate. The doping concentration of the second concentration doping layer 5220 is not greater than the doping concentration of the first concentration doping layer 5210 and is less than the doping concentration of the third concentration doping layer 5230. That is, the concentration of the third concentration doping layer 5230 can be larger, that is, the doping concentration of the side of the drift layer 5200 close to the anode layer 5300 can be larger, so that the carrier concentration on the side of the drift layer 5200 close to the anode layer 5300 during forward conduction can be reduced, thereby effectively reducing the peak current of reverse recovery.

[0269] Moreover, the doping concentration of the second concentration-doped layer 5220 can be relatively low, that is, the doping concentration of the second concentration-doped layer 5220 can be less than the doping concentration of the first concentration-doped layer 5210 and the doping concentration of the third concentration-doped layer 5230, or, the doping concentration of the second concentration-doped layer 5220 can be equal to the doping concentration of the first concentration-doped layer 5210 and less than the doping concentration of the third concentration-doped layer 5230. This can reduce the electric field gradient of the second concentration-doped layer 5220, which is beneficial to improving the reverse withstand voltage performance of the fast recovery diode 500.

[0270] In addition, the doping concentration of the first-concentration-doped layer 5210 gradually decreases in the direction away from the substrate 5100, and the anode layer 5300 is provided on the side of the third-concentration-doped layer 5230 facing away from the substrate 5100. In other words, the side of the first-concentration-doped layer 5210 away from the anode layer 5300 is the point where the doping concentration of the first-concentration-doped layer 5210 is the highest, and the side of the first-concentration-doped layer 5210 close to the anode layer 5300 is the point where the doping concentration of the first-concentration-doped layer 5210 is the lowest. The doping concentration of the side of the first-concentration-doped layer 5210 away from the anode layer 5300 can be higher, and the doping concentration of the side of the first-concentration-doped layer 5210 close to the anode layer 5300 can be lower. In this way, the electric field gradient can gradually increase in the direction away from the anode layer 5300. This makes the width of the depletion region 5600 of the fast recovery diode 500 narrower during the reverse recovery process under the same reverse withstand voltage, avoiding current interruption, and the first concentration-doped layer 5210 can inject sufficient carriers so that the residual carriers on the side of the first concentration-doped layer 5210 away from the anode layer 5300 can be more, which is beneficial to increasing the reverse recovery softness factor of the fast recovery diode 500, that is, improving the reverse recovery softness, which is beneficial to improving the stability and reliability of the circuit, and at the same time can ensure that the reverse withstand voltage of the fast recovery diode 500 is high, avoiding circuit damage.

[0271] Thus, the fast recovery diode 500 according to some embodiments of the present application has the advantages of good voltage resistance, small reverse recovery peak current and high circuit stability.

[0272] In some embodiments, as shown in FIG43 and FIG44 , the concentration of the first concentration-doped layer 5210 decreases linearly away from the substrate 5100. Specifically, the first concentration-doped layer may include multiple sub-concentration-doped layers 5211, and the concentrations of the multiple sub-concentration-doped layers 5211 gradually decrease away from the substrate 5100. That is, the first concentration-doped layer 5210 is composed of multiple layers of decreasing doping concentration epitaxially. The first concentration-doped layer 5210 is then diffused through a thermal process to obtain a distribution in which the doping concentration decreases approximately linearly. This allows the electric field gradient to increase linearly away from the anode layer 5300, thereby narrowing the width of the depletion region 5600 during the reverse recovery process of the fast recovery diode 500 at the same reverse withstand voltage, thereby preventing current interruption. The first concentration-doped layer 5210 can have more residual carriers on the side away from the anode layer 5300, which helps increase the reverse recovery softness factor of the fast recovery diode 500 and improve the stability and reliability of the circuit.

[0273] In some embodiments, as shown in Figures 42-50, the thicknesses of the first concentration-doped layer 5210, the second concentration-doped layer 5220, and the third concentration-doped layer 5230 decrease in sequence. That is, the minimum thickness of the first concentration-doped layer 5210 is not less than the maximum thickness of the second concentration-doped layer 5220, and the minimum thickness of the second concentration-doped layer 5220 is not less than the maximum thickness of the first concentration-doped layer 5210. In this way, the thickness of the third concentration-doped layer 5230 can be relatively thin, thereby ensuring a high reverse withstand voltage of the fast recovery diode 500. At the same time, the thickness of the first concentration-doped layer 5210 can be relatively thick to reduce the forward conduction voltage drop and allow more carriers to be injected into the first concentration-doped layer 5210 to ensure soft recovery of the fast recovery diode 500.

[0274] In some embodiments, the thickness of the first concentration-doped layer 5210 is 30um to 35um. For example, the thickness of the first concentration-doped layer 5210 can be 30um, 31um, 32um, 33um, 34um or 35um. This can, on the one hand, prevent the thickness of the first concentration-doped layer 5210 from being too small, so that enough carriers can be injected into the first concentration-doped layer 5210 to ensure the soft recovery of the fast recovery diode 500. On the other hand, it can prevent the thickness of the first concentration-doped layer 5210 from being too large, thereby preventing the forward conduction voltage drop of the fast recovery diode 500 from increasing.

[0275] In addition, the thickness of the second concentration-doped layer 5220 is 20um to 25um. For example, the thickness of the second concentration-doped layer 5220 can be 20um, 21um, 22um, 23um, 24um or 25um. On the one hand, this can prevent the thickness of the second concentration-doped layer 5220 from being too small, so that the fast recovery diode 500 has better voltage resistance performance. On the other hand, it can prevent the thickness of the second concentration-doped layer 5220 from being too large, thereby preventing the forward conduction voltage drop of the fast recovery diode 500 from increasing.

[0276] In addition, the thickness of the third concentration-doped layer 5230 is 8um to 12um. For example, the thickness of the third concentration-doped layer 5230 can be 8um, 9um, 10um, 11um or 12um. This can, on the one hand, prevent the thickness of the third concentration-doped layer 5230 from being too small, thereby effectively reducing the peak current of reverse recovery. On the other hand, it can prevent the thickness of the third concentration-doped layer 5230 from being too large, thereby preventing the reverse withstand voltage of the fast recovery diode 500 from being reduced.

[0277] In some embodiments, the thickness of the drift layer 5200 is 60um to 80um, wherein the thickness of the drift layer 5200 is the sum of the thickness of the first concentration-doped layer 5210, the thickness of the second concentration-doped layer 5220 and the thickness of the third concentration-doped layer 5230, that is, the thickness of the drift layer 5200, that is, the sum of the thickness of the first concentration-doped layer 5210, the thickness of the second concentration-doped layer 5220 and the thickness of the third concentration-doped layer 5230 is 60um to 80um.

[0278] For example, the thickness of the drift layer 5200 can be 60um, 62um, 64um, 66um, 68um, 70um, 72um, 74um, 76um, 78um or 80um. This can prevent the thickness of the drift layer 5200 from being too small, thereby ensuring that the fast recovery diode 500 has better voltage resistance performance, and can also prevent the thickness of the drift layer 5200 from being too large, thereby preventing the forward conduction voltage drop of the fast recovery diode 500 from increasing significantly.

[0279] In addition, the junction depth of the anode layer 5300 is 3 um to 5 um, that is, the junction depth of the anode layer 5300 can be 3 um, 4 um or 5 um, which can ensure that the overall thickness of the fast recovery diode 500 is moderate.

[0280] In some embodiments, as shown in FIG43 , the doping concentration of the second-concentration-doped layer 5220 is a constant value, wherein the doping concentration of the second-concentration-doped layer 5220 is required to be no greater than the minimum doping concentration of the first-concentration-doped layer 5210, and the doping concentration of the second-concentration-doped layer 5220 is less than the minimum doping concentration of the third-concentration-doped layer 5230. This can reduce the electric field gradient of the second-concentration-doped layer 5220, thereby improving the reverse withstand voltage performance of the fast recovery diode 500, thereby achieving a compromise between the reverse recovery peak current and the withstand voltage performance of the fast recovery diode 500.

[0281] In some embodiments, as shown in FIG44 , the doping concentration of the second-concentration-doped layer 5220 gradually increases in a direction away from the substrate 5100. Specifically, the doping concentration on the side of the second-concentration-doped layer 5220 away from the substrate 5100 is greater than the minimum doping concentration of the first-concentration-doped layer 5210, and the doping concentration on the side of the second-concentration-doped layer 5220 away from the substrate 5100 is less than the minimum doping concentration of the third-concentration-doped layer 5230. This can reduce the electric field gradient of the second-concentration-doped layer 5220, thereby improving the reverse withstand voltage performance of the fast recovery diode 500 and achieving a compromise between the reverse recovery peak current and the withstand voltage performance of the fast recovery diode 500.

[0282] In some embodiments, as shown in FIG43 , the doping concentration of the third concentration-doped layer 5230 is a constant, wherein the doping concentration of the third concentration-doped layer 5230 needs to be greater than the maximum concentration of the second concentration-doped layer 5220. This can reduce the carrier concentration on the side of the drift layer 5200 close to the anode layer 5300 during forward conduction, thereby effectively reducing the peak current of reverse recovery.

[0283] In some embodiments, as shown in FIG44 , the doping concentration of the third concentration-doped layer 5230 gradually increases in a direction away from the substrate 5100, wherein the doping concentration of the third concentration-doped layer 5230 on the side close to the substrate 5100 needs to be greater than the maximum concentration of the second concentration-doped layer 5220. This can reduce the carrier concentration on the side of the drift layer 5200 close to the anode layer 5300 during forward conduction, thereby effectively reducing the peak current of reverse recovery.

[0284] In some embodiments, as shown in FIG43 , the doping concentration of the side of the first concentration doped layer 5210 close to the substrate 5100 is greater than the doping concentration of the third concentration doped layer 5230. In this way, the doping concentration of the side of the first concentration doped layer 5210 close to the substrate 5100 can be larger, which can make the width of the depletion region 5600 of the fast recovery diode 500 narrower under the same reverse withstand voltage during the reverse recovery process, thereby preventing the depletion region 5600 from expanding toward the side close to the substrate 5100 during the reverse recovery process, ensuring that the cathode stores sufficient carriers and avoiding current interruption. In addition, the doping concentration of the side of the first concentration doped layer 5210 away from the substrate 5100 is equal to the doping concentration of the side of the second concentration doped layer 5220 close to the substrate 5100. This can avoid the first concentration doped layer 5210 from The doping concentration is too high, so that sufficient carriers can be injected into the first concentration doped layer 5210, so that the residual carriers on the side of the first concentration doped layer 5210 close to the substrate 5100 can be more, which is beneficial to increase the reverse recovery softness factor of the fast recovery diode 500, that is, improve the reverse recovery softness.

[0285] In some embodiments, the doping concentration of the side of the first concentration-doped layer 5210 close to the substrate 5100 is 8×1014 cm-3 to 10×1014 cm-3. On the one hand, this can prevent the doping concentration of the first concentration-doped layer 5210 from being too low, so that the width of the depletion region 5600 of the fast recovery diode 500 in the reverse recovery process under the same reverse withstand voltage is narrower, thereby avoiding current interruption. On the other hand, it can prevent the doping concentration of the first concentration-doped layer 5210 from being too high, so that enough carriers can be injected into the first concentration-doped layer 5210, so that there can be more residual carriers on the side of the first concentration-doped layer 5210 close to the substrate 5100, which is beneficial to increase the reverse recovery softness factor of the fast recovery diode 5001, that is, improve the reverse recovery softness.

[0286] In addition, the doping concentration of the second concentration-doped layer 5220 is 1×1014 cm-3 to 1.5×1014 cm-3. On the one hand, this can prevent the doping concentration of the second concentration-doped layer 5220 from being too low, so that the voltage resistance performance of the fast recovery diode 500 is better. On the other hand, it can prevent the doping concentration of the second concentration-doped layer 5220 from being too high, thereby preventing the forward conduction voltage drop of the fast recovery diode 500 from increasing.

[0287] In addition, the doping concentration of the third concentration-doped layer 5230 is 5×1014 cm-3 to 6×1014 cm-3. This can, on the one hand, prevent the doping concentration of the third concentration-doped layer 5230 from being too low, thereby effectively reducing the peak current of reverse recovery. On the other hand, it can prevent the doping concentration of the third concentration-doped layer 5230 from being too high, thereby preventing the reverse withstand voltage of the fast recovery diode 500 from being reduced.

[0288] In some embodiments, as shown in FIG48 , the fast recovery diode 500 further includes an anode metal layer 5400, which is disposed on a side of the anode layer 5300 facing away from the drift layer 5200. The fast recovery diode 500 further includes a cathode metal layer 5500, which is disposed on a side of the substrate 5100 facing away from the drift layer 5200. That is, the third concentration-doped layer 5230, the second concentration-doped layer 5220, and the first concentration-doped layer 5210 are sequentially arranged from the anode metal layer 5400 toward the cathode metal layer 5500, and the doping concentration of the first concentration-doped layer 5210 gradually increases from the anode metal layer 5400 toward the cathode metal layer 5500.

[0289] The following describes the manufacturing process of the fast recovery diode 500 according to some embodiments of the present application with reference to Figures 42 to 50:

[0290] First, as shown in FIG47 , a first concentration doped layer 5210 , a second concentration doped layer 5220 , and a third concentration doped layer 5230 are sequentially grown epitaxially on a substrate 5100 ;

[0291] Then, as shown in FIG48 , Pwell ions are implanted into the side of the third concentration doped layer 5230 facing away from the substrate 5100 to form a P-type region, which is also the anode layer 5300 in some embodiments of the present application.

[0292] Next, as shown in FIG49 , an anode metal is deposited on the side of the anode layer 5300 facing away from the substrate 5100 to form an anode metal layer 5400 ;

[0293] Finally, as shown in FIG. 50 , the substrate 5100 is thinned, and a cathode metal is deposited on a side of the substrate 5100 facing away from the anode metal layer 5400 to form a cathode metal layer 5500 .

[0294] Other structures and operations of the fast recovery diode 500 according to some embodiments of the present application are known to those skilled in the art and will not be described in detail here.

[0295] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A semiconductor device comprising: a drift layer of a first conductivity type; a well region of a second conductivity type, the well region being disposed in the drift layer, and an upper surface of the well region constituting at least a portion of an upper surface of the drift layer; A field stop layer, the field stop layer being arranged on a lower surface of the drift layer; A collector layer of the second conductivity type is arranged on the lower surface of the field stop layer, an emitter layer of the first conductivity type is arranged in the collector layer, the semiconductor device has an active area, and the emitter layer and the active area are staggered. 2 . The semiconductor device according to claim 1 , comprising a transition region, wherein the well region is provided at a portion of the drift layer corresponding to the transition region of the semiconductor device, and the emitter layer is located at a portion of the collector layer corresponding to the transition region. 3 . The semiconductor device according to claim 2 , wherein the well region and the emitter layer correspond to each other in a vertical direction. The semiconductor device according to claim 3 , wherein the emitter layer is circumferentially disposed in the transition region.

5. According to the semiconductor device according to claim 4, the terminal region of the semiconductor device is circumferentially arranged on the outside of the active region of the semiconductor device, the terminal region is spaced apart from the active region, the transition region is circumferentially arranged on the outside of the active region and is located between the active region and the terminal region, and the emitter layer is circumferentially arranged on the outside of the active region. The semiconductor device according to claim 5 , wherein the emitter layer is spaced apart from the active region. The semiconductor device according to claim 5 , wherein the emitter layer is spaced apart from the termination region. 8 . The semiconductor device according to claim 3 , wherein the emitter layer is multiple and the multiple emitter layers are arranged at intervals in the transition region.

9. According to the semiconductor device of claim 8, the terminal region of the semiconductor device is circumferentially arranged outside the active region of the semiconductor device, the terminal region and the active region are spaced apart, the transition region is circumferentially arranged outside the active region and is located between the active region and the terminal region, and the plurality of emitter layers are circumferentially spaced apart in the transition region. 10 . The semiconductor device according to claim 9 , wherein the emitter layer is spaced apart from the active region, and the emitter layer is spaced apart from the termination region. 11 . The semiconductor device according to claim 1 , wherein a doping concentration of the emitter layer is greater than a doping concentration of the drift layer. 12 . The semiconductor device according to claim 1 , further comprising a gate pad and a dielectric layer, wherein the dielectric layer is disposed on an upper surface of the well region, the gate pad is disposed on an upper surface of the dielectric layer, and the emitter layer is opposite to the gate pad. 13 . The semiconductor device according to claim 12 , wherein the width of the well region in the first direction is W1 , the width of the emitter layer in the first direction is W2 , and W1 and W2 satisfy the relationship: W1>W2 . 14 . The semiconductor device according to claim 13 , wherein a cross section of the emitter layer in a vertical direction is in a strip shape continuous in the first direction.

15. According to the semiconductor device according to claim 13, the cross-section of the emitter layer in the up and down directions includes a plurality of emitter portions, the plurality of emitter portions are spaced apart in the first direction, the sum of the widths of the plurality of emitter portions in the first direction is W2, the widths of the plurality of emitter portions in the first direction are the same; or the widths of the plurality of emitter portions in the first direction are not completely the same.

16. The semiconductor device according to claim 12, from a top view perspective, the emitter layer is at least one of a square, a rounded rectangle, a circle, a small ellipse and a hexagon; and / or the emitter layer is a combination of at least two of a plurality of small squares, small circles, small ellipses and small rounded rectangles.

17. According to the semiconductor device of claim 13, the drift layer is provided with a plurality of groove portions spaced apart in a first direction in a portion corresponding to an active area of ​​the semiconductor device, the spacing distance between two adjacent groove portions in the first direction is L1, and the distance from one of the plurality of groove portions adjacent to the well region to the well region in the first direction is W3, and W3 and L1 satisfy the relationship: W3≥L1.

18. The semiconductor device according to claim 12, wherein the drift layer is provided with a groove portion, the groove portion is extended in the second direction, there are a plurality of groove portions, and the plurality of groove portions are spaced apart in the first direction; or The groove portion is extended in the first direction, there are a plurality of groove portions, and the plurality of groove portions are spaced apart in the second direction.

19. The semiconductor device according to claim 12, wherein the gate pad is located at one side of the drift layer in the second direction, and the gate pad is symmetrically arranged about a center line extending in the second direction of the drift layer; or the gate pad is located at one end of the drift layer in the first direction.

20. The semiconductor device according to claim 18, wherein an emitter metal is further disposed on the upper surface of the dielectric layer, a first contact hole is disposed on the dielectric layer, at least a portion of the emitter metal passes through the first contact hole and contacts the well region, and the first contact hole is in a continuous long strip shape; or The first contact holes are rectangular and multiple, and the multiple first contact holes are spaced apart in the first direction.

21. The semiconductor device according to claim 20, wherein the groove portion comprises a gate groove portion and a dummy gate groove portion, at least one dummy gate groove portion is disposed between two adjacent gate groove portions, and the first contact hole is located between the two adjacent gate groove portions and is spaced apart from the dummy gate groove portion in the second direction; The first contact hole and the gate trench portion are spaced apart in a first direction.

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