Address allocation method, battery module management method, and electronic device

Abstract

The present application relates to the technical field of communications, and discloses an address allocation method, a battery module management method, and an electronic device. The address allocation method comprises: acquiring first device direct-current internal resistance of a first node and second device direct-current internal resistance of a plurality of second nodes that are in communication connection with the first node; according to a preset test rule, sequentially determining cable direct-current resistance between the first node and each second node among the plurality of second nodes; on the basis of the first device direct-current internal resistance, the second device direct-current internal resistance, and the cable direct-current resistance, determining the cable resistance value of a transmission cable between the first node and each second node; and on the basis of an ascending order of the cable resistance value, allocating a network address for each second node.

Description

Address allocation method, battery module management method and electronic equipment

[0001] Cross-references

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on June 30, 2023, with application number 202310803137.X and invention name “Address allocation method, battery module management method and electronic device”. The entire contents of the application are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the field of industrial control technology, and in particular to an address allocation method, a battery module management method, and an electronic device. Background Art

[0004] With the development of technology and the improvement of living standards, electronic products such as industrial control, medical, communication, and consumer products are becoming increasingly intelligent. Embedded systems with microprocessors as the core have been widely used, and on-site networking and management of these intelligent devices have also become the focus of embedded applications.

[0005] In the industrial control field, embedded devices use fieldbuses such as RS485 and Controller Area Network (CAN) to implement local area network communication at the field device level. One embedded device (called a master) can monitor other embedded devices (called slaves). Due to the large number of slaves, the master typically uses device communication addresses to distinguish between them. If a slave fails, its address is lost, or a duplicate address causes a bus conflict, the communication address must be reassigned to ensure normal communication.

[0006] Existing address allocation methods generally include the following:

[0007] (1) DIP configuration. The slave device to be configured has a DIP switch. Each DIP switch has multiple key positions. The key positions of the DIP switches of different slave devices must be different.

[0008] (2) Binding. When using the binding method, you need to press the button one by one to trigger the slave to enter the binding mode, and press the button again to exit the mode after the binding is completed.

[0009] (3) Power on one by one. Power on the slaves whose addresses are to be configured one by one (other slaves are powered off or not working), and let the host complete the address setting of the connected slaves in sequence through the CAN network.

[0010] (4) Auxiliary information identification method. This involves adding auxiliary identification information for each slot to the slave, such as assigning a different voltage level to each slot. The most common approach is to add a socket voltage bus (SVB) with precision resistors connected in series to provide a different voltage level to each slot. The slave recognizes this voltage level and can then set a different communication address value.

[0011] (5) Daisy chain or token ring method. This method adds a daisy chain channel between each slave node, with the input of each slave connected to the output of the previous slave. The address is allocated sequentially by passing information to the next slave node step by step.

[0012] The aforementioned address allocation methods, which rely on dial-up configuration, code pairing, and power-up, require manual operation and are prone to coding errors. While auxiliary information recognition, daisy chain, or token ring methods can automatically assign addresses, the wiring system is no longer based on standard single-pair twisted-pair cabling, creating compatibility issues. Furthermore, new signal lines must be added to the standard communication bus, making the interface more complex. This system also increases the potential for external risks, requiring additional electrostatic discharge (ESD) and surge protection for the newly added interfaces, reducing communication reliability.

[0013] Summary of the Invention

[0014] Embodiments of the present application provide an address allocation method, a battery module management method, and an electronic device.

[0015] In a first aspect, an embodiment of the present application provides an address allocation method, including: obtaining the DC internal resistance of a first device of a first node and the DC internal resistance of a second device of a plurality of second nodes that are interconnected and communicatively connected to the first node; determining the DC resistance of the cable between the first node and each of the plurality of second nodes in sequence according to a preset test rule; determining the cable resistance of the transmission cable between the first node and each second node based on the DC internal resistance of the first device, the DC internal resistance of the second device, and the DC resistance of the cable; and allocating a network address to each second node in ascending order of the cable resistance.

[0016] In a second aspect, an embodiment of the present application provides a battery module management method for controlling a battery energy storage system, wherein the battery energy storage system includes a battery system controller, a battery cluster management unit, and a battery module; the battery system controller is communicatively connected to multiple battery cluster management units via a field bus, and each battery cluster management unit is communicatively connected to multiple battery modules via a field bus, and the field bus communication address is allocated based on the method described in the first aspect above.

[0017] In a third aspect, an embodiment of the present application provides a measurement circuit for the DC resistance of a cable, comprising: a first node, the first node comprising a first transceiver, a first branch, and a second branch; wherein a first switch and a first matching resistor are connected in series in sequence to form the first branch; a first on-resistance, a second switch, a bridge measurement topology circuit, a third switch, and a second on-resistance are connected in series in sequence to form the second branch; the first transceiver, the first branch, and the second branch are connected in parallel to a field bus; a plurality of second nodes, wherein each second node comprises: a second transceiver, a third branch, and a fourth branch; a fourth switch and a second matching resistor are connected in series in sequence to form the third branch; a fifth switch and a third on-resistance are connected in series in sequence to form the fourth branch; the second transceiver, the third branch, and the fourth branch are connected in parallel to the field bus; a bridge measurement topology circuit is constructed at both ends of the first node, and is used to measure the DC resistance of the cable between the first node and the second node to be measured when the second switch, the third switch, and the fifth switch in each branch of the first node and the second node to be measured in the plurality of second nodes are turned on.

[0018] In a fourth aspect, an embodiment of the present application provides an electronic device, characterized in that it includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the first or second aspect above are implemented.

[0019] In a fifth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first or second aspect above are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0021] FIG1 is a schematic diagram showing a flow chart of an address allocation method provided in an embodiment of the present application;

[0022] FIG2 shows an overall architecture diagram of a battery energy storage system provided in an embodiment of the present application;

[0023] FIG3 shows a schematic diagram of a CAN network daisy chain engineering wiring according to an embodiment of the present application;

[0024] FIG4 shows a topological structure diagram of a standard dual-terminal CAN network bus provided in an embodiment of the present application;

[0025] FIG5 shows a circuit diagram of a CAN network cable DC resistance measurement circuit according to an embodiment of the present application;

[0026] FIG6 shows a schematic diagram of the operation of allocating sub-device addresses on a CAN network according to an embodiment of the present application;

[0027] FIG7 shows a flowchart of sequentially allocating communication addresses of sub-devices according to an embodiment of the present application;

[0028] FIG8 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0030] In the industrial control field, embedded devices use fieldbuses such as RS485 and CAN to implement local area network communication at the field device level. One embedded device (called a master) can monitor other embedded devices (called slaves). Due to the large number of slaves, the master typically uses device communication addresses to distinguish between them. For example, in a typical large-scale energy storage system, numerous battery modules connected in series and parallel are typically interconnected via a CAN bus and managed by a higher-level management unit (such as a battery cluster controller or battery system controller). This system performs charge and discharge control, balancing, current sharing, and abnormal protection, thereby achieving valuable services such as frequency and peak regulation, multi-energy complementarity, smooth power generation, and peak-load shifting.

[0031] When constructing a field area network using a fieldbus like CAN, individual slave devices must be distinguished by device identification. The simplest method is to use the device communication address. In an energy storage system CAN network, the battery cluster controller or battery system controller is typically the master, while the numerous battery modules are slaves. Each slave device has a unique communication address to prevent bus conflicts.

[0032] Existing address allocation methods include dial-code configuration, pairing, and power-up-by-power-up. These methods often require manual operation and are prone to coding errors. Other methods, such as auxiliary information recognition, daisy chaining, or token ring, can automatically assign addresses, but the cabling system is no longer standard single-twisted-pair cabling, which presents compatibility issues as it evolves to future technologies such as SPE. Furthermore, new signal lines must be added to the standard communication bus, further complicating the interface. This also increases the potential for external risks, requiring additional ESD and surge protection for the newly added interfaces, reducing communication reliability.

[0033] Furthermore, neither method automatically solves the resistor matching problem. CAN bus topologies generally fall into three categories: daisy chain, tree, and star. Daisy chain, the most commonly used topology on project sites, typically requires a 120-ohm termination resistor at each end of the bus (the initiating and ending devices) to achieve impedance matching between the transmission line and the load, reducing signal reflections and improving signal quality and anti-interference capabilities. Currently, this resistor must be manually connected at the start of a network, which is complex and requires significant labor costs.

[0034] An embodiment of the present application provides an address allocation method that determines the physical order of node device cable connections based on the cable resistance of a transmission cable between a first node and a second node, and assigns a corresponding network address to each node, thereby reducing the complexity of the communication interface and improving system reliability. As shown in FIG1 , the address allocation method 100 may include the following steps: S101: obtaining the DC internal resistance of a first device of a first node and the DC internal resistance of a second device of a plurality of second nodes that are communicatively connected to the first node; S102: sequentially determining the DC resistance of the cable between the first node and each of the plurality of second nodes according to a preset test rule; S103: determining the cable resistance of the transmission cable between the first node and each of the second nodes based on the first device DC internal resistance, the second device DC internal resistance, and the cable DC resistance; S104: assigning a network address to each second node in ascending order of the cable resistance.

[0035] This is illustrated with a specific example. For example, as shown in Figure 2, an energy storage system includes a battery management unit (BMU), a battery cluster management unit (BCMU), and a battery system management unit (BSMU). The BMU, BCMU, and BSMU together form a standard three-tier BMS technology architecture: the BCMU manages multiple BMUs via the CAN bus. The BCMUs work together to sequentially identify and assign BMU network addresses by carefully measuring the resistance of the transmission cables between the BCMU master node and each BMU slave node. The BSMU also sequentially identifies and assigns network addresses to each BCMU.

[0036] Since the cable resistance of the transmission cable is usually small, it is necessary to consider the DC internal resistance of the equipment at each node. In order to accurately determine the cable resistance, the embodiment of the present application tests the DC resistance of the cable between the master node and the slave node, determines the cable resistance based on the cable DC resistance and the DC internal resistance of the equipment at each node, and then sorts the cable resistances from large to small, correspondingly identifies the physical connection order of each slave node device, and sequentially assigns a network address to each slave node. Compared to the existing auxiliary information identification method, daisy chain or token ring method, this method does not require the addition of new signal lines, and the sequential allocation of network addresses can be achieved by measuring the DC resistance of the cable. In this way, the complexity of the communication interface can be reduced, and the possibility of introducing external risks can be reduced, thereby helping to improve the reliability of the system.

[0037] In a possible implementation, in the above step S101, obtaining the first device DC internal resistance of the first node and the second device DC internal resistance of multiple second nodes that are communicatively connected to the first node includes: cascading the first node and the multiple second nodes in a daisy chain manner in sequence to establish a communication network between the first node and the multiple second nodes; sending a request message to a target node in the communication network, and receiving a request response message carrying configuration information returned by the target node, the target node including the first node and the second node; determining the first device DC internal resistance of the first node and the second device DC internal resistance of the multiple second nodes based on the configuration information carried in the request response message.

[0038] In a specific implementation, since the network engineering wiring based on the field bus is usually a sequential structure in the form of a daisy chain, the first node and the multiple second nodes are cascaded in sequence in a daisy chain manner, and the engineering wiring is shown in Figure 3, thereby establishing a communication network between the first node and the multiple second nodes. In addition, the first node and the multiple second nodes are cascaded in a daisy chain manner, and the cable length between each second node and the first node is different. In this way, the network address is assigned to each second node in the order of cable resistance from small to large, which can effectively avoid the problem of network address conflict.

[0039] Then, a request message is periodically sent to a target node in the communication network, and the target node responds and sends a request response message carrying configuration information; based on the configuration information carried in the request response message, the DC internal resistance of the first device of the first node and the DC internal resistance of the second devices of multiple second nodes are determined.

[0040] In which, the configuration information includes the device serial number; in the above step S102, the DC resistance of the cable between the first node and each of the multiple second nodes is determined in sequence according to the preset test rules, including: sorting the target nodes according to the device serial number, and determining the test serial number corresponding to the target node according to the sorting result; sending test configuration information to the target node, and when it is determined that the target node enters the test state, measuring the DC resistance of the cable between the first node and each of the multiple second nodes, the test configuration information including the test serial number.

[0041] In practice, each target node is uniquely identified by its device serial number (DSN). These nodes are sorted by DSN size and assigned a test sequence number. A notification is broadcast over the established communication network to all target nodes, informing them that the resistance network test procedure is ready to begin. The test configuration information sent includes the total number of tests, the duration of a single test (also known as a test cycle), and the test sequence number of the specified DSN. For example, if there are 16 slave nodes and a single test duration of 2 seconds, the entire test duration is 32 seconds.

[0042] If the target node is determined to have entered the test state, the DC resistance of the cable between the first node and each of the plurality of second nodes is measured. The target node is determined to have entered the test state upon receiving a response message from the target node. Specifically, the test process is officially initiated by broadcasting a notification to all target nodes via the established communication network. If each target node confirms the response, all nodes enter the test state.

[0043] In one possible embodiment, the DC resistance of the cable between a first node and each of a plurality of second nodes can be measured in the following manner: the electrical connection between the first node and a second node to be tested among the plurality of second nodes and the field bus is controlled to be conductive, so as to form a closed loop between the first node and the second node to be tested; and the DC resistance of the cable between the first node and the second node to be tested is measured by pre-building a bridge topology circuit at both ends of the first node.

[0044] The standard dual-terminal CAN network bus topology is shown in Figure 4 , where a first node (BCMU) is connected to each second node (BMU.1, ..., BMU.m) via a CAN bus. Matching resistors are connected to each end of the bus (the initiating device and the terminal device) to achieve impedance matching between the transmission line and the load. In this embodiment, a first node and a second node to be tested are first connected to form a closed loop via a field bus; then, a bridge measurement topology circuit pre-established at both ends of the first node is used to measure the DC resistance of the cable between the first node and the second node to be tested.

[0045] The embodiment of the present application further provides a measurement circuit for a cable DC resistance, as shown in FIG5 , the measurement circuit includes a first node, a plurality of second nodes, and a bridge measurement topology circuit; wherein the first node includes a first transceiver r T0 , the first branch and the second branch; the first switch 1 and the first matching resistor r M0 are connected in series to form the first branch; the first on-resistance r 0n2 , the second switch 2, the bridge measurement topology circuit, the third switch 3 and the second on-resistance r 0n3 The first transceiver, the first branch and the second branch are connected in parallel to each other and then connected to the field bus; each second node includes a second transceiver r t1 or r tm , the third branch, the fourth branch; the fourth switch 2 and the second matching resistor r M1 The third branch is formed in series; the fifth switch 1 and the third on-resistor r 0n1 The fourth branch is formed in series in sequence; the second transceiver, the third branch, and the fourth branch are connected in parallel to the field bus; a bridge measurement topology circuit is built at both ends of the first node, and is used to measure the DC resistance of the cable between the first node and the second node to be measured when the second switch 2, the third switch 3, and the fifth switch 1 in each branch of the first node and the second node to be measured among the multiple second nodes are turned on.

[0046] In conjunction with the circuit structure shown in FIG5 , the process of measuring the DC resistance of a cable may include the following steps.

[0047] Step 1: Test the slave node with the smallest sequence number and enter the test state first.

[0048] Step 2: For the second node (slave node) to be tested, close switch 1 on the CAN interface, i.e., the on-resistance switch, to achieve a loop of the cable to be tested; at the same time, open switch 2 on the CAN interface, i.e., the matching resistor switch, to eliminate the influence of the matching resistor.

[0049] Step 3: For other slave nodes not measured, keep switches 1 and 2 on the CAN interface normally open.

[0050] Step 4: For the first node (master node), disconnect the matching resistor switch 1 on the CAN interface and close the bridge measurement topology switches 2 and 3.

[0051] Step 5: The master node uses a bridge measurement topology circuit to measure the DC resistance Zt of the entire cable between the master node and the slave node under test. To avoid clock skew, it's best to measure Zt near the center of the test cycle. For example, if the test cycle is 2 seconds, the test should be performed between 0.9 and 1.1 seconds.

[0052] Step 6: The cable resistance can be determined as follows: Subtract the master node device DC internal resistance (DDIR) from the total cable DC resistance Zt, and then subtract the slave node DDIR value to obtain the actual transmission cable resistance (TCR) of the twisted pair.

[0053] Step 7: Wait for the test cycle to end.

[0054] Step 8: According to the rules, start the slave node test with the next test sequence number.

[0055] Step 9: Repeat steps 2 to 7 to complete the cable resistance TCR test for all slave nodes.

[0056] Step 10: Complete all tests.

[0057] The device DC internal resistance is the sum of the single-board internal resistance and the analog switch on-resistance of the network interface end of the target node; the device DC internal resistance is determined by: using a multimeter to measure the device DC internal resistance at the network interface end of the target node; or, directly connecting the first node and the second node one-to-one with a cable, and using a bridge topology circuit pre-built at both ends of the first node to measure the device DC internal resistance at the network interface end of the second node.

[0058] In practice, during the factory commissioning phase, the DC internal resistance (DDIR) of each node is tested. Using the circuit structure shown in Figure 5, the steps for pre-shipment DDIR testing are as follows: Step 1: After powering on the first node (master), run the commissioning subroutine, open switch 1, and close switches 2 and 3. Using a multimeter to measure low-resistance resistance with high precision (such as four-wire measurement or four-wire measurement with a constant current source to reduce feeder resistance errors), measure the resistance across the CAN interface, i.e., the master node's DDIR. Alternatively, a bridge-topology tool for low-resistance measurement can be built to automate the measurement. Step 2: After powering on the second node (slave), run the commissioning subroutine, close switch 1, and open switch 2. Similar to the master node, use a multimeter or a bridge-topology tool to measure the slave node's DDIR. Alternatively, a tool can be built using the master node's internal bridge topology. For example, the master node and the slave node are directly connected one by one, and the connecting cable is as short as possible. After running the cable resistance test process and obtaining the cable DC resistance Zt, subtract the master node DDIR to obtain the slave node DDIR value (assuming the connecting cable is as short as possible and the cable resistance is 0).

[0059] In a possible implementation, in the above step S104, after allocating a network address to each second node in the order of the cable resistance from small to large, the address allocation method 100 further includes: the first node sends an address allocation message to each second node, and the address allocation message includes the device serial number and network address of the second node.

[0060] In a specific implementation, network addresses are assigned to each second node in ascending order of cable resistance. The specific steps are as follows: Step 1: The master node and slave nodes end the test state and return to the initial state; all switches on the CAN interfaces of all nodes are restored to the normally open state. The CAN network resumes normal communication; Step 2: The master node sorts the TCR values ​​of all slave nodes from small to large; Step 3: The smaller the TCR value, the shorter the cable length, and the closer to the master node, the smallest the assigned device network address (DNA), and the addresses are assigned sequentially starting from 1; Step 4: The master node saves all DNA values ​​in the system configuration table and broadcasts the assigned DSN and assigned network address DNA to each slave node via the CAN network; each slave node assigned a DSN confirms the response and saves the DNA locally; Step 5: The sequential allocation of network addresses to all slave nodes is completed.

[0061] In a possible implementation, in the above step S104, after assigning a network address to each second node in the order of the cable resistance from small to large, the address assignment method 100 further includes: configuring a first matching resistor at both ends of the first node, and configuring a second matching resistor at both ends of the second node with the largest network address among the multiple second nodes.

[0062] In a specific implementation, combined with the circuit structure shown in Figure 5, a first matching resistor is configured at both ends of a first node via analog switches, and a second matching resistor is configured at both ends of the second node with the largest network address among multiple second nodes. Specifically, the master node closes switch 1 on the CAN interface to configure the matching resistor at the beginning of the network. The slave node with the largest DNA address closes switch 2 on the CAN interface to configure the matching resistor at the end of the network. All other nodes and all switches remain normally open, and each node locally stores whether the matching resistor is configured.

[0063] In one possible embodiment, after receiving the request response message carrying configuration information returned by the target node, the method further includes: storing the configuration information of the target node in a system configuration table; obtaining a configuration information change message sent by the target second node, and updating the configuration information corresponding to the target second node in the system configuration table according to the configuration change information carried in the configuration information change message.

[0064] Among them, the system configuration table is shown in Table 1:

[0065] Table 1 System Configuration Table

[0066] From the above system configuration table, the number of slave nodes and the configuration information of the master node and each slave node can be obtained. The configuration information of the node can be as shown in Table 2:

[0067] Table 2 Node configuration table

[0068] The device serial number DSN can be used as an index of the configuration information of each target node, and the device DC internal resistance, the assigned device network address and the calculated transmission cable resistance are all stored in the system configuration table.

[0069] When the configuration information of the target second node changes, the target second node actively reports a configuration information change message, and updates the configuration information corresponding to the target second node in the system configuration table according to the configuration change information carried in the configuration information change message.

[0070] In a specific implementation, if the second node is replaced in situ, for example, a sub-node device is unplugged due to a fault, and then a new device is inserted to replace it. Since the new device has just been connected to the network, it will actively broadcast its own DSN and apply to the system for address configuration. After the master node recognizes this scenario (the original node exits and the new node joins), the corresponding processing steps are as follows: the master node updates the sub-device configuration information table; the sub-device with a certain communication address is replaced, and the original DSN is replaced with the new DSN; the master node informs the new sub-device through CAN communication to use the configuration information of the original node, including the assigned sequential network address and whether the matching resistor is configured.

[0071] After updating the configuration information corresponding to the target second node in the system configuration table, the method further includes: determining an updated cable resistance value of the transmission cable between the first node and each second node based on the configuration information of each target node in the updated system configuration table; allocating a temporary network address to each second node in ascending order of the updated cable resistance value; and configuring a second matching resistor at both ends of the second node having the largest temporary network address among each second node.

[0072] Optionally, after allocating a temporary network address to each second node in the order of the updated cable resistance from small to large, the method further includes: updating the network address of each second node to the temporary network address; the first node sends an address allocation message to each second node, and the address allocation message includes the device serial number of the second node and the updated network address.

[0073] During the operation and maintenance phase, complex scenarios such as equipment expansion or partial replacement may also occur. It is even more important to ensure simple and fast configuration of address settings, as well as automatic identification and automatic updating. The core technology is to achieve this through intelligent collaboration among various devices, which can be divided into the following scenarios.

[0074] The first possible scenario involves a reduction in child nodes. For example, a child node device experiences a malfunction and is removed from its slot for maintenance. For a CAN network, this is equivalent to a child node exiting. When the master node detects a child node exiting the network, it handles the following steps.

[0075] If the exiting child node is an end-device, that is, the child node with the highest DNA value, the master node will notify the child node with the next highest DNA value to configure the end-matching resistor; all other system configuration information remains unchanged. If the exiting child node is an intermediate child device, that is, the child node with a lower DNA value, all system configuration information remains unchanged. Of course, according to some user maintenance requirements or practices, you can also re-execute the automatic configuration at the start of the deployment to re-assign the addresses and avoid discontinuities in the child node addresses.

[0076] The second possible scenario: The addition of child nodes is equivalent to system expansion. Newly added child nodes will proactively broadcast their own DSNs and request address configuration from the system, allowing the system to detect new devices. Once the master node recognizes this scenario, it will proceed as follows.

[0077] Re-execute the automatic configuration at the start of the deployment to temporarily redistribute the addresses. Analyze and compare the original and new address allocation results. If the address assigned to the newly added sub-node is ranked highest, it means that the system expansion is sequential (that is, the new sub-device is after the original sub-device). The system uses the latest allocation result and notifies the new node with the highest address to configure terminal resistance matching. If the address assigned to the newly added sub-node is ranked in the middle, it means that the system expansion is vacant (that is, the new sub-device is inserted into the vacant slot in the middle of the original device). At this time, the system uses the latest allocation result and notifies the operation and maintenance system of the information of all sub-nodes with changed network addresses (indexed by DSN).

[0078] Through this approach, the system automatically identifies and updates address configurations during the operation and maintenance phase, regardless of changes such as equipment expansion, replacement, or reduction. In particular, when network start and end devices change, the terminal matching resistors can be automatically and dynamically updated simultaneously. The child node with the largest network address is detected in real time and notified to dynamically configure the matching resistor by closing the matching resistor switch.

[0079] The address allocation method provided in the embodiment of the present application can realize the automatic configuration of matching resistors, avoid the most common phenomenon of manual matching resistor omission changes in daily operation and maintenance, and eliminate operational risks such as occasional communication anomalies and positioning difficulties caused by resistance mismatch in the subsequent operation of the CAN network.

[0080] The above steps are described in detail below with reference to specific examples.

[0081] Consider a company that provides a large-capacity telecom battery energy storage product for a telecom operator's core and aggregation equipment rooms, replacing the existing lead-acid battery system. This energy storage product consists of up to 192 48V / 100Ah smart lithium-ion battery modules connected in parallel. Each 32 modules form a battery cabinet, managed by a controller (BCMU) on the cabinet via the CAN network. Up to six such cabinets connected in parallel form the entire energy storage system, which is managed by a centralized controller (BSMU) over the CAN network. This constitutes a standard three-tier BMS architecture.

[0082] In the original design, each of the 32 battery modules in the CAN network was assigned communication addresses 1 to 32 through address competition. Obviously, these communication addresses were completely inconsistent with the actual physical slot addresses, causing significant inconvenience during daily operations and maintenance. Therefore, adopting the proposed solution, modifying the BMU, BCMU, and BSMU in the battery module effectively ensures the sequential allocation of communication addresses for each battery module and BCMU in the CAN network.

[0083] As shown in Figure 6, during the product design phase, hardware modifications to the CAN interface of each node are required. This involves adding low-resistance analog switches to the slave nodes and a bridge topology for low-resistance measurement to the master node. Furthermore, analysis of the twisted-pair cable and CAN interface is required.

[0084] 1) CAN communication cables are standard twisted-pair cables, the most commonly used transmission medium in structured cabling projects. Category 3 links are generally required to have a resistance of no more than 170Ω, and Category 3 and higher links no more than 30Ω. The ISO / IEC 11801 standard stipulates that the DC resistance of twisted-pair cables must not exceed 19.2Ω, and the difference in DC resistance between each twisted-pair pair must be less than 0.1Ω. Therefore, the DC loop resistance of each slave node cable to be measured should be on the order of 0.1Ω.

[0085] 2) The CAN interface of each node device is typically located near the external connector, and the printed circuit board (PCB) resistance is typically on the order of 0.1Ω. Common CAN transceivers in the industry typically have input resistances exceeding 20kΩ. We selected the high-speed CAN transceiver TJA1051T / E, which has a typical input impedance of 30kΩ and offers ideal passive performance when the CAN bus is powered off (i.e., the transceiver can disconnect from the bus), making it ideal for measuring cable DC loop resistance.

[0086] 3) Since the cable DC loop resistance is on the order of 0.1Ω, in the bridge circuit in the master node, R0 is selected as a 1.0Ω precision resistor, R1 and R2 are selected as 10Ω precision resistors, and the ratio arm multiplier k = R1 / R2 = 1.0 can obtain the highest test sensitivity.

[0087] 4) Similarly, since the cable's DC loop resistance is on the order of 0.1Ω, the analog switch's on-resistance must be minimal, otherwise measurement accuracy will be affected. Therefore, we chose the TS5A23166 dual SPST analog switch, which has a typical on-resistance of just 0.9Ω and a maximum flatness of only 0.2Ω.

[0088] During factory commissioning, the DDIR of each node must be tested and stored along with the DSN. This commissioning process utilizes self-developed tooling. The core of this tooling is a Kelvin bridge (double-arm bridge method) capable of performing precision testing of small resistance values. The measured values ​​are then transmitted to the node devices via communication for configuration and storage, enhancing the automation level of production commissioning.

[0089] At system startup, the master BCMU and each slave BMU in each cabinet are sequentially connected using a CAN bus daisy-chain connection. Similarly, the master BSMU in the system control unit is connected to the slave BCMUs in each parallel cabinet. As shown in Figure 7, using a battery cabinet as an example, the address sequence and matching resistors of each slave BMU are automatically configured. The specific steps are as follows.

[0090] 1) The BCMU and each slave node BMU in the cabinet are powered on and running. Each slave node, newly connected to the network, proactively requests an address configuration. The master node BCMU obtains and saves the DSN and DDIR of each slave node.

[0091] 2) The master node BCMU sorts the DSN sizes of each slave node and assigns a test sequence number.

[0092] 3) The master node announces its readiness to initiate the resistance network test and provides the test procedures: total number of tests, single test duration, and the test sequence number of the specified DSN. Each slave node confirms its response. Clearly, the number of slave nodes is 32, the single test duration is 2 seconds, and the total test duration is 64 seconds.

[0093] 4) The master and slave nodes cooperate to complete the TCR test of the transmission cable resistance of all slave nodes in sequence.

[0094] 5) The master node sorts all the tested TCR values ​​from small to large, and uses the slave node's DSN as the index, assigning addresses sequentially starting from 1; the node with the smallest TCR value is assigned the smallest address DNA.

[0095] 6) The master node broadcasts the network address DNA assigned to each slave node by specifying the DSN. Each designated slave node confirms and responds; in this way, the network address sequence of all slave nodes is assigned.

[0096] 7) The master node and the slave node with the largest address complete the resistance matching at the beginning and end.

[0097] Other battery cabinets can be operated in parallel to complete the sequential configuration of the BMU addresses of all slave nodes. Similarly, the sequential configuration of all BCMU addresses can also be completed.

[0098] Because the DC loop resistance of the cable to be measured is relatively low, an analog switch with low on-resistance is selected to improve measurement accuracy. Since analog switches vary from vendor to vendor and from batch to batch, their on-resistance (Ron) may vary somewhat. This is addressed by configuring the DC internal resistance (DDIR) of the factory test equipment. Furthermore, Ron flatness is a concern. Ron varies with the power supply voltage and input voltage, and the difference between its maximum and minimum values ​​represents Ron flatness. Device data from various manufacturers indicates excellent flatness when the power supply voltage is high (e.g., exceeding 3.3V) or the input voltage is high (e.g., exceeding 2.5V). This means that the Ron value remains essentially stable.

[0099] Therefore, on the one hand, when supplying the analog switch, try to select a higher voltage level. For example, the TS5A23166 has a supply voltage range of -0.5V to 6.5V. Therefore, when provided with a standard 5.0V power supply, Ron flatness is better. On the other hand, during the factory commissioning phase, when testing the DDIR of each node, multi-point testing with different input voltages can be performed and the test results can be saved in the node configuration table. When the host measures the DC loop resistance of the cable, it can perform fitting or compensation based on the actual input voltage value to obtain more accurate loop resistance measurements.

[0100] FIG8 shows a schematic diagram of the hardware structure of an electronic device that implements an embodiment of the present application. Referring to the figure, at the hardware level, the electronic device includes a processor, and optionally, an internal bus, a network interface, and a memory. The memory may include a memory, such as a high-speed random access memory (RAM), and may also include a non-volatile memory (non-volatile memory), such as at least one disk storage device. Of course, the electronic device may also include hardware required for other services.

[0101] The processor, network interface, and memory can be interconnected via an internal bus, which can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, among others. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, the figure uses only one bidirectional arrow, but this does not imply that there is only one bus or type of bus. The memory stores programs. Specifically, the program can include program code, which includes computer operating instructions. The memory can include internal memory and non-volatile memory, and provides instructions and data to the processor. The processor reads the corresponding computer program from the non-volatile memory into the internal memory and then runs it, forming a device for locating the target user at a logical level. The processor executes the program stored in the memory and specifically performs the method disclosed in the embodiment shown in FIG1 and implements the functions and beneficial effects of each method described in the preceding method embodiments, which will not be described in detail here.

[0102] The method disclosed in the embodiment shown in FIG1 of the present application can be implemented in a processor or by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor or software instructions. The above processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The various methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0103] The electronic device can also execute the methods described in the above method embodiments and realize the functions and beneficial effects of the methods described in the above method embodiments, which will not be described in detail here.

[0104] Of course, in addition to software implementation, the electronic device of this application does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0105] The present application also proposes a computer-readable storage medium that stores one or more programs. When the one or more programs are executed by an electronic device including multiple application programs, the electronic device executes the method disclosed in the embodiment shown in FIG1 and realizes the functions and beneficial effects of the various methods described in the above method embodiments. The computer-readable storage medium includes a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0106] Furthermore, an embodiment of the present application also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the following process is implemented: the method disclosed in the embodiment shown in Figure 1 and the functions and beneficial effects of the various methods described in the previous method embodiments are implemented, which will not be repeated here.

[0107] In short, the above description is only a preferred embodiment of the present application and does not limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

[0108] The systems, devices, modules, or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0109] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0110] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0111] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

Claims

1. An address allocation method, comprising: Acquire a first device DC internal resistance of a first node and a second device DC internal resistance of a plurality of second nodes that are communicatively connected to the first node; Determine the cable DC resistance between the first node and each of the plurality of second nodes in sequence according to a preset test rule; Determine a cable resistance of a transmission cable between the first node and each second node according to the DC internal resistance of the first device, the DC internal resistance of the second device, and the DC resistance of the cable; A network address is allocated to each second node in the ascending order of the cable resistance.

2. The method according to claim 1, wherein: The step of obtaining a first device DC internal resistance of a first node and a second device DC internal resistance of a plurality of second nodes that are communicatively connected to the first node includes: The first node and the plurality of second nodes are sequentially cascaded in a daisy chain manner to establish a communication network between the first node and the plurality of second nodes; Sending a request message to a target node in the communication network, and receiving a request response message carrying configuration information returned by the target node, the target node including a first node and a second node; According to the configuration information carried in the request response message, a first device DC internal resistance of the first node and second device DC internal resistances of multiple second nodes are determined.

3. The method according to claim 2, wherein: The configuration information includes a device serial number; and determining the cable DC resistance between the first node and each of the plurality of second nodes in sequence according to a preset test rule includes: Sorting the target nodes according to the device serial numbers, and determining the test serial numbers corresponding to the target nodes according to the sorting results; Send test configuration information to the target node, and when it is determined that the target node enters a test state, measure the DC resistance of the cable between the first node and each of the plurality of second nodes, wherein the test configuration information includes a test sequence number.

4. The method according to claim 3, wherein: The step of determining that the target node enters a test state includes: In case of receiving the response message from the target node, it is determined that the target node enters a test state.

5. The method according to claim 3, wherein: The measuring the cable DC resistance between the first node and each second node of the plurality of second nodes comprises: Controlling the electrical connection between the first node and a second node to be tested among a plurality of second nodes and a field bus to be turned on, so as to form a closed loop between the first node and the second node to be tested; The direct current resistance of the cable between the first node and the second node to be tested is measured by using a bridge measurement topology circuit pre-built at both ends of the first node.

6. The method according to claim 2, wherein: The determining, according to the DC internal resistance of the first device, the DC internal resistance of the second device, and the DC resistance of the cable, a cable resistance of the transmission cable between the first node and each second node includes: The device DC internal resistance is determined according to the first device DC internal resistance and the second device DC internal resistance, and the difference between the cable DC resistance and the device DC internal resistance is determined as the cable resistance.

7. The method according to claim 6, wherein: The device DC internal resistance is the sum of the single board internal resistance of the network interface end of the target node and the analog switch on-resistance; The DC internal resistance of the device is determined in the following manner: Use a multimeter to measure the DC internal resistance of the device at the network interface end of the target node; or, The first node and the second node are directly connected one-to-one by cable, and a bridge topology circuit pre-built at both ends of the first node is used to measure the DC internal resistance of the device at the network interface end of the second node.

8. The method according to claim 1, wherein: After allocating a network address to each second node in the ascending order of the cable resistance, the method further includes: The first node sends an address allocation message to each second node, where the address allocation message includes a device serial number and a network address of the second node.

9. The method according to claim 1, wherein: After allocating a network address to each second node in the ascending order of the cable resistance, the method further includes: A first matching resistor is configured at both ends of the first node, and a second matching resistor is configured at both ends of a second node having a largest network address among the plurality of second nodes.

10. The method according to claim 2, wherein: After receiving the request response message carrying the configuration information returned by the target node, the method further includes: Storing the configuration information of the target node in a system configuration table; A configuration information change message sent by the target second node is obtained, and the configuration information corresponding to the target second node in the system configuration table is updated according to the configuration change information carried in the configuration information change message.

11. The method according to claim 10, wherein: After updating the configuration information corresponding to the target second node in the system configuration table, the method further includes: Determine, according to the configuration information of each target node in the updated system configuration table, an updated cable resistance value of the transmission cable between the first node and each second node; Allocating a temporary network address to each second node in the ascending order of the cable update resistance value; Second matching resistors are configured at both ends of the second node having the largest temporary network address among the second nodes.

12. The method according to claim 11, wherein: After allocating a temporary network address to each second node in the ascending order of the updated cable resistance value, the method further includes: Updating the network address of each second node to the temporary network address; The first node sends an address allocation message to each second node, where the address allocation message includes a device serial number and an updated network address of the second node.

13. A battery module management method for controlling a battery energy storage system, wherein the battery energy storage system comprises a battery system controller, a battery cluster management unit and a battery module; the battery system controller is communicatively connected to a plurality of battery cluster management units via a field bus, each battery cluster management unit is communicatively connected to a plurality of battery modules via a field bus, and the field bus communication address is allocated based on the method described in any one of claims 1 to 12.

14. A cable DC resistance measurement circuit, comprising: A first node, the first node comprises a first transceiver, a first branch and a second branch; wherein a first switch and a first matching resistor are sequentially connected in series to form the first branch; a first on-resistance, a second switch, a bridge measurement topology circuit, a third switch and a second on-resistance are sequentially connected in series to form the second branch; the first transceiver, the first branch and the second branch are connected in parallel to a field bus; A plurality of second nodes, wherein each of the second nodes comprises: a second transceiver, a third branch, The fourth branch; the fourth switch and the second matching resistor are connected in series to form the third branch; the fifth switch and the third on-resistor are connected in series to form the fourth branch; the second transceiver, the third branch and the fourth branch are connected in parallel to the field bus; A bridge measurement topology circuit is built at both ends of the first node, and is used to measure the DC resistance of the cable between the first node and the second node to be measured when the second switch, the third switch and the fifth switch in each branch of the first node and the second node to be measured among the plurality of second nodes are turned on.

15. An electronic device, comprising a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the method according to any one of claims 1 to 13 are implemented.

16. A readable storage medium storing a program or an instruction, wherein the program or the instruction, when executed by a processor, implements the steps of the method according to any one of claims 1 to 13.

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