Wiring method and device for multi-chip package

Abstract

A wiring method and device for a multi-chip package. The wiring method for a multi-chip package comprises: acquiring a multi-chip theoretical wiring solution for multi-chip connection (S11); dividing the multi-chip theoretical wiring solution into multiple single-chip theoretical wiring solutions on the basis of the multi-chip theoretical wiring solution (S12); on the basis of the single-chip theoretical wiring solutions, dividing the wiring between every two adjacent chips into an inter-chip connection section, a first chip following section, and an intra-chip connection section (S13); and adjusting the poses of the first chip following section and the intra-chip connection section on the basis of movement poses of the chips to obtain a first actual wiring solution (S14).

Description

Multi-chip package wiring method and device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 29, 2023, with application number 202310779286.7, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip packaging technology, for example, to a wiring method and device for multi-chip packaging. Background Art

[0003] In fan-out panel-level packages (PLPs), multi-chip packaging requires mounting multiple chips onto a substrate, followed by encapsulation and drilling. During the chip mounting and encapsulation process, temperature fluctuations and other factors can cause the chips to shift and rotate, shifting the electrode positions on the chips. This can affect subsequent circuit layout and the positional relationship between chips, ultimately impacting the chip's electrical properties.

[0004] Summary of the Invention

[0005] The present application provides a wiring method and device for multi-chip packaging to solve the problem that the position relationship between chips changes due to chip position offset during the packaging process, which in turn affects the electrical properties of the chips and leads to a high scrap rate of multi-chip packaging.

[0006] According to one aspect of the present application, a wiring method for a multi-chip package is provided, comprising:

[0007] Obtain a multi-chip theoretical wiring solution when multiple chips are connected;

[0008] Dividing the multi-chip theoretical wiring scheme into a plurality of single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme;

[0009] According to the single-chip theoretical wiring scheme, the wiring between two adjacent chips is divided into an inter-chip connection section, a first chip follower section, and an intra-chip connection section; the inter-chip connection section is connected to its adjacent chip, the first chip follower section is connected to the electrode in the chip, and the intra-chip connection section is connected to the inter-chip connection section and the first chip follower section respectively;

[0010] The positions of the first chip following sub-section and the intra-chip connecting sub-section are adjusted according to the moving posture of the chip to obtain a first actual wiring scheme.

[0011] According to another aspect of the present application, a wiring device for a multi-chip package is provided, comprising:

[0012] A multi-chip theoretical wiring acquisition module is configured to acquire a multi-chip theoretical wiring scheme when multiple chips are connected;

[0013] a multi-chip theoretical wiring division module configured to divide the multi-chip theoretical wiring scheme into a plurality of single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme; divide the wiring between two adjacent chips into an inter-chip connection subsection, a first chip follower subsection, and an intra-chip connection subsection according to the single-chip theoretical wiring scheme; the inter-chip connection subsection is connected to the adjacent chip, the first chip follower subsection is connected to the electrode in the chip, and the intra-chip connection subsection is connected to the inter-chip connection subsection and the first chip follower subsection respectively;

[0014] The multi-chip actual wiring determination module is configured to adjust the posture of the first chip following sub-section and the intra-chip connection sub-section according to the movement posture of the chip to obtain a first actual wiring plan.

[0015] According to another aspect of the present application, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a wiring method for a multi-chip package when executing the computer program.

[0016] According to another aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, a wiring method for a multi-chip package is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following will introduce the drawings required for the description of the embodiments. The drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] FIG1 is a flow chart of a first multi-chip package wiring method provided according to an embodiment of the present application;

[0019] FIG2 is a schematic structural diagram of wiring division of a multi-chip package provided according to an embodiment of the present application;

[0020] 3 is a flow chart of a second multi-chip package wiring method provided according to an embodiment of the present application;

[0021] FIG4 is a flow chart of a third multi-chip package wiring method provided according to an embodiment of the present application;

[0022] 5 is a flow chart of a fourth multi-chip package wiring method provided according to an embodiment of the present application;

[0023] 6 is a flow chart of a fifth multi-chip package wiring method provided according to an embodiment of the present application;

[0024] 7 is a flowchart of a sixth multi-chip package wiring method provided according to an embodiment of the present application;

[0025] FIG8 is a schematic diagram of a wiring structure of a first multi-chip package provided according to an embodiment of the present application;

[0026] 9 is a schematic diagram of a wiring structure of a second multi-chip package provided according to an embodiment of the present application;

[0027] 10 is a flowchart of a seventh multi-chip package wiring method provided according to an embodiment of the present application;

[0028] 11 is a flowchart of an eighth multi-chip package wiring method provided according to an embodiment of the present application;

[0029] 12 is a flowchart of a ninth multi-chip package wiring method according to an embodiment of the present application;

[0030] 13 is a schematic structural diagram of the wiring division between the chip and the external pins provided in an embodiment of the present application;

[0031] 14 is a flowchart of a tenth multi-chip package wiring method provided according to an embodiment of the present application;

[0032] 15 is a flowchart of an eleventh multi-chip package wiring method provided according to an embodiment of the present application;

[0033] 16 is a flowchart of a twelfth multi-chip package wiring method provided according to an embodiment of the present application;

[0034] 17 is a flowchart of a thirteenth multi-chip package wiring method provided according to an embodiment of the present application;

[0035] FIG18 is a schematic diagram of a wiring structure of a third multi-chip package provided according to an embodiment of the present application;

[0036] 19 is a schematic diagram of a wiring structure of a fourth multi-chip package provided according to an embodiment of the present application;

[0037] 20 is a flowchart of a fourteenth multi-chip package wiring method according to an embodiment of the present application;

[0038] 21 is a flowchart of a fifteenth multi-chip package wiring method provided according to an embodiment of the present application;

[0039] FIG22 is a schematic structural diagram of a wiring device for a multi-chip package provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present application in conjunction with the accompanying drawings. The embodiments described are only some of the embodiments related to the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of this application.

[0041] It should be noted that the terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0042] FIG1 is a flow chart of a first multi-chip package wiring method according to an embodiment of the present application, and FIG2 is a schematic structural diagram of a multi-chip package wiring division according to an embodiment of the present application. This embodiment is applicable to multi-chip packages. As shown in FIG1 and FIG2 , the method includes:

[0043] S11. Obtain a multi-chip theoretical wiring solution when multiple chips are connected.

[0044] In some instances, in the process of packaging multiple chips on the same substrate, each chip needs to be mounted on the substrate. During the mounting process, temperature changes will cause the position of the chip to change, thereby affecting the changes in the wiring between the chip and the pins and the changes in the spacing between the chips. The multi-chip theoretical wiring scheme can be a connection path between the chip and the pin determined according to the distribution position of the electrodes in each chip, the pre-attachment position of each chip, and the distribution position of the pins before the chip is mounted on the substrate. The connection path may include parameters such as line length, line size, line area, and line routing path. The connection path also determines the positional relationship between the chips. The multi-chip theoretical wiring scheme must meet the basic electrical connection specifications for the connection between the chip and the pin and the electrical requirements of the customer's wiring.

[0045] S12. Divide the multi-chip theoretical wiring scheme into multiple single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme.

[0046] In some instances, a single-chip theoretical wiring scheme may be the connection path between a single chip and its pins on a substrate before packaging. Because a multi-chip theoretical wiring scheme includes connection paths between multiple chips and pins, the multi-chip theoretical wiring scheme can be divided into multiple single-chip-pin connection path schemes by chip. In the embodiments of the present application, by dividing the multi-chip theoretical wiring scheme into single-chip theoretical wiring schemes, subsequent adjustments to the wiring schemes for individual chips are facilitated.

[0047] S13. According to the single-chip theoretical wiring scheme, the wiring between two adjacent chips is divided into an inter-chip connection section, a first chip follower section, and an intra-chip connection section; the inter-chip connection section is connected to its adjacent chip, the first chip follower section is connected to the electrode in the chip, and the intra-chip connection section is respectively connected to the inter-chip connection section and the first chip follower section.

[0048] In some embodiments, the inter-chip connection subsection 1, the first chip follower subsection 2, and the intra-chip connection subsection 3 are configured such that the inter-chip connection subsection 1 can be used for connecting between chips; the first chip follower subsection 2 can be used for connecting electrodes within a chip; and the intra-chip connection subsection 3 connects the inter-chip connection subsection 1 and the first chip follower subsection 2. The inter-chip connection subsection 1, the first chip follower subsection 2, and the intra-chip connection subsection 3 collectively connect the chip to the pins, thereby achieving chip-to-chip connection. In an embodiment of the present application, the inter-chip connection subsection 1, the first chip follower subsection 2, and the intra-chip connection subsection 3 are divided and routed in a feasible manner, and the interception position can be determined based on the routing adjustment requirements.

[0049] S14. Adjust the positions of the first chip following sub-section and the intra-chip connection sub-section according to the movement posture of the chip to obtain a first actual wiring scheme.

[0050] In some instances, during the chip mounting process, temperature changes may cause the chip's position on the substrate to be inconsistent with the position in the multi-chip theoretical wiring scheme, that is, the chip's position changes. At this time, it is necessary to adjust the first chip follower section 2 so that the first chip follower section 2 remains connected to the chip's electrode; adjust the position of the chip's internal connection section 3 so that the wiring scheme after packaging meets the basic specifications for chip-to-pin connection, the specifications for the positional relationship between chips, and the customer's special electrical requirements, thereby forming an actual multi-chip wiring scheme.

[0051] Exemplarily, a multi-chip theoretical wiring scheme on a substrate is obtained, and the multi-chip theoretical wiring scheme is divided into a single chip theoretical wiring scheme for subsequent wiring adjustments. In combination with the extension direction of the line and the correlation between the lines, and taking into account the customer's special electrical requirements, the division principle of the inter-chip connection division 1, the first chip follower division 2 and the intra-chip connection division 3 can be divided from the inside to the outside of the chip. In the process of dividing according to the single-chip theoretical wiring scheme, the corresponding parallel lines of the adjacent parallel lines on the same side can be intercepted as the intra-chip connection division 3. When the customer has a clear requirement for the offset size, the line lengths of the inter-chip connection division 1, the first chip follower division 2 and the intra-chip connection division 3 need to be adjusted to be greater than the limit offset value. In the embodiment of the present application, by intercepting parallel lines as the intra-chip connection division 3, the intra-chip connection division 3 will not intersect when moving at the same time, and the routing direction remains consistent to achieve the basic electrical connection specifications and customer wiring requirements. At the same time, during the adjustment process, it is necessary to ensure that the positional relationship between the chips meets the basic electrical connection specifications and customer wiring requirements.

[0052] In an embodiment of the present application, a multi-chip theoretical wiring scheme is divided into multiple single-chip theoretical wiring schemes, and the wiring between chips is divided into an inter-chip connection section, a first chip following section, and an intra-chip connection section according to the single-chip theoretical wiring scheme. During the chip mounting process, the posture of the first chip following section and the intra-chip connection section is adjusted according to the chip movement posture, so that the first actual wiring scheme meets the corresponding wiring specifications and the customer's electrical requirements, thereby ensuring the yield of the multi-chip after packaging and reducing the precision requirements of the placement machine and the cost of the chip packaging process.

[0053] In some examples, based on the above embodiments, FIG3 is a flow chart of a second multi-chip package wiring method provided according to an embodiment of the present application. FIG3 is a flowchart of determining the interference between chips after obtaining the first actual wiring scheme. In combination with FIG2 and FIG3 , the multi-chip package wiring method includes:

[0054] S21. Obtain a multi-chip theoretical wiring solution when multiple chips are connected.

[0055] S22. Divide the multi-chip theoretical wiring scheme into multiple single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme.

[0056] S23. According to the single-chip theoretical wiring scheme, the wiring between two adjacent chips is divided into an inter-chip connection section, a first chip follower section, and an intra-chip connection section; the inter-chip connection section is connected to its adjacent chip, the first chip follower section is connected to the electrode in the chip, and the intra-chip connection section is respectively connected to the inter-chip connection section and the first chip follower section.

[0057] S24 , adjusting the positions of the first chip following sub-unit and the intra-chip connection sub-unit according to the movement posture of the chip to obtain a first actual wiring scheme.

[0058] S25. Determine whether the wiring between two adjacent chips meets a preset interference requirement.

[0059] In some instances, the corresponding wiring specifications specify that chips have corresponding offset ranges. In the embodiments of the present application, after obtaining the first actual wiring scheme, it is necessary to determine whether there is interference between the wiring of two adjacent chips. For example, after moving a chip, it may exceed the chip's offset range, resulting in a small spacing between the chips and causing mutual interference between the chips; or the length, area, size, and routing path of the line connecting the subsection 3 within the chip may exceed the chip's wiring range, causing interference to other chips.

[0060] S26. If not, that is, the wiring between the two adjacent chips does not meet the preset interference requirement, the single-chip theoretical wiring plan is adjusted according to the multi-chip theoretical wiring plan.

[0061] In some examples, when the wiring between two adjacent chips does not meet the preset interference requirement, the single-chip theoretical wiring scheme is adjusted according to the wiring specifications in the multi-chip theoretical wiring scheme.

[0062] In an embodiment of the present application, after obtaining the first actual wiring scheme, it is determined whether there is interference in the wiring between chips, thereby avoiding the situation where, after adjusting the connection division within the chip, the line length, line area, line size and line routing path of the connection division within the chip exceed the chip wiring range, causing interference to other chips; at the same time, it also avoids the situation where the spacing between chips is too small, causing interference between the spacing between chips.

[0063] In some examples, based on the above embodiments, FIG4 is a flow chart of a third multi-chip package wiring method provided according to an embodiment of the present application. The wiring method shown in FIG4 illustrates how to adjust the posture of the first chip following subsection and the connecting subsection according to the movement posture of the chip. In combination with FIG2 and FIG4, the wiring method of the multi-chip package includes:

[0064] S31. Obtain a multi-chip theoretical wiring solution when multiple chips are connected.

[0065] S32. Divide the multi-chip theoretical wiring scheme into multiple single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme.

[0066] S33. According to the single-chip theoretical wiring scheme, the wiring between two adjacent chips is divided into an inter-chip connection section, a first chip follower section, and an intra-chip connection section; the inter-chip connection section is connected to its adjacent chip, the first chip follower section is connected to the electrode in the chip, and the intra-chip connection section 3 is respectively connected to the inter-chip connection section and the first chip follower section.

[0067] S34 , maintaining the shape of the first chip following sub-part unchanged, and adjusting the position of the first chip following sub-part according to the moving posture of the chip.

[0068] In some instances, the unchanged shape of the first chip following section 2 means that the shape of the connection between the wiring segment on the first chip following section 2 and the electrode of the chip remains unchanged. For example, the shape of the first chip following section 2 is V-shaped. After the chip posture changes, the V-shape of the first chip following section 2 does not change, and the connection angle between the first chip following section 2 and the chip and the angle between the first chip following section 2 and the internal connection section 3 of the chip do not change; at the same time, the first chip following section 2 adjusts the corresponding position according to the movement posture of the chip. For example, the chip rotates 5 degrees clockwise with the electrode as the center, then the first chip following section 2 also rotates 5 degrees clockwise with the chip electrode as the center while keeping its own shape unchanged, so that the first chip following section 2 adjusts the corresponding position according to the posture of the chip.

[0069] S35. Maintain the shape and position of the inter-chip connection section unchanged, adjust at least one of the line width of the intra-chip connection section, the extension direction of the intra-chip connection section, the connection angle between the intra-chip connection section and the first chip follower section, and the connection angle between the intra-chip connection section and the inter-chip connection section to ensure that the intra-chip connection section is connected to the first chip follower section and the inter-chip connection section respectively.

[0070] In some instances, maintaining the shape and position of the inter-chip connection section 1 unchanged prevents the inter-chip connection section 1 from changing with the chip's position. By adjusting the line width and extension direction of the intra-chip connection section 3, the connection between the chip and the pin is ensured. At the same time, at least one of the connection angles between the intra-chip connection section 3 and the first chip follower section 2 and the connection angle between the intra-chip connection section 3 and the inter-chip connection section 1 is adjusted to ensure that the connection angles between the intra-chip connection section 3 and the first chip follower section 2, and between the intra-chip connection section 3 and the inter-chip connection section 1, meet the electrical requirements of the multi-chip packaging circuit and do not interfere with other chips.

[0071] In some examples, based on the above embodiments, FIG5 is a flow chart of a fourth multi-chip package wiring method provided according to an embodiment of the present application. The wiring method shown in FIG5 illustrates how to verify whether the adjusted wiring method meets the wiring requirements. In combination with FIG2 and FIG5 , the wiring method of the multi-chip package includes:

[0072] S41. Obtain a multi-chip theoretical wiring solution when multiple chips are connected.

[0073] S42. Divide the multi-chip theoretical wiring scheme into multiple single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme.

[0074] S43. According to the single-chip theoretical wiring scheme, the wiring between two adjacent chips is divided into an inter-chip connection section, a first chip follower section, and an intra-chip connection section; the inter-chip connection section is connected to its adjacent chip, the first chip follower section is connected to the electrode in the chip, and the intra-chip connection section is respectively connected to the inter-chip connection section and the first chip follower section.

[0075] S44 , maintaining the shape of the first chip following sub-part unchanged, and adjusting the position of the first chip following sub-part according to the moving posture of the chip.

[0076] S45. Maintain the shape and position of the inter-chip connection section unchanged, adjust at least one of the line width of the intra-chip connection section, the extension direction of the intra-chip connection section, the connection angle between the intra-chip connection section and the first chip follower section, and the connection angle between the intra-chip connection section and the inter-chip connection section to ensure that the intra-chip connection section is connected to the first chip follower section and the inter-chip connection section respectively.

[0077] S46. Determine whether the line width of the intra-chip connection section meets the minimum line width requirement, whether the distance between the intra-chip connection sections of two adjacent wirings meets the minimum line spacing requirement, whether the connection angle between the intra-chip connection section and the first chip follower section, and whether the connection angle between the intra-chip connection section and the inter-chip connection section meets the corner requirement.

[0078] In some instances, during multi-chip packaging, the connection specifications between each chip and the pins are not identical. The line width can affect the chip's resistivity and impedance; the distance between two adjacent intra-chip connection sections 3 can affect the line area and, consequently, the circuit's electrical properties. Uneven angles between the intra-chip connection section 3 and the first chip follower section 2, and between the intra-chip connection section 3 and the inter-chip connection section 1, can lead to charge accumulation and, consequently, tip discharge. In the chip-to-pin connection requirements, the minimum line width and minimum line spacing of the lines can be quantified. During the movement of the intra-chip connection section 3, the line width of the intra-chip connection section 3 must meet the minimum line width requirement, and the distance between two adjacent intra-chip connection sections 3 must meet the minimum line spacing requirement. Furthermore, to prevent charge accumulation from affecting circuit electrical properties, the angles between the intra-chip connection section 3 and the first chip follower section 2, and between the connection section and the inter-chip connection section 1, must meet corner requirements. This involves rounding corners or adding a fold to prevent charge accumulation at corners.

[0079] S47. If the line width of the intra-chip connection section meets the minimum line width requirement, the distance between the intra-chip connection sections of two adjacent wirings meets the minimum line spacing requirement, the connection angle between the intra-chip connection section and the first chip follower section, and the connection angle between the intra-chip connection section and the inter-chip connection section meet the corner requirement, then retain the division information of the inter-chip connection section, the first chip follower section, and the intra-chip connection section, as well as the line width information of the connection section, the extension direction information of the intra-chip connection section, the connection angle information between the intra-chip connection section and the first chip follower section, and the connection angle information between the intra-chip connection section and the inter-chip connection section.

[0080] In some instances, when the line width of the intra-chip connection section 3 meets the minimum line width requirement, the distance between two adjacent intra-chip connection sections 3 meets the minimum line spacing requirement, the connection angle between the intra-chip connection section 3 and the first chip follower section 2, and the connection angle between the intra-chip connection section 3 and the inter-chip connection section 1 meet the corner requirement, it is determined that the line connection method at this time meets the wiring requirements and the special requirements for the connection between the chip and the pin, and the line connection method at this time is determined to be the first actual wiring scheme.

[0081] In the embodiment of the present application, by determining the line width, line spacing and connection angle of the connection section of each chip, the basic requirements for the connection between the chip and the pin are guaranteed, thereby ensuring the electrical requirements of the circuit, reducing the chip scrap rate, and ensuring the yield of the chip packaging.

[0082] In some examples, based on the above embodiments, FIG6 is a flow chart of a fifth multi-chip package wiring method provided according to an embodiment of the present application. The wiring method shown in FIG6 illustrates how to adjust the wiring scheme when the adjusted wiring scheme does not meet the wiring requirements. In combination with FIG2 and FIG6 , the wiring method of the multi-chip package includes:

[0083] S51. Obtain a multi-chip theoretical wiring solution when multiple chips are connected.

[0084] S52. Divide the multi-chip theoretical wiring scheme into multiple single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme.

[0085] S53. According to the single-chip theoretical wiring scheme, the wiring between two adjacent chips is divided into an inter-chip connection section, a first chip follower section, and an intra-chip connection section; the inter-chip connection section is connected to its adjacent chip, the first chip follower section is connected to the electrode in the chip, and the intra-chip connection section is connected to the inter-chip connection section and the first chip follower section respectively.

[0086] S54 , maintaining the shape of the first chip following sub-part unchanged, and adjusting the position of the first chip following sub-part according to the movement posture of the chip.

[0087] S55. Maintain the shape and position of the inter-chip connection section unchanged, adjust at least one of the line width of the intra-chip connection section, the extension direction of the intra-chip connection section, the connection angle between the intra-chip connection section and the first chip follower section, and the connection angle between the intra-chip connection section and the inter-chip connection section to ensure that the intra-chip connection section is connected to the first chip follower section and the inter-chip connection section respectively.

[0088] S56. Determine whether the line width of the intra-chip connection section meets the minimum line width requirement, whether the distance between the intra-chip connection sections of two adjacent wirings meets the minimum line spacing requirement, whether the connection angle between the intra-chip connection section and the first chip follower section, and whether the connection angle between the intra-chip connection section and the inter-chip connection section meets the corner requirement.

[0089] S57. If the line width of the intra-chip connection division meets the minimum line width requirement, the distance between the intra-chip connection divisions of two adjacent wirings meets the minimum line spacing requirement, the connection angle between the intra-chip connection division and the first chip follower division, and the connection angle between the intra-chip connection division and the inter-chip connection division meet the corner requirement, then retain the division information of the inter-chip connection division, the first chip follower division, and the intra-chip connection division, as well as the line width information of the connection division, the extension direction information of the intra-chip connection division, the connection angle information between the intra-chip connection division and the first chip follower division, and the connection angle information between the intra-chip connection division and the inter-chip connection division.

[0090] S58. If not, that is, the line connection method at this time does not meet at least one of the following conditions: the line width of the intra-chip connection section does not meet the minimum line width requirement, the distance between two adjacent intra-chip connection sections does not meet the minimum line distance requirement, the connection angle between the intra-chip connection section and the first chip follower section, and the connection angle between the intra-chip connection section and the inter-chip connection section do not meet the corner requirement, then adjust the wiring division method according to the single-chip theoretical wiring plan.

[0091] In some instances, in response to determining that the line connection method at this time does not meet at least one of the following conditions: the line width of the intra-chip connection section 3 does not meet the minimum line width requirement, the distance between two adjacent intra-chip connection sections 3 does not meet the minimum line spacing requirement, the connection angle between the intra-chip connection section 3 and the first chip follower section 2, and the connection angle between the intra-chip connection section 3 and the inter-chip connection section 1 do not meet the corner requirement, the division method of the intra-chip connection section 3, the first chip follower section 2 and the inter-chip connection section 1 is adjusted according to the single-chip theoretical wiring scheme, so that the intra-chip connection section 3 meets the corresponding requirements, the fault tolerance of the chip and pin connection is improved, and the electrical requirements of the chip after packaging are guaranteed.

[0092] In some examples, based on the above embodiments, FIG7 is a flow chart of a sixth wiring method for a multi-chip package provided according to an embodiment of the present application, FIG8 is a schematic diagram of a wiring structure of a first multi-chip package provided according to an embodiment of the present application, and FIG9 is a schematic diagram of a wiring structure of a second multi-chip package provided according to an embodiment of the present application. The wiring method shown in FIG7 illustrates how to adjust the wiring scheme when the adjusted wiring method does not meet the wiring requirements. In combination with FIG2 , FIG7 , FIG8 , and FIG9 , there are two adjacent wirings electrically connected to the same chip, including a first wiring 501 and a second wiring 502. The first wiring 501 includes a first intra-chip connection segment 3, and the second wiring 502 includes a second intra-chip connection segment 3. The area of ​​the second intra-chip connection segment 3 is larger than the area of ​​the first intra-chip connection segment 3. The wiring method for the multi-chip package includes:

[0093] S61. Obtain a multi-chip theoretical wiring solution when multiple chips are connected.

[0094] S62. Divide the multi-chip theoretical wiring scheme into multiple single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme.

[0095] S63. According to the single-chip theoretical wiring scheme, the wiring between two adjacent chips is divided into an inter-chip connection section, a first chip follower section, and an intra-chip connection section; the inter-chip connection section is connected to its adjacent chip, the first chip follower section is connected to the electrode in the chip, and the intra-chip connection section is respectively connected to the inter-chip connection section and the first chip follower section.

[0096] S64 , maintaining the shape of the first chip following sub-part unchanged, and adjusting the position of the first chip following sub-part according to the moving posture of the chip.

[0097] S65. Maintain the shape and position of the inter-chip connection section unchanged, adjust at least one of the line width of the intra-chip connection section, the extension direction of the intra-chip connection section, the connection angle between the intra-chip connection section and the first chip follower section, and the connection angle between the intra-chip connection section and the inter-chip connection section to ensure that the intra-chip connection section is connected to the first chip follower section and the inter-chip connection section respectively.

[0098] S66. Determine whether the line width of the intra-chip connection section meets the minimum line width requirement, whether the distance between the intra-chip connection sections of two adjacent wirings meets the minimum line spacing requirement, whether the connection angle between the intra-chip connection section and the first chip follower section, and whether the connection angle between the intra-chip connection section and the inter-chip connection section meets the corner requirement.

[0099] S67. If the line width of the intra-chip connection section meets the minimum line width requirement, the distance between the intra-chip connection sections of two adjacent wirings meets the minimum line spacing requirement, the connection angle between the intra-chip connection section and the first chip follower section, and the connection angle between the intra-chip connection section and the inter-chip connection section meet the corner requirement, then retain the division information of the inter-chip connection section, the first chip follower section, and the intra-chip connection section, as well as the line width information of the connection section, the extension direction information of the intra-chip connection section, the connection angle information between the intra-chip connection section and the first chip follower section, and the connection angle information between the intra-chip connection section and the inter-chip connection section.

[0100] S68. When the line width of the first intra-chip connection sub-section cannot meet the minimum line width requirement, reduce the line width of the second intra-chip connection sub-section to increase the line width of the first intra-chip connection sub-section to ensure that the line width of the first intra-chip connection sub-section meets the minimum line width requirement; and / or

[0101] When the distance between the first intra-chip connection section and the second intra-chip connection section cannot meet the minimum line spacing requirement, the line width of the second intra-chip connection section is reduced to increase the distance between the first intra-chip connection section and the second intra-chip connection section to ensure that the distance between the first intra-chip connection section and the second intra-chip connection section meets the minimum line spacing requirement.

[0102] In some examples, as shown in conjunction with Figures 7, 8, and 9, line width affects the area of ​​the intra-chip connection segment 3 and the spacing between intra-chip connection segments 3. During the chip packaging process, multiple wiring lines are present, wherein a first wiring line 501 and a second wiring line 502 are adjacent wiring lines. Adjustment of the intra-chip connection segment 3 of the first wiring line 501 will affect the line width of the second wiring line 502, and adjustment of the connection segment of the second wiring line 502 will affect the line width of the first wiring line 501. Therefore, when adjusting the wiring lines, the line widths of all wiring lines must be met. Specifically, the line widths of the wiring lines must be adjusted using the area of ​​the intra-chip connection segment 3 so that all wiring lines meet the corresponding line width requirements.

[0103] When the area of ​​the second intra-chip connection section 3 is larger than that of the first intra-chip connection section, the area of ​​the second intra-chip connection section 3 can be reduced. After the area of ​​the second intra-chip connection section 3 is reduced, the spacing between the first intra-chip connection section 3 and the second intra-chip connection section 3 is increased, so that the first intra-chip connection section 3 has enough space to meet the minimum line requirement; and / or, when the distance between the first intra-chip connection section 3 and the second intra-chip connection section 3 does not meet the minimum line spacing requirement, since the adjustment range of the second intra-chip connection section 3 with a larger area is wider, the line width of the second intra-chip connection section 3 is reduced, so that the spacing between the second intra-chip connection section 3 and the first intra-chip connection section 3 is increased to meet the minimum line spacing requirement.

[0104] In the process of adjusting the connection divisions within a single chip, in order to ensure the line width and line spacing requirements, the embodiment of the present application utilizes the area relationship between two adjacent connection divisions to adjust the area of ​​the connection divisions and increase the spacing between the connection divisions. While ensuring that the total area requirements of each line are met, the lines all meet the corresponding line width and line spacing requirements, thereby ensuring the electrical properties of the chip package.

[0105] In some examples, based on the above embodiments, FIG10 is a flow chart of a seventh multi-chip package wiring method provided according to an embodiment of the present application. The wiring method shown in FIG10 illustrates how to divide the external connection section, the first chip follower section, and the connection section according to the single-chip theoretical wiring scheme. In conjunction with FIG2 and FIG10 , the wiring method of the multi-chip package includes:

[0106] S71. Obtain a multi-chip theoretical wiring solution when multiple chips are connected.

[0107] S72. Divide the multi-chip theoretical wiring scheme into multiple single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme.

[0108] S73. Determine the extension direction of the wiring and the distance between two adjacent wirings according to a single-chip theoretical wiring scheme.

[0109] In some instances, the extension direction of the wiring may be the routing path of the circuit. Based on the extension direction in the theoretical wiring scheme of a single chip and the spacing between two adjacent wirings, the chip circuit may be divided from the inside to the outside, and the required minimum line width, minimum line spacing and other extreme offset values ​​may be achieved.

[0110] S74. Divide the areas with the same extension direction and larger spacing between two adjacent wirings according to the extension direction of the wiring and the spacing between the two adjacent wirings as intra-chip connection divisions, select the areas connected to the intra-chip connection divisions and used to connect with other chips as inter-chip connection divisions, and select the areas connected to the intra-chip connection divisions and used to connect with the electrodes of the chip as the first chip follower divisions.

[0111] In some instances, regions of two adjacent wirings extending in the same direction and having a large spacing therebetween are used as intra-chip connection sections 3, so that the intra-chip connection sections 3 of mutually parallel lines can be adjusted simultaneously while maintaining the relative positional relationship unchanged, thereby avoiding intersections between the lines that affect the normal operation of the lines and ensuring the consistency of the routing directions.

[0112] S75 , adjusting the positions of the first chip following sub-unit and the intra-chip connection sub-unit according to the movement posture of the chip to obtain a first actual wiring scheme.

[0113] In some examples, based on the above embodiments, FIG11 is a flow chart of an eighth multi-chip package wiring method provided according to an embodiment of the present application. The wiring method shown in FIG11 illustrates how to determine a theoretical multi-chip wiring scheme. In conjunction with FIG2 and FIG11 , the wiring method of the multi-chip package includes:

[0114] S81, obtaining the preset positions of multiple chips and the arrangement of electrodes in each chip.

[0115] In some instances, the preset position of the chip may be a chip mounting position preset before the chip is mounted on the substrate. In a multi-chip packaging process, each chip has a corresponding preset position, and the arrangement of electrodes in each chip is obtained according to the preset position.

[0116] S82. Determine a multi-chip theoretical wiring scheme based on the preset positions of the multiple chips and the arrangement of the electrodes in each chip.

[0117] In some instances, the relative position relationship between the electrodes and the pins in the chip can be determined based on the preset positions of the multiple chips and the arrangement of the electrodes in each chip. The electrodes and pins in the chip are preset connected according to the circuit connection specifications of the multi-chip package and the customer's electrical requirements. The preset positions of the chips, the arrangement of the electrodes in the chip and the preset connection paths together constitute the theoretical wiring scheme of the multi-chip.

[0118] S83. Divide the multi-chip theoretical wiring scheme into multiple single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme.

[0119] S84. According to the single-chip theoretical wiring scheme, the wiring between two adjacent chips is divided into an inter-chip connection section, a first chip follower section, and an intra-chip connection section; the inter-chip connection section is connected to its adjacent chip, the first chip follower section is connected to the electrode in the chip, and the intra-chip connection section is respectively connected to the inter-chip connection section and the first chip follower section.

[0120] S85 , adjusting the positions of the first chip following sub-unit and the intra-chip connection sub-unit according to the movement posture of the chip to obtain a first actual wiring scheme.

[0121] This application divides the multi-chip theoretical wiring scheme into multiple single-chip theoretical wiring schemes, and divides the wiring between chips into inter-chip connection divisions, first chip following divisions and intra-chip connection divisions according to the single-chip theoretical wiring schemes. During the chip mounting process, the positions of the first chip following divisions and the intra-chip connection divisions are adjusted according to the chip movement posture, so that the first actual wiring scheme meets the corresponding wiring specifications and the customer's electrical requirements, ensures the yield after multi-chip packaging, and reduces the precision requirements for the placement machine and the cost in the chip packaging process.

[0122] The above embodiment illustrates the wiring method for multi-chip theoretical wiring between chips when multiple chips are connected to each other. It is understood that in addition to the wiring between chips, the chips also need to be wired and connected to external pins. The wiring method between the chips and external pins is described below.

[0123] In some examples, based on the above embodiments, FIG12 is a flow chart of a ninth wiring method for a multi-chip package according to an embodiment of the present application, and FIG13 is a structural diagram of wiring division for connecting chips to external pins according to an embodiment of the present application. In combination with FIG12 and FIG13 , the wiring method further includes:

[0124] S90. Obtain a theoretical external connection wiring scheme when the chip is connected to external pins.

[0125] In some instances, chip packaging is the process of connecting the electrodes in the chip to the pins in the external circuit. The external connection theoretical wiring scheme can be the theoretical connection path between the chip and the external pins, determined based on the distribution position of the electrodes in the chip, the pre-attachment position of the chip, and the distribution position of the external pins before the chip is connected to the external pins. The connection path includes parameters such as line length, line size, line area, and line routing path. The wiring here can also be called rewiring or rewiring. The external connection theoretical wiring scheme must meet the basic electrical connection specifications and customer wiring requirements for the connection between the chip and the external pins.

[0126] S91. Divide the wiring into an external connection section, a second chip follower section and a connection section according to the external connection theory wiring scheme; the external connection section is connected to the external pin, the second chip follower section is connected to the electrode in the chip, and the connection section is connected to the external connection section and the second chip follower section respectively.

[0127] In some examples, as shown in FIG12 , the external connection segment 4, the second chip follower segment 5, and the connection segment 6 are represented by lines of different thicknesses. These segments collectively connect the chip to external pins, dividing the wiring in the theoretical external connection wiring scheme into three parts: the external connection segment 4, the second chip follower segment 5, and the connection segment 6. During the division process, the cutout locations of the external connection segment 4, the second chip follower segment 5, and the connection segment 6 can be changed based on wiring adjustment requirements.

[0128] For example, in combination with the extension direction of the line and the correlation between the lines, and taking into account the extreme offset value required by the customer, the external connection section 4, the second chip follower section 5 and the connection section 6 can be divided from the inside to the outside of the chip. For adjacent lines on the same side, parallel lines can be intercepted as the connection section 6. When the customer explicitly requires the size of the extreme offset value, the line lengths of the external connection section 4, the second chip follower section 5 and the connection section 6 need to be adjusted to be greater than the size of the extreme offset value. Intercepting parallel lines as the connection section 6 can ensure that the connection sections 6 do not intersect when moving simultaneously, and the routing direction of the connection section 6 can remain consistent, which facilitates the subsequent adjustment of the second chip follower section 5 and the connection section 6 to obtain a second actual wiring solution.

[0129] The external connection division 4 is fixedly connected to the external pins, and the external connection division 4 cannot be moved after packaging; the second chip follower division 5 is fixedly connected to the electrodes in the chip, and the second chip follower division 5 can move with the movement of the chip after the chip is packaged. During the chip mounting process, temperature changes will cause the actual mounting position of the chip to shift and rotate. At the same time, the second chip follower division 5 will change with the change of the chip position, but since the second chip follower division 5 is fixedly connected to the chip, the relative position of the chip electrode and the second chip follower division 5 will not change; the connection division 6 is respectively connected to the external connection division 4 and the second chip follower division 5. After packaging, the connection division 6 can move freely while keeping the connection relationship unchanged to adjust the wiring scheme.

[0130] S92. Adjust the posture of the second chip following sub-part and the connecting sub-part according to the movement posture of the chip to obtain a second actual wiring plan.

[0131] In some instances, the chip's movement can occur during the chip mounting process, where the actual placement position of the chip shifts and rotates due to temperature changes, causing the chip's wiring to deviate from the theoretical wiring scheme. As the chip's position changes, the position of the second chip follower segment 5, connected to the chip's electrodes, also changes. By adjusting the position of the connecting segment 6, the post-package wiring scheme meets the basic specifications for connecting the chip to external pins and the special requirements of chip packaging, thereby forming a second actual wiring scheme.

[0132] In the embodiments of the present application, the wiring in the theoretical external connection wiring scheme is divided into an external connection section, a second chip follower section, and a connection section. After the chip is packaged, the positions of the second chip follower section and the connection section are adjusted according to the position changes of the chip after packaging, so that the wiring scheme meets the corresponding wiring specifications and the corresponding electrical requirements of the customer. At the same time, adjusting the wiring after chip packaging ensures the chip packaging yield, reduces the precision requirements of the placement machine, and reduces the cost of the chip packaging process.

[0133] In some examples, based on the above embodiments, FIG14 is a flow chart of a tenth wiring method for a multi-chip package provided according to an embodiment of the present application. The wiring method shown in FIG14 illustrates how to adjust the posture of the second chip following subsection and the connecting subsection according to the movement posture of the chip. In combination with FIG13 and FIG14 , the wiring method includes:

[0134] S110 , obtaining a theoretical external connection wiring scheme when the chip is connected to external pins.

[0135] S111. Divide the wiring into an external connection section, a second chip follower section and a connection section according to the external connection theory wiring scheme; the external connection section is connected to the external pin, the second chip follower section is connected to the electrode in the chip, and the connection section is connected to the external connection section and the second chip follower section respectively.

[0136] S112: Maintain the shape of the second chip following sub-part unchanged, and adjust the position of the second chip following sub-part according to the movement posture of the chip.

[0137] In some instances, the unchanged shape of the second chip following section 5 means that the shape of the connection between the wiring segment on the second chip following section 5 and the electrode of the chip remains unchanged. For example, the shape of the second chip following section 5 is V-shaped. After the chip posture changes, the V-shape of the second chip following section 5 does not change, and the connection angle between the second chip following section 5 and the chip and the angle between the second chip following section 5 and the connection section do not change; at the same time, the second chip following section 5 adjusts the corresponding position according to the movement posture of the chip. For example, the chip rotates 5 degrees clockwise with the electrode as the center, and the second chip following section 5 also rotates 5 degrees clockwise with the chip electrode as the center while keeping its own shape unchanged, so that the second chip following section 5 adjusts the corresponding position according to the posture of the chip.

[0138] S113. Maintain the shape and position of the external connection branch unchanged, adjust at least one of the line width of the connection branch, the extension direction of the connection branch, the connection angle between the connection branch and the second chip follower branch, and the connection angle between the connection branch and the external connection branch to ensure that the connection branch is connected to the second chip follower branch and the external connection branch respectively.

[0139] In some instances, the shape and position of the external connection section 4 are maintained, that is, the fixed connection between the external connection section 4 and the pin is maintained, and only the line width, extension direction, connection angle between the connection section 6 and the second chip follower section 5 and the connection angle between the connection section 6 and the external connection section 4 are adjusted to ensure the connection between the chip and the pin. Among them, since the electrical signal requirements for the circuits in each chip are different, special requirements are required for the line width and extension direction of the chip circuits. The embodiment of the present application maintains the shape of the second chip follower section 5 unchanged, so that the second chip follower section 5 changes according to the change of the chip posture, and at the same time adjusts the connection section 6, while ensuring the connection relationship between the connection section 6 and the second chip follower section 5 and the external connection, so that the connection section 6 has the line width, extension direction and connection angle corresponding to the load requirements, thereby ensuring the wiring requirements and electrical requirements of each circuit.

[0140] In some examples, based on the above embodiments, FIG15 is a flow chart of an eleventh multi-chip package wiring method provided according to an embodiment of the present application. The wiring method shown in FIG15 illustrates how to verify whether the adjusted wiring method meets the wiring requirements. In combination with FIG13 and FIG15 , the wiring method includes:

[0141] S120: Obtain a theoretical external connection wiring scheme when the chip is connected to external pins.

[0142] S121. Divide the wiring into an external connection section, a second chip follower section and a connection section according to the external connection theory wiring scheme; the external connection section is connected to the external pin, the second chip follower section is connected to the electrode in the chip, and the connection section is connected to the external connection section and the second chip follower section respectively.

[0143] S122 , adjusting the postures of the second chip following sub-part and the connecting sub-part according to the movement posture of the chip to obtain a second actual wiring plan.

[0144] S123. Determine whether the line width of the connection section meets the minimum line width requirement, whether the distance between two adjacent connection sections meets the minimum line spacing requirement, whether the connection angle between the connection section and the second chip follower section, and whether the connection angle between the connection section and the external connection section meets the corner requirement.

[0145] In some instances, the line width can affect the resistivity and impedance of the chip; the distance between two adjacent connection sections 6 can affect the area of ​​the line and thus the electrical properties of the line; and uneven connection angles between the connection section 6 and the second chip follower section 5, and between the connection section 6 and the external connection section 4, may lead to charge accumulation and thus problems such as tip discharge. In the chip-to-pin connection requirements, the minimum line width and minimum line spacing of the line can be quantified. During the movement of the connection section 6, the line width of the connection section 6 must meet the minimum line width requirement, and the distance between two adjacent connection sections 6 must meet the minimum line spacing requirement. At the same time, to prevent charge accumulation from affecting the electrical properties of the line, the connection angles between the connection section 6 and the second chip follower section 5, and between the connection section 6 and the external connection section 4, must meet the corner requirements. This means that the corners are rounded or angled to prevent charge accumulation at the corners.

[0146] S124. If the line width of the connection division meets the minimum line width requirement, the distance between two adjacent connection divisions meets the minimum line spacing requirement, the connection angle between the connection division and the second chip follower division, and the connection angle between the connection division and the external connection division meet the corner requirement, then retain the division information of the external connection division, the second chip follower division, and the connection division, as well as the line width information of the connection division, the extension direction information of the connection division, the connection angle information between the connection division and the second chip follower division, and the connection angle information between the connection division and the external connection division.

[0147] In some instances, when the line width of the connection section 6 meets the minimum line width requirement, the distance between two adjacent connection sections 6 meets the minimum line spacing requirement, the connection angle between the connection section 6 and the second chip follower section 5, and the connection angle between the connection section 6 and the external connection section 4 meet the corner requirement, it is determined that the line connection method at this time meets the wiring requirements and the special requirements for the connection between the chip and the pin, and the line connection method at this time is defined as the second actual wiring scheme.

[0148] In the embodiment of the present application, by determining the line width, line spacing and connection angle of the connection section, the basic requirements for the connection between the chip and the pin are guaranteed, thereby ensuring the electrical requirements of the circuit, reducing the chip scrap rate, and ensuring the yield of the chip packaging.

[0149] In some examples, based on the above embodiments, FIG16 is a flow chart of a twelfth multi-chip package wiring method provided according to an embodiment of the present application. The wiring method shown in FIG16 illustrates how to adjust the wiring scheme when the adjusted wiring method does not meet the wiring requirements. In conjunction with FIG13 and FIG16 , the wiring method includes:

[0150] S130: Obtain a theoretical external connection wiring scheme when the chip is connected to external pins.

[0151] S131. Divide the wiring into an external connection section, a second chip follower section and a connection section according to the external connection theory wiring scheme; the external connection section is connected to the external pin, the second chip follower section is connected to the electrode in the chip, and the connection section is connected to the external connection section and the second chip follower section respectively.

[0152] S132: Adjust the posture of the second chip following sub-part and the connecting sub-part according to the movement posture of the chip to obtain a second actual wiring plan.

[0153] S133. Determine whether the line width of the connection section meets the minimum line width requirement, whether the distance between two adjacent connection sections meets the minimum line spacing requirement, whether the connection angle between the connection section and the second chip follower section, and whether the connection angle between the connection section and the external connection section meets the corner requirement.

[0154] S134. If the line width of the connection division meets the minimum line width requirement, the distance between two adjacent connection divisions meets the minimum line spacing requirement, the connection angle between the connection division and the second chip follower division, and the connection angle between the connection division and the external connection division meet the corner requirement, then retain the division information of the external connection division, the second chip follower division, and the connection division, as well as the line width information of the connection division, the extension direction information of the connection division, the connection angle information between the connection division and the second chip follower division, and the connection angle information between the connection division and the external connection division.

[0155] S135. If not, that is, the line connection method at this time does not meet at least one of the following conditions: the line width of the connection section does not meet the minimum line width requirement, the distance between two adjacent connection sections does not meet the minimum line distance requirement, the connection angle between the connection section and the second chip follower section, and the connection angle between the connection section and the external connection section do not meet the corner requirement, then adjust the wiring division method according to the external connection theoretical wiring plan.

[0156] In some instances, in response to determining that the line connection method at this time does not meet at least one of the following conditions: the line width of the connection division 6 does not meet the minimum line width requirement, the distance between two adjacent connection divisions 6 does not meet the minimum line spacing requirement, the connection angle between the connection division 6 and the second chip follower division 5, and the connection angle between the connection division 6 and the external connection division 4 do not meet the corner requirement, the division method of the external connection division 4, the second chip follower division 5 and the connection division 6 can be adjusted according to the external connection theoretical wiring scheme, so that the connection division 6 meets the corresponding requirements, improves the fault tolerance of the chip and pin connection, and ensures the electrical requirements of the chip after packaging.

[0157] In some examples, based on the above embodiments, there are two adjacent wirings including a first wiring and a second wiring, the first wiring including a first connection segment, the second wiring including a second connection segment, and the area of ​​the second connection segment is larger than the area of ​​the first connection segment; FIG17 is a flowchart of a thirteenth wiring method for a multi-chip package provided according to an embodiment of the present application. The wiring method shown in FIG17 illustrates how to adjust the wiring scheme when the adjusted wiring scheme does not meet the wiring requirements. In combination with FIG13 and FIG17, the wiring method includes:

[0158] S140: Obtain a theoretical external connection wiring scheme when the chip is connected to external pins.

[0159] S141. Divide the wiring into an external connection section, a second chip follower section and a connection section according to the external connection theory wiring scheme; the external connection section is connected to the external pin, the second chip follower section is connected to the electrode in the chip, and the connection section is connected to the external connection section and the second chip follower section respectively.

[0160] S142 , adjusting the postures of the second chip following sub-part and the connecting sub-part according to the movement posture of the chip to obtain a second actual wiring plan.

[0161] S143. Determine whether the line width of the connection section meets the minimum line width requirement, whether the distance between two adjacent connection sections meets the minimum line spacing requirement, whether the connection angle between the connection section and the second chip follower section, and whether the connection angle between the connection section and the external connection section meets the corner requirement.

[0162] S144. If the line width of the connection division meets the minimum line width requirement, the distance between two adjacent connection divisions meets the minimum line spacing requirement, the connection angle between the connection division and the second chip follower division, and the connection angle between the connection division and the external connection division meet the corner requirement, then retain the division information of the external connection division, the second chip follower division, and the connection division, as well as the line width information of the connection division, the extension direction information of the connection division, the connection angle information between the connection division and the second chip follower division, and the connection angle information between the connection division and the external connection division.

[0163] S145. When the line width of the first connection segment is less than the minimum line width requirement, reduce the line width of the second connection segment to increase the line width of the first connection segment to ensure that the line width of the first connection segment meets the minimum line width requirement; and / or

[0164] When the distance between the first connection section and the second connection section is less than the minimum line distance requirement, the line width of the second connection section is reduced to increase the distance between the first connection section and the second connection section to ensure that the distance between the first connection section and the second connection section meets the minimum line distance requirement.

[0165] In some examples, FIG18 is a schematic diagram of the wiring structure of a third multi-chip package provided according to an embodiment of the present application, and FIG19 is a schematic diagram of the wiring structure of a fourth multi-chip package provided according to an embodiment of the present application. As shown in FIG17 , FIG18 , and FIG19 , line width affects the area of ​​the connection segment 6 and the spacing between the connection segments 6. During the chip packaging process, multiple wiring lines are present, wherein the third wiring line 503 and the fourth wiring line 504 are adjacent wiring lines. Adjustment of the connection segment 6 of the third wiring line 503 will affect the line width of the fourth wiring line 504, and adjustment of the connection segment 6 of the fourth wiring line 504 will affect the line width of the third wiring line 503. Therefore, when adjusting the wiring lines, the line widths of all wiring lines must be met. That is, the line widths of the wiring lines must be adjusted based on the area of ​​the connection segment 6 so that all wiring lines meet the corresponding line width requirements.

[0166] When the area of ​​the second connection section is larger than that of the first connection section, the area of ​​the second connection section can be reduced. After the area of ​​the second connection section is reduced, the spacing between the first connection section and the second connection section is increased, so that the first connection section has enough space to meet the minimum line requirement; and / or, when the distance between the first connection section and the second connection section does not meet the minimum line spacing requirement, since the adjustment range of the second connection section with a larger area is wider, the line width of the second connection section is reduced, so that the spacing between the second connection section and the first connection section is increased to meet the minimum line spacing requirement.

[0167] In the process of adjusting a single connection section in the embodiment of the present application, in order to ensure the line width and line spacing requirements, the area relationship between two adjacent connection sections is utilized to adjust the area of ​​the connection section and increase the spacing between the connection sections. While ensuring that the total area requirements of each line are met, the lines all meet the corresponding line width and line spacing requirements, thereby ensuring the electrical properties of the chip package.

[0168] In some examples, based on the above embodiments, FIG20 is a flow chart of a fourteenth multi-chip package wiring method provided according to an embodiment of the present application. The wiring method shown in FIG20 illustrates how to divide the external connection section, the second chip follower section, and the connection section according to the external connection theory wiring scheme. In conjunction with FIG13 and FIG20 , the wiring method includes:

[0169] S150: Obtain a theoretical external connection wiring scheme when the chip is connected to external pins.

[0170] S151. Determine the extension direction of the wiring and the distance between two adjacent wirings according to the external connection theory wiring scheme.

[0171] In some instances, the extension direction of the wiring may be the routing path of the circuit. Based on the extension direction in the external connection theory wiring scheme and the spacing between two adjacent wirings, the chip circuit may be divided from the inside to the outside, and the required minimum line width, minimum line spacing and other extreme offset values ​​may be achieved.

[0172] S152. According to the extension direction of the wiring and the spacing between two adjacent wirings, the areas with the same extension direction and a larger spacing between two adjacent wirings are divided as connection divisions, the areas connected to the connection divisions and to external pins are divided as external connection divisions, and the areas connected to the connection divisions and to the electrodes of the chip are divided as second chip follower divisions.

[0173] In some instances, the areas of two adjacent wirings with the same extension direction and a large spacing are used as connection sections 6, so that the connection sections 6 of the parallel lines can be adjusted at the same time while keeping the relative position relationship unchanged, avoiding intersection between the lines, affecting the normal operation of the lines, and ensuring the consistency of the routing direction.

[0174] S153 , adjusting the postures of the second chip following sub-part and the connecting sub-part according to the movement posture of the chip to obtain a second actual wiring plan.

[0175] In some examples, based on the above embodiments, FIG21 is a flow chart of a fifteenth multi-chip package wiring method provided according to an embodiment of the present application. The wiring method shown in FIG21 illustrates how to determine a theoretical wiring scheme for external connections. In combination with FIG13 and FIG21 , the wiring method includes:

[0176] S160: Obtain the preset position of the chip, the arrangement of the electrodes in the chip, and the setting positions of the external pins.

[0177] In some examples, the predetermined position of the chip may be the relative position of the chip and the pins when connected before packaging. Determining the predetermined position of the chip, the arrangement of the electrodes in the chip, and the location of the external pins facilitates connecting the chip electrodes to the external pins.

[0178] S161. Determine a theoretical wiring scheme for external connections based on the preset position of the chip, the arrangement of electrodes in the chip, and the setting positions of external pins.

[0179] In some instances, when determining the external connection theoretical wiring plan, the minimum line width, minimum line spacing and other extreme offset values ​​of the line should also be considered to facilitate subsequent adjustment of the line according to the external connection theoretical wiring plan to obtain a second actual wiring plan.

[0180] S162. Divide the wiring into an external connection section, a second chip follower section and a connection section according to the external connection theory wiring scheme; the external connection section is connected to the external pin, the second chip follower section is connected to the electrode in the chip, and the connection section is connected to the external connection section and the second chip follower section respectively.

[0181] S163 , adjusting the postures of the second chip following sub-part and the connecting sub-part according to the movement posture of the chip to obtain a second actual wiring plan.

[0182] This application divides the wiring in the external connection theoretical wiring scheme into an external connection section, a second chip follower section, and a connection section. After the chip is packaged, the position of the second chip follower section and the connection section is adjusted according to the chip's post-package position change, ensuring that the wiring scheme meets the corresponding wiring specifications and the customer's corresponding electrical requirements. At the same time, adjusting the wiring after chip packaging ensures the chip packaging yield, reduces the precision requirements of the placement machine, and reduces the cost of the chip packaging process.

[0183] The present application also provides a wiring device for a multi-chip package. FIG22 is a schematic structural diagram of a wiring device for a multi-chip package according to an embodiment of the present application. As shown in FIG22 , the wiring device includes:

[0184] The multi-chip theoretical wiring acquisition module 100 is configured to acquire a multi-chip theoretical wiring solution when multiple chips are connected.

[0185] The multi-chip theoretical wiring division module 200 is configured to divide the multi-chip theoretical wiring scheme into multiple single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme; divide the wiring between two adjacent chips into an inter-chip connection division, a first chip follower division and an intra-chip connection division according to the single-chip theoretical wiring scheme; the inter-chip connection division is connected to the chip adjacent to it, the first chip follower division is connected to the electrode in the chip, and the intra-chip connection division is respectively connected to the inter-chip connection division and the first chip follower division.

[0186] The multi-chip actual wiring determination module 300 is configured to adjust the posture of the first chip following sub-section and the intra-chip connection sub-section according to the movement posture of the chip to obtain a first actual wiring plan.

[0187] Since the wiring device for multi-chip package is used to execute the wiring method for multi-chip package, the wiring device for multi-chip package also has the beneficial effects of the wiring method for multi-chip package in the above embodiment.

[0188] An embodiment of the present application also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a wiring method for a multi-chip package when executing the program.

[0189] In some examples, the number of processors in a computer device may be one or more; the memory, processor, and computer programs stored in the memory and executable on the processor in the computer device may be connected via a bus or other means.

[0190] Memory, as a computer-readable storage medium, can be used to store software programs, computer executable programs, and modules, such as the wiring method for a multi-chip package in the embodiments of the present application. The processor executes the computer program stored in the memory to perform various functional applications and data processing of the computer device, namely, the wiring method for a multi-chip package.

[0191] The memory may primarily include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal, etc. Furthermore, the memory may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state memory device. In some instances, the memory may include memory remotely located relative to the processor, and such remote memory may be connected to the computer device via a network. Examples of such networks include the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0192] An embodiment of the present application may also provide a computer-readable storage medium having a computer program stored thereon, which implements a wiring method for a multi-chip package when the computer program is executed by a processor.

[0193] An embodiment of the present application provides a computer-readable storage medium, whose computer-executable instructions are not limited to the method operations described above, and can also execute related operations in the wiring method of the multi-chip package provided by any embodiment of the present application.

[0194] The various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the multiple steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of this application can be achieved.

Claims

1. A wiring method for a multi-chip package, comprising: Get the multi-chip theoretical wiring scheme when multiple chips are connected; Dividing the multi-chip theoretical wiring scheme into a plurality of single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme; According to the single-chip theoretical wiring scheme, the wiring between two adjacent chips is divided into an inter-chip connection section, a first chip follower section, and an intra-chip connection section; the inter-chip connection section is connected to the adjacent chip, the first chip follower section is connected to the electrode in the chip, and the intra-chip connection section is connected to the inter-chip connection section and the first chip follower section respectively; The positions of the first chip following section and the intra-chip connecting section are adjusted according to the moving posture of the chip to obtain a first actual wiring scheme.

2. The wiring method according to claim 1, after adjusting the positions of the first chip following sub-section and the intra-chip connecting sub-section according to the moving posture of the chip to obtain a first actual wiring scheme, the method further comprises: Determining whether the wiring between two adjacent chips meets a preset interference requirement; In response to the wiring between two adjacent chips not meeting the preset interference requirement, the single-chip theoretical wiring scheme is adjusted according to the multi-chip theoretical wiring scheme.

3. The wiring method according to claim 1, wherein: The step of adjusting the positions of the first chip following sub-section and the intra-chip connecting sub-section according to the moving posture of the chip to obtain a first actual wiring scheme includes: Maintaining the shape of the first chip following sub-section unchanged, and adjusting the position of the first chip following sub-section according to the moving posture of the chip; Maintaining the shape and position of the inter-chip connection section unchanged, adjusting at least one of the line width of the intra-chip connection section, the extension direction of the intra-chip connection section, the connection angle between the intra-chip connection section and the first chip follower section, and the connection angle between the intra-chip connection section and the inter-chip connection section, to ensure that the intra-chip connection section is respectively connected to the first chip follower section and the inter-chip connection section.

4. The wiring method according to claim 3, after adjusting the positions of the first chip following sub-section and the intra-chip connecting sub-section according to the moving posture of the chip to obtain a first actual wiring scheme, the method further comprises: Determine whether the line width of the chip connection sub-section meets the minimum line width requirement, whether the distance between two adjacent chip connection sub-sections of the wiring meets the minimum line distance requirement, the connection angle between the chip connection sub-section and the first chip follower sub-section, and the connection angle between the chip connection sub-section and the chip Whether the connection angles between the connecting sections meet the corner requirements; In response to the line width of the intra-chip connection section satisfying the minimum line width requirement, the distance between two adjacent intra-chip connection sections of the wiring satisfying the minimum line spacing requirement, the connection angle between the intra-chip connection section and the first chip follower section, and the connection angle between the intra-chip connection section and the inter-chip connection section satisfying the corner requirement, the division information of the inter-chip connection section, the first chip follower section, and the intra-chip connection section, as well as the line width information of the connection section, the extension direction information of the intra-chip connection section, the connection angle information between the intra-chip connection section and the first chip follower section, and the connection angle information between the intra-chip connection section and the inter-chip connection section are retained.

5. The wiring method according to claim 4, after judging whether the line width of the intra-chip connection section meets the minimum line width requirement, whether the distance between two adjacent intra-chip connection sections of the wiring meets the minimum line distance requirement, whether the connection angle between the intra-chip connection section and the first chip follower section and the connection angle between the intra-chip connection section and the inter-chip connection section meets the corner requirement, the method further comprises: In response to determining that at least one of the following conditions is not met: the line width of the intra-chip connection section does not meet the minimum line width requirement, the distance between two adjacent intra-chip connection sections of the wiring does not meet the minimum line distance requirement, the connection angle between the intra-chip connection section and the first chip follower section and the connection angle between the intra-chip connection section and the inter-chip connection section do not meet the corner requirement, the wiring division method is adjusted according to the single-chip theoretical wiring scheme.

6. The wiring method according to claim 4, wherein: There are two adjacent wirings electrically connected to the same chip, including a first wiring and a second wiring, the first wiring includes a first intra-chip connection sub-portion, the second wiring includes a second intra-chip connection sub-portion, and the area of ​​the second intra-chip connection sub-portion is larger than the area of ​​the first intra-chip connection sub-portion; After determining whether the line width of the intra-chip connection sub-section meets the minimum line width requirement, whether the distance between two adjacent intra-chip connection sub-sections of the wiring meets the minimum line distance requirement, whether the connection angle between the intra-chip connection sub-section and the first chip follower sub-section and the connection angle between the intra-chip connection sub-section and the inter-chip connection sub-section meets the corner requirement, the method further includes at least one of the following: In response to the line width of the first intra-chip connection subdivision failing to meet the minimum line width requirement, reducing the line width of the second intra-chip connection subdivision to increase the line width of the first intra-chip connection subdivision to ensure that the line width of the first intra-chip connection subdivision meets the minimum line width requirement; In response to the fact that the distance between the first intra-chip connection subdivision and the second intra-chip connection subdivision cannot meet the minimum line spacing requirement, the line width of the second intra-chip connection subdivision is reduced to increase the distance between the first intra-chip connection subdivision and the second intra-chip connection subdivision to ensure that the first intra-chip connection subdivision is The distance between the connecting section and the second intra-chip connecting section meets the minimum line spacing requirement.

7. The wiring method according to claim 1, wherein: The method of dividing the wiring between two adjacent chips into an inter-chip connection section, a first chip follower section and an intra-chip connection section according to the single-chip theoretical wiring scheme includes: Determine the extension direction of the wiring and the distance between two adjacent wirings according to the single-chip theoretical wiring scheme; According to the extension direction of the wiring and the spacing between two adjacent wirings, the areas with the same extension direction and a larger spacing between the two adjacent wirings are divided as the intra-chip connection section, and the area connected to the intra-chip connection section and used to connect to other chips is selected as the inter-chip connection section, and the area connected to the intra-chip connection section and used to connect to the electrode of the chip is selected as the first chip follower section.

8. The wiring method according to claim 1, wherein: The method of obtaining a multi-chip theoretical wiring scheme when connecting multiple chips includes: Obtaining the preset positions of the plurality of chips and the arrangement of the electrodes in each of the chips; A multi-chip theoretical wiring scheme is determined according to the preset positions of the plurality of chips and the arrangement of electrodes in each chip.

9. The wiring method according to claim 1, further comprising: Obtain the external connection theoretical wiring scheme when the chip is connected to the external pins; According to the external connection theoretical wiring scheme, the wiring is divided into an external connection section, a second chip follower section and a connection section; the external connection section is connected to the external pin, the second chip follower section is connected to the electrode in the chip, and the connection section is connected to the external connection section and the second chip follower section respectively; The positions of the second chip following section and the connecting section are adjusted according to the moving posture of the chip to obtain a second actual wiring scheme.

10. A wiring device for a multi-chip package, comprising: A multi-chip theoretical wiring acquisition module, configured to acquire a multi-chip theoretical wiring scheme when multiple chips are connected; A multi-chip theoretical wiring division module, configured to divide the multi-chip theoretical wiring scheme into a plurality of single-chip theoretical wiring schemes according to the multi-chip theoretical wiring scheme; According to the single-chip theoretical wiring scheme, the wiring between two adjacent chips is divided into an inter-chip connection section, a first chip follower section, and an intra-chip connection section; the inter-chip connection section is connected to the adjacent chip, the first chip follower section is connected to the electrode in the chip, and the intra-chip connection section is connected to the chip The inter-connection sub-section is connected with the first chip follower sub-section; The multi-chip actual wiring determination module is configured to adjust the posture of the first chip following section and the intra-chip connection section according to the moving posture of the chip to obtain a first actual wiring plan.

11. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 9 when executing the computer program.

12. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method according to any one of claims 1 to 9.

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