Image sensor system, electronic device and operating method

Abstract

An image sensor system comprises a pixel array with a plurality of pixels, a buffer memory and a matrix memory configured to store a unity matrix and at least one edge detection matrix. A control block effects readout and digitizing of at least four signal values during at least four integration periods, storing the signal values of a selected subsection of the pixel array into the respective pluralities of memory cells of the buffer memory, selects a coefficient matrix from the matrix memory, and effects generation of respective processed signal values corresponding to the pixels of the selected subsection by applying the selected coefficient matrix onto the stored digitized signal values. A computation block determines at least one derivative pixel value based on a difference between at least two values selected from the respective processed signal values and on a duration of at least one of the integration periods.

Description

[0001] IMAGE SENSOR SYSTEM, ELECTRONIC DEVICE AND OPERATING METHOD

[0002] TECHNICAL FIELD

[0003] The disclosure relates to an image sensor system. The disclosure further relates to an electronic device employing such an image sensor system and to a method for operating an image sensor.

[0004] RELATED APPLICATIONS

[0005] This patent application claims the priority of U.S. provisional patent application 63 / 510,378, the disclosure content of which is hereby incorporated by reference.

[0006] BACKGROUND

[0007] In applications such as augmented reality (AR) , virtual reality (VR) , robotics, and computer vision, CMOS Image Sensor (CIS) cameras are used to monitor the surrounding environment. The images taken by CIS cameras are postprocessed to track objects in the environment. In addition to object detection and identification, the algorithms may also track the motion of objects in the scene. The tracking of motion involves estimating position, velocity and acceleration of the objects. The object motion tracking mechanism involves estimating the position, velocity and acceleration of the objects computed from images / videos taken of the scene. In conventional implementations, data outputs of CIS cameras, i.e., images and videos, are fed into complex Al assisted algorithms to identify and track objects. The conventional systems require high power consumption and multiple external hardware and software components. SUMMARY OF INVENTION

[0008] The present disclosure provides an improved imaging concept that allows a more ef ficient generation of data in an image sensor usable for obj ect identi fication and tracking .

[0009] The improved imaging concept is based on the insight that as well pixel values and edge information of the pixel values as velocity values and acceleration values related thereto form a data set that is supportive for obj ect identi fication and motion tracking algorithms . Hence the improved imaging concept proposes to , instead of calculating edges of obj ects within image , velocity and acceleration based on full images or videos on the application processor, integrate both the determination of edge information and the determination of velocity values and acceleration values , at the source , right on the chip of the image sensor system .

[0010] To this end the improved imaging concept allows for calculation of the edges within the image using e . g . a programmable matrix convolution unit with the choice of matrix determined by choice of edge detection algorithm . Derivative values like the velocity and acceleration values can be provided concurrently for each pixel of the image sensor at its output , unlike in a conventional image sensor, which only provides regular pixel values . For example , charge values and signals derived thereof of four or more subsequent integration periods are used to calculate a velocity value based on a time-weighted di f ference of these signals . Similarly, an acceleration value is determined based on a time-weighted di f ference of these velocity values . In other words , the velocity values and the acceleration values are each determined by numerical derivation of respective signals in the at least four subsequent integration periods for each pixel .

[0011] The improved imaging concept provides a solution for a compact , solid-state , CMOS imaging sensor with simultaneous outputs of image data, edge data within an image , velocity map of either image or edge data, and acceleration map of either image or edge data . The image sensor system outputs the various data modes using the same readout circuitry and pipeline for all the data streams . The improved imaging concept allows for low power operation, as the calculation of edges , and velocity and acceleration maps are done at the pixel level thereby eliminating the need for software postprocessing to calculate edges , velocity and acceleration from captured image / video streams . The simultaneous output of image data and velocity map data and / or acceleration map data of edges within images from the same image sensor will allow users to simpli fy their systems and allow them to quickly identi fy and track obj ects within the scene . Post processing steps , which are needed in conventional image sensors , can therefore be eliminated .

[0012] For example , the improved imaging concept directly uses charge values stored on capacitors located within each of the individual pixels with a speci fic sampling and read-out scheme , which are processed by a computation block, e . g . computation processor or computation circuit , located within the image sensor system .

[0013] The benefit of in-pixel simultaneous calculation of data modes ( image , edge , velocity, acceleration) will result in overall system performance to be improved, require less computation, and improve overall system power consumption . This can make battery powered applications such as mobile , AR / VR, robotics , computer vision, etc . more ef ficient .

[0014] An implementation of an image sensor system according to the improved imaging concept comprises a pixel array with a plurality of pixels . Each of the pixels comprises a photodiode . Further elements like a pixel buf fer and a trans fer gate coupled between the photodiode and an input of the pixel buf fer could be included in each of the pixels .

[0015] The image sensor system comprises a buf fer memory comprising a first , a second, a third and a fourth plurality of memory cells , each plurality configured for representing a subsection of the pixel array . The image sensor system further comprises a matrix memory configured to store a unity matrix and at least one edge detection matrix .

[0016] The image sensor system further comprises a control block, e . g . control circuit or controller, that is configured to control read-out and digiti zing for all pixels of the pixel array . The control block is configured to , for each of the pixels , ef fect read-out and digiti zing of a first signal value associated with charges collected by the photodiode during a first integration period, ef fect read-out and digiti zing of a second signal value associated with charges collected by the photodiode during a second integration period following the first integration period, ef fect readout and digiti zing of a third signal value associated with charges collected by the photodiode during a third integration period following the second integration period, and ef fect read-out and digiti zing of a fourth signal value associated with charges collected by the photodiode during a fourth integration period following the third integration period . For example , an analog-to-digital-converter , ADC, is employed for digiti zing . In various implementations several pixels may share a common ADC, such that a number of ADCs employed in the image sensor system is smaller than the number of pixels . In some implementations , a separate ADC may be provided for each pixel or for each row or column of pixels .

[0017] The control block is further configured to ef fect storing the digiti zed first , second, third and fourth signal values corresponding to pixels of a selected subsection of the pixel array into the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively . That is , first signal values associated with the first integration period go into the first plurality of memory cells of the buf fer memory, second signal values associated with the second integration period go into the first plurality of memory cells of the buf fer memory, etc . For example , the respective pluralities of memory cells for a matrix structure corresponding to the selected subsection of the pixel array .

[0018] The control block is further configured to select a coef ficient matrix from the matrix memory based on a matrix selection signal , and to ef fect generation of a first , a second, a third and a fourth plurality of processed signal values corresponding to the pixels of the selected subsection by applying the selected coef ficient matrix onto the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively . I f the unity matrix is selected, the processed signal values correspond to the digiti zed signal values , which e . g . are pixel values . I f one or more edge detection matrices are selected, the processed signal values correspond to edge data .

[0019] The image sensor system further comprises a computation block that is configured to , for each of the pixels of the selected subsection, determine at least one derivative signal value based on a di f ference between at least two values , which correspond to the respective pixel and are selected from the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values , and based on a duration of at least one of the first integration period, the second integration period, the third integration period and the fourth integration period .

[0020] In various implementations , for determining the at least one derivative pixel value , the computation block is configured to , for each of the pixels of the selected subsection, determine a first signal velocity value based on a di f ference between the corresponding processed signal values in the first and the second plurality of processed signal values , and on a duration of the second integration period, determine a second signal velocity value based on a di f ference between the corresponding processed signal values in the third and the fourth plurality of processed signal values , and on a duration of the fourth integration period, and determine a signal acceleration value based on a di f ference between the second signal velocity value and the first signal velocity value and on a duration of the second integration period, the third integration period and the fourth integration period .

[0021] For applying the selected coef ficient matrix, a dedicated matrix operation block, e . g . dedicated matrix operation circuit , may be employed . For example , a matrix convolution operation or a matrix multiplication operation is performed with the selected coef ficient matrix and a matrix representation of the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively .

[0022] In various implementations the at least one edge detection matrix is one or more of the following : one or more Prewitt Matrices , one or more Sobel Matrices , one or more Krisch Matrices , one or more Laplace Matrices .

[0023] In various implementations the computation block is configured to , for each of the pixels of the selected subsection, i f the selected coef ficient matrix is the at least one edge detection matrix, to perform an intensity gradient and / or gradient thresholding computation based on the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values .

[0024] In various implementations the image sensor system may further comprise an output block, e . g . output circuit , being configured to provide , for each of the pixels of the selected subsection, an output pixel signal based on at least one of the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values , a velocity signal based on at least one of the first signal velocity value and a second signal velocity value , and an acceleration signal based on the signal acceleration value .

[0025] For example , the output pixel signal is based on a combination, e . g . a sum, of the first signal value , the second signal value, the third signal value and the fourth signal value.

[0026] For example, the velocity signal may be selected from one of the first signal velocity value and a second signal velocity value or may be based on a combination, e.g. a weighted sum or average of the first signal velocity value and a second signal velocity value.

[0027] In various implementations the image sensor system is configured to be selectively operated, e.g., based on a user input, in a standard operating mode and in at least one of a velocity operating mode and a pixel operating mode. Herein, in a standard operating mode the output block is configured, for each of the pixels of the selected subsection, to provide the output pixel signal, the velocity signal and the acceleration signal. In the velocity operating mode, the output block is configured, for each of the pixels of the selected subsection, to provide the output pixel signal and the velocity signal, e.g. without providing the acceleration signal. In the pixel operating mode, the output block is configured, for each of the pixels of the selected subsection, to provide the output pixel signal, in particular only the output signal, e.g. without the velocity signal and the acceleration signal.

[0028] Depending on the selected operating mode, determination of the excluded signal types, e.g. acceleration signal and / or velocity signal, may be suspended, such that useless operation of the computation block can be avoided and power can be saved. The computation block or the output block may still determine the output pixel signal, which is present in each of the possible operating modes. In some implementations the image sensor system comprises , for each of the pixels , an associated sampling bank . Each sampling bank comprises a first signal sampling stage connected to an output of the respective pixel buf fer, a second signal sampling stage connected in cascade with the first signal sampling stage , a third signal sampling stage connected in cascade with the second signal sampling stage , and a fourth signal sampling stage connected in cascade with the third signal sampling stage .

[0029] In such configuration the control block is configured to , for each of the pixels , ef fect sampling of charges collected by the photodiode during a first integration period at least onto the fourth signal sampling stage , ef fect sampling of charges collected by the photodiode during a second integration period following, e . g . subsequently following, the first integration period at least onto the third signal sampling stage , ef fect sampling of charges collected by the photodiode during a third integration period following, e . g . subsequently following, the second integration period at least onto the second signal sampling stage , and ef fect sampling of charges collected by the photodiode during a fourth integration period following, e . g . subsequently following, the third integration period onto the first signal sampling stage .

[0030] The control block herein is further configured to , for each of the pixels , ef fect read-out and digiti zing of a first signal value from the fourth signal sampling stage , of a second signal value from the third signal sampling stage , of a third signal value from the second signal sampling stage and of a fourth signal value from the first signal sampling stage . These signal values are to be stored in the buf fer memory accordingly .

[0031] The sampling bank may be a signal sampling bank .

[0032] In various implementations the image sensor system further comprises , for each of the pixels , an associated further sampling bank, which may be a reset sampling bank in which only the reset signal is stored to ensure full correlated double sampling of the read signal . Each further sampling bank comprises a first reset sampling stage connected to the output of the respective pixel buf fer, a second reset sampling stage connected in cascade with the first reset sampling stage , a third reset sampling stage connected in cascade with the second reset sampling stage , and a fourth reset sampling stage connected in cascade with the third reset sampling stage .

[0033] Herein the control block is further configured to , for each of the pixels , ef fect sampling of a first reset level state associated with the first integration period at least onto the fourth reset sampling stage , ef fect sampling of a second reset level state associated with the second integration period at least onto the third reset sampling stage , ef fect sampling of a third reset level state associated with the third integration period at least onto the second reset sampling stage , and ef fect sampling of a fourth reset level state associated with the fourth integration period onto the first reset sampling stage . The control block is further configured to , for each of the pixels , ef fect the read-out and digiti zing of the first signal value from the fourth signal sampling stage and the fourth reset sampling stage , of the second signal value from the third signal sampling stage and the third reset sampling stage , of the third signal value from the second signal sampling stage and the second reset sampling stage , and of the fourth signal value from the first signal sampling stage and the first reset sampling stage .

[0034] For example , the further sampling bank allows to perform correlated double sampling, CDS , which allows to increase the signal quality of the pixels or the image sensor, for example with respect to PVT variations .

[0035] For example , the outputs of the sampling bank respectively signal sampling bank and the further sampling bank respectively reset sampling bank are coupled to a first and a second input of a di f ferential ADC . Hence , each of the first , the second, the third and the fourth signal values are based on the di f ference between a signal level and a reset level as soon as entering the digital domain .

[0036] I f the further sampling bank respectively reset sampling bank is not present in the image sensor system, a di f ferential double sampling, DDS , can be performed, e . g . by providing a predetermined reset level signal to the ADC when digiti zing the first , the second, the third and the fourth signal value . Such predetermined reset level signal may still be variable during operation of the image sensor system . For example , the reset level signal may be determined using calibration during operation, before operation or other well-known methods .

[0037] An image sensor system according to one of the implementations described above or elsewhere in this disclosure may be employed in a camera system that is included in an electronic device , for example . For example , such an electronic device may be used in the field of AR / VR, robotics and computer vision, to name only a few .

[0038] The improved imaging concept is not limited to the apparatusbased implementations but can also be implemented with a corresponding operating method .

[0039] For example , a method for operating an image sensor according to the improved imaging concept is provided . Herein the image sensor is implemented according to one of the example implementations described above . The method comprises ,

[0040] - for each of the pixels , reading out and digiti zing of a first signal value associated with charges collected by the photodiode during a first integration period;

[0041] - for each of the pixels , reading out and digiti zing of a second signal value associated with charges collected by the photodiode during a second integration period following the first integration period;

[0042] - for each of the pixels , reading out and digiti zing of a third signal value associated with charges collected by the photodiode during a third integration period following the second integration period;

[0043] - for each of the pixels , reading out and digiti zing of a fourth signal value associated with charges collected by the photodiode during a fourth integration period following the third integration period;

[0044] - storing the digiti zed first , second, third and fourth signal values corresponding to pixels of a selected subsection of the pixel array into the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively;

[0045] - selecting a coef ficient matrix from the matrix memory based on a matrix selection signal ; - generating a first , a second, a third and a fourth plurality of processed signal values corresponding to the pixels of the selected subsection by applying the selected coef ficient matrix onto the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively; and

[0046] - for each of the pixels of the selected subsection, determining at least one derivative signal value based on a di f ference between at least two values , which correspond to the respective pixel and are selected from the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values , and based on a duration of at least one of the first integration period, the second integration period, the third integration period and the fourth integration period .

[0047] In various implementations determining the at least one derivative pixel value comprises

[0048] - determining a first signal velocity value based on a di f ference between the corresponding processed signal values in the first and the second plurality of processed signal values , and on a duration of the second integration period;

[0049] - determining a second signal velocity value based on a di f ference between the corresponding processed signal values in the third and the fourth plurality of processed signal values , and on a duration of the fourth integration period; and

[0050] - determining a signal acceleration value based on a di f ference between the second signal velocity value and the first signal velocity value and on a duration of the second integration period, the third integration period and the fourth integration period .

[0051] In various implementations the method further comprises

[0052] - outputting an output pixel signal based on at least one of the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values ;

[0053] - selectively outputting a velocity signal based on at least one of the first signal velocity value and the second signal velocity value ; and

[0054] - selectively outputting an acceleration signal based on the signal acceleration value .

[0055] In various implementations of the method applying the selected coef ficient matrix comprises a matrix convolution operation or a matrix multiplication operation, each with the selected coef ficient matrix and a matrix representation of the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively .

[0056] Further implementations of the operating method become readily apparent for the skilled reader from the description of the various implementations of the image sensor system above . For example , the method may be implemented in an image sensor system as described above .

[0057] BRIEF DESCRIPTION OF DRAWINGS

[0058] The improved imaging concept will be explained in more detail in the following with the aid of the drawings . Elements and functional blocks , e . g . functional circuits , having the same or similar function bear the same reference numerals throughout the drawings . Hence their description is not necessarily repeated in the following drawings .

[0059] In the drawings :

[0060] Figures 1 to 3 show example implementations of an image sensor system;

[0061] Figure 4 shows a further example implementation of an image sensor system;

[0062] Figure 5 shows a detail of an example implementation of an image sensor system;

[0063] Figure 6 shows an example timing diagram for the image sensor system in Fig . 5 ;

[0064] Figure 7 shows a detail of a further example implementation of an image sensor system;

[0065] Figure 8 shows an example timing diagram for the image sensor system in Fig . 7 ;

[0066] Figure 9 shows an example representation of charge stores in the image sensor system in Fig . 7 ;

[0067] Figure 10 shows an example implementation of wafers for an image sensor system;

[0068] Figure 11 shows an example implementation of a sampling bank; Figure 12 shows an example implementation of an electronic device ; and

[0069] Figure 13 shows a block diagram of an example implementation of a method for operating an image sensor system .

[0070] DETAILED DESCRIPTION

[0071] Figure 1 shows an example implementation of an image sensor system 10 comprising a pixel array 100 , for which a readout can be controlled for example via a row driver RDR and a column driver CDR . For example , the pixel array 100 has a si ze of N rows and M columns , with N and M being integers of a si ze selectable depending on the desired application . Hence the pixel array 100 includes NxM pixels . Each of the pixels at least comprises a photodiode or a pinned photodiode ( PPD) as an Active Pixel Array (APS ) . The image sensor system 10 further comprises a sampling block 200 , e . g . sampling circuit , for sampling charges collected by the pixels of the pixel array 100 . An analog to digital converter, ADC, 500 is coupled downstream the sampling block 200 for digiti zing respective sampled charges and providing them to a buf fer memory 600 .

[0072] The buf fer memory 600 includes a plurality of memory cells , in particular organi zed as a first , a second, a third and a fourth plurality of memory cells , wherein each plurality of memory cells is configured for representing a subsection of the pixel array 100 . To this end each of the first , the second, the third and the fourth plurality of memory cells can represent a matrix corresponding to a subsection of the pixel array 100 having a predefined si ze . For example , respective matrices with K rows and M columns are formed with each plurality of memory cells. Other sizes of subsections should not be excluded by such example.

[0073] The image sensor system 10 further comprises a matrix memory 700, which stores a unity matrix and at least one edge detection matrix, a matrix operation block 800, e.g. matrix operation circuit 800, and a computation block 400, e.g. computation circuit. All of the elements are controlled by a control block 300, e.g. controller or control circuit. The matrix memory 700 may be configured for storing KxK matrices.

[0074] According to the improved imaging concept the control block 300 is configured to control read-out and digitizing for all pixels of the pixel array, e.g. via sampling block 200 and ADC 500. The control block 300 is configured to, for each of the pixels, effect read-out and digitizing of a first signal value associated with charges collected by the photodiode during a first integration period, effect read-out and digitizing of a second signal value associated with charges collected by the photodiode during a second integration period following the first integration period, effect readout and digitizing of a third signal value associated with charges collected by the photodiode during a third integration period following the second integration period, and effect read-out and digitizing of a fourth signal value associated with charges collected by the photodiode during a fourth integration period following the third integration period .

[0075] The control block 300 is further configured to effect storing the digitized first, second, third and fourth signal values corresponding to pixels of a selected subsection of the pixel array into the first, the second, the third and the fourth plurality of memory cells of the buf fer memory 600 , respectively .

[0076] Hence each plurality of memory cells stores the digiti zed signal values of the selected subsection corresponding to one of the integration periods .

[0077] The control block 300 is further configured to select a coef ficient matrix from the matrix memory 700 based on a matrix selection signal MSEL, and to ef fect generation of a first , a second, a third and a fourth plurality of processed signal values corresponding to the pixels of the selected subsection by applying the selected coef ficient matrix onto the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively . Application of the selected coef ficient matrix for example is performed by the matrix operation block 800 .

[0078] For example , applying the selected coef ficient matrix comprises a matrix convolution operation or a matrix multiplication operation, each with the selected coef ficient matrix and a matrix representation of the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buf fer memory 600 , respectively . In some implementations the matrix operation block 800 comprises a multiply-accumulate block / circuit or matrix multiplication block / circuit for the matrix operation, i . e . the edge computing .

[0079] I f the selected coef ficient matrix is the unity matrix, the result of the operation basically corresponds to the input . In this case the digiti zed signal values can be further evaluated or processed according to user selection in the computation block 400.

[0080] If, however according to the improved imaging concept edge data is desired, the selected coefficient matrix is at least one edge detection matrix. In various implementations the at least one edge detection matrix is one or more of the following: one or more Prewitt Matrices, one or more Sobel Matrices, one or more Krisch Matrices, one or more Laplace Matrices .

[0081] For example, Prewitt Matrices for vertical (Gx) and horizontal (Gy) edge detection can look like:

[0082] As another (Gx) and horizontal

[0083] Both directions can be applied in each case.

[0084] The result of the operation are edge data within the selected subsection, which can be assembled to edge data of the full pixel array accordingly. In this case the edge data are the respective processed signal values.

[0085] The computation block 400 is generally configured to, for each of the pixels of the selected subsection, determine at least one derivative signal value based on a di f ference between at least two values , which correspond to the respective pixel and are selected from the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values , and based on a duration of at least one of the first integration period, the second integration period, the third integration period and the fourth integration period .

[0086] For example , the computation block 400 determines , for each of the pixels of the selected subsection, a first signal velocity value based on a di f ference between the corresponding processed signal values in the first and the second plurality of processed signal values , and on a duration of the second integration period . Similarly, the computation block 400 determines , for each of the pixels of the selected subsection, a second signal velocity value based on a di f ference between the corresponding processed signal values in the third and the fourth plurality of processed signal values , and on a duration of the fourth integration period .

[0087] The first and the second signal velocity value , for example , are numerical derivatives of the corresponding signal values . For example , the signal velocity values are indicative of a velocity of a changing pixel value such that they can be used for tracking an obj ect in the image represented by the pixel array .

[0088] A signal acceleration value is determined by the computation block 400 based on a di f ference between the second signal velocity value and the first signal velocity value and on a duration of the second integration period, the third integration period and the fourth integration period .

[0089] Also , the signal acceleration value can be seen as a numerical derivative of the signal velocity values or a second derivative of the signal values . Like the signal velocity values , also the signal acceleration value can be used for tracking obj ects in the image represented by the pixel array . Hence providing the computation block in an image sensor system according to the improved imaging concept allows for outputting velocity and acceleration images on chip in addition to normal imaging modes . This allows for high-speed acceleration and velocity images for computer vision applications , eliminating post processing steps required in conventional image sensor implementations .

[0090] Hence image data, edge data within an image , velocity map of either image or edge data, and acceleration map of either image or edge data can be generated . However, it is selectable , which type of data is actually output by the image sensor system 400 , i . e . via the matrix selection signal MSEL and an output selection signal OSEL that determines which of signal values and / or derivative signal values are to be output .

[0091] For example , the available options for data output can be summari zed as detailed in the table below . Several options may be combined, which may require an intermediate storage . Table :

[0092] In some implementations the computation block 400 is configured to , for each of the pixels of the selected subsection, i f the selected coef ficient matrix is the at least one edge detection matrix, to perform an intensity gradient and / or gradient thresholding computation based on the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values . This allows for further refinement in the edge data analysis thereby reducing the burden on user software . Furthermore, intensity gradients can be used to combine the X&Y edge matrix data (optional, only if required) . Thresholding based on the intensity value can help in elimination of f alse / spurious edges.

[0093] For example, an intensity amplitude |G| can be calculated according to

[0094] Similarly, a phase 0 of the intensity can be calculated according to

[0095] In the implementation according to Figure 1, a single ADC 500 is used for reading the pixel array 100 row by row serially into the buffer memory 600.

[0096] Figure 2 shows another example implementation of an image sensor system 10 that basically corresponds to that of Figure 1. One difference is given in that multiple ADCs 500 are used reading e.g. K rows in parallel into the buffer memory 600.

[0097] Figure 3 shows another example implementation of an image sensor system 10 that also basically corresponds to that of Figure 1. One difference is given in that a switch or multiplexer (MUX) 550 is used to multiplex data into each row of the pluralities of memory cells of the buffer memory 600 which can then be used to perform the matrix operation with the edge detection matrix or matrices, Figure 4 shows a further example implementation of an image sensor system 10 comprising a pixel array 100 with a plurality of pixels 101 , 102 , ..., l On . The image sensor system further comprises a sampling block 200 with, for each of the pixels 101 , 102 , ..., l On, an associated sampling bank 201 , 202 , ..., 20n, wherein each sampling bank 201 , 202 , ..., 20n comprises a first , a second, a third and a fourth signal sampling stage that are connected in cascade with each other, wherein the first signal sampling stage is connected to the corresponding pixel or a pixel buf fer of the respective pixel .

[0098] For example , sampling bank 201 comprises a first signal sampling stage 211 that is connected to an output of pixel 101 , a second signal sampling stage 212 connected in cascade with the first signal sampling stage 211 , a third signal sampling stage 213 connected in cascade with the second signal sampling stage 212 , and a fourth signal sampling stage 214 connected in cascade with the third signal sampling stage 213 . The other sampling banks 202 , ..., 20n have the same structure .

[0099] The image sensor system 10 further comprises the control block 300 , the ADC 500 and the buf fer memory 600 . The ADC 500 is coupled to outputs of the sampling banks 201 , 202 , ..., 20n for digiti zing respective signals received from the sampling banks . An output of the ADC 500 is coupled to the buf fer memory 600 . The computation block 400 , the matrix memory 700 and the matrix operation block 800 depicted in Figures 1 to 3 are not shown here for the reasons of a better overview only .

[0100] Referring now to Figure 5 , a detail of an example implementation of an image sensor system, e . g . employed in the image sensor system of one of Figures 1 to 4, is shown. In particular, Figure 5 shows an example implementation of one of the pixels 101 in combination with the corresponding sampling bank 201 with the sampling stages 211, 212, 213, 214 as e.g. shown in Figure 4. The pixel 101 for example is a standard 4T pixel comprising a photodiode PD, a pixel buffer SF and a transfer gate TX coupled between the photodiode PD and an input of the pixel buffer SF. The input of the pixel buffer SF corresponds for example to a floating diffusion. As should be well-known to the skilled reader, a reset circuitry with a reset transistor RST and a dual conversion gain transistor DCG and a capacitor CLG can be employed. A drain terminal of the reset transistor RST is connected to a supply potential VDD. A drain terminal of the pixel buffer SF is connected to a dedicated supply potential VDD_PIX, and a source terminal of the pixel buffer SF is connected to a reference potential terminal VSS via a precharge transistor PC.

[0101] It should be noted that the structure of the pixel 101 is chosen as an example only and other implementations of pixels could be used as well. One common feature of such arbitrary pixel implementations is that an output of the pixel buffer SF, respectively the source terminal of the pixel buffer SF is connected to the sampling bank 201 respectively the first signal sampling stage 211. A connection PS between the pixel buffer SF and the sampling bank 201 can be used as a pixel stack connection, e.g., for in pixel stacking, which will be described in more detail in connection with Figure 10.

[0102] Each of the signal sampling stages 211, 212, 213, 214 comprises a sample switch and a storage element. In detail, first signal sampling stage 211 comprises a first sample switch S I and a third storage element Cl . The first sample switch S I is connected to the output of the pixel buf fer SF and to a first end of the first storage element Cl . Similarly, the second signal sampling stage 212 comprises a second storage element C3 and a second sample switch S3 connected between an output of the first sample switch S I and a first terminal of the second storage element C3 . The third signal sampling stage 213 comprises a third storage element C5 and a third sample switch S5 connected between an output of the second sample switch S3 and a first terminal of the third storage element C5 . The fourth signal sampling stage 214 comprises a fourth storage element C7 and a fourth sample switch S7 connected between an output of the third sample switch S5 and a first terminal of the fourth storage element C7 and also a gate of a first read-out transistor . The respective second terminals of the storage elements Cl , C3 , C5 , C7 are connected to the reference potential terminal VSS , which also is coupled to a gate terminal of a second read-out transistor . A drain terminal of the first read-out transistor is connected to the dedicated pixel supply voltage VDD_PIX, while its source terminal is connected to a drain terminal of the second read-out transistor . A source of the second readout transistor serving an output potential V_OUT1 is coupled to the ADC 500 .

[0103] Due to the cascaded connection of the signal sampling stages 211 , 212 , 213 , 214 , the first signal sampling stage 211 is selectively operable through the first sample switch, the second signal sampling stage 212 is selectively operable through the first sample switch S I and the second sample switch S3 , the third signal sampling stage 213 is selectively operable through the first sample switch S I , the second sample switch S3 and the third sample switch S5 , and the fourth signal sampling stage 214 is selectively operable through the first sample switch S I , the second sample switch S3 , the third sample switch S5 and the fourth sample switch S7 . Referring back to Figure 4 , it should be noted that each of the pixels 101 , 102 , ..., l On may comprise a photodiode RD, a pixel buf fer SF and the corresponding trans fer gate TX, and that each of the first signal sampling stages is connected to an output of the respective pixel buf fer of the corresponding pixel .

[0104] For example , the control block 300 is configured to , for each of the pixels , ef fect sampling of charges collected by the photodiode during a first integration period at least onto the fourth signal sampling stage , ef fect sampling of charges collected by the photodiode during a second integration period following the first integration period at least onto the third signal sampling stage , ef fect sampling of charges collected by the photodiode during a third integration period following the second integration period at least onto the second signal sampling stage , and ef fect sampling of charges collected by the photodiode during a fourth integration period following the third integration period onto the first signal sampling stage . This procedure is based on the ef fect that the signal sampling stages 211 , 212 , 213 , 214 are arranged in a cascaded fashion such that the last or fourth signal sampling stage 214 can only sample through the other signal sampling stages 211 , 212 and 213 , et cetera .

[0105] Referring now to Figure 6 , an example timing diagram for the image sensor system in Figure 5 is shown, wherein respective high signals correspond to a closing of the respective switches or transistors . With respect to the previously described sampling, the period between tO and tl corresponds to the first integration period, the period between tl and t2 corresponds to the second integration period, the period between t2 and t3 corresponds to the third integration period and the period between t3 and t4 corresponds to the fourth integration period .

[0106] The control block 300 is further configured to , for each of the pixels , ef fect read-out and digiti zing, e . g . via the ADC 500 , of a first signal value s i from the fourth signal sampling stage 214 , of a second signal value s2 from the third signal sampling stage 213 , of a third signal value s3 from the second signal sampling stage 212 , and of a fourth signal value s4 from the first signal sampling stage 211 .

[0107] Hence , after a full sampling and read-out cycle , the first , second, third and fourth signal values s i , s2 , s3 , s4 are present in a digital form . These signal values apparently can be used, either alone or in combination, as pixel values of pixels in the pixel array of the image sensor, similar to conventional image sensors .

[0108] Inter alia for preparing the application of the matrix operation, the control block 300 is configured to ef fect storing the digiti zed first , second, third and fourth signal values corresponding to pixels of a selected subsection of the pixel array 100 into the first , the second, the third and the fourth plurality of memory cells of the buf fer memory 600 , respectively . These plurality of memory cells each form a matrix representation of the signal values of the selected subsection, such that the selected coef ficient matrix can be applied onto the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buffer memory, respectively, as described in conjunction with Figure 1.

[0109] It should be noted that with the example implementation as shown in Figure 5 and Figure 6, only a single sampling bank is provided, which allows for example performing a differential double sampling, DDS, e.g. by providing one or more predefined reset level signals to the ADC 500 during digitizing. It should be noted that even with the example implementation as shown in Figure 5 also correlated double sampling, CDS, can be performed using a sampling and readout scheme as described, for example, in US patent application 17 / 818,962, which is incorporated herein by reference in its entirety .

[0110] However, the present disclosure is not limited to such implementation but allows CDS also by providing, for each pixel, a further sampling bank or reset sampling bank. Referring now to Figure 7, a detail of a further example implementation of an image sensor system according to the improved imaging concept is shown, which is based on the example implementation of Figure 5. In addition to the elements already explained in conjunction with Figure 5, there is additionally provided the further sampling bank 201' with corresponding first, second, third, fourth reset sampling stages 211', 212', 213' and 214', which are connected in cascade with each other, wherein the reset sampling bank 201' is connected at its input, i.e. the input of the first reset sampling stage 211', to the output of the pixel buffer SF at the pixel stack connection PS.

[0111] For example, the first reset sampling stage 211' comprises a first reset storage element C2 and a first reset sample switch S2 connected between the output of the pixel buf fer SF and a first terminal of the first reset storage element . The second reset sampling stage 211 ' comprises a second reset storage element C4 and a second reset sample switch S4 connected between an output of the first reset sample switch S2 and a first terminal of the second reset storage element C4 . The third reset sampling stage 213 ' comprises a third reset storage element C6 and a third reset sample switch S 6 connected between an output of the second reset sample switch S4 and a first terminal of the third reset storage element C6 . The fourth reset sampling stage 214 ' comprises a fourth reset storage element C8 and a fourth reset sample switch S 8 connected between an output of the third reset sample switch S 6 and a first terminal of the fourth reset storage element C8 and to a gate of a first output transistor of the reset sampling bank 201 ' . Second terminals of the first , second, third and fourth reset storage elements C2 , C4 , C6 , C8 are commonly connected to the reference potential terminal VSS and to a gate of a second output transistor of the reset sampling bank 201 ' . Similar as for the signal sampling bank 201 , a drain terminal of the first output transistor of the reset sampling bank 201 is connected to the pixel supply voltage terminal VDD_PIX, while the source terminal of this first output transistor is connected to a drain terminal of the second output transistor of the reset sampling bank 201 ' . A source terminal of this second output transistor is coupled to the ADC 500 and provides a potential V_OUT2 .

[0112] For example , the control block 300 is further configured to , for each of the pixels , ef fect sampling of a first reset level state associated with the first integration period at least onto the fourth reset sampling stage , ef fect sampling of a second reset level state associated with the second integration period onto the third reset sampling stage , ef fect sampling of a third reset level state associated with the third integration period at least onto the second reset sampling stage , and ef fect sampling of a fourth reset level state associated with a fourth integration period onto the first reset sampling stage . A corresponding example timing diagram for full operation of the image sensor system as shown in Figure 7 is depicted in Figure 8 .

[0113] Figure 9 shows an example representation of charge stores in the image sensor system in Figure 7 , in particular indicating the amount of charges stored in the respective charge stores or storage elements Cl to C8 .

[0114] Accordingly, the ADC 500 having a first input coupled to the signal sampling bank 201 and having a second input coupled to the reset sampling bank 201 ' is configured for digiti zing of the first signal value s i , the second signal value s2 , the third signal value s3 and the fourth signal value s4 . As described before , the signal values are stored in the respective pluralities of memory cells of the buf fer memory 600 .

[0115] In the various implementations described above , the first integration period, the second integration period, the third integration period and the fourth integration period may have the same duration .

[0116] In various implementations of the computation block 400 the first signal velocity value vmapl is calculated according to and the second signal velocity value vmap2 is calculated according to s4 — s3 vmap2 = — -

[0117] Kt4 - t3

[0118] Similarly, the signal acceleration value amap may be calculated according to

[0119] In some implementations the computation of velocity and acceleration values may be performed only selectively, e . g . i f selected by a user or an application by the output selection signal OSEL .

[0120] For example , the image sensor system 10 may be configured to be selectively operated in a standard operating mode and in at least one of a velocity operating mode and a pixel operating mode . In the standard operating mode the output block is configured to provide the output pixel signal , the velocity signal and the acceleration signal . In the velocity operating mode the output block is configured to provide the output pixel signal and the velocity signal , in particular without the acceleration signal . In the pixel operating mode the output block is configured to provide the output pixel signal , in particular without the velocity signal and the acceleration signal . Accordingly, respective computations that are not required for the requested operating mode can be omitted, thus saving power .

[0121] In various implementations of the image sensor system 10 , each of the pixels may be arranged on a first wafer, and each of the associated sampling banks , i . e . signal sampling banks and optionally reset sampling banks , is arranged on a second wafer bonded to the first wafer. This may be useful to implement in-pixel stacking.

[0122] Figure 10 shows an example implementation of such arrangement with a first wafer 1010 carrying the pixels 101, 102, ..., lOn and optionally further components. The second wafer 1020 being bonded to the first wafer 1010 carries the associated sampling banks 201, 202, ..., 20n, optionally together with the respective reset sampling banks and further components like the control block 300, the ADC 500, the computation block 400, the buffer memory 600, the matrix memory 700 and the matrix operation block 800. As can be seen, the respective pairs of pixels and sampling banks are respectively connected, e.g. by inter-waver connections at the respective pixel stack connection PS as shown in Figure 5 and Figure 7. Hence an in-pixel stacking is achieved. In-pixel stacking makes a pixel level capacitor bank feasible.

[0123] For example, each of the pixels, each of the associated sampling banks, including the optional reset sampling banks, the control block 300, the ADC 500, the computation block 400, the buffer memory 600, the matrix memory 700 and the matrix operation block 800 are implemented on a single chip of the image sensor system.

[0124] Figure 11 shows an example implementation of a sampling bank that can be used in any of the image sensor systems described above. Instead of having four sampling stages 211, 212, 213, 214, a greater number n of sampling stages being connected in cascade is provided in the sampling bank 201, such that the last sampling stage 21n, which comprises an n-th sample switch Sn and an n-th storage element Cn, is connected to the first and the second readout transistor. Respective operation of such sampling bank should be apparent to the skilled reader from the description of the implementation shown in Figure 5 and Figure 7 above. The sampling bank with n sampling stages can also be used a further sampling bank or reset sampling bank. If a greater number n of sampling stages is present, also the structure of the buffer memory 600 may be adapted correspondingly.

[0125] For example, n may be 10, without excluding smaller or greater numbers. A number n of greater than 4 can be used for additional first and second derivatives or pixel velocity and signal acceleration values.

[0126] Considering, for example, a burst camera where we store n frames in memory, we could achieve the same effect using n storage elements like S / H capacitors within the capacitive sampling bank.

[0127] Referring now to Figure 12, an electronic device 1200 is shown which includes a camera system 1210 comprising an image sensor system 10 according to one of the implementations described in this disclosure. Such electronic device may specifically be adapted for AR, VR, robotics and / or computer vision applications.

[0128] Figure 13 shows a block diagram of an example implementation of a method for operating an image sensor system. For example, such image sensor system is implemented according to one of the examples described above. For example, in step 1301, signal values from the pixels are read out and digitized, e.g. using an ADC, in order to retrieve the first, second, third and fourth signal values si, s2, s3, s4 as described above. In step 1302 the digitized signal values corresponding to pixels of a selected subsection of the pixel array are stored into the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively .

[0129] In step 1303 a coef ficient matrix is selected from the matrix memory based on a matrix selection signal , such that either a unity matrix or at least one edge detection matrix is selected . In step 1304 the selected coef ficient matrix is applied onto the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively . Hence , i f the selected coef ficient matrix is the at least one edge detection matrix, edge data can be generated as described above .

[0130] Depending on an output selection signal , in step 1305 a signal velocity is determined for each pixel of the selected subsection of the pixel array, as described above , e . g . by calculating a first and a second signal velocity value . Correspondingly, in step 1306 a signal acceleration is determined based on the previously determined signal velocity values .

[0131] I f the selected coef ficient matrix is the at least one edge detection matrix, in step 1307 an intensity gradient and / or gradient thresholding computation is performed based on the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values

[0132] In step 1308 the selected values are output depending on a selection from a user or an application . As discussed above , determination of the pixel velocity in step 1305 and / or determination of the pixel acceleration in step 1306 may be omitted i f these values are not required for the current selection or the current mode of operation . The method 1300 may start over after output of the selected values .

[0133] The embodiments of the improved imaging concept disclosed herein have been discussed for the purpose of familiari zing the reader with novel aspects of the implementation of the improved imaging concept . Although preferred embodiments have been shown and described, many changes , modi fications , equivalents and substitutions of the disclosed concepts may be made by one having skill in the art without departing from the scope of the claims .

[0134] In particular, the implementation of the improved imaging concept is not limited to the disclosed embodiments , and gives examples of many alternatives possible for the features included in the embodiments discussed . However, it is intended that any modi fications , equivalents and substitutions of the disclosed concepts be included within the scope of the claims which are appended hereto .

[0135] Features recited in separate dependent claims may be advantageously combined . Moreover, reference signs used in the claims are not limited to be construed as limiting the scope of the claims .

[0136] Furthermore , as used herein, the term "comprising" does not exclude other elements . In addition, as used herein, the article "a" is intended to include one or more than one component or element , and is not limited to be construed as meaning only one . References

[0137] FD floating di f fusion

[0138] PD photodiode

[0139] TX trans fer gate

[0140] RST reset switch

[0141] SF pixel buf fer

[0142] PS pixel stack connection

[0143] CRD column driver

[0144] RDR row driver

[0145] MSEL matrix selection signal

[0146] OSEL output selection signal

[0147] 10 image sensor system

[0148] 100 pixel array

[0149] 101 to l On pixels

[0150] 200 sampling block

[0151] 201 to 20n signal sampling bank

[0152] 201 ’ to 20n ' reset sampling bank

[0153] 211 to 214 , 21n sampling stage

[0154] 300 control block

[0155] 400 computation block

[0156] 500 ADC

[0157] 550 multiplexer

[0158] 600 buf fer memory

[0159] 700 matrix memory

[0160] 800 matrix operation block

[0161] 1010 , 1020 wafer

[0162] 1200 electronic device

[0163] 1210 camera system

[0164] 1300 method

[0165] 1301 to 1308 method steps

Claims

Claims1 . An image sensor system comprising- a pixel array with a plurality of pixels , each of the pixels comprising a photodiode ;- a buf fer memory comprising a first , a second, a third and a fourth plurality of memory cells , each plurality configured for representing a subsection of the pixel array;- a matrix memory configured to store a unity matrix and at least one edge detection matrix ;- a control block being configured to ,- for each of the pixels , ef fect read-out and digiti zing of a first signal value associated with charges collected by the photodiode during a first integration period;- for each of the pixels , ef fect read-out and digiti zing of a second signal value associated with charges collected by the photodiode during a second integration period following the first integration period;- for each of the pixels , ef fect read-out and digiti zing of a third signal value associated with charges collected by the photodiode during a third integration period following the second integration period;- for each of the pixels , ef fect read-out and digiti zing of a fourth signal value associated with charges collected by the photodiode during a fourth integration period following the third integration period;- ef fect storing the digiti zed first , second, third and fourth signal values corresponding to pixels of a selected subsection of the pixel array into the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively;- select a coef ficient matrix from the matrix memory based on a matrix selection signal ; and- ef fect generation of a first , a second, a third and a fourth plurality of processed signal values corresponding to the pixels of the selected subsection by applying the selected coef ficient matrix onto the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively; and- a computation block being configured to , for each of the pixels of the selected subsection, determine at least one derivative signal value based on a di f ference between at least two values , which correspond to the respective pixel and are selected from the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values , and based on a duration of at least one of the first integration period, the second integration period, the third integration period and the fourth integration period .2 . The image sensor system according to claim 1 , wherein, for determining the at least one derivative pixel value , the computation block is configured to , for each of the pixels of the selected subsection,- determine a first signal velocity value based on a di f ference between the corresponding processed signal values in the first and the second plurality of processed signal values , and on a duration of the second integration period;- determine a second signal velocity value based on a di f ference between the corresponding processed signal values in the third and the fourth plurality of processedsignal values , and on a duration of the fourth integration period; and- determine a signal acceleration value based on a di f ference between the second signal velocity value and the first signal velocity value and on a duration of the second integration period, the third integration period and the fourth integration period .3 . The image sensor system according to claim 2 , further comprising an output block being configured to selectively provide , for each of the pixels of the selected subsection,- an output pixel signal based on at least one of the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values ;- a velocity signal based on at least one of the corresponding first signal velocity value and the corresponding second signal velocity value ; and- an acceleration signal based on the corresponding signal acceleration value .4 . The image sensor system according to claim 3 , wherein the velocity signal is based on a combination of the corresponding first signal velocity value and the corresponding second signal velocity value .5 . The image sensor system according to claim 3 or 4 , wherein the output pixel signal is based on a combination, in particular a sum, of the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values .6 . The image sensor system according to one of claims 3 to 5 , which is configured to be selectively operated in a standard operating mode and in at least one of a velocity operating mode and a pixel operating mode , wherein- in the standard operating mode the output block is configured, for each of the pixels of the selected subsection, to provide the output pixel signal , the velocity signal and the acceleration signal ;- in the velocity operating mode the output block is configured, for each of the pixels of the selected subsection, to provide the output pixel signal and the velocity signal , in particular without the acceleration signal ; and- in the pixel operating mode the output block is configured, for each of the pixels of the selected subsection, to provide the output pixel signal , in particular without the velocity signal and the acceleration signal .7 . The image sensor system according to one of claims 2 to 6 , wherein, for each of the pixels of the selected subsection,- the first signal velocity value vmapl is calculated according to- the second signal velocity value vmap2 is calculated according to- with s i being the corresponding processed signal value in the first plurality of processed signal values , s2 being the corresponding processed signal value in the second plurality of processed signal values , s3 being the corresponding processed signal value in the third pluralityof processed signal values , s4 being the corresponding processed signal value in the fourth plurality of processed signal values , tl being a start instant of the second integration period, t2 being an end instant of the second integration period, t3 being a start instant of the fourth integration period and t4 being an end instant of the fourth integration period .8 . The image sensor system according to claim 7 , wherein the signal acceleration value amap is calculated according to vmap2 — vmapl amap = t4 - tl9 . The image sensor system according to one of claims 1 to 8 , wherein the first integration period, the second integration period, the third integration period and the fourth integration period have the same duration .10 . The image sensor system according to one of claims 1 to 9 , wherein applying the selected coef ficient matrix comprises a matrix convolution operation or a matrix multiplication operation with the selected coef ficient matrix and a matrix representation of the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively .11 . The image sensor system according to one of claims 1 to10 , wherein the at least one edge detection matrix is one or more of the following :- one or more Prewitt Matrices ;- one or more Sobel Matrices ;- one or more Krisch Matrices ;- one or more Laplace Matrices .12 . The image sensor system according to one of claims 1 to11 , wherein the computation block is configured to , for each of the pixels of the selected subsection, i f the selected coef ficient matrix is the at least one edge detection matrix, to perform an intensity gradient and / or gradient thresholding computation based on the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values .13 . The image sensor system according to one of claims 1 to12 , wherein each of the pixels , the buf fer memory, the matrix memory, the control block and the computation block are implemented on a single chip .14 . An electronic device with a camera system comprising an image sensor system according to one of claims 1 to 13 .15 . A method for operating an image sensor that comprises- a pixel array with a plurality of pixels , each of the pixels comprising a photodiode ;- a buf fer memory comprising a first , a second, a third and a fourth plurality of memory cells , each plurality configured for representing a subsection of the pixel array; and- a matrix memory configured to store a unity matrix and at least one edge detection matrix ; the method comprising,- for each of the pixels , reading out and digiti zing of a first signal value associated with charges collected by the photodiode during a first integration period;- for each of the pixels , reading out and digiti zing of a second signal value associated with charges collected by the photodiode during a second integration period following the first integration period;- for each of the pixels , reading out and digiti zing of a third signal value associated with charges collected by the photodiode during a third integration period following the second integration period;- for each of the pixels , reading out and digiti zing of a fourth signal value associated with charges collected by the photodiode during a fourth integration period following the third integration period;- storing the digiti zed first , second, third and fourth signal values corresponding to pixels of a selected subsection of the pixel array into the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively;- selecting a coef ficient matrix from the matrix memory based on a matrix selection signal ;- generating a first , a second, a third and a fourth plurality of processed signal values corresponding to the pixels of the selected subsection by applying the selected coef ficient matrix onto the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively; and- for each of the pixels of the selected subsection, determining at least one derivative signal value based on a di f ference between at least two values , which correspond to the respective pixel and are selected from the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values , and based on a duration of at least one of the first integration period, the second integration period, the third integration period and the fourth integration period .16 . The method according to claim 15 , wherein determining the at least one derivative pixel value comprises- determining a first signal velocity value based on a di f ference between the corresponding processed signal values in the first and the second plurality of processed signal values , and on a duration of the second integration period;- determining a second signal velocity value based on a di f ference between the corresponding processed signal values in the third and the fourth plurality of processed signal values , and on a duration of the fourth integration period; and- determining a signal acceleration value based on a di f ference between the second signal velocity value and the first signal velocity value and on a duration of the second integration period, the third integration period and the fourth integration period .17 . The method according to claim 16 , further comprising- outputting an output pixel signal based on at least one of the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values ;- selectively outputting a velocity signal based on at least one of the first signal velocity value and the second signal velocity value ; and- selectively outputting an acceleration signal based on the signal acceleration value .18 . The method according to one of claims 15 to 17 , wherein applying the selected coef ficient matrix comprises a matrix convolution operation or a matrix multiplication operation with the selected coef ficient matrix and a matrixrepresentation of the digiti zed signal values stored in the first , the second, the third and the fourth plurality of memory cells of the buf fer memory, respectively . 19 . The method according to one of claims 15 to 18 , wherein the at least one edge detection matrix is one of the following :- one or more Prewitt Matrices ;- one or more Sobel Matrices ; - one or more Krisch Matrices ;- one or more Laplace Matrices .20 . The method according to one of claims 15 to 19 , further comprising, for each of the pixels of the selected subsection, i f the selected coef ficient matrix is the at least one edge detection matrix, performing an intensity gradient and / or gradient thresholding computation based on the corresponding processed signal values in the first , the second, the third and the fourth plurality of processed signal values .

Images