Three-dimensional stacked memory device using semiconductor element

Abstract

This three-dimensional stacked dynamic flash memory device comprises a plurality of stacked memory cells on a substrate. A first memory cell has a semiconductor layer which is composed of a first semiconductor layer that extends in a first direction in a plan view, and a second semiconductor layer that is connected to one side of the first semiconductor layer and extends in a second direction that is orthogonal to the first direction. The first memory cell has: first and second impurity regions that are respectively in contact with both ends of the first semiconductor layer in the first direction in a plan view; a third impurity region that is in contact with an end of the second semiconductor layer in a plan view, the end being on the opposite side of the end which is in contact with the first semiconductor layer; a first gate insulating layer that is in contact with the side surface of the first semiconductor layer in a plan view; a first gate conductor layer that is in contact with the first gate insulating layer; and second and third gate conductor layers that are in contact with respective side surfaces of second and third gate insulating layers that are respectively in contact with both side surfaces of the second semiconductor layer in a plan view.

Description

Three-dimensional stacked memory device using semiconductor elements

[0001] The present invention relates to a three-dimensional stacked memory device using semiconductor elements.

[0002] In recent years, in the development of LSI (Large Scale Integration), there has been a demand for memory devices using semiconductor elements to have higher integration, higher performance, lower power consumption, and higher functionality.

[0003] Along with this, the performance of semiconductor memory elements has been improved, and there are various types of memory elements, such as DRAM (Dynamic Random Access Memory) (see, for example, Non-Patent Document 2), which uses an SGT (Surrounding Gate Transistor) (see, for example, Patent Document 1 and Non-Patent Document 1) as a selection transistor and connects a capacitor, PCRAM (Phase Change RAM) (see, for example, Non-Patent Document 3), ReRAM (Resistive RAM) (see, for example, Non-Patent Document 4), MRAM (Magneto-resistive RAM) which changes the resistance by changing the direction of magnetic spin with a current (see, for example, Non-Patent Document 5), and FeRAM (Ferroelectric RAM) which stores data by changing the direction of ferroelectric polarization with an electric field (see, for example, Non-Patent Document 6).

[0004] There are also 1T-DRAM memory cells (see Patent Document 2 and Non-Patent Documents 7-12) that consist of a single MOS transistor without a capacitor formed on an SOI (Silicon-on-Insulator) substrate. For example, a current between the source and drain of an N-channel MOS transistor generates holes and electrons in the channel due to impact ionization. Some or all of the holes are retained in the channel to write logical data "1." Alternatively, holes are removed from the channel to write logical data "0." In this memory cell, "1"-write cells and "0"-write cells exist randomly for a common selected word line. However, when an on-voltage is applied to the selected word line, the potential of the floating cell channel of the selected memory cell connected to this selected word line fluctuates significantly due to capacitive coupling between the word line gate conductor and the channel. Therefore, issues remain regarding the potential fluctuations in the floating cell channel, which reduce the operating margin, and the degradation of retention characteristics due to the removal of some of the holes (signal charge) retained in the channel.

[0005] There are also twin-transistor MOS transistor memory devices in which two KOS transistors are used to form a memory cell on an SOI substrate (see, for example, Patent Documents 3 and 4, and Non-Patent Document 12). In these devices, an N+ layer, which serves as the source or drain, is formed between the floating cell channels of the two MOS transistors and is in contact with an insulating layer on the substrate side. This N+ layer electrically isolates the floating cell channels of the two MOS transistors. Signal holes are stored in only one floating cell channel, while the other MOS transistor acts as a switch to read the signal holes stored in the other MOS transistor. Because signal holes are stored in the channel of only one MOS transistor, this memory cell also suffers from issues such as reduced operating margins and poor data retention, similar to the 1T-DRAM memory cell described above.

[0006] Recently, a new memory cell called a dynamic flash memory (DFM) has been proposed, which is composed of MOS transistors on a silicon substrate, as shown in Figures 6(A) and 6(B) (see, for example, Patent Document 5). In this memory, as shown in (A), a silicon P layer 61 having P-type conductivity and containing acceptor impurities is located on a silicon substrate 80. In contact with the P layer 61 is a semiconductor having an N layer 63a containing donor impurities. In contact with a portion of the N layer 63a is a semiconductor having a vertically standing columnar N layer 63b containing donor impurities. Above the N layer 63a is a columnar P layer 64 containing acceptor impurities and having a rectangular horizontal cross section. A first insulating layer 62 covers portions of the N layer 63a and N layer 63b, and a first gate insulating layer 65 contacts the first insulating layer 62 and covers a portion of the P layer 64. A first gate conductor layer 82 is also located in contact with the first insulating layer 62 and the first gate insulating layer 65. There is a second insulating layer 66 in contact with the gate insulating layer 65 and the gate conductor layer 82. In contact with the P layer 64 is a P layer 68 containing acceptor impurities.

[0007] The N+ layer 67a of this memory is connected to the source line SL, which is the first wiring conductive layer; the N+ layer 67b is connected to the bit line BL, which is the second wiring conductive layer; the gate conductor layer 70 is connected to the word line WL, which is the third wiring conductive layer; the gate conductor layer 82 is connected to the plate line PL, which is the fourth wiring conductive layer; and the N layer 63a is connected to the control line CDC, which is the fifth wiring conductive layer. The memory is operated by controlling the voltages applied to the source line SL, bit line BL, plate line PL, word line WL, and control line CDC. Figure 6B shows a perspective view of the memory cell structure according to this embodiment.

[0008] In the dynamic flash memory described above, the threshold voltage of the MOSFET formed below the gate conductor layer 70 can be changed by controlling the hole concentration in the pillar-shaped P layer 64 containing the acceptor impurities and having a rectangular horizontal cross section, thereby enabling a larger hole accumulation amount than in the 1T-DRAM memory cell, thereby achieving an increased information retention time, an expanded memory operating margin, high-speed memory operation, and reduced power consumption. Furthermore, in both write and erase operations, the substrate bias does not become unstable in a floating state during MOSFET operation, as in the SOI structure, and the semiconductor portion below the gate insulating layer 69 does not become completely depleted. This means that the MOSFET threshold value, drive current, etc. are less susceptible to operating conditions, enabling stable writing, erasing, and reading of memory information.

[0009] In the future, there will be a demand for dynamic flash memories with such excellent characteristics to have significantly larger capacities. This application relates to a three-dimensional stacked memory device that enables larger capacities for dynamic flash memory devices that can be configured using only MOS transistors, without having resistance change elements or capacitors.

[0010] JP-A-2-188966 JP-A-3-171768 US2008 / 0137394 A1 US2003 / 0111681 A1 US2023 / 0077140 A1

[0011] IEEE Transactions on Electron Devices, Vol.38, No.3, pp.573-578 (1991)H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, KWSong, J. Kim, YC Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung: “4F2 DRAM Cell with Vertical Pillar Transistor(VPT),” HS Philip Wong, S. Raoux, 2011; S. Kim, Jiale Liang, JR Reifenberg, B. Rajendran, M. Asheghi and KE Goodson: “Phase Change Memory,” Proceeding of IEEE, Vol. Tsunoda, K .Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama : “Low Power and High Speed ​​Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of Less Than 3V,” IEDM (2007)W. Kang , L. Zhang , J. Klein , Y. Zhang , D. Ravelosona , and W .Zhao: “Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology,” IEEE Transaction on Electron Devices, pp.1-9 (2015)N.Nagel, I.Kunishima:"Key Technologies for High Density FeRAM Applications", Integrated Ferroelectrics 48(1) pp.127-137 (2002)M. G. Ertosun, K. Lim, C. Park, J. Oh, P. Kirsch, and K. C. Saraswat : “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electron,” IEEE Electron Device Letter, Vol. 31, No.5, pp.35-37 (2010)J. Wan, L. Rojer, A. Zaslavsky, and S. Critoloveanu: “A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration,” Electron Device Letters, Vol. 35, No.2, pp.179-181 (2012)T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory design using a one-transistor gain cell on SOI,” IEEE JSSC, vol.37, No.11, pp1510-1522 (2002).T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F. Matsuoka, Y. Kajitani, R.Fukuda, Y. Watanabe, Y. Minami, A. Sakamoto, J. Nishimura, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, A. Nitayama: “Floating Body RAM Technology and its Scalability to 32nm Node and Beyond,” IEEE IEDM (2006). Drain-Leakage (GIDL) Current for Low-Power and High-Speed ​​Embedded Memory,” IEEE IEDM (2006).F. Morishita, H. Noda, I. Hayashi, T. Gyohten, M. Oksmoto, T. Ipposhi, S. Maegawa, K. Dosaka, and K. Arimoto: “Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI,”IEICE Trans. Electron., Vol. E90-c., No.4 pp. 765-771 (2007).

[0012] In dynamic flash memory devices using semiconductor elements that can be configured only with MOS transistors, it is necessary to achieve a significant reduction in cost and an increase in capacity of memory cells.

[0013] In order to solve the above problems, a three-dimensional stacked memory device according to a first invention includes a plurality of memory cells on a substrate, in which semiconductor layers and first insulating layers are alternately stacked in a direction perpendicular to the substrate, wherein a first memory cell among the plurality of memory cells includes a first semiconductor layer extending in a first direction in a plan view, and a second semiconductor layer connected to one side of the first semiconductor layer and extending in a second direction orthogonal to the first direction, a first impurity region and a second impurity region respectively in contact with both ends of the first semiconductor layer in the first direction in a plan view, a third impurity region in contact with an end of the second semiconductor layer opposite to the end in contact with the first semiconductor layer in a plan view, a first gate insulating layer in contact with a side of the first semiconductor layer opposite to the side in contact with the second semiconductor layer in a plan view, and a first gate conductor layer in contact with the first gate insulating layer, In plan view, the semiconductor device has a second gate insulating layer in contact with both side surfaces of the second semiconductor layer, a third gate insulating layer, a second gate conductor layer in contact with the second gate insulating layer, and a third gate conductor layer in contact with the third gate insulating layer.

[0014] A second invention is characterized in that, in the first invention, a second memory cell having the same structure as the first memory cell is stacked vertically on a substrate, a gate conductor layer of the second memory cell corresponding to the first gate conductor layer of the first memory cell is connected vertically to the first gate conductor layer, a gate conductor layer of the second memory cell corresponding to the second gate conductor layer of the first memory cell is connected vertically to the second gate conductor layer, and a gate conductor layer of the second memory cell corresponding to the third gate conductor layer of the first memory cell is connected vertically to the third gate conductor layer.

[0015] A third invention is characterized in that, in the above-mentioned first invention, the first memory cell has a first wiring conductor layer extending in the second direction in the same plane parallel to the substrate and in contact with the first impurity region, and the first wiring conductor layer is in contact with an impurity region corresponding to the first impurity region of a third memory cell having the same structure as the first and second memory cells and adjacent to the first memory cell in the second direction in the same plane parallel to the substrate.

[0016] A fourth invention is characterized in that, in the above-mentioned first invention, the first memory cell has a third wiring conductor layer extending vertically to the substrate and in contact with an impurity region corresponding to the third impurity region of the second memory cell, and the third wiring conductor layer is in contact with an impurity region corresponding to the third impurity region of the second memory cell.

[0017] A fifth invention is characterized in that, in the above-mentioned first invention, the first memory cell has a second wiring conductor layer extending vertically to the substrate and in contact with the second impurity region, and the second wiring conductor layer is in contact with an impurity region corresponding to the second impurity region of the second memory cell.

[0018] A sixth invention is characterized in that, in the fifth invention, a fourth memory cell having a structure that is mirror-symmetrical to the first memory cell with respect to a plane perpendicular to the substrate extending in the second direction within the same plane parallel to the substrate is adjacent to the first memory cell in the first direction, and an impurity region of the fourth memory cell corresponding to the second impurity region of the first memory cell is in contact with the second wiring conductor layer that is in contact with the second impurity region of the first memory cell.

[0019] The seventh invention is characterized in that, in the above-mentioned fourth invention, a fifth memory cell having a structure that is mirror-symmetrical to the first memory cell with respect to a plane perpendicular to the substrate extending in the first direction within the same plane parallel to the substrate is adjacent to the first memory cell in the second direction, and an impurity region of the fifth memory cell corresponding to the third impurity region of the first memory cell is in contact with the third wiring conductor layer that is in contact with the third impurity region of the first memory cell.

[0020] The eighth invention is characterized in that, in the above-mentioned first invention, the second semiconductor layer of the first memory cell extending in the second direction is arranged so that the distance between the second semiconductor layer and the first impurity region is different from the distance between the second semiconductor layer and the second impurity region.

[0021] A ninth invention is a sixth memory cell according to the eighth invention, which has a structure in which the first memory cell is rotated 180 degrees about an axis perpendicular to the substrate within the same plane parallel to the substrate, wherein the sixth memory cell is adjacent to the first memory cell in the second direction within the same plane parallel to the substrate, the second gate conductor layer of the first memory cell is adjacent to a gate conductor layer of the sixth memory cell at a position opposite to the gate conductor layer corresponding to the second gate conductor layer of the first memory cell, and the first wiring conductor layer in contact with the first impurity region of the first memory cell is in contact with an impurity region of the sixth memory cell corresponding to the second impurity region of the first memory cell.

[0022] A tenth invention is characterized in that, in the above-mentioned third invention, the first memory cell has a fourth wiring conductor layer extending in the second direction in the same plane parallel to the substrate and in contact with the second impurity region, and the fourth wiring conductor layer is in contact with an impurity region of the third memory cell adjacent to the first memory cell in the second direction in the same plane parallel to the substrate, the impurity region corresponding to the second impurity region of the first memory cell.

[0023] An eleventh invention is characterized in that, in the seventh invention, the first memory cell has a fifth wiring conductor layer extending in the second direction in the same plane parallel to the substrate and in contact with the second impurity region, and the fifth wiring conductor layer is in contact with an impurity region corresponding to the second impurity region of the first memory cell of a fifth memory cell adjacent to the first memory cell in the second direction in the same plane parallel to the substrate.

[0024] A twelfth invention is characterized in that, in the above-mentioned ninth invention, the first memory cell has a sixth wiring conductor layer extending in the second direction in the same plane parallel to the substrate and in contact with the second impurity region, and the sixth wiring conductor layer is in contact with an impurity region corresponding to the second impurity region of the first memory cell of a sixth memory cell adjacent to the first memory cell in the second direction in the same plane parallel to the substrate.

[0025] Shown is a simplified partial perspective view omitting the description of the insulating layer for explaining the structure of a three-dimensional stacked memory device according to the first embodiment of the disclosure. Shown is a simplified partial plan view omitting the description of the insulating layer for explaining the structure of a three-dimensional stacked memory device according to the first embodiment of the disclosure. Shown is a simplified partial cross-sectional view in the direction perpendicular to the substrate along x1 - x2 described in FIG. 1B for explaining the structure of a three-dimensional stacked memory device according to the first embodiment of the disclosure. Shown is a simplified partial cross-sectional view in the direction perpendicular to the substrate along x3 - x4 described in FIG. 1B for explaining the structure of a three-dimensional stacked memory device according to the first embodiment of the disclosure. Shown is a simplified partial cross-sectional view in the direction perpendicular to the substrate along y1 - y2 described in FIG. 1B for explaining the structure of a three-dimensional stacked memory device according to the first embodiment of the disclosure. Shown is a simplified partial perspective view omitting the description of the insulating layer for explaining the second structure of a three-dimensional stacked memory device according to the second embodiment of the disclosure. Shown is a simplified partial perspective view omitting the description of the insulating layer for explaining the third structure of a three-dimensional stacked memory device according to the third embodiment of the disclosure. Shown is a simplified partial plan view omitting the description of the insulating layer for explaining the structure of a three-dimensional stacked memory device according to the third embodiment of the disclosure. Shown is a simplified partial cross-sectional view in the direction perpendicular to the substrate along x5 - x6 described in FIG. 2B - 2 for explaining the structure of a three-dimensional stacked memory device according to the third embodiment of the disclosure. Shown is a simplified partial cross-sectional view in the direction perpendicular to the substrate along x7 - x8 described in FIG. 2B - 2 for explaining the structure of a three-dimensional stacked memory device according to the third embodiment of the disclosure. Shown is a simplified partial cross-sectional view in the direction perpendicular to the substrate along x9 - x10 described in FIG. 2B - 2 for explaining the structure of a three-dimensional stacked memory device according to the third embodiment of the disclosure. Shown is a simplified partial perspective view omitting the description of the insulating layer for explaining the fourth structure of a three-dimensional stacked memory device according to the fourth embodiment of the disclosure. Shown is a simplified partial perspective view omitting the description of the insulating layer for explaining the fifth structure of a three-dimensional stacked memory device according to the fifth embodiment of the disclosure. Shown is a simplified partial perspective view omitting the description of the insulating layer for explaining the sixth structure of a three-dimensional stacked memory device according to the sixth embodiment of the disclosure. Shown is a process flow diagram of one embodiment of a method for forming a three-dimensional stacked memory device according to the embodiments described in this specification. Shown is a simplified partial perspective view for explaining a method for forming a three-dimensional stacked memory device according to the disclosed embodiment.FIG. 1 shows simplified partial perspective views illustrating a method of forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 2 shows simplified partial perspective views illustrating a method of forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 3 shows simplified partial perspective views illustrating a method of forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 4 shows simplified partial perspective views illustrating a method of forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 5 shows simplified partial perspective views illustrating a method of forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 6 shows simplified partial perspective views illustrating a method of forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 1 shows a simplified partial perspective view illustrating a method for forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 2 shows a simplified partial perspective view illustrating a method for forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 3 shows a simplified partial perspective view illustrating a method for forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 4 shows a simplified partial perspective view illustrating a method for forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 5 shows a simplified partial perspective view illustrating a method for forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 6 shows a simplified partial perspective view illustrating a method for forming a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 7 shows a simplified partial perspective view illustrating a method for forming a three-dimensional stacked memory device according to an embodiment of the disclosure, with insulating layers omitted, illustrating the structure of a three-dimensional stacked memory device according to an embodiment of the disclosure; FIG. 8 shows a simplified partial plan view illustrating a state of a three-dimensional stacked memory device according to an embodiment of the disclosure during a write operation. 1 shows simplified current-voltage characteristics illustrating the state of a three-dimensional stacked memory device during a write operation according to disclosed embodiments.1A and 1B are a schematic partial plan view and a schematic current-voltage characteristic diagram illustrating a state during an erase operation of a three-dimensional stacked memory device according to an embodiment of the present invention;

[0026] Hereinafter, a three-dimensional stacked memory device using semiconductor elements and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

[0027] (First embodiment) The structure of a memory cell array of a three-dimensional stacked memory cell device according to a first embodiment of the present invention will be described using Figure 1. Figure 1A is a simplified partial perspective view in which the insulating layers of the memory cell array of the three-dimensional stacked memory cell device according to the first embodiment of the present invention are omitted, Figure 1B is a simplified partial plan view of the structure of Figure 1A seen from above the substrate, Figure 1C is a simplified partial cross-sectional view taken along x1-x2 in Figure 1B in a direction perpendicular to the substrate, Figure 1D is a simplified partial cross-sectional view taken along x3-x4 in Figure 1B in a direction perpendicular to the substrate, and Figure 1E is a simplified partial cross-sectional view taken along y1-y2 in Figure 1B in a direction perpendicular to the substrate.

[0028] 1A and 1B, memory cell cells 2a each composed of a P-type first semiconductor layer (an example of a "semiconductor layer" in the claims) containing acceptor impurities are three-dimensionally arranged vertically and horizontally on a substrate 1 (an example of a "substrate" in the claims). The memory cell 2a has a roughly T-shaped structure in which a first semiconductor layer 2ax having impurity regions at both ends thereof and extending in the x1-x2 direction as shown in FIG. 1B is connected to a second semiconductor layer 2ay having an impurity region at one end thereof and extending in the y1-y2 direction. At the end of the first semiconductor layer 2ax, a source line 5a (an example of a "second wiring conductor layer" in the claims) is formed perpendicular to the substrate, and a bit line 6 (an example of a "first wiring conductor layer" in the claims) is formed horizontally to the substrate. A bottom line 7 (an example of a "third wiring conductor layer" in the claims) is formed perpendicular to the substrate at the end of the second semiconductor layer 2ay opposite to the surface where the second semiconductor layer 2ay is connected to the first semiconductor layer 2ax. A word line gate electrode 3 (an example of a "first gate conductor layer" in the claims) is formed on the side of the first semiconductor layer 2ax opposite to the side in contact with the second semiconductor layer 2ay, and a plate line gate electrode 4a (an example of a "second gate conductor layer" in the claims) and a plate line gate electrode 4b (an example of a "third gate conductor layer" in the claims) are formed perpendicular to the substrate on the side of the second semiconductor layer 2ay.

[0029] Furthermore, as shown in the cross-sectional views of Figures 1C and 1E, a source impurity region 10a (an example of the "second impurity region" in the claims), a drain impurity region 11a (an example of the "first impurity region" in the claims), and a bottom impurity region 12 (an example of the "third impurity region" in the claims) made of an N+ semiconductor layer containing donor impurities are formed between the memory cell 2a and the source line 5a, the bit line 6, and the bottom line 7.

[0030] Furthermore, as shown in the cross-sectional views of FIGS. 1D and 1E, a plate line gate insulating layer 9a (an example of the "second gate insulating layer" in the claims), a plate line gate insulating layer 9b (an example of the "third gate insulating layer" in the claims), and a word line gate insulating layer 8 (an example of the "first gate insulating layer" in the claims) are formed between the memory cell 2a and the plate line gate electrode 4a, the plate line gate electrode 4b, and the word line gate electrode 3, respectively. The memory cell 2a forms a MOS transistor with the source impurity region 10a, the drain impurity region 11a, and the word line gate electrode 3. Furthermore, as shown in FIG. 1B, a memory cell 2c (an example of the "third memory cell" in the claims) adjacent to the memory cell 2a in the direction along y1-y2 on the same plane parallel to the substrate shares a bit line 6 with the memory cell 2a.

[0031] 1B, memory cell 2d (an example of a "fourth memory cell" in the claims) adjacent to memory cell 2a in the x1-x2 direction on the same plane parallel to substrate 1 has a mirror-symmetric structure with memory cell 2a with respect to a plane perpendicular to substrate 1 extending in the y1-y2 direction, and memory cell 2d shares source line 5a in contact with memory cell 2a. Furthermore, as shown in FIGS. 1C to 1E, memory cell 2b (an example of a "second memory cell" in the claims) arranged in parallel with memory cell 2a in the vertical direction to substrate 1 shares source line 5a, bottom line 7, word line gate electrode 3, and plate line gate electrodes 4a and 4b with memory cell 2a.

[0032] As mentioned above, Figure 1A is a simplified partial perspective view that omits the illustration of insulating layers in the memory cell array of the three-dimensional stacked memory cell device, and in reality, the voids in Figure 1A are filled with insulating layers.

[0033] Second Embodiment FIG. 2A is a simplified partial perspective view of a memory cell array structure of a 3D stacked memory device using semiconductor elements according to a second embodiment of the present invention, omitting the insulating layers. The structure of a single memory cell in FIG. 2A is the same as that of the 3D stacked memory device using semiconductor elements according to the first embodiment of the present invention shown in FIG. 1A. FIG. 2A differs from FIG. 1A in the structure of the memory cell array in which memory cells are arranged three-dimensionally. Memory cell 2e (an example of the "fifth memory cell" in the claims) adjacent to memory cell 2a in the direction y1-y2 on the same plane parallel to substrate 1 has a mirror-symmetric structure with respect to memory cell 2a with respect to a plane perpendicular to substrate 1 extending in the direction x1-x2. Memory cell 2a and memory cell 2e share a bottom line 7.

[0034] Third Embodiment Figure 2B-1 shows a simplified partial perspective view of the memory cell array structure of a three-dimensional stacked memory device using semiconductor elements according to a third embodiment of the present invention, omitting the insulating layers. Figure 2B-2 shows a simplified partial plan view of the structure of Figure 2B-1 as seen from above the substrate. Figure 2B-3 shows a simplified partial cross-sectional view perpendicular to the substrate along x5-x6 in Figure 2B-2. Figure 2B-4 shows a simplified partial cross-sectional view perpendicular to the substrate along x7-x8 in Figure 2B-2. Figure 2B-5 shows a simplified partial cross-sectional view perpendicular to the substrate along x9-x10 in Figure 2B-2. In Figure 1A, the second semiconductor layer 2ay is connected to the first semiconductor layer 2ax at the center of the first semiconductor layer 2ax in a plan view. In contrast, in this embodiment, as shown in FIG. 2B-2, in memory cell 2f, the position where the first semiconductor layer extending in the x5-x6 direction shown in FIG. 2B-2 and the second semiconductor layer extending in the y3-y4 direction shown in FIG. 2B-2 are connected is eccentric from the midpoint between the drain impurity region 11b and the source impurity region 10b in the first semiconductor layer extending in the x5-x6 direction. The structures of the individual memory cells are essentially the same except for the connection position between the first semiconductor layer 2ax and the second semiconductor layer 2ay. As shown in FIG. 2B-2, memory cell 2g is adjacent to memory cell 2f in the y3-y4 direction shown in FIG. 2B-2 in the same plane parallel to the substrate 1. As shown in Figures 2B-2, 2B-3, and 2B-5, the shape of memory cell 2g is similar to the shape of memory cell 2f (an example of the "sixth memory cell" in the claims) rotated 180 degrees about an axis perpendicular to substrate 1. The drain impurity region 11c of memory cell 2g is located at a position corresponding to the source impurity region 11b of memory cell 2f, and the source impurity region 10c of memory cell 2g is located at a position corresponding to the drain impurity region 11b of memory cell 2f. A bit line 6 is connected to drain impurity region 11b and drain impurity region 11c. Furthermore, as shown in Figure 2B-4, the plate line 4c of memory cell 2f is adjacent to and faces the plate line 4d of memory cell 2g.

[0035] (Fourth Embodiment) FIG. 2C is a simplified partial perspective view, omitting the insulating layers, of the memory cell array structure of a three-dimensional stacked memory device using semiconductor elements according to a fourth embodiment of the present invention. The structure of a single memory cell in FIG. 2C is the same as that of the three-dimensional stacked memory device using semiconductor elements according to the first embodiment of the present invention shown in FIG. 1A. Unlike the memory cell array structure of the three-dimensional stacked memory device using semiconductor elements according to the first embodiment of the present invention shown in FIG. 1A, FIG. 2C differs from the memory cell array structure of the three-dimensional stacked memory device using semiconductor elements according to the first embodiment of the present invention shown in FIG. 1A in that a source line 5d (an example of the "fourth wiring conductor layer" in the claims) is formed parallel to the bit line 6 on the same plane parallel to the substrate 1 and is connected to the source impurity region 10a at the end of the memory cell 2a. Furthermore, the source line 5d is shared between adjacent memory cells 2c on the same plane parallel to the substrate.

[0036] Fifth Embodiment FIG. 2D is a simplified partial perspective view, omitting the insulating layers, of the memory cell array structure of a three-dimensional stacked memory device using semiconductor elements according to a fifth embodiment of the present invention. The structure of a single memory cell in FIG. 2D is the same as that of the three-dimensional stacked memory device using semiconductor elements according to the first embodiment of the present invention shown in FIG. 2A. Unlike the memory cell array structure of the three-dimensional stacked memory device using semiconductor elements according to the second embodiment of the present invention shown in FIG. 2A, a source line 5e (an example of a "fifth wiring conductor layer" in the claims) is formed parallel to the bit line 6 on the same plane parallel to the substrate 1 and is connected to the source impurity region 10a at the end of the memory cell 2a. Furthermore, the source line 5e is shared between adjacent memory cells 2e on the same plane parallel to the substrate.

[0037] Sixth Embodiment FIG. 2E is a simplified partial perspective view, omitting the insulating layers, of the memory cell array structure of a three-dimensional stacked memory device using semiconductor elements according to a sixth embodiment of the present invention. The structure of a single memory cell in FIG. 2E is the same as that of the three-dimensional stacked memory device using semiconductor elements according to the first embodiment of the present invention shown in FIG. 2B-1. Unlike the memory cell array structure of the three-dimensional stacked memory device using semiconductor elements according to the third embodiment of the present invention shown in FIG. 2B-1, the source line 5f (an example of the "sixth wiring conductor layer" in the claims) is formed parallel to the bit line 6 on the same plane parallel to the substrate 1 and is connected to the source impurity region 10b at the end of the memory cell 2f. Furthermore, the source line 5e is shared between adjacent memory cells 2g on the same plane parallel to the substrate.

[0038] In the structure of the present embodiment described above, the first semiconductor layer constituting the memory cell is a P-type semiconductor layer, and the source impurity region 10 a, the drain impurity region 11 a, and the bottom impurity region 12 are N+ semiconductor layers, but this combination is not limiting, and the first semiconductor layer may be an N-type semiconductor layer, and the source impurity region 10 a, the drain impurity region 11 a, and the bottom impurity region 12 may be P+ semiconductor layers.

[0039] The source line 5a, bottom line 7, and bit line 6 are preferably made of metal layers of W, Ti, TiN, Cu, Ta, TaN, Co, Mo, Ru, or combinations thereof, but are not limited to these materials and may be, for example, transition metal silicides or semiconductor layers heavily doped with impurities.

[0040] In the above-described embodiment, two adjacent bit lines 6 in the same plane parallel to the substrate are electrically insulated via an insulating layer, but these two adjacent bit lines may be at the same potential, or these two adjacent bit lines may be configured as a single bit line.

[0041] In the above embodiment, it is desirable that the area where the plate line gate electrode 4a contacts the memory cell 2a via the plate line gate insulating layer 9a is larger than the area where the word line gate electrode 3 contacts the memory cell 2a via the word line gate insulating layer 8.

[0042] In the above-described embodiment, an insulating layer is filled between the memory cells 2a and 2b that are adjacent in the vertical direction to the substrate, but this insulating layer may be removed and the plate line gate electrode 4a may be formed to surround the outer periphery of the memory cells 2a and 2b.

[0043] The substrate 1 used in the above-described embodiment may be a semiconductor substrate, or may be an amorphous substrate such as a glass substrate.

[0044] In the above-described embodiment, only the structure of the memory cell array of the three-dimensional stacked memory device of the present invention has been described in detail, but a part of the transistor region necessary for the peripheral circuitry to operate this memory cell array may be structured to be above the substrate surface and included in the same depth region as the memory cell array of the three-dimensional stacked memory device.

[0045] Furthermore, by using the method of the present invention, it is possible to simultaneously form some of the transistors required for the peripheral circuits for operating the memory cell array using memory cells 2a, word line gate insulating layers 8 or plate line gate insulating layers 9a, word line gate electrodes 3 or plate line gate electrodes 4a, and source lines 5a or bit lines 6 or bottom lines 7 using substantially the same process as that for the memory cell array.

[0046] Furthermore, the transistors required for the peripheral circuits may be gate-all-around transistors in which a gate electrode surrounds the periphery of a semiconductor region that constitutes the transistor, or double-gate transistors in which two gate electrodes face each other in a direction perpendicular to the substrate.

[0047] 3 shows a process flow diagram of a first exemplary embodiment for forming a three-dimensional stacked memory cell array according to the present invention. Those skilled in the art will recognize that a method for manufacturing a memory cell array of a three-dimensional stacked memory cell device according to the first embodiment can include any or all of the processes illustrated in FIG. 3. Furthermore, the order of the individual processes can be partially changed. The first embodiment can start with any of the listed processes without departing from the present disclosure.

[0048] Next, a method for manufacturing a three-dimensional stacked memory cell array according to a first embodiment of the present invention will be described with reference to Fig. 4. Fig. 4A to Fig. 4S are simplified partial perspective views for explaining an embodiment of each step of a method for forming a three-dimensional stacked memory device.

[0049] As shown in FIG. 4A, a first semiconductor layer 30 and a second semiconductor layer 31 are grown on a single crystal semiconductor substrate 1 by chemical vapor deposition (CVD). The first semiconductor layer 30 is, for example, a Si layer, and the second semiconductor layer 31 is, for example, a Si(1-x)Gex layer. The first semiconductor layer 30 is a semiconductor layer containing P-type impurities. The value of x in the second semiconductor layer 31 can be appropriately selected from a range of 0.05 to 0.5, but this value is more preferably in a range of 0.2 to 0.4 to reduce strain between the first semiconductor layer 30 and the second semiconductor layer 31. The thickness of each semiconductor layer 31 can be appropriately selected from a range of 5 nm or more, but more preferably in a range of 5 nm to 100 nm. The thickness of each first semiconductor layer 30 can be appropriately selected from a range of 5 nm or more, but more preferably in a range of 10 nm to 100 nm. There is no limit to the number of layers in the stacked structure 32 in which the first semiconductor layer 30 and the second semiconductor layer 31 are alternately stacked. The object of this embodiment can be achieved by depositing at least one first semiconductor layer 30 and at least one second semiconductor layer 31.

[0050] Next, as shown in FIG. 4B, only the second semiconductor layer 31 is selectively etched away from the first semiconductor layer 30, and the resulting void is filled with a first dielectric layer 33 using, for example, a CVD method or an atomic layer deposition (ALD) method. The selective etching of only the second semiconductor layer 31 can be performed using one or a combination of the following methods: dry etching without plasma, reactive ion etching using plasma, or wet etching using a chemical solution. The first dielectric layer 33 can be, for example, a silicon oxide (SiO2) film.

[0051] Next, as shown in FIG. 4C, a desired pattern is formed in a portion of the area where the memory cell array is to be formed using photolithography, and then the stacked film of the first semiconductor layer 30 and the first dielectric layer 33 is vertically etched using reactive ion etching to form a first slit region 34.

[0052] 4D, the first slit region 34 is filled with a second dielectric layer 35 of a different type from the first dielectric layer 33 by, for example, a CVD method or an ALD method. The second dielectric layer 35 may be, for example, a silicon nitride (SiN) film.

[0053] Next, as shown in Figure 4E, a desired pattern is formed in a portion of the area where the memory cell array is to be formed using photolithography, and then the stacked film of the first semiconductor layer 30 and the first dielectric layer 33 is vertically etched using reactive ion etching to form a second slit region 36, thereby exposing the side of the first semiconductor layer 30.

[0054] 4F, only the region of the first semiconductor layer 30 exposed in the slit region 36 that is a desired distance from the sidewall is selectively etched away with respect to the first dielectric layer 33 to form a recessed region 37. The method for selectively etching away only the desired region of the first semiconductor layer 30 can be one or a combination of dry etching that does not use plasma, reactive ion etching that uses plasma, or wet etching that uses a chemical solution.

[0055] Next, as shown in FIG. 4G , a third dielectric layer 38 is filled in the second slit region 36 and the recessed region 37 using, for example, a CVD method or an ALD method. The third dielectric layer 38 is a film of a different type from the first dielectric layer 33, such as a SiN film. However, the first and third dielectric layers 33 and 38 do not necessarily have to be made of the aforementioned types of films. The object of the present invention can be achieved as long as the first and third dielectric layers 33 and 38 are made of different etching rates, using at least one of dry etching (not using plasma), reactive ion etching (using plasma), and wet etching (using a chemical solution), and the third dielectric layer 38 filled in the recessed region 37 has a faster etching rate than the first dielectric layer 33.

[0056] Next, as shown in FIG. 4H, a desired pattern is formed in a portion of the area where the memory cell array is to be formed using photolithography, and then the stacked structure consisting of the first semiconductor layer 30 and the first dielectric layer 33 is vertically etched to a desired depth using anisotropic reactive ion etching using plasma to form memory cells 2.

[0057] 4I, the gap around the memory cell 2 is filled with a fourth dielectric layer 39 by, for example, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or a solution coating method. The fourth dielectric layer 39 is a film of a different type from the third dielectric layer 38, and may be, for example, an SiO2 film.

[0058] Next, as shown in FIG. 4J, a desired pattern is formed using photolithography in an area adjacent to a portion of memory cell 2 in the area that constitutes the memory cell array, and then bottom electrode hole 40 is formed by vertically etching fourth dielectric layer 39 to a desired depth using anisotropic reactive ion etching using plasma.

[0059] 4K, the bottom electrode hole 40 is filled with a fifth dielectric layer 41 by, for example, a CVD method, an ALD method, or a solution coating method. The fifth dielectric layer 41 is preferably a film of the same type as the third dielectric layer 38, and may be, for example, a SiN film.

[0060] Next, as shown in FIG. 4L, only the fourth dielectric layer 39 in the area where the memory cell array is to be formed is vertically etched to a desired depth using an anisotropic reactive ion etching method using plasma, thereby exposing the side 42 of the memory cell 2.

[0061] 4M, a word line gate insulating layer 8 and a plate line gate insulating layer 9 are formed on the memory cell side portion 42. The word line gate insulating layer 8 and the plate line gate insulating layer 9 may be an oxide of the first semiconductor layer 30 constituting the memory cell 2, or a transition metal oxide layer, or a laminated film thereof, and can be formed by, for example, a thermal oxidation method, a plasma oxidation method, or a deposition method using a CVD method, an ALD method, or a combination thereof.

[0062] Next, a polycrystalline Si layer, for example, is deposited on the entire surface as a gate electrode layer, for example, by CVD. Then, as shown in FIG. 4N, photolithography and anisotropic reactive ion etching using plasma are used to leave only desired regions of the polycrystalline Si layer, thereby forming word line gate electrodes 3 and plate line gate electrodes 4. At this time, the word line gate electrodes 3 and plate line gate electrodes 4 are electrically isolated between different memory cells 2 adjacent to each other in the same plane, and are electrically connected between different memory cells 2 adjacent to each other in the vertical direction to the substrate and insulated by a first dielectric layer 33. The material of the word line gate electrodes 3 and plate line gate electrodes 4 is not limited to polycrystalline Si, and may be other metal films or laminated metal films that can be deposited by CVD, ALD, or the like, such as a laminated film of a TiN film and W.

[0063] Next, as shown in FIG. 4O, photolithography and anisotropic reactive ion etching using plasma are used to leave only desired regions of the second dielectric layer 35 and the third dielectric layer 38, thereby forming dummy bit line regions 45 and dummy source line regions 46.

[0064] 4P, the gaps between the memory cells 2 are filled with a sixth dielectric layer 47 by using, for example, a CVD method, an ALD method, or a solution coating method. The sixth dielectric layer 47 is preferably a film of the same type as the first dielectric layer 33, and may be, for example, an SiO2 film, but is not limited thereto. The object of the present invention can be achieved as long as the sixth dielectric layer 47 is made of a material that has an etching rate slower than at least the second dielectric layer 35, the third dielectric layer 38, and the fifth dielectric layer 41 with respect to an etching solution or etching gas.

[0065] 4Q, the second dielectric layer 35 constituting the dummy source line region 46 and the third dielectric layer 38 and fifth dielectric layer 41 constituting the dummy bit line region 45 are selectively removed relative to the sixth dielectric layer 47 by reactive ion etching using plasma or wet etching using a chemical solution, or a combination of these, to form dummy source line holes 48, dummy bottom line holes 49, and dummy bit line holes 50. At this time, ends of the first semiconductor layer 30 constituting the memory cell 2 are exposed inside the formed dummy source line holes 48, dummy bottom line holes 49, and dummy bit line holes 50.

[0066] 4R, source impurity region 10, drain impurity region 11, and bottom impurity region 12, each composed of a semiconductor region containing impurities exhibiting the opposite polarity to the impurities contained in first semiconductor layer 30, are formed on the exposed surfaces of the ends of first semiconductor layer 30 inside dummy source line hole 48, dummy bottom line hole 49, and dummy bit line hole 50. At this time, the impurity contained in first semiconductor layer 30 is, for example, boron (Boron (B)) exhibiting P type, and the impurity contained in source impurity region 10, drain impurity region 11, and bottom impurity region 12 is, for example, arsenic (Arsenic (As)) exhibiting N type.

[0067] The source impurity region 10, the drain impurity region 11, and the bottom impurity region 12 may be formed by selectively growing a semiconductor layer containing impurities exhibiting an opposite polarity to the impurities contained in the first semiconductor layer 30 deposited using, for example, a selective vapor phase epitaxial growth method, or by depositing a polycrystalline or amorphous semiconductor film containing impurities exhibiting an opposite polarity and then performing a heat treatment to selectively precipitate single-crystal semiconductor regions on the exposed surfaces of the first semiconductor layer 30 in the dummy source line holes 48, the dummy bottom line holes 49, and the dummy bit line holes 50, and then removing only the deposited polycrystalline or amorphous semiconductor film, or by depositing a metal thin film containing impurities exhibiting an opposite polarity using, for example, a CVD method, and then performing a heat treatment to diffuse the impurities into the exposed surfaces of the first semiconductor layer 30, or by performing a heat treatment in a gas atmosphere containing the metal element of the impurity exhibiting the opposite polarity.

[0068] Next, as shown in FIG. 4S, a metal wiring layer is filled into dummy source line holes 48, dummy bottom line holes 49, and dummy bit line holes 50 to form source lines 5, bit lines 6, and bottom lines 7. The metal wiring layer filling source lines 5, bit lines 6, and bottom lines 7 can be formed using one or a combination of two or more of the following methods: CVD, ALD, electrolytic plating, and electroless plating. The metal layer can be formed, for example, from a stacked film of titanium nitride (TiN) and tungsten (W), a stacked film of titanium nitride (TiN) and tungsten silicide (WSix), or a stacked film of tantalum nitride (TaN) and copper (Cu). However, the metal layer is not limited to these materials. The object of the present invention can be achieved by using any material that can provide good electrical connection with source impurity region 10, drain impurity region 11, and bottom impurity region 12.

[0069] Through the steps up to this point, a cell array of a three-dimensionally stacked three-dimensional memory device is formed, which is composed of memory cells 2, word line gate electrodes 3, plate line gate electrodes 4, source lines 5, bit lines 6, and bottom lines 7, and in which multiple memory cells arranged perpendicular to the substrate 1 are electrically connected by the word line gate electrodes 3, plate line gate electrodes 4, and source lines 5 formed perpendicular to the substrate, and multiple memory cells arranged on the same plane are electrically connected by the bit lines 6 formed parallel to the substrate 1. Figure 4T is a simplified partial perspective view of the cell array of the three-dimensionally stacked three-dimensional memory device formed, omitting the illustration of the sixth dielectric layer 47, for easier understanding.

[0070] In the above embodiment, a SiO2 film is used for the sixth dielectric layer 47, but this SiO2 film may be a low-κ SiO2 film having a lower dielectric constant than that of ordinary SiO2. In the above embodiment, the source impurity region 10, the drain impurity region 11, and the bottom impurity region 12, which contain impurities of the opposite polarity to that of the impurities contained in the first semiconductor layer 30, are formed after the second dielectric layer 35, the third dielectric layer 38, and the fifth dielectric layer 41 are etched away. However, the present invention is not limited to this process. For example, the process may be performed after the formation of the second slit region 36 shown in FIG. 4E, after the formation of the recessed region 37 shown in FIG. 4F, and after the formation of the bottom electrode hole 40 shown in FIG. 4J. The object of the present invention can be achieved by performing the process at least before the formation of the source line 5, the bottom line 7, and the bit line 6.

[0071] Furthermore, in the above-described embodiment, a method for forming a structure in which the source lines 5 and the bit lines 6 intersect each other at right angles has been described. However, it goes without saying that it is also possible to form a structure in which the source lines 5 and the bit lines 6 are parallel to each other, as shown in the fourth embodiment illustrated in FIG. 2C. In this case, it is not necessary to separately form dummy source line holes for forming source lines and dummy bit line holes for forming bit lines. Since the source lines and the bit lines can be formed in the same process, it is possible to form a cell array of a 3D stacked memory device in a shorter process. Furthermore, in the above-described embodiment, as illustrated in FIG. 4S, for example, the space between two adjacent bit lines 6 formed in parallel is filled with the sixth dielectric layer 47. However, the space between these two adjacent bit lines may not be completely filled with the dielectric layer 47, and an air gap may be formed. Similarly, for example, an air gap may be formed between the source line 5d illustrated in FIG. 2C, the source line 5e illustrated in FIG. 2D, or the source line 5f illustrated in FIG. 2E and the adjacent source lines formed in parallel thereto.

[0072] Next, a method for operating the three-dimensional stacked memory cell will be described. FIG. 5 of this embodiment is a schematic diagram illustrating a method for operating the three-dimensional stacked memory cell of the first embodiment. In this memory cell, memory operation is achieved by manipulating the voltages applied to the source line 5, bit line 6, plate line gate electrode 4, word line gate electrode 3, and bottom line 7 shown in FIG. 5A. In the structure of this embodiment, the threshold voltage of the MOSFET formed below the word line gate electrode 3 can be changed by controlling the hole concentration in the memory cell 2 made of a P-type semiconductor.

[0073] As shown in Figure 5A, 0 V is applied to the source line 5a, a positive voltage is applied to the bit line 6, and a negative voltage is applied to the plate line gate electrodes 4a and 4b. Next, a voltage higher than the pre-program threshold voltage of the MOSFET connected to the word line electrode 3 is applied to the word line electrode 3. This causes a partial inversion layer 22 to form directly below the word line gate insulating layer 8 connected to the word line electrode 3, forming a pinch-off point 20. As a result, the electric field becomes maximum between the pinch-off point 20 and the drain impurity region 11 in the MOSFET with the word line electrode 3. Impact ionization occurs in this region, generating electron-hole pairs. The generated holes diffuse toward the lower hole concentration due to their concentration gradient. While some of the generated electrons flow to the word line electrode 3, the majority flow to the drain impurity region 11 connected to the bit line 6. As a result, a group of holes 21 accumulates in the memory cell 2a.

[0074] As a result, as shown in Figure 5B, the threshold voltage of the MOSFET connected to the word line electrode 3 becomes lower than before writing due to the positive substrate bias effect caused by the holes temporarily stored in the memory cell 2a. This write state is assigned to logical storage data "1".

[0075] Next, as shown in Figure 5C, during the erase operation, the voltages on the source line 5, bit line 6, word line electrode 3, and bottom line 7 are set to 0V. A positive voltage is applied to the plate line gate electrodes 4a and 4b. As a result, an electron inversion layer 23 is formed at the interface between the plate line gate insulating layer 9 and memory cell 2, regardless of the initial potential of memory cell 2a. As a result, holes stored in memory cell 2a flow from memory cell 2a to the inversion layer 23 and recombine with electrons. Some holes also flow to the drain impurity region 11, source impurity region 10, and bottom impurity region 12, where they also recombine with electrons. As a result, the hole concentration in memory cell 2a decreases over time, and as shown in Figure 5D, the MOSFET threshold voltage becomes higher than when "1" was written, returning to its initial state. This erased state of the memory corresponds to logically stored data "0." By the above operation, logical memory data "1" or "0" is written into memory cell 2a, and the written information can be determined by applying an appropriate word line voltage and measuring the current flowing through the MOSFET.

[0076] This embodiment has the following features: (Feature 1) A three-dimensional stacked memory device according to an embodiment of the present invention is configured in such a manner that a plurality of memory cells arranged in parallel perpendicular to a substrate are electrically connected by word line gate electrodes, plate line gate electrodes, and bottom lines formed perpendicular to the substrate, and a plurality of memory cells arranged on the same plane parallel to the substrate are electrically connected by bit lines formed parallel to the substrate. Therefore, by increasing the number of stacked layers compared to conventional two-dimensionally arranged dynamic flash memory devices, a three-dimensional high density memory cell array can be easily achieved, thereby achieving a significant increase in the capacity of the memory device and a significant reduction in the cost per bit.

[0077] (Feature 2) In a three-dimensional stacked memory device according to an embodiment of the present invention, the volume of the semiconductor region sandwiched between plate lines that accumulate carriers in the memory cell can be freely adjusted without changing the thickness perpendicular to the substrate. This makes it easy to increase the number of carriers accumulated during writing, thereby widening the margin of memory operation without significantly changing the manufacturing process.

[0078] (Feature 3) In the three-dimensional stacked memory device according to the embodiment of the present invention, a metal layer with low resistance can be used for the bottom electrode, which enables reduced power consumption and faster memory operation compared to conventional dynamic flash memories that use a semiconductor layer with high resistance for the bottom electrode.

[0079] The present invention is not limited to the above-described embodiments, and various embodiments and modifications are possible without departing from the broad spirit and scope of the present invention. Each of the above-described embodiments is intended to explain one example of the present invention and does not limit the scope of the present invention. It goes without saying that the present invention can be applied to structures that combine these embodiments and structures that are variously modified within the scope of the gist of the present invention, and the above-described embodiments and modifications can be combined arbitrarily. Furthermore, even if some of the constituent elements of the above-described embodiments are omitted as necessary, the scope of the technical concept of the present invention remains.

[0080] By using the semiconductor element according to the present invention, it is possible to provide a three-dimensional stacked memory device with higher density and lower bit cost than conventional devices.

[0081] 1: Substrate 2, 2a, 2b, 2c, 2d, 2e, 2f, 2g: Memory cell cells 2ax, 2ay: Semiconductor layer 3: Word line gate electrode 4, 4a, 4b, 4c, 4d: Plate line gate electrode 5, 5a, 5d, 5e, 5f: Source line 6: Bit line 7: Bottom line 8: Word line gate insulating layer 9, 9a, 9b: Plate line gate insulating layer 10, 10a, 10b, 10c: Source impurity region 11, 11a, 11b, 11c: Drain impurity region 12: Bottom impurity region 20: Pinch-off point 21: Hole group 22, 23: Inversion layer 30: First semiconductor layer 31: Second semiconductor layer 32: Stacked structure 33: First dielectric layer 34: First slit region 35: Second dielectric layer 36: Second slit region 37: Recessed region 38: Third dielectric layer 39: Fourth dielectric layer 40: Bottom electrode hole 41: Fifth dielectric layer 42: Memory cell side 45: Dummy bit line region 46: Dummy source line region 47: Sixth dielectric layer 48: Dummy source line hole 49: Dummy bottom line hole 50: Dummy bit line hole 51, 52: Memory cell 61: P layer 62: First insulating layer 63a, 63b: N layer 64: P layer 65: First gate insulating layer 66: Second insulating layer 67a, 67b: N+ layer 68: P layer 69: Gate insulating layer 70: Gate conductor layer 80: Si substrate 82: First gate conductor layer SL: First wiring conductive layer BL: Second wiring conductive layer WL: Third wiring conductive layer PL: Fourth wiring conductive layer CDC: Fifth wiring conductive layer

Claims

1. A substrate includes a plurality of memory cells in which semiconductor layers and first insulating layers are alternately stacked on the substrate in a direction perpendicular to the substrate, and a first memory cell of the plurality of memory cells includes a first semiconductor layer extending in a first direction in a plan view, and a second semiconductor layer connected to one side of the first semiconductor layer and extending in a second direction perpendicular to the first direction, and includes a first impurity region and a second impurity region respectively in contact with both ends of the first semiconductor layer in the first direction in a plan view, a third impurity region in contact with an end of the second semiconductor layer opposite to the end in contact with the first semiconductor layer in a plan view, a first gate insulating layer in contact with a side of the first semiconductor layer opposite to the side in contact with the second semiconductor layer in a plan view, and a first gate conductor layer in contact with the first gate insulating layer, and a second gate insulating layer in contact with both side surfaces of the second semiconductor layer in a plan view. a second gate conductor layer in contact with the second gate insulating layer, and a third gate conductor layer in contact with the third gate insulating layer.

2. The three-dimensional stacked memory device of claim 1, characterized in that a second memory cell having the same structure as the first memory cell is stacked vertically on the substrate, a gate conductor layer of the second memory cell corresponding to the first gate conductor layer of the first memory cell is vertically connected to the first gate conductor layer, a gate conductor layer of the second memory cell corresponding to the second gate conductor layer of the first memory cell is vertically connected to the second gate conductor layer, and a gate conductor layer of the second memory cell corresponding to the third gate conductor layer of the first memory cell is vertically connected to the third gate conductor layer.

3. The three-dimensional stacked memory device of claim 1, characterized in that the first memory cell has a first wiring conductor layer extending in the second direction in the same plane parallel to the substrate and in contact with the first impurity region, and the first wiring conductor layer is in contact with an impurity region corresponding to the first impurity region of a third memory cell having the same structure as the first and second memory cells and adjacent to the first memory cell in the second direction in the same plane parallel to the substrate.

4. The three-dimensional stacked memory device of claim 1, characterized in that: the first memory cell has a third wiring conductor layer extending vertically to the substrate and in contact with an impurity region corresponding to the third impurity region of the second memory cell; and the third wiring conductor layer is in contact with an impurity region corresponding to the third impurity region of the second memory cell.

5. The three-dimensional stacked memory device of claim 1, wherein the first memory cell has a second wiring conductor layer extending vertically to the substrate and in contact with the second impurity region, and the second wiring conductor layer is in contact with an impurity region corresponding to the second impurity region of the second memory cell.

6. The three-dimensional stacked memory device according to claim 5, characterized in that a fourth memory cell having a structure that is mirror-symmetric to the first memory cell with respect to a plane perpendicular to the substrate extending in the second direction within the same plane parallel to the substrate is adjacent to the first memory cell in the first direction, and an impurity region of the fourth memory cell corresponding to the second impurity region of the first memory cell is in contact with the second wiring conductor layer that is in contact with the second impurity region of the first memory cell.

7. The three-dimensional stacked memory device of claim 4, characterized in that a fifth memory cell having a structure that is mirror-symmetric to the first memory cell with respect to a plane perpendicular to the substrate extending in the first direction within the same plane parallel to the substrate is adjacent to the first memory cell in the second direction, and an impurity region of the fifth memory cell corresponding to the third impurity region of the first memory cell is in contact with the third wiring conductor layer that is in contact with the third impurity region of the first memory cell.

8. The three-dimensional stacked memory device of claim 1, characterized in that the second semiconductor layer of the first memory cell extending in the second direction is arranged such that the distance between the second semiconductor layer and the first impurity region is different from the distance between the second semiconductor layer and the second impurity region.

9. The three-dimensional stacked memory device according to claim 8, characterized in that a sixth memory cell has a structure in which the first memory cell is rotated 180 degrees with respect to an axis perpendicular to the substrate within the same plane parallel to the substrate, the sixth memory cell being adjacent to the first memory cell in the second direction within the same plane parallel to the substrate, the second gate conductor layer of the first memory cell being adjacent to a gate conductor layer of the sixth memory cell at a position facing the gate conductor layer corresponding to the second gate conductor layer of the first memory cell, and the first wiring conductor layer in contact with the first impurity region of the first memory cell being in contact with an impurity region of the sixth memory cell corresponding to the second impurity region of the first memory cell.

10. The three-dimensional stacked memory device of claim 3, characterized in that the first memory cell has a fourth wiring conductor layer extending in the second direction in the same plane parallel to the substrate and in contact with the second impurity region, and the fourth wiring conductor layer is in contact with an impurity region of the third memory cell adjacent to the first memory cell in the second direction in the same plane parallel to the substrate, the impurity region corresponding to the second impurity region of the first memory cell.

11. The three-dimensional stacked memory device of claim 7, characterized in that the first memory cell has a fifth wiring conductor layer extending in the second direction in the same plane parallel to the substrate and in contact with the second impurity region, and the fifth wiring conductor layer is in contact with an impurity region corresponding to the second impurity region of the first memory cell of a fifth memory cell adjacent to the first memory cell in the second direction in the same plane parallel to the substrate.

12. The three-dimensional stacked memory device of claim 9, characterized in that the first memory cell has a sixth wiring conductor layer extending in the second direction within the same plane parallel to the substrate and in contact with the second impurity region, and the sixth wiring conductor layer is in contact with an impurity region corresponding to the second impurity region of the first memory cell of a sixth memory cell adjacent to the first memory cell in the second direction within the same plane parallel to the substrate.

Images