Abnormality detection circuit, abnormality detection method, and imaging system

Abstract

An abnormality detection circuit according to an embodiment of the present disclosure comprises: a counter capable of performing a count operation on the basis of pulses corresponding to a synchronization signal, thereby detecting a time length between two pulses corresponding to the synchronization signal; and a determination circuit capable of determining an abnormality of the synchronization signal on the basis of a count value of the counter.

Description

ABNORMALITY DETECTION CIRCUIT, ABNORMALITY DETECTION METHOD, AND IMAGING SYSTEM

[0001] The present disclosure relates to an abnormality detection circuit, an abnormality detection method, and an imaging system that detect an abnormality in a circuit related to a synchronization signal.

[0002] In an imaging device, an imaging operation is performed based on various control signals. For example, Patent Document 1 discloses an imaging device that detects an abnormality in a pixel control signal that controls the operation of pixels.

[0003] International Publication No. 2017 / 209221

[0004] In an imaging device, imaging operations are performed based on vertical and horizontal synchronization signals, and therefore it is desirable to detect abnormalities in such synchronization signals.

[0005] It is desirable to provide an anomaly detection circuit, an anomaly detection method, and an imaging system that can detect anomalies in a synchronization signal.

[0006] According to an embodiment of the present disclosure, an abnormality detection device includes a counter and a determination circuit. The counter performs a counting operation based on pulses corresponding to a synchronization signal, thereby detecting the length of time between two pulses corresponding to the synchronization signal. The determination circuit determines whether the synchronization signal is abnormal based on the count value of the counter.

[0007] An abnormality detection method in one embodiment of the present disclosure includes detecting the time length between two pulses corresponding to the synchronization signal by performing a counting operation based on pulses corresponding to the synchronization signal, and determining an abnormality in the synchronization signal based on the count value in the counting operation.

[0008] An imaging system according to an embodiment of the present disclosure includes an imaging device and an image processing device. The imaging device is capable of performing an imaging operation based on a synchronization signal. The image processing device is capable of performing image processing based on an imaging result of the imaging device. The image processing device has a counter and a determination circuit. The counter is capable of detecting a time length between two pulses corresponding to the synchronization signal by performing a count operation based on pulses corresponding to the synchronization signal. The determination circuit is capable of determining an abnormality in the synchronization signal based on the count value of the counter.

[0009] In the anomaly detection device, the anomaly detection method, and the imaging system according to an embodiment of the present disclosure, a counting operation is performed based on pulses corresponding to a synchronization signal, thereby detecting the time length between two pulses corresponding to the synchronization signal, and an anomaly in the synchronization signal is determined based on the count value in this counting operation.

[0010] FIG. 1 is a block diagram illustrating an example configuration of an imaging system according to a first embodiment of the present disclosure. FIG. 2 is a timing diagram illustrating an example operation of the abnormality detection circuit illustrated in FIG. 1. FIG. 3 is another timing diagram illustrating an example operation of the abnormality detection circuit illustrated in FIG. 1. FIG. 4 is a block diagram illustrating an example configuration of an imaging system according to a modified example of the first embodiment. FIG. 5 is an explanatory diagram illustrating an example signal format of an image signal. FIG. 6 is a timing diagram illustrating an example operation of the abnormality detection circuit according to a modified example of the first embodiment. FIG. 7 is an explanatory diagram illustrating another example signal format of an image signal. FIG. 8 is a timing diagram illustrating an example operation of the abnormality detection circuit according to another modified example of the first embodiment. FIG. 9 is an explanatory diagram illustrating another example signal format of an image signal. FIG. 10 is a timing diagram illustrating an example operation of the abnormality detection circuit according to another modified example of the first embodiment. FIG. 11 is a block diagram illustrating an example configuration of an imaging system according to a second embodiment. FIG. 12 is a timing diagram illustrating an example operation of the abnormality detection circuit illustrated in FIG. 11. FIG. 13 is another timing diagram illustrating an example operation of the abnormality detection circuit illustrated in FIG. 11. Fig. 14 is a timing chart showing an example of operation of an abnormality detection circuit according to a modified example of the second embodiment. Fig. 15 is a timing chart showing an example of operation of an abnormality detection circuit according to another modified example of the second embodiment. Fig. 16 is an explanatory diagram showing an example of the configuration of an inspection system according to an application example. Fig. 17 is a block diagram showing an example of the schematic configuration of a vehicle control system. Fig. 18 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. First embodiment 2. Second embodiment 3. Application example 4. Application example to a moving body

[0012] 1 shows an example of the configuration of an imaging system 1 including an abnormality detection circuit according to a first embodiment. An abnormality detection method according to an embodiment of the present disclosure is also embodied in this embodiment, and will be described together with the method. The imaging system 1 includes an imaging device 10 and an image processing device 20.

[0013] The imaging device 10 is a so-called image sensor configured to capture an image of a subject. The imaging device 10 includes a clock signal generating unit 11, a synchronization signal generating unit 12, an imaging unit 13, and an image signal generating unit 14.

[0014] The clock signal generating unit 11 is configured to generate a clock signal CK used in the imaging device 10 .

[0015] The synchronization signal generating unit 12 is configured to generate synchronization signals XVS and XHS based on a clock signal CK. The synchronization signal XVS is a so-called vertical synchronization signal, and the synchronization signal XHS is a so-called horizontal synchronization signal.

[0016] The imaging unit 13 has, for example, a plurality of imaging pixels, and is configured to perform imaging operations based on the synchronization signals XVS and XHS, thereby generating image data of the captured image.

[0017] The image signal generating section 14 is configured to generate an image signal Spic based on the image data of the captured image supplied from the imaging section 13, using the synchronization signals XVS and XHS.

[0018] The imaging device 10 captures an image of a subject using this configuration. The imaging device 10 then supplies the image processing device 20 with an image signal Spic indicating the captured image and synchronization signals XVS and XHS.

[0019] The image processing device 20 is configured to perform predetermined image processing on the captured image represented by the image signal supplied from the imaging device 10. The image processing device 20 has an image processing unit 21, a clock signal generating unit 22, a counter 23, a comparing unit 24, and a control unit 25. The counter 23 and the comparing unit 24 configure an abnormality detection circuit 29.

[0020] The image processing unit 21 is configured to perform predetermined image processing based on the image signal Spic and the synchronization signals XVS and XHS supplied from the imaging device 10. The image processing unit 21 then outputs the image processing results.

[0021] The clock signal generating unit 22 is configured to generate a clock signal CK2 used in the image processing device 20 .

[0022] The counter 23 is configured to perform a counting operation OP that counts the number of clock pulses of the clock signal CK2 based on the pulses included in the synchronization signal XVS, thereby detecting the time length between two pulses included in the synchronization signal XVS. The counter 23 outputs a count value CNT while the counting operation OP is being performed.

[0023] The comparator 24 is configured to compare the count value CNT of the counter 23 with a predetermined threshold value TH, and to generate a signal CTL indicating whether the count value CNT has exceeded the threshold value TH.

[0024] The control unit 25 is configured to control the operation of the image processing device 20. Furthermore, the control unit 25 is configured to stop the operation of the image processing device 20 based on the signal CTL supplied from the comparison unit 24.

[0025] With this configuration, the abnormality detection circuit 29, which is made up of the counter 23 and the comparison unit 24, determines whether pulses of the synchronization signal XVS appear at predetermined intervals corresponding to the time length of the frame period F. This allows the abnormality detection circuit 29 to detect an abnormality in the clock signal generation unit 11 or the synchronization signal generation unit 12 in the imaging device 10.

[0026] Here, the abnormality detection circuit 29 corresponds to a specific example of an "abnormality detection circuit" in an embodiment of the present disclosure. The counter 23 corresponds to a specific example of a "counter" in an embodiment of the present disclosure. The comparison unit 24 corresponds to a specific example of a "determination circuit" in an embodiment of the present disclosure. The synchronization signal XVS corresponds to a specific example of a "synchronization signal" in an embodiment of the present disclosure.

[0027] [Operation and Function] Next, the operation and function of the imaging system 1 of this embodiment will be described.

[0028] (Overall Operation Overview) First, an overview of the overall operation of the imaging system 1 will be described with reference to Fig. 1. A clock signal generation unit 11 of the imaging device 10 generates a clock signal CK used in the imaging device 10. A synchronization signal generation unit 12 generates synchronization signals XVS and XHS based on the clock signal CK. The imaging unit 13 performs an imaging operation based on the synchronization signals XVS and XHS to generate image data of the captured image. The image signal generation unit 14 generates an image signal Spic using the synchronization signals XVS and XHS based on the image data of the captured image supplied from the imaging unit 13.

[0029] The image processing unit 21 of the image processing device 20 performs predetermined image processing based on the image signal Spic and synchronization signals XVS and XHS supplied from the imaging device 10. The clock signal generation unit 22 generates a clock signal CK2 used in the image processing device 20. The counter 23 of the abnormality detection circuit 29 starts a counting operation OP, which counts the number of clock pulses of the clock signal CK2 based on the pulses included in the synchronization signal XVS, thereby detecting the time length between two pulses included in the synchronization signal XVS. The counter 23 outputs a count value CNT during the counting operation OP. The comparator 24 of the abnormality detection circuit 29 compares the count value CNT of the counter 23 with a predetermined threshold TH and generates a signal CTL indicating whether the count value CNT exceeds the threshold TH. The control unit 25 is configured to control the operation of the image processing device 20. The control unit 25 also stops the operation of the image processing device 20 based on the signal CTL supplied from the comparator 24.

[0030] (Detailed Operation) FIG. 2 shows an example of operation of the abnormality detection circuit 29, where (A) shows the waveform of the synchronization signal XVS and (B) shows the waveform of the synchronization signal XHS. At timing t1, a pulse appears in the synchronization signal XVS (FIG. 2(A)). This starts a frame period F. The counter 23 then starts a counting operation OP based on this pulse. Then, at timing t2, a second pulse appears in the synchronization signal XVS (FIG. 2(A)). This ends the frame period F and starts a new frame period F. The counter 23 stops the counting operation OP based on this pulse. The comparator 24 determines whether the count value CNT exceeds the threshold value TH during this counting operation OP. The threshold value TH is set to a value such that the count value CNT does not exceed this threshold value TH when pulses of the synchronization signal XVS appear at a predetermined interval corresponding to the duration of the frame period F.

[0031] 3 shows a more detailed example of the operation of the abnormality detection circuit 29 when the second pulse does not appear in the synchronization signal XVS, where (A) shows the waveform of the clock signal CK, (B) shows the waveform of the synchronization signal XVS, (C) shows the count value CNT of the counter 23, (D) shows the threshold value TH in the comparison unit 24, and (E) shows the waveform of the signal CTL. In this Figure 3, (B) and (E) show the signals when the second pulse appears in the synchronization signal XVS with dashed lines. Timings t11 and t13 in this Figure 3 correspond to timings t1 and t2 in Figure 2, respectively.

[0032] In the imaging device 10, the synchronization signal generating section 12 generates a synchronization signal XVS based on the clock signal CK generated by the clock signal generating section 11 (FIGS. 3A and 3B).

[0033] When a pulse appears in the synchronization signal XVS at timing t11 (FIG. 3B), the counter 23 in the image processing device 20 starts counting operation OP based on this pulse, for example, at timing t12, and the count value CNT of the counter 23 begins to increase (FIG. 3C). In this example, the threshold value TH is "N" (FIG. 3D). When the count value CNT is equal to or less than this threshold value TH, the signal CTL is maintained at a low level (FIG. 3E).

[0034] For example, when the imaging system 1 is operating normally, a pulse appears in the synchronization signal XVS at timing t13 (FIG. 3B). The counter 23 stops the counting operation OP based on this pulse. For example, the counter 23 may stop the counting operation OP by stopping the incrementing operation of the count value CNT, or may stop the counting operation OP by resetting the count value CNT. After resetting the count value CNT, the counter 23 may immediately start the next counting operation OP.

[0035] At this timing t13, the count value CNT is "N." In this example, the counter 23 stops the counting operation OP, so the count value CNT does not exceed the threshold value TH ("N").

[0036] For example, if the clock signal generator 11 or the synchronization signal generator 12 in the imaging device 10 fails after timing t11, no pulse will appear in the synchronization signal XVS at timing t13. In this case, the count value CNT of the counter 23 continues to increase (FIG. 3C). At timing t14, when the count value CNT reaches "N+1," the count value CNT exceeds the threshold value TH ("N"), and the comparator 24 changes the signal CTL from low to high (FIG. 3E).

[0037] Based on the change in this signal CTL, the control unit 25 stops the operation of the image processing device 20. That is, for example, the operation of the image processing device 20 is stopped because an abnormality has occurred in the clock signal generating unit 11 or the synchronization signal generating unit 12 in the imaging device 10.

[0038] In this way, the abnormality detection circuit 29 is provided with the counter 23 that can detect the time length between two pulses corresponding to the synchronization signal XVS by performing the count operation OP based on the pulses corresponding to the synchronization signal XVS, and the comparator 24 that can determine an abnormality in the synchronization signal XVS based on the count value CNT of the counter 23. This makes it possible for the abnormality detection circuit 29 to detect an abnormality in the synchronization signal XVS caused by, for example, a failure in the clock signal generator 11 or the synchronization signal generator 12 in the imaging device 10.

[0039] Furthermore, in the abnormality detection circuit 29, the counter 23 can start the counting operation OP based on the first of the two pulses and can stop the counting operation OP based on the second of the two pulses. The comparator 24 can determine an abnormality by determining whether the count value CNT exceeds a predetermined threshold value TH. As a result, for example, if a circuit generating the synchronization signal XVS fails during operation, it will generate the first pulse but not the second pulse, causing the count value CNT to exceed the threshold value TH. This allows the abnormality detection circuit 29 to detect an abnormality in the synchronization signal XVS.

[0040] Furthermore, in the abnormality detection circuit 29, the synchronization signal XVS includes a first pulse and a second pulse, so that the abnormality detection circuit 29 can directly detect an abnormality in the synchronization signal XVS based on the two pulses in the synchronization signal XVS.

[0041] [Effect] As described above, in this embodiment, a counter that can detect the time length between two pulses corresponding to the synchronization signal by performing a counting operation based on pulses corresponding to the synchronization signal, and a comparison unit that can determine an abnormality in the circuit that generates the synchronization signal based on the count value of the counter are provided, so that an abnormality in the synchronization signal can be detected.

[0042] In this embodiment, the counter can start counting based on the first of the two pulses and can stop counting based on the second of the two pulses. The comparator can determine whether the count value exceeds a predetermined threshold value to determine an abnormality. This makes it possible to detect an abnormality in the synchronization signal.

[0043] In this embodiment, the synchronization signal includes a first pulse and a second pulse, so that an abnormality in the synchronization signal can be detected.

[0044] [Modification 1-1] In the above embodiment, it is directly detected whether the pulses of the synchronization signal XVS appear at a predetermined interval corresponding to the length of the frame period F, but this is not limited to this, and instead, for example, it is also possible to indirectly detect whether the pulses of the synchronization signal XVS appear at a predetermined interval corresponding to the length of the frame period F. This modification will be described in detail below with some examples.

[0045] 4 shows an example configuration of an imaging system 1A according to this modification. This imaging system 1A includes an image processing device 20A. The image processing device 20A has a decoder 26A and a counter 23A. In this example, the imaging device 10 and the image processing device 20A communicate using an SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock) interface. The decoder 26A, the counter 23A, and the comparator 24 constitute an abnormality detection circuit 29A.

[0046] The decoder 26A is configured to detect control data indicating the start of a frame, which is included in the image signal Spic, and to generate a trigger signal TRG based on the control data.

[0047] The counter 23A is configured to detect the time length between two pulses included in the trigger signal TRG by performing a counting operation OP that counts the number of clock pulses of the clock signal CK2 based on the pulses included in the trigger signal TRG.

[0048] 5 shows an example of the signal format of the image signal Spic when an SLVS-EC interface is used. The image signal Spic includes multiple packets. Each of the multiple packets includes a packet header PH, data, and a packet footer PF. The multiple packets include packets containing blank data and packets containing valid data. The multiple packets are transmitted in synchronization with the synchronization signal XHS. The packet header PH of the first packet of the multiple packets in one frame period F includes control data indicating the start of the frame.

[0049] Here, the abnormality detection circuit 29A corresponds to a specific example of an "abnormality detection circuit" in an embodiment of the present disclosure. The decoder 26A corresponds to a specific example of a "decoder" in an embodiment of the present disclosure. The counter 23A corresponds to a specific example of a "counter" in an embodiment of the present disclosure. The image signal Spic corresponds to a specific example of an "image signal" in an embodiment of the present disclosure. The frame period F corresponds to a specific example of a "cycle period" in an embodiment of the present disclosure.

[0050] Figure 6 shows an example of the operation of the abnormality detection circuit 29A when using an SLVS-EC interface, where (A) shows the waveform of the synchronization signal XVS, (B) shows the waveform of the synchronization signal XHS, and (C) shows the waveform of the trigger signal TRG.

[0051] At timing t21, a pulse appears in the synchronization signal XVS (FIG. 6(A)). This marks the start of a frame period F. At timing t22, the decoder 26A detects control data indicative of the start of a frame, which is included in the image signal Spic, and generates a pulse of the trigger signal TRG based on this control data (FIG. 6(C)). The counter 23A starts a counting operation OP based on this pulse.

[0052] Then, at timing t23, a second pulse appears in the synchronization signal XVS (FIG. 6(A)). This ends the frame period F and starts a new frame period F. At timing t24, the decoder 26A detects control data indicative of the start of a frame, which is included in the image signal Spic, and generates a pulse of the trigger signal TRG based on this control data (FIG. 6(C)). The counter 23A stops its counting operation OP based on this pulse. The comparator 24 determines whether the count value CNT has exceeded the threshold value TH during this counting operation OP.

[0053] The abnormality detection circuit 29A detects the time length between two pulses in the trigger signal TRG generated by the decoder 26A. Specifically, the abnormality detection circuit 29A detects the time length between the control data indicating the start of a frame in each of two adjacent frame periods F. This allows the abnormality detection circuit 29A to indirectly detect whether pulses of the synchronization signal XVS appear at a predetermined interval corresponding to the length of the frame period F.

[0054] Next, another imaging system 1A according to this modification will be described. In this example, the imaging device 10 and the image processing device 20A communicate with each other using an SLVS interface. A decoder 26A of this imaging system 1A is configured to detect control data attached to valid data included in the image signal Spic and generate a trigger signal TRG based on the control data.

[0055] 7 shows an example of the signal format of the image signal Spic when an SLVS interface is used. The image signal Spic includes multiple packets. Each of the multiple packets includes a packet header SAV, data, and a packet footer EAV. The multiple packets include packets containing blank data and packets containing valid data. The multiple packets are transmitted in synchronization with the synchronization signal XHS. The packet header SAV of a packet containing valid data includes control data indicating that the packet contains valid data.

[0056] FIG. 8 shows an example of the operation of the abnormality detection circuit 29A when an SLVS interface is used, where (A) shows the waveform of the synchronization signal XVS, (B) shows the waveform of the synchronization signal XHS, and (C) shows the waveform of the trigger signal TRG.

[0057] At timing t31, a pulse appears in the synchronization signal XVS (FIG. 8A). This marks the start of a frame period F. At timing t32, the decoder 26A detects control data in the image signal Spic indicating that the packet contains valid data, and changes the trigger signal TRG from low to high based on this control data (FIG. 8C). The counter 23A starts a counting operation OP based on this change in the trigger signal TRG. In this example, during the period from timing t32 to t33, each of the multiple packets in the image signal Spic contains control data indicating that the packet contains valid data, so the decoder 26A maintains the trigger signal TRG at high level during this period. Then, at timing t33, when the packet no longer contains valid data, the decoder 26A changes the trigger signal TRG from high to low.

[0058] Then, at timing t34, a second pulse appears in the synchronization signal XVS (FIG. 6(A)). This ends the frame period F and starts a new frame period F. At timing t35, the decoder 26A detects control data, included in the image signal Spic, indicating that the packet contains valid data, and changes the trigger signal TRG from low to high based on this control data (FIG. 8(C)). The counter 23A stops its counting operation OP based on this change in the trigger signal TRG. The comparator 24 determines whether the count value CNT has exceeded the threshold value TH during this counting operation OP.

[0059] The abnormality detection circuit 29A detects the time length between two pulses in the trigger signal TRG generated by the decoder 26A. Specifically, the abnormality detection circuit 29A detects the time length between the start timings of valid data in each of two adjacent frame periods F. This allows the abnormality detection circuit 29A to indirectly detect whether pulses of the synchronization signal XVS appear at a predetermined interval corresponding to the length of the frame period F.

[0060] Next, another imaging system 1A according to this modification will be described. In this example, the imaging device 10 and the image processing device 20A communicate with each other using MIPI (Mobile Industry Processor Interface). A decoder 26A of this imaging system 1A is configured to detect control data indicating the start of a frame, which is included in the image signal Spic, and to generate a trigger signal TRG based on the control data.

[0061] 9 shows an example of the signal format of the image signal Spic when MIPI is used. The image signal Spic includes multiple packets. Each of the multiple packets includes a packet header PH, data, and a packet footer PF. The multiple packets are transmitted in synchronization with a synchronization signal XHS. The multiple packets in one frame period F are sandwiched between control data indicating the start of the frame (frame start FS) and control data indicating the end of the frame (frame end FE).

[0062] FIG. 10 shows an example of the operation of the abnormality detection circuit 29A when MIPI is used, where (A) shows the waveform of the synchronization signal XVS, (B) shows the waveform of the synchronization signal XHS, (C) shows the waveform of the image signal Spic, and (D) shows the waveform of the trigger signal TRG.

[0063] At timing t41, a pulse appears in the synchronization signal XVS (FIG. 10(A)). This starts the frame period F. At timing t42, a short packet indicating the start of a frame appears in the image signal Spic (FIG. 10(C)). This short packet contains control data indicating the frame start FS shown in FIG. 9. The decoder 26A generates a pulse of the trigger signal TRG based on the control data contained in this short packet (FIG. 10(D)). The counter 23A starts a counting operation OP based on this pulse.

[0064] Then, at timing t43, a second pulse appears in the synchronization signal XVS (FIG. 6(A)). This ends the frame period F and a new frame period F begins. At timing t44, a short packet indicating the start of this frame appears in the image signal Spic (FIG. 10(C)). The decoder 26A generates a pulse of the trigger signal TRG based on the control data contained in this short packet (FIG. 10(D)). The counter 23A stops the counting operation OP based on this pulse. The comparator 24 determines whether the count value CNT exceeds the threshold value TH during this counting operation OP.

[0065] The abnormality detection circuit 29A detects the time length between two pulses in the trigger signal TRG generated by the decoder 26A. Specifically, the abnormality detection circuit 29A detects the time length between short packets indicating the start of a frame in each of two adjacent frame periods F. This allows the abnormality detection circuit 29A to indirectly detect whether pulses of the synchronization signal XVS appear at a predetermined interval corresponding to the length of the frame period F.

[0066] As described above, the abnormality detection circuit 29A according to this modification further includes a decoder 26A capable of decoding control data included in the image signal Spic in response to the synchronization signal XVS and provided at a predetermined timing position in a frame period corresponding to one cycle of the synchronization signal XVS. The decoder 26A is capable of generating a first pulse based on the control data in a first frame period F, and is capable of generating a second pulse based on the control data in a second frame period F following the first frame period F. This allows the abnormality detection circuit 29A to indirectly detect an abnormality in the synchronization signal XVS based on the two pulses generated by the decoder 26A.

[0067] [Modification 1-2] In the above embodiment, an abnormality in the synchronization signal XVS is detected, but the present invention is not limited to this. Instead, an abnormality in the synchronization signal XHS, for example, may be detected.

[0068] 2. Second Embodiment Next, an imaging system 2 according to a second embodiment will be described. In this embodiment, the period for detecting the time length is different from that of the first embodiment. That is, while the first embodiment detects the time length of the frame period F, this embodiment detects the time length of the response time of the imaging device to the synchronization signal XVS. Note that components that are substantially the same as those in the imaging system 1 according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0069] 11 shows an example of the configuration of the imaging system 2. The imaging system 2 includes an imaging device 30 and an image processing device 40. In this example, the imaging device 30 and the image processing device 40 communicate with each other using an SLVS-EC interface. The image signal Spic has the signal format shown in FIG. 5.

[0070] The imaging device 30 is configured to capture an image of a subject based on the synchronization signal XVS supplied from the image processing device 40. The imaging device 30 has a synchronization signal generation unit 32. The synchronization signal generation unit 32 is configured to generate a synchronization signal XHS based on the synchronization signal XVS supplied from the image processing device 40.

[0071] The image processing device 40 includes a decoder 41, a synchronization signal generating section 42, and a counter 43. The decoder 41, the counter 43, and the comparing section 24 constitute an abnormality detection circuit 49.

[0072] The decoder 41 is configured to detect control data indicating the start of a frame, which is included in the image signal Spic, and to generate a trigger signal TRG based on the control data.

[0073] The synchronization signal generating unit 42 is configured to generate a synchronization signal XVS based on the clock signal CK2 generated by the clock signal generating unit 22. The image processing device 40 is configured to supply the synchronization signal XVS generated by the synchronization signal generating unit 42 to the imaging device 30.

[0074] The counter 43 is configured to detect the time length between the pulse of the synchronization signal XVS and the pulse of the trigger signal TRG by starting a counting operation OP that counts the number of clock pulses of the clock signal CK2 supplied from the clock signal generating unit 22 based on the pulse contained in the synchronization signal XVS.

[0075] Here, the abnormality detection circuit 49 corresponds to a specific example of an "abnormality detection circuit" in an embodiment of the present disclosure. The decoder 41 corresponds to a specific example of a "decoder" in an embodiment of the present disclosure. The synchronization signal generation unit 42 corresponds to a specific example of a "synchronization signal generation circuit" in an embodiment of the present disclosure.

[0076] FIG. 12 shows an example of the operation of the abnormality detection circuit 49, where (A) shows the waveform of the synchronization signal XVS, (B) shows the waveform of the synchronization signal XHS, and (C) shows the waveform of the trigger signal TRG. At timing t51, a pulse appears in the synchronization signal XVS (FIG. 12(A)). This marks the start of a frame period F. The counter 43 starts a counting operation OP based on this pulse. Then, at timing t52, the decoder 41 detects control data indicative of the start of a frame, which is included in the image signal Spic, and generates a pulse of the trigger signal TRG based on this control data (FIG. 12(C)). The counter 43 stops the counting operation OP based on this pulse. During this counting operation OP, the comparator 24 determines whether the count value CNT exceeds the threshold value TH. The threshold value TH is set to a value such that the count value CNT does not exceed this threshold value TH when the response time of the imaging device 30, from the timing of the pulse of the synchronization signal XVS to the time when the imaging device 30 generates control data indicating the start of a frame, is a normal time.

[0077] FIG. 13 shows a more detailed example of the operation of the abnormality detection circuit 49 when the pulse of the trigger signal TRG is delayed, in which (A) shows the waveform of the clock signal CK2, (B) shows the waveform of the synchronization signal XVS, (C) shows the waveform of the trigger signal TRG, (D) shows the count value CNT of the counter 43, (E) shows the threshold value TH in the comparison unit 24, and (F) shows the waveform of the signal CTL.

[0078] In the imaging device 30, the synchronization signal generating section 42 generates the synchronization signal XVS based on the clock signal CK2 generated by the clock signal generating section 22 (FIGS. 13A and 13B).

[0079] When a pulse appears in the synchronization signal XVS at timing t61 (FIG. 13(B)), the counter 43 in the image processing device 40 starts a counting operation OP based on this pulse, for example, at timing t62, and the count value CNT of the counter 43 begins to increase (FIG. 13(D)). In this example, the threshold value TH is "10" (FIG. 13(E)). When the count value CNT is equal to or less than this threshold value TH, the signal CTL is maintained at a low level (FIG. 13(F)).

[0080] For example, when the imaging system 2 is operating normally, at timing t63, the decoder 41 detects control data indicating the start of a frame, which is included in the image signal Spic, and generates a pulse of the trigger signal TRG based on this control data (FIG. 13(C)). Based on this pulse, the counter 43 stops the counting operation OP.

[0081] At this timing t63, the count value CNT is "10." In this example, the counter 43 stops the counting operation OP, so the count value CNT does not exceed the threshold value TH ("10").

[0082] For example, if an abnormality occurs in the signal path of the synchronization signal XVS from the image processing device 40 to the image capture device 30, or if the image signal generation unit 14 in the image capture device 30 fails, the timing at which a pulse appears in the trigger signal TRG may be delayed from timing t63. In this case, the count value CNT of the counter 43 continues to increase (FIG. 13(D)). At timing t64, when the count value CNT reaches "11," the count value CNT exceeds the threshold value TH ("10"), and the comparator 24 changes the signal CTL from low to high (FIG. 13(F)).

[0083] Based on this change in signal CTL, control unit 25 stops the operation of image processing device 40. That is, the operation of image processing device 40 is stopped because an abnormality has occurred in the signal path of synchronization signal XVS from image processing device 40 to imaging device 30, or because image signal generation unit 14 in imaging device 30 has failed.

[0084] In this way, the abnormality detection circuit 49 is provided with the counter 43 that can detect the time length between two pulses corresponding to the synchronization signal XVS by performing the count operation OP based on the pulses corresponding to the synchronization signal XVS, and the comparator 24 that can determine an abnormality in the synchronization signal XVS based on the count value CNT of the counter 43. As a result, the abnormality detection circuit 49 can detect an abnormality in the synchronization signal XVS caused by, for example, an abnormality in the signal path of the synchronization signal XVS from the image processing device 40 to the imaging device 30 or a failure in the image signal generation unit 14 in the image processing device 40.

[0085] The abnormality detection circuit 49 further includes a synchronization signal generation unit 42 capable of generating a synchronization signal XVS, and a decoder 41 capable of decoding control data included in an image signal Spic in response to the synchronization signal XVS and provided at a predetermined timing position in a frame period F corresponding to one cycle of the synchronization signal XVS. The synchronization signal XVS includes a first pulse. The decoder 41 is capable of generating a second pulse based on the control data. This allows the abnormality detection circuit 49 to detect an abnormality in the synchronization signal XVS due to, for example, an abnormality in the signal path of the synchronization signal XVS from the image processing device 40 to the imaging device 30 or a malfunction of the image signal generation unit 14 in the imaging device 30. Other effects are similar to those of the first embodiment.

[0086] [Modification 2-1] In the above embodiment, the imaging device 30 and the image processing device 40 communicate using an SLVS-EC interface, but this is not limited to this. Instead, for example, they may communicate using an SLVS interface or MIPI.

[0087] FIG. 14 shows an example of the operation of the abnormality detection circuit 49 when an SLVS interface is used, where (A) shows the waveform of the synchronization signal XVS, (B) shows the waveform of the synchronization signal XHS, and (C) shows the waveform of the trigger signal TRG.

[0088] At timing t71, a pulse appears in the synchronization signal XVS (FIG. 14(A)). This starts a frame period F. The counter 43 starts a counting operation OP based on this pulse. Then, at timing t32, the decoder 41 detects control data, which is included in the image signal Spic and indicates that the packet contains valid data, and changes the trigger signal TRG from low to high based on this control data (FIG. 14(C)). The counter 43 stops the counting operation OP based on this change in the trigger signal TRG. The comparator 24 determines whether the count value CNT exceeds the threshold value TH during this counting operation OP.

[0089] FIG. 15 shows an example of the operation of the abnormality detection circuit 49 when MIPI is used, where (A) shows the waveform of the synchronization signal XVS, (B) shows the waveform of the synchronization signal XHS, (C) shows the waveform of the image signal Spic, and (D) shows the waveform of the trigger signal TRG.

[0090] At timing t81, a pulse appears in the synchronization signal XVS (FIG. 15(A)). This starts the frame period F. The counter 43 starts the counting operation OP based on this pulse. At timing t82, a short packet indicating the start of a frame appears in the image signal Spic (FIG. 15(C)). The decoder 41 generates a pulse of the trigger signal TRG based on the control data contained in this short packet (FIG. 15(D)). The counter 43 stops the counting operation OP based on this pulse. The comparator 24 determines whether the count value CNT exceeds the threshold value TH during this counting operation OP.

[0091] [Modification 2-2] In the above embodiment, an abnormality in the synchronization signal XVS is detected, but this is not limiting. Instead, an abnormality in the synchronization signal XHS, for example, may be detected.

[0092] 3. Application Examples Next, application examples of the imaging systems described in the above embodiments and modifications will be described.

[0093] 16 shows an example of the configuration of an inspection system 90 to which the imaging system 2 of the second embodiment or the like is applied. The inspection system 90 is configured to, for example, capture images of industrial products transported by a belt conveyor and inspect the industrial products using the obtained images. The inspection system 90 includes a belt conveyor 91, imaging devices 92A to 92C, and an inspection processing unit 93.

[0094] The belt conveyor 91 is configured to convey industrial products to be inspected in a conveying direction A. The belt conveyor 91 is capable of controlling the conveying speed based on a control signal supplied from the inspection processing unit 93.

[0095] The imaging devices 92A to 92C are configured to capture images of industrial products transported by the belt conveyor 91. The imaging devices 92A to 92C capture images of the industrial products from different directions. Each of the imaging devices 92A to 92C performs an imaging operation based on a synchronization signal XVS supplied from the inspection processing unit 93, and supplies an image signal Spic indicating image data of the captured image to the inspection processing unit 93.

[0096] The inspection processing unit 93 is configured to control the inspection processing in the inspection system 90. The inspection processing unit 93 controls the conveying speed of the belt conveyor 91 by supplying a control signal to the belt conveyor 91. The inspection processing unit 93 controls the imaging timing of the imaging devices 92A to 92C when imaging industrial products by supplying a synchronization signal XVS to the imaging devices 92A to 92C. The inspection processing unit 93 then inspects the industrial products based on image data indicated by the image signals Spic supplied from the imaging devices 92A to 92C.

[0097] For example, each of the imaging devices 92A to 92C corresponds to, for example, the imaging device 30 shown in Fig. 11. The inspection processing unit 93 corresponds to, for example, the image processing device 40 shown in Fig. 11. The abnormality detection circuit 49 provided in the inspection processing unit 93 can detect an abnormality in the synchronization signal XVS due to an abnormality in the signal path of the synchronization signal XVS from the inspection processing unit 93 to the imaging devices 92A to 92C or a failure in the image signal generation unit 14 in the imaging devices 92A to 92C.

[0098] 4. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0099] FIG. 17 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0100] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 17, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown in the figure are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 as functional components of the integrated control unit 12050.

[0101] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0102] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0103] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0104] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0105] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0106] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0107] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0108] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0109] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 17, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0110] FIG. 18 is a diagram showing an example of the installation position of the imaging unit 12031.

[0111] In FIG. 18, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0112] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0113] 18 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0114] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0115] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0116] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0117] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0118] The above describes an example of a vehicle control system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to the imaging unit 12031 of the above-described configuration. The imaging device mounted on the vehicle can improve the reliability of the vehicle control system by detecting an abnormality in the synchronization signal. As a result, the vehicle control system 12000 can improve the reliability of functions such as a vehicle collision avoidance or collision mitigation function, a following driving function based on the following distance, a vehicle speed maintenance function, a vehicle collision warning function, and a vehicle lane departure warning function.

[0119] The present technology has been described above by giving several embodiments and modifications thereof, as well as specific application examples and application examples to electronic devices. However, the present technology is not limited to these embodiments, and various modifications are possible.

[0120] For example, in the above-described embodiments, an abnormality in the synchronization signal is detected by detecting the loss or delay of the synchronization signal, but this is not limiting. Instead, an abnormality in the synchronization signal may be detected when, for example, a pulse of the synchronization signal appears earlier than desired.

[0121] For example, in the above embodiments, the SLVS-EC interface, the SLVS interface, and the MIPI interface are shown as examples, but the present invention is not limited to these and can be applied to various interfaces. Furthermore, the control data detected by the decoder is not limited to the examples shown in the embodiments and modifications, and various control data can be used.

[0122] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0123] The present technology can be configured as follows: According to the present technology configured as follows, an abnormality in a synchronization signal can be detected.

[0124] (1) An abnormality detection circuit comprising: a counter capable of detecting a time length between two pulses corresponding to a synchronization signal by performing a count operation based on pulses corresponding to the synchronization signal; and a determination circuit capable of determining an abnormality in the synchronization signal based on a count value of the counter. (2) The counter is capable of starting the count operation based on a first pulse of the two pulses and stopping the count operation based on a second pulse of the two pulses, and the determination circuit is capable of determining the abnormality by determining whether the count value exceeds a predetermined threshold. (3) The abnormality detection circuit according to (2), wherein the synchronization signal includes the first pulse and the second pulse. (4) The abnormality detection circuit according to (2), further comprising a decoder capable of decoding control data included in an image signal corresponding to the synchronization signal and provided at a predetermined timing position in a cycle period corresponding to one cycle of the synchronization signal, and wherein the decoder is capable of generating the first pulse based on the control data in a first cycle period and generating the second pulse based on the control data in a second cycle period after the first cycle period. (5) The abnormality detection circuit according to (2), further comprising: a synchronization signal generation circuit capable of generating the synchronization signal; and a decoder capable of decoding control data included in an image signal corresponding to the synchronization signal and provided at a predetermined timing position in a period corresponding to one period of the synchronization signal, wherein the synchronization signal includes the first pulse, and the decoder is capable of generating the second pulse based on the control data. (6) The abnormality detection circuit according to (4) or (5), wherein the control data is data indicating a start of a frame. (7) The abnormality detection circuit according to (4) or (5), wherein the control data is data indicating whether data included in the image signal is valid. (8) An abnormality detection method comprising: detecting a time length between two pulses corresponding to the synchronization signal by performing a counting operation based on pulses corresponding to the synchronization signal; and determining an abnormality in the synchronization signal based on a count value in the counting operation.(9) An imaging system comprising: an imaging device capable of performing an imaging operation based on a synchronization signal; and an image processing device capable of performing image processing based on an imaging result of the imaging device, wherein the image processing device has: a counter capable of detecting a time length between two pulses corresponding to the synchronization signal by performing a count operation based on pulses corresponding to the synchronization signal; and a determination circuit capable of determining an abnormality in the synchronization signal based on a count value of the counter. (10) The imaging system described in (9), wherein the image processing device is capable of stopping the image processing when the determination circuit determines the abnormality.

[0125] This application claims priority based on Japanese Patent Application No. 2023-104877, filed on June 27, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0126] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. An abnormality detection circuit comprising: a counter capable of detecting the length of time between two pulses corresponding to a synchronization signal by performing a counting operation based on a pulse corresponding to the synchronization signal; and a judgment circuit capable of judging an abnormality in the synchronization signal based on the count value of the counter.

2. The abnormality detection circuit according to claim 1, wherein the counter is capable of starting the counting operation based on a first pulse of the two pulses and is capable of stopping the counting operation based on a second pulse of the two pulses, and the determination circuit is capable of determining the abnormality by determining whether the count value has exceeded a predetermined threshold value.

3. The abnormality detection circuit according to claim 2, wherein the synchronization signal includes the first pulse and the second pulse.

4. The abnormality detection circuit according to claim 2, further comprising a decoder capable of decoding control data included in an image signal corresponding to the synchronization signal and provided at a predetermined timing position in a cycle period corresponding to one cycle of the synchronization signal, wherein the decoder is capable of generating the first pulse based on the control data in a first cycle period, and is capable of generating the second pulse based on the control data in a second cycle period following the first cycle period.

5. The abnormality detection circuit according to claim 2, further comprising: a synchronization signal generating circuit capable of generating the synchronization signal; and a decoder capable of decoding control data included in an image signal corresponding to the synchronization signal and provided at a predetermined timing position in a period corresponding to one period of the synchronization signal, wherein the synchronization signal includes the first pulse, and the decoder is capable of generating the second pulse based on the control data.

6. The abnormality detection circuit according to claim 4, wherein the control data is data indicating the start of a frame.

7. The abnormality detection circuit according to claim 4, wherein the control data is data indicating whether the data contained in the image signal is valid.

8. An abnormality detection method comprising: detecting a time length between two pulses corresponding to a synchronization signal by performing a counting operation based on a pulse corresponding to the synchronization signal; and determining an abnormality in the synchronization signal based on a count value in the counting operation.

9. An imaging system comprising: an imaging device capable of performing imaging operation based on a synchronization signal; and an image processing device capable of performing image processing based on the imaging result of the imaging device, wherein the image processing device has: a counter capable of detecting the length of time between two pulses corresponding to the synchronization signal by performing a counting operation based on a pulse corresponding to the synchronization signal; and a judgment circuit capable of judging an abnormality in the synchronization signal based on the count value of the counter.

10. The imaging system according to claim 9, wherein the image processing device is capable of stopping the image processing when the determination circuit determines that an abnormality has occurred.

Images