Imaging device and camera system

Abstract

In the present invention, an imaging device comprises a pixel including a photoelectric conversion unit that converts light into an electric charge, a signal-reading current source that is connected to the pixel, and a reset current source that is connected to the signal-reading current source and that converts a first current generated by the signal reading current source into a second current. The reset current source supplies a second current to the pixel.

Description

Imaging device and camera system

[0001] The present disclosure relates to an imaging device and a camera system including the imaging device.

[0002] In recent years, imaging devices have been widely used in various fields, such as video cameras, digital still cameras, surveillance cameras, in-vehicle cameras, etc. Examples of imaging devices include a charge coupled device (CCD) solid-state imaging element and a complementary metal oxide semiconductor (CMOS) solid-state imaging element (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2020-162117

[0004] An object of the present disclosure is to provide an imaging device and a camera system having an excellent power supply rejection ratio (PSRR). Here, PSRR refers to the ability to remove power supply ripples when they exist in the power supply of the imaging device, in other words, power supply noise immunity.

[0005] In order to achieve the above object, an imaging device according to one embodiment of the present disclosure includes a pixel including a photoelectric conversion unit that converts light into an electric charge, a current source connected to the pixel, and a conversion circuit connected to the current source that converts a first current generated by the current source into a second current, and the conversion circuit supplies the second current to the pixel.

[0006] In order to achieve the above object, a camera system according to one embodiment of the present disclosure includes a lens optical system and the imaging device that converts light passing through the lens optical system into an electric charge.

[0007] The present disclosure provides an imaging device and a camera system with excellent PSRR.

[0008] FIG. 1 is a block diagram showing a schematic configuration of an imaging device according to an embodiment. FIG. 2 is a circuit diagram showing an example of a detailed configuration of a pixel included in an imaging device according to an embodiment, and an example of a configuration of a current source unit according to a conventional technique. FIG. 3 is a circuit diagram showing an example of a detailed configuration of a pixel and a current source unit included in an imaging device according to an embodiment. FIG. 4 is a timing chart showing the operation of the current source unit shown in FIG. 3. FIG. 5 is a circuit diagram showing an example of a detailed configuration of a current source unit according to a first modification of an embodiment. FIG. 6 is a circuit diagram showing an example of a detailed configuration of a pixel according to a second modification of an embodiment, and an example of a configuration of a current source unit according to a conventional technique. FIG. 7 is a circuit diagram showing an example of a detailed configuration of a pixel and a current source unit included in an imaging device according to a second modification of an embodiment. FIG. 8 is a circuit diagram showing an example of a detailed configuration of a current source unit according to a third modification of an embodiment. FIG. 9 is a circuit diagram showing an example of a detailed configuration of a current source unit according to a fourth modification of an embodiment. FIG. 10 is a block diagram showing an example of a configuration of a camera system according to an embodiment.

[0009] (Findings Forming the Basis of the Present Disclosure) In the technology of Patent Document 1, a pixel of an imaging device includes a photoelectric conversion unit that converts light into signal charges, a charge accumulation node that accumulates the signal charges, an amplifier transistor whose gate is connected to the charge accumulation node, and a grounded-gate amplifier circuit that amplifies the output of the amplifier transistor and outputs the amplified output to the charge accumulation node. The grounded-gate amplifier circuit includes a feedback transistor whose source or drain is connected to one of the source or drain of the amplifier transistor and whose other source or drain is connected to the charge accumulation node. This feedback transistor allows the signal charges generated by the photoelectric conversion unit to be read out while suppressing random noise.

[0010] However, in the technology of Patent Document 1, the reset current source that supplies a constant current during reset is configured with a PMOS transistor or the like, while the signal readout current source, which is a constant current source for reading out the signal output from the amplification transistor, is configured with an NMOS transistor or the like. In this way, the technology of Patent Document 1 includes two current sources. Therefore, in order to stabilize the signal readout from the pixel, it is necessary to take measures against noise in the power supply voltage and the bias voltage applied to the gate for both the transistor that configures the reset current source and the transistor that configures the signal readout current source.

[0011] Therefore, the inventors have intensively studied such noise countermeasures and arrived at the configuration of the present disclosure, which utilizes a constant current generated by one of the signal readout current source and the reset current source, and generates a constant current supplied by the other of the signal readout current source and the reset current source using a conversion circuit such as a current mirror circuit.The inventors have also found that this configuration eliminates the need for noise countermeasures against the power supply voltage required by the transistor constituting the other of the signal readout current source and the reset current source, and the bias voltage applied to the gate.

[0012] More specifically, the imaging device according to the first aspect of the present disclosure comprises a pixel including a photoelectric conversion unit that converts light into an electric charge, a current source connected to the pixel, and a conversion circuit connected to the current source that converts a first current generated by the current source into a second current, and the conversion circuit supplies the second current to the pixel.

[0013] As a result, the first current generated by the current source is converted into a second current by the conversion circuit and supplied to the pixel. Therefore, noise countermeasures for the power supply voltage required for one of the signal readout current source and the reset current source and the bias voltage to the transistor gate are no longer necessary, resulting in an imaging device with excellent PSRR. Specifically, there is no need to use wide wiring for the power supply voltage connected to one of the transistors of the signal readout current source and the reset current source. Furthermore, the bias voltage line connected to the gate of that transistor is also no longer necessary. Furthermore, resistance to ground fluctuations is improved.

[0014] In addition, an imaging device according to a second aspect of the present disclosure is the imaging device according to the first aspect, further comprising a first switch connected between the pixel and the current source, a second switch connected between the current source and the conversion circuit, and a third switch connected between the conversion circuit and the pixel.

[0015] As a result, the pixel and the current source, the current source and the conversion circuit, and the conversion circuit and the pixel are connected via switches, so that it is possible to easily switch between a state in which a constant current is supplied to the pixel from the current source and a state in which a constant current is supplied to the pixel from the conversion circuit.

[0016] An imaging device according to a third aspect of the present disclosure is the imaging device according to the second aspect, in which the first switch, the second switch, and the third switch are turned on and off mutually exclusively.

[0017] This makes it possible to exclusively realize a state in which a constant current is supplied to the pixel from the current source and a state in which a constant current is supplied to the pixel from the conversion circuit.

[0018] Furthermore, an imaging device according to a fourth aspect of the present disclosure is an imaging device according to any of the first to third aspects, in which the current source includes a first transistor having one of a source and a drain connected to the pixel, and the conversion circuit includes a second transistor having one of a source and a drain connected to the current source and the one of a source and a drain connected to a gate, and a third transistor having a gate connected to the gate of the second transistor and one of a source and a drain connected to the pixel.

[0019] This allows, for example, the current source to be configured with one transistor, while the conversion circuit can be configured with two transistors, such as a current mirror circuit.

[0020] An imaging device according to a fifth aspect of the present disclosure is the imaging device according to the fourth aspect, in which the polarity of the first transistor is different from the polarity of the second transistor and the polarity of the third transistor.

[0021] This allows the current source to be constructed with NMOS or PMOS transistors, while the conversion circuit can be constructed with PMOS or NMOS transistors of opposite polarity.

[0022] Furthermore, an imaging device according to a sixth aspect of the present disclosure is the imaging device according to the fourth or fifth aspect, in which the ratio of the gate width to the gate length of the second transistor is different from the ratio of the gate width to the gate length of the third transistor.

[0023] This allows the ratio of the current supplied by the current source to the current supplied by the conversion circuit to be set arbitrarily.

[0024] Furthermore, an imaging device according to a seventh aspect of the present disclosure is an imaging device according to any one of the fourth to sixth aspects, in which the conversion circuit further includes a fourth transistor different from the third transistor, having a gate connected to the gate of the second transistor and one of a source and a drain connected to the pixel.

[0025] This allows the current supplied from the conversion circuit to the pixel to be increased.

[0026] Furthermore, an imaging device according to an eighth aspect of the present disclosure is an imaging device according to any one of the first to seventh aspects, in which the pixel includes a fifth transistor having a gate connected to the photoelectric conversion unit, the current source is connected to one of the source and drain of the fifth transistor, and the conversion circuit is connected to the one of the source and drain of the fifth transistor.

[0027] This allows both the current source and the conversion circuit to supply a constant current to a common location in the pixel, such as a vertical signal line.

[0028] Furthermore, an imaging device according to a ninth aspect of the present disclosure is an imaging device according to any one of the first to seventh aspects, in which the pixel includes a fifth transistor having a gate connected to the photoelectric conversion unit, the current source is connected to one of the source and drain of the fifth transistor, and the conversion circuit is connected to the other of the source and drain of the fifth transistor.

[0029] This allows the current source and the conversion circuit to supply constant current to different locations in the pixel, such as the vertical signal line and the power supply line, respectively.

[0030] An imaging device according to a tenth aspect of the present disclosure is the imaging device according to the eighth aspect, in which the pixel includes a sixth transistor connected between the fifth transistor and the current source.

[0031] This allows the pixel to comprise a selection transistor connected between the amplification transistor and the current source.

[0032] An imaging device according to an eleventh aspect of the present disclosure is the imaging device according to the ninth aspect, in which the pixel includes a seventh transistor connected between the fifth transistor and the conversion circuit.

[0033] This allows the pixel to comprise a selection transistor connected between the amplification transistor and the conversion circuit.

[0034] Furthermore, a camera system according to a twelfth aspect of the present disclosure includes a lens optical system and an imaging device according to any one of the first to eleventh aspects that converts light passing through the lens optical system into an electric charge.

[0035] As a result, the camera system equipped with the imaging device has excellent PSRR.

[0036] (Embodiments) Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that each embodiment described below represents a specific example of the present disclosure. Numerical values, circuit elements, connection configurations between circuit elements, transistor polarity, voltage, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is not necessarily an exact illustration. In each figure, substantially identical configurations are assigned the same reference numerals, and redundant explanations are omitted or simplified. Furthermore, "A and B are connected" means that A and B are electrically connected, and includes not only the case where A and B are directly connected, but also the case where A and B are indirectly connected with another circuit element interposed between A and B.

[0037] 1 is a block diagram showing a schematic configuration of an image pickup device 10 according to an embodiment. The image pickup device 10 is a CMOS solid-state image pickup element, and includes, as its main components, an array of pixels 11 arranged two-dimensionally, a row scanning circuit 12, a column scanning circuit 13, a current source 14, and a column signal processing circuit 15.

[0038] The pixel 11 is connected to a power supply line 25 and an accumulation control line 21 for applying a voltage, converts incident light into an electric signal, and outputs the signal via a vertical signal line 22 .

[0039] The row scanning circuit 12 controls the array of pixels 11 via control lines 12 a and 12 b to cause the pixels 11 to output signals to the column scanning circuit 13 on a row-by-row basis.

[0040] The current source 14 is a constant current source provided for each vertical signal line 22 and is used as a constant current source when reading out signals from the pixels 11 .

[0041] The column signal processing circuit 15 is provided for each vertical signal line 22 and performs noise suppression processing and A / D conversion.

[0042] The column scanning circuit 13 reads out and outputs the digital values ​​output from the column signal processing circuit 15 for all columns in order.

[0043] Although not shown in FIG. 1, the imaging device 10 also includes other components such as a control circuit for controlling each component, a power supply, a bias voltage generating circuit, a current source, and wiring for connecting each component.

[0044] 2 is a circuit diagram showing an example of a detailed configuration of a pixel 11 included in an imaging device 10 according to an embodiment, and an example of a configuration of a current source unit 50 according to the prior art. The circuit configuration of the pixel 11 disclosed in this diagram is common to the embodiment and the prior art. The current source unit 50 is a component included in an imaging device according to the prior art, and is shown for reference. The current source unit 50 is a circuit provided for each column in an array of pixels 11.

[0045] The pixel 11 includes a photoelectric conversion unit 30, an amplification transistor 31, a selection transistor 32, a reset transistor 33, a feedback transistor 34, a first capacitance element 35, a second capacitance element 36, and a charge storage node 38.

[0046] The photoelectric conversion unit 30 is an element that converts light into electric charges, and is typically composed of a photoelectric conversion film and two electrode layers that sandwich the photoelectric conversion film from above and below. The photoelectric conversion film is laminated on a semiconductor substrate on which the pixels 11 are formed. The photoelectric conversion film is made of an organic material or an inorganic material such as amorphous silicon. The photoelectric conversion film may include a layer made of an organic material and a layer made of an inorganic material.

[0047] The charge storage node 38 is connected to one of the two electrode layers that make up the photoelectric conversion unit 30, and is also called a "floating diffusion node." It stores one of the charges of the hole-electron pairs generated by photoelectric conversion in the photoelectric conversion unit 30.

[0048] The amplification transistor 31 is an example of a fifth transistor having a gate connected to the photoelectric conversion unit 30. The amplification transistor 31 has a gate connected to the charge storage node 38, amplifies a voltage corresponding to the charge stored in the charge storage node 38, and outputs the amplified voltage signal to the source or drain.

[0049] The selection transistor 32 is an example of a sixth transistor connected between the fifth transistor and the current source. The selection transistor 32 passes the signal output from the amplification transistor 31 to the vertical signal line 22 in accordance with a control signal sent from the row scanning circuit 12 via the control line 12 a.

[0050] The reset transistor 33 has a source or drain connected to the charge storage node 38, and becomes conductive in accordance with a control signal sent from the row scanning circuit 12 via the control line 12b, thereby resetting the potential of the charge storage node 38 to a constant potential.

[0051] The first capacitance element 35 is connected in parallel to the reset transistor 33 and functions as a feedback capacitance.

[0052] The feedback transistor 34 becomes conductive in accordance with a control signal sent from the row scanning circuit 12, thereby feeding back the signal output to the vertical signal line 22 to the charge storage node 38 via the feedback signal line 24.

[0053] The second capacitance element 36 is connected between the connection point of the feedback transistor 34 and the reset transistor 33 and a sensitivity adjustment line 37 to which a predetermined potential is supplied. By appropriately setting the capacitances of the first capacitance element 35 and the second capacitance element 36, it is possible to sufficiently suppress reset noise that occurs when the feedback transistor 34 is turned off.

[0054] The current source unit 50 according to the conventional technology includes a switch element S1a connected between the power supply wiring 25 and the power supply voltage AVDD, a switch element S1b connected between the power supply wiring 25 and the reference potential AVSS, a switch element S2a and a signal readout current source 53a connected in series between the vertical signal line 22 and the reference potential AVSS, and a switch element S2b and a reset current source 53b connected in series between the vertical signal line 22 and the power supply voltage AVDD.

[0055] The reset current source 53b is, for example, a PMOS transistor operating as a constant current source, with its source connected to the power supply voltage AVDD and its gate receiving a bias voltage Vbp, as shown in a dashed line frame.The signal readout current source 53a is, for example, an NMOS transistor operating as a constant current source, with its source connected to the reference potential AGND and its gate receiving a bias voltage Vbn, as shown in a dashed line frame.

[0056] When a signal is read out from the pixel 11, of the four switch elements S1a, S1b, S2a, and S2b, only the switch elements S1a and S2a are turned on. This connects the power supply line 25 to the power supply voltage AVDD, and the vertical signal line 22 to the signal readout current source 53a. As a result, a constant current flows from the signal readout current source 53a in a direction from the amplification transistor 31 to the selection transistor 32, and the potential of the charge storage node 38 amplified by the amplification transistor 31 operating as a source follower circuit is detected.

[0057] On the other hand, when resetting the pixel 11, of the four switch elements S1a, S1b, S2a, and S2b, only switch elements S1b and S2b are turned on. This connects the power supply line 25 to the reference potential AVSS, and the vertical signal line 22 to the reset current source 53b. As a result, a current flows through the selection transistor 32 and the amplification transistor 31 in the opposite direction to that during signal readout. At this time, a feedback circuit is formed including the amplification transistor 31, selection transistor 32, feedback signal line 24, feedback transistor 34, and reset transistor 33, and the charge storage node 38 is reset to a constant potential. Because the selection transistor 32 and the amplification transistor 31 are cascode-connected, the feedback circuit performs noise cancellation with a large gain.

[0058] Fig. 3 is a circuit diagram showing an example of the detailed configuration of the pixel 11 and current source unit 90 included in the imaging device 10 according to the embodiment. The circuit configuration of the pixel 11 disclosed in this figure is the same as that shown in Fig. 2. The current source unit 90 is a circuit provided for each column in the array of pixels 11, and is a circuit that replaces part of the current source unit 50 in Fig. 2 (i.e., the signal readout current source 53a, the reset current source 53b, and the switch elements S2a and S2b).

[0059] The current source unit 90 according to the present embodiment includes a signal readout current source 70, a reset current source 80, and switch elements S5a, S5b, and S5c. The signal readout current source 70 is an example of a current source connected to the pixel 11, and in this embodiment, is configured by an NMOS transistor 70a. The reset current source 80 is an example of a conversion circuit connected to the current source and converts a first current generated by the current source into a second current, and in this embodiment, is configured by two PMOS transistors 82 and 83 that form a current mirror circuit.

[0060] The NMOS transistor 70a is an example of a first transistor, one of whose source and drain is connected to the pixel 11. The NMOS transistor 70a has its source connected to the reference potential AVSS, its gate connected to the bias voltage line 23, and its drain connected to the switch elements S5a and S5b, and operates as a constant current source. The bias voltage line 23 is commonly connected to the gates of the multiple NMOS transistors 70a provided for each column of the array of pixels 11.

[0061] The switch element S5a is an example of a first switch connected between the pixel 11 and a current source. The switch element S5a is a switch whose on / off state is controlled by a control signal LC, and is connected between the vertical signal line 22 and the drain of the NMOS transistor 70a.

[0062] The switch element S5b is an example of a second switch connected between the current source and the conversion circuit. The switch element S5b is a switch whose on / off state is controlled by a control signal LCP, and is connected between the drain of the NMOS transistor 70a and the drain and gate of one of the PMOS transistors 82 that constitute the current mirror circuit.

[0063] The two PMOS transistors 82 and 83 that make up the current mirror circuit have their sources connected to the power supply voltage AVDD and their gates connected to each other. The gate and drain of the PMOS transistor 82 are short-circuited. The PMOS transistor 82 is an example of a second transistor in which one of its source and drain is connected to a current source and the other is connected to its gate. The PMOS transistor 83 is an example of a third transistor in which its gate is connected to the gate of the second transistor and one of its source and drain is connected to the pixel 11.

[0064] In this embodiment, the two PMOS transistors 82 and 83 have the same characteristics (i.e., the same ratio of gate width to gate length), so in the current mirror circuit, a current of the same magnitude as the current flowing through the source PMOS transistor 82 flows through the destination PMOS transistor 83.

[0065] The switch element S5c is an example of a third switch connected between the conversion circuit and the pixel 11. The switch element S5c is a switch whose on / off is controlled by the control signal LCP, similar to the switch element S5b, and is connected between the drain of the PMOS transistor 83 and the vertical signal line 22.

[0066] Fig. 4 is a timing chart showing the operation of the current source unit 90 shown in Fig. 3. The timing chart shows the timing of the control signal LC that controls the switch element S5a and the control signal LCP that controls the switch elements S5b and S5c. Both control signals turn the switch element on when high and turn the switch element off when low.

[0067] 4, the control signal LC is high and the control signal LCP is low, resulting in the switch element S5a being turned on and the switch elements S5b and S5c being turned off. As a result, of the signal readout current source 70 and the reset current source 80, only the signal readout current source 70 is connected to the vertical signal line 22. The power supply wiring 25 is connected to the power supply voltage AVDD via the switch element S1a.

[0068] As a result, a constant current determined by the voltage VBIAS_N of the bias voltage line 23 flows from the amplification transistor 31 of the pixel 11 through the vertical signal line 22, the switch element S5a, and the NMOS transistor 70a toward the reference potential AVSS. As a result, the potential of the charge storage node 38 amplified by the amplification transistor 31 operating as a source follower circuit is detected, and a signal is read out from the pixel 11.

[0069] 4, the control signal LC is low and the control signal LCP is high, resulting in the switch element S5a being turned off and the switch elements S5b and S5c being turned on. As a result, of the signal readout current source 70 and the reset current source 80, only the reset current source 80 is connected to the vertical signal line 22. That is, the NMOS transistor 70a is connected to the PMOS transistor 82 constituting the current mirror circuit via the switch element S5b, and the PMOS transistor 83 constituting the current mirror circuit is connected to the vertical signal line 22. The power supply wiring 25 is connected to the reference potential AVSS via the switch element S1b.

[0070] As a result, a constant current from the NMOS transistor 70a determined by the voltage VBIAS_N of the bias voltage line 23 flows through the PMOS transistor 82 that constitutes the current mirror circuit, and a current of the same magnitude as this constant current flows through the PMOS transistor 83 that constitutes the current mirror circuit and the switch element S5c to the vertical signal line 22. As a result, in the pixel 11, in the feedback circuit that includes the amplification transistor 31, the selection transistor 32, the feedback signal line 24, the feedback transistor 34, and the reset transistor 33, the selection transistor 32 and the amplification transistor 31 are cascode-connected, and the pixel 11 is reset with high-gain noise cancellation.

[0071] Here, as can be seen by comparing the current source section 50 according to the prior art shown in FIG. 2 with the current source section 90 according to the embodiment shown in FIG. 3, in the current source section 90 according to the embodiment, the reset current source 80 is configured as a current mirror circuit, and therefore, unlike the reset current source 53b according to the prior art, generates a stable constant current that is independent of the power supply voltage AVDD and the bias voltage Vbp.

[0072] This eliminates the need for noise countermeasures for the power supply voltage and the bias voltage to the transistor gate, which were required in conventional reset current sources, and realizes an imaging device 10 with excellent PSRR. Specifically, there is no need to use wide wiring for the power supply voltage AVDD required in the reset current source 80. In addition, the bias voltage line connected to the gate of the transistor that constitutes the conventional reset current source is also no longer necessary. Furthermore, resistance to ground fluctuations is improved.

[0073] In the current source section 90 shown in FIG. 3, the signal read current source 70 and the reset current source 80 are each configured with one NMOS transistor and two PMOS transistors that form a current mirror circuit, but the transistor configuration is not limited to this, and a transistor configuration in which the polarity of the transistors (here, PMOS / NMOS) is logically inverted may also be used.

[0074] 5 is a circuit diagram showing an example of a detailed configuration of a current source unit 90a according to a first modification of the embodiment. Here, the signal read current source 71 and the reset current source 81 are configured with transistors of opposite polarity to those of the current source unit 90 shown in FIG.

[0075] That is, in this modification, the reset current source 81 is an example of a current source connected to the pixel 11, and is configured by a PMOS transistor 81 a in this modification. The signal readout current source 71 is an example of a conversion circuit that is connected to a current source and converts a first current generated by the current source into a second current, and is configured by two NMOS transistors 72 and 73 that configure a current mirror circuit in this modification.

[0076] The PMOS transistor 81a has a source connected to the power supply voltage AVDD, a gate connected to the bias voltage line 23a, and a drain connected to the switch elements S5a and S5b, and operates as a constant current source. The bias voltage line 23a is commonly connected to the gates of the multiple PMOS transistors 81a provided for each column of the array of pixels 11.

[0077] The switch element S5a is a switch whose on / off state is controlled by a control signal LCP, and is connected between the vertical signal line 22 and the drain of the PMOS transistor 81a.

[0078] The switch element S5b is a switch whose on / off state is controlled by a control signal LC, and is connected between the drain of the PMOS transistor 81a and the drain and gate of the NMOS transistor 72, one of the NMOS transistors that constitute the current mirror circuit.

[0079] The two NMOS transistors 72 and 73 that form the current mirror circuit have their sources connected to the reference potential AVSS and their gates connected to each other. The gate and drain of the NMOS transistor 72 are short-circuited.

[0080] The switch element S5c is a switch that is controlled to be turned on or off by the control signal LC, similarly to the switch element S5b, and is connected between the drain of the NMOS transistor 73 and the vertical signal line 22.

[0081] 4 , in the current source unit 90a according to the present modification, the switch elements S5b and S5c are on and the switch element S5a is off. Therefore, similarly to the current source unit 90 according to the embodiment, only the signal readout current source 71 of the signal readout current source 71 and the reset current source 81 is connected to the vertical signal line 22. That is, the PMOS transistor 81a is connected to the NMOS transistor 72 constituting the current mirror circuit via the switch element S5b, and the NMOS transistor 73 constituting the current mirror circuit is connected to the vertical signal line 22.

[0082] As a result, a constant current determined by the voltage VBIAS_P of the bias voltage line 23a flows through the NMOS transistor 72 constituting the current mirror circuit from the PMOS transistor 81a, and a current of the same magnitude as the constant current flows through the NMOS transistor 73 constituting the current mirror circuit and the switch element S5c to the vertical signal line 22. The power supply line 25 is connected to the power supply voltage AVDD through the switch element S1a.

[0083] As a result, a current having the same magnitude as the constant current of the PMOS transistor 81a determined by the power supply voltage AVDD and the voltage VBIAS_P of the bias voltage line 23a flows from the amplification transistor 31 of the pixel 11 toward the reference potential AVSS via the vertical signal line 22, the switch element S5c, and the NMOS transistor 73. As a result, in the pixel 11, the potential of the charge storage node 38 amplified by the amplification transistor 31 operating as a source follower circuit is detected, and a signal is read out from the pixel 11.

[0084] 4, the switch element S5a is on, and the switch elements S5b and S5c are off. Therefore, similar to the current source unit 90 according to the embodiment, only the reset current source 81 of the signal readout current source 71 and the reset current source 81 is connected to the vertical signal line 22. That is, a constant current from the PMOS transistor 81a, determined by the power supply voltage AVDD and the voltage VBIAS_P of the bias voltage line 23a, flows from the drain of the PMOS transistor 81a to the vertical signal line 22 via the switch element S5a. The power supply wiring 25 is connected to the reference potential AVSS via the switch element S1b.

[0085] As a result, in the pixel 11, in the feedback circuit including the amplification transistor 31, the selection transistor 32, the feedback signal line 24, the feedback transistor 34, and the reset transistor 33, the selection transistor 32 and the amplification transistor 31 are cascode-connected, and the pixel 11 is reset with high-gain noise cancellation.

[0086] 2, in the above-described embodiment and the first modified example, both of the two current sources are connected to the vertical signal line 22. However, the current source unit according to the present disclosure can be applied even to a configuration in which the two current sources are connected to different sides of the vertical signal line 22 and the power supply wiring 25.

[0087] 6 is a circuit diagram showing an example of a detailed configuration of a pixel 11a according to a second modification of the embodiment, and an example of a configuration of current source units 60a and 60b according to the prior art. The pixel 11a shown in this diagram is common to this modification and the prior art. The current source units 60a and 60b are components provided in an imaging device according to the prior art, and are shown for reference.

[0088] The pixel 11a includes a photoelectric conversion unit 30, an amplifier transistor 31, a first selection transistor 32a, a second selection transistor 32b, a reset transistor 33, and a charge storage node 38a. The pixel 11a differs from the pixel 11 of the above embodiment in that the feedback circuit is simply configured, the vertical signal line 22 is connected to one of the source and drain of the amplifier transistor 31 via the first selection transistor 32a, and the second selection transistor 32b is connected to the other of the source and drain of the amplifier transistor 31.

[0089] The first selection transistor 32a is an example of a sixth transistor connected between the amplifier transistor 31 (the fifth transistor) and a current source, and the second selection transistor 32b is an example of a seventh transistor connected between the amplifier transistor 31 (the fifth transistor) and a conversion circuit.

[0090] The current source unit 60a according to the conventional technology includes a switch element S3a connected between the power supply voltage VDD and the power supply wiring 25, and a PMOS transistor 61a and a switch element S3a connected in series between the power supply voltage VD and the power supply wiring 25. The PMOS transistor 61a is a constant current source with its source grounded, and functions as a reset current source 61.

[0091] The current source unit 60b according to the conventional technology includes a switch element S4a connected between the vertical signal line 22 and the reference potential BGND, and a switch element S4b and an NMOS transistor 66a connected in series between the vertical signal line 22 and the reference potential AGND. The NMOS transistor 66a is a constant current source with its source grounded, and functions as the current source 66 for signal readout.

[0092] When a signal is read from the pixel 11a, of the four switch elements S3a, S3b, S4a, and S4b in the current source units 60a and 60b, only the switch elements S3a and S4b are turned on. As a result, a constant current determined by the bias voltage Vbn flows from the NMOS transistor 66a from the power supply voltage VDD to the reference potential AGND via the switch element S3a, the power supply line 25, the second selection transistor 32b, the amplifier transistor 31, the first selection transistor 32a, the vertical signal line 22, the switch element S4b, and the NMOS transistor 66a serving as the signal read current source 66. As a result, the potential of the charge storage node 38a amplified by the amplifier transistor 31 operating as a source follower circuit is detected.

[0093] On the other hand, when resetting the pixel 11a, of the four switch elements S3a, S3b, S4a, and S4b in the current source units 60a and 60b, only the switch elements S3b and S4a are turned on. As a result, a constant current from the PMOS transistor 61a, determined by the power supply voltage VD and the bias voltage Vbp, flows to the reference potential BGND via the switch element S3b, the power supply line 25, the second selection transistor 32b, the amplifier transistor 31, the first selection transistor 32a, the vertical signal line 22, and the switch element S4a. At this time, a feedback circuit including the amplifier transistor 31 and the reset transistor 33 is formed in the pixel 11a, the amplifier transistor 31 operates as a source-grounded amplifier circuit, and the charge storage node 38a is reset to a constant potential.

[0094] Fig. 7 is a circuit diagram showing an example of the detailed configuration of a pixel 11a and a current source unit 90b included in an imaging device 10 according to a second modified example of the embodiment. The circuit configuration of the pixel 11a disclosed in this figure is the same as that shown in Fig. 6. The current source unit 90b is a circuit provided for each column in the array of pixels 11, and is a circuit that replaces part of the current source units 60a and 60b in Fig. 6 (i.e., the signal readout current source 66, the reset current source 61, and the switch elements S3b and S4b).

[0095] The current source section 90b according to this modification basically has the same configuration as the current source section 90 according to the embodiment shown in Fig. 3. That is, the current source section 90b according to this modification includes a signal read current source 70, a reset current source 80, and switch elements S5a, S5b, and S5c.

[0096] However, the connection relationships in the current source section 90b according to this modification are different from those in the current source section 90 according to the embodiment. That is, in the current source section 90b according to this modification, the drain of the PMOS transistor 83 that constitutes the current mirror circuit is connected via the switch element S5c to the power supply wiring 25, rather than to the vertical signal line 22. The other connection relationships in the current source section 90b are the same as those in the current source section 90 according to the embodiment.

[0097] 4, in the current source unit 90b according to the present modification, the switch element S5a is turned on and the switch elements S5b and S5c are turned off, and therefore, similarly to the current source unit 90 according to the embodiment, only the signal readout current source 70 of the signal readout current source 70 and the reset current source 80 is connected to the vertical signal line 22. The power supply voltage VDD is applied to the drain of the amplification transistor 31 via the switch element S3a, the power supply line 25, and the second selection transistor 32b.

[0098] As a result, a constant current determined by the voltage VBIAS_N of the bias voltage line 23 flows from the amplification transistor 31 of the pixel 11a, which operates as a source follower circuit, through the vertical signal line 22, the switch element S5a, and the NMOS transistor 70a toward the reference potential AGND, thereby reading out a signal from the pixel 11a.

[0099] 4, the switch element S5a is turned off and the switch elements S5b and S5c are turned on, so that the reset current source 80 is connected to the power supply wiring 25. That is, a constant current determined by the voltage VBIAS_N of the bias voltage line 23 flows through the PMOS transistor 82 constituting the current mirror circuit from the NMOS transistor 70a, and a current of the same magnitude as this constant current flows to the power supply wiring 25 via the PMOS transistor 83 and switch element S5c constituting the current mirror circuit. The vertical signal line 22 is connected to the reference potential BGND via the switch element S4a.

[0100] At this time, in the pixel 11a, a feedback circuit including the amplifier transistor 31 and the reset transistor 33 is formed, the amplifier transistor 31 operates as a source-grounded amplifier circuit, and the charge storage node 38a is reset to a constant potential.

[0101] Here, as can be seen by comparing the current source sections 60a and 60b according to the prior art shown in FIG. 6 with the current source section 90b according to the second modified example shown in FIG. 7, in the current source section 90b according to the second modified example, the reset current source 80 is configured as a current mirror circuit, and therefore, unlike the reset current source 61 according to the prior art, generates a stable constant current that is not dependent on the power supply voltage AVDD and the bias voltage Vbp.

[0102] This eliminates the need for noise countermeasures for the power supply voltage and the bias voltage to the transistor gate, which were required in conventional reset current sources, and realizes an imaging device 10 with excellent PSRR. Specifically, there is no need to use wide wiring for the power supply voltage AVDD required in the reset current source 80. In addition, the bias voltage line connected to the gate of the transistor that constitutes the conventional reset current source is also no longer necessary. Furthermore, resistance to ground fluctuations is improved.

[0103] In the current source section 90b shown in FIG. 7, the signal read current source 70 and the reset current source 80 are each configured with one NMOS transistor and two PMOS transistors that form a current mirror circuit, but the transistor configuration is not limited to this, and a transistor configuration in which the polarity of the transistors (here, PMOS / NMOS) is logically inverted may also be used.

[0104] 8 is a circuit diagram showing an example of a detailed configuration of a current source section 90c according to a third modification of the embodiment. Here, the signal readout current source 71 and the reset current source 81 are composed of transistors of opposite polarity to those of the current source section 90b shown in FIG. 7. That is, in this modification, the signal readout current source 71 is composed of two NMOS transistors 72 and 73 that form a current mirror circuit. The reset current source 81 is composed of a PMOS transistor 81a.

[0105] The current source section 90c according to this modification basically has the same configuration as the current source section 90a according to the first modification shown in Fig. 5. That is, the current source section 90c according to this modification includes a signal read current source 71, a reset current source 81, and switch elements S5a, S5b, and S5c.

[0106] However, the connection relationships in the current source section 90c according to this modification are different from those in the current source section 90a according to the first modification. That is, in the current source section 90c according to this modification, the drain of the PMOS transistor 81a constituting the reset current source 81 is connected via a switch element S5a to the power supply wiring 25, not to the vertical signal line 22. The other connection relationships in the current source section 90c are the same as those in the current source section 90a according to the first modification.

[0107] 4 , in the current source section 90c according to this modification, the switch elements S5b and S5c are on and the switch element S5a is off. Therefore, similar to the current source section 90a according to the first modification, of the signal readout current source 71 and the reset current source 81, only the signal readout current source 71 is connected to the vertical signal line 22. That is, the PMOS transistor 81a is connected to the NMOS transistor 72 constituting the current mirror circuit via the switch element S5b, and the NMOS transistor 73 constituting the current mirror circuit is connected to the vertical signal line 22.

[0108] As a result, a constant current determined by the PMOS transistor 81a based on the voltage VBIAS_P of the bias voltage line 23a flows through the NMOS transistor 72 that constitutes the current mirror circuit, and a current of the same magnitude as this constant current flows to the vertical signal line 22 via the NMOS transistor 73 and switch element S5c that constitute the current mirror circuit. As a result, a current flows from the amplifier transistor 31 of the pixel 11a toward the reference potential AGND via the vertical signal line 22, switch element S5c, and NMOS transistor 73. The magnitude of this current is the same as the constant current determined by the PMOS transistor 81a based on the power supply voltage AVDD and the voltage VBIAS_P of the bias voltage line 23a. As a result, in the pixel 11a, the potential of the charge storage node 38a amplified by the amplifier transistor 31 that operates as a source follower circuit is detected, and a signal is read out from the pixel 11a.

[0109] 4, the switch element S5a is turned on, and the switch elements S5b and S5c are turned off. This results in a state in which the reset current source 81 is connected to the power supply line 25. That is, a constant current from the PMOS transistor 81a, which is determined by the power supply voltage AVDD and the voltage VBIAS_P of the bias voltage line 23a, flows from the drain of the PMOS transistor 81a to the power supply line 25 via the switch element S5a. At this time, in the pixel 11a, a feedback circuit including the amplifier transistor 31 and the reset transistor 33 is formed, the amplifier transistor 31 operates as a source-grounded amplifier circuit, and the charge storage node 38a is reset to a constant potential.

[0110] In the above-described embodiment and modified examples, the current mirror circuit is configured with a source transistor and a destination transistor having the same characteristics (i.e., the same ratio of gate width to gate length), but the current mirror circuit does not necessarily have to be configured with transistors having the same characteristics, and may be configured with transistors having different characteristics. For example, if the ratio of gate width to gate length of the source transistor is 1, then by setting the ratio of gate width to gate length of the destination transistor to 2, the destination transistor can generate a current that is twice the current that flows through the source transistor.

[0111] Furthermore, in the above-described embodiment and modified example, the current mirror circuit has one copy destination transistor, but it may have two or more.

[0112] 9 is a circuit diagram showing an example of a detailed configuration of a current source unit 90d according to a fourth modification of the embodiment. Here, the current source unit 90d is shown to include a current mirror circuit including two copy destination transistors. That is, the current source unit 90d according to this modification includes a signal read current source 70, a reset current source 80a, and switch elements S5a, S5b, S5c, and S5d. The current source unit 90d according to this modification has a configuration in which a PMOS transistor 84, switch elements S5d, and switch elements S6 are added to the circuit of the current source unit 90 according to the embodiment shown in FIG. 3.

[0113] The PMOS transistor 84 and the switch element S5d form a series circuit and are connected in parallel to the series circuit consisting of the PMOS transistor 83 and the switch element S5c. In this modification, the PMOS transistor 84 has the same characteristics as the PMOS transistors 82 and 83. The switch element S5d is connected between the drain of the PMOS transistor 84 and the vertical signal line 22. The PMOS transistor 84 has a gate connected to the gate of the second transistor, which is the PMOS transistor 82, and one of its source and drain is connected to the pixel 11. The PMOS transistor 84 is an example of a fourth transistor different from the third transistor, which is the PMOS transistor 83.

[0114] The switch element S6 is a switch whose on / off state is controlled by a control signal IUP, and is connected between the gate of the PMOS transistor 83 and the gate of the PMOS transistor 84.

[0115] The current source unit 90d according to this modification basically operates in the same manner as the current source unit 90 according to the embodiment. That is, during the period (i) in Fig. 4, the switch element S5a is turned on and the switch elements S5b, S5c, and S5d are turned off, so that only the signal readout current source 70 out of the signal readout current source 70 and the reset current source 80a is connected to the vertical signal line 22.

[0116] On the other hand, during period (ii) in Figure 4, the switch element S5a is turned off and the switch elements S5b, S5c, and S5d are turned on, so that only the reset current source 80a of the signal readout current source 70 and the reset current source 80a is connected to the vertical signal line 22.

[0117] However, in the current source unit 90d according to this modification, when the switch element S6 is turned on by the control signal IUP, the reset current source 80a supplies twice as much constant current to the vertical signal line 22 as the reset current source 80 of the current source unit 90 according to the embodiment. This is because the currents supplied from the two PMOS transistors 83 and 84 are added together and supplied to the vertical signal line 22. Note that when the switch element S6 is turned off, the reset current source 80a supplies the same amount of constant current to the vertical signal line 22 as that of the current source unit 90 according to the embodiment.

[0118] In this way, according to the current source unit 90d of this modified example, by increasing the number of copy destination transistors that the current mirror circuit has, the magnitude of the current supplied by the current mirror circuit can be set to be switchable between twice or once that of the embodiment, depending on the on / off state of the switch element S6.

[0119] It should be noted that PMOS transistor 84 does not necessarily have to have the same characteristics as PMOS transistors 82 and 83. By making the characteristics of PMOS transistor 84 different from those of PMOS transistors 82 and 83, the multiple of the constant current described above, which is 2 times, can be changed to any multiple such as 1.5 times or 3 times.

[0120] Furthermore, the variations on the current mirror circuit described above (i.e., the source transistor and the destination transistor having different characteristics, and having two or more destination transistors) can be applied not only to current mirror circuits constituting reset current sources as shown in FIGS. 3 and 7, but also to current mirror circuits constituting signal read current sources as shown in FIGS. 5 and 8.

[0121] In the above-described embodiment and its modified examples, the photoelectric conversion unit 30 may be a photodiode.

[0122] In the above embodiment and modified example, one of the two current sources is used as a read current source and the other is used as a reset current source. However, the two current sources may be used as current sources for other purposes.

[0123] 10 is a block diagram showing an example of the configuration of a camera system 95 according to an embodiment. The camera system 95 is a digital camera, and includes a lens optical system 96, an image capturing device 10, a system controller 97, and a camera signal processing unit 98.

[0124] The lens optical system 96 is an optical device that focuses light onto the imaging surface of the imaging device 10, and includes, for example, an autofocus lens, a zoom lens, and an aperture.

[0125] The system controller 97 is a circuit that controls the entire camera system 95, and can be realized by, for example, a microcomputer.

[0126] The imaging device 10 is an imaging device according to an embodiment that converts light passing through a lens optical system 96 into electric charges, and may be an imaging device that includes a current source unit according to any of the first to fourth variants.

[0127] The camera signal processing unit 98 functions as a signal processing circuit that processes the output signal from the imaging device 10, and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing unit 98 can be realized by, for example, a DSP (Digital Signal Processor).

[0128] The camera system 95 according to this embodiment has an imaging device including a current source unit according to the embodiment or the first to fourth modifications, and therefore has an excellent PSRR.

[0129] While the imaging device and camera system according to the present disclosure have been described above based on the embodiments and modifications, the present disclosure is not limited to these embodiments and modifications. As long as they do not deviate from the gist of the present disclosure, various modifications that would occur to a person skilled in the art to the present embodiments or modifications, and other forms constructed by combining some of the components of the embodiments and modifications, are also included within the scope of the present disclosure.

[0130] The present disclosure can be used as an imaging device and a camera system including the imaging device, and in particular as an imaging device and a camera system having excellent PSRR.

[0131] REFERENCE SIGNS LIST 10 Imaging device 11, 11a Pixel 12 Row scanning circuit 12a, 12b Control line 13 Column scanning circuit 14 Current source 15 Column signal processing circuit 21 Storage control line 22 Vertical signal line 23, 23a Bias voltage line 24 Feedback signal line 25 Power supply wiring 30 Photoelectric conversion unit 31 Amplifying transistor 32 Selection transistor 32a First selection transistor 32b Second selection transistor 33 Reset transistor 34 Feedback transistor 35 First capacitance element 36 Second capacitance element 37 Sensitivity adjustment line 38, 38a Charge storage node 50, 60a, 60b, 90, 90a, 90b, 90c, 90d Current source unit S1a, S1b, S2a, S2b, S3a, S3b, S4a, S4b, S5a, S5b, S5c, S5d, S6 Switch elements 53a, 66, 70, 71 Signal readout current sources 53b, 61, 80, 80a, 81 Reset current sources 66a, 70a, 72, 73 NMOS transistors 61a, 81a, 82, 83, 84 PMOS transistors 95 Camera system 96 Lens optical system 97 System controller 98 Camera signal processing unit

Claims

1. An imaging device comprising: a pixel including a photoelectric conversion unit that converts light into an electric charge; a current source connected to the pixel; and a conversion circuit connected to the current source that converts a first current generated by the current source into a second current, wherein the conversion circuit supplies the second current to the pixel.

2. The imaging device of claim 1, further comprising: a first switch connected between the pixel and the current source; a second switch connected between the current source and the conversion circuit; and a third switch connected between the conversion circuit and the pixel.

3. The imaging device according to claim 2, wherein the first switch, the second switch and the third switch are turned on and off mutually exclusively.

4. An imaging device as claimed in any one of claims 1 to 3, wherein the current source includes a first transistor, one of whose source and drain is connected to the pixel, and the conversion circuit includes a second transistor, one of whose source and drain is connected to the current source and one of whose source and drain is connected to a gate, and a third transistor, having a gate connected to the gate of the second transistor and one of whose source and drain is connected to the pixel.

5. The imaging device according to claim 4, wherein the polarity of the first transistor is different from the polarity of the second transistor and the polarity of the third transistor.

6. The imaging device according to claim 4, wherein a ratio of the gate width to the gate length of the second transistor is different from a ratio of the gate width to the gate length of the third transistor.

7. The imaging device according to claim 4, wherein the conversion circuit further includes a fourth transistor different from the third transistor, the fourth transistor having a gate connected to the gate of the second transistor and one of a source and a drain connected to the pixel.

8. An imaging device as claimed in any one of claims 1 to 3, wherein the pixel includes a fifth transistor having a gate connected to the photoelectric conversion unit, the current source is connected to one of the source and drain of the fifth transistor, and the conversion circuit is connected to the one of the source and drain of the fifth transistor.

9. The imaging device according to claim 8, wherein the pixel includes a sixth transistor connected between the fifth transistor and the current source.

10. An imaging device as described in any one of claims 1 to 3, wherein the pixel includes a fifth transistor having a gate connected to the photoelectric conversion unit, the current source is connected to one of the source and drain of the fifth transistor, and the conversion circuit is connected to the other of the source and drain of the fifth transistor.

11. The imaging device according to claim 10, wherein the pixel includes a seventh transistor connected between the fifth transistor and the conversion circuit.

12. A camera system comprising: a lens optical system; and an imaging device according to any one of claims 1 to 3, which converts light passing through the lens optical system into an electric charge.

Images