Semiconductor memory device

Abstract

Wires (71, 72) corresponding to bit lines BLB, BL are formed in a metal wiring layer. A SRAM cell is provided with: a power supply wiring (11) that is formed in a first back surface wiring layer on the back surface side of a transistor, overlaps with active regions (P1, P2) in plan view, and supplies a power supply voltage VDD; a power supply wiring (13) that is formed in the first back surface wiring layer, overlaps with an active region (N2) in plan view, and supplies a power supply voltage VSS; and a power supply wiring (12) that is formed in the first back surface wiring layer, overlaps with an active region (N1) in plan view, and supplies the power supply voltage VSS.

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device, and in particular to a layout structure of a static random access memory (SRAM) cell (hereinafter, also simply referred to as a cell, as appropriate).

[0002] SRAMs are widely used in semiconductor integrated circuits.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltage, and improved operating speed through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. One example of a three-dimensional transistor is the nanosheet FET (Field Effect Transistor).

[0004] Patent Document 1 discloses a technique for providing word lines on the back surface of the substrate directly below the transistors in order to achieve even higher integration.

[0005] US Patent Application Publication No. 2022 / 0336474

[0006] In the technology of Patent Document 1, the bit lines and power supply lines are provided in the same wiring layer, so the wiring width of the bit lines cannot be increased. This increases the wiring resistance of the bit lines and reduces the operating speed of the semiconductor memory device. Furthermore, since the bit lines and power supply lines are provided in the same wiring layer, the wiring width of the power supply lines cannot be increased. This increases the wiring resistance of the power supply lines and increases the power supply voltage drop, reducing the operating speed of the semiconductor memory device. Furthermore, the distance between the bit lines and power supply lines is short, so parasitic capacitance increases and the operating speed of the semiconductor memory device is reduced.

[0007] Furthermore, since the word lines are provided on the back side of the substrate, in order to connect the word lines to the wiring on the front side of the substrate in the peripheral circuit, a connection part for connecting the wiring on the back side and the wiring on the front side is required, which increases the area of ​​the semiconductor memory device and reduces the operating speed of the semiconductor memory device due to the resistance of the connection part.

[0008] The present disclosure aims to prevent an increase in the area of ​​a semiconductor memory device while preventing a decrease in the operating speed of the semiconductor memory device in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor.

[0009] In a first aspect of the present disclosure, there is provided a semiconductor memory device including an SRAM cell, the SRAM cell comprising: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a drain connected to the second node and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, wherein the first bit line is formed in a metal wiring layer above the first to sixth transistors and includes a first wiring extending in a first direction, and the second bit line is a second wiring formed in the metal wiring layer and extending in the first direction, the SRAM cell comprising: a first active region constituting the channel, source, and drain of the first transistor, the channel including a nanosheet extending in the first direction; a second active region constituting the channel, source, and drain of the second transistor, the channel including a nanosheet extending in the first direction; a third active region constituting the channel, source, and drain of the third transistor, the channel including a nanosheet extending in the first direction; a fourth active region constituting the channel, source, and drain of the fourth transistor, the channel including a nanosheet extending in the first direction; a first power supply wiring formed in a first back wiring layer on the back side of the first to sixth transistors, extending in the first direction, overlapping with the first and second active regions in a plan view, and connected to the first power supply; and a first power supply wiring formed in the first back wiring layer, extending in the first direction, overlapping with the third active region in a plan view.a second power supply wiring connected to the second power supply; a third power supply wiring formed in the first backside wiring layer, extending in the first direction, overlapping with the fourth active region in a plan view, and connected to the second power supply; a first via formed at a position where a first region constituting a source in the first active region and the first power supply wiring overlap, connecting the first region and the first power supply wiring; a second via formed at a position where a second region constituting a source in the second active region and the first power supply wiring overlap, connecting the second region and the first power supply wiring; a third via formed at a position where a third region constituting a source in the third active region and the second power supply wiring overlap, connecting the third region and the second power supply wiring; and a fourth via formed at a position where a fourth region constituting a source in the fourth active region and the third power supply wiring overlap, connecting the fourth region and the third power supply wiring.

[0010] According to the present disclosure, a first power supply wiring for supplying a first power supply voltage and second and third power supply wiring for supplying a second power supply voltage are formed in a first back wiring layer, which is a wiring layer on the back side of the transistors. First and second wirings corresponding to the bit lines BLB and BL, respectively, are formed in a metal wiring layer above the first to sixth transistors. This results in only power supply wiring being formed in the first back wiring layer. Furthermore, the first power supply wiring overlaps the first and second active regions in a planar view. The second power supply wiring overlaps the third active region in a planar view. The fourth power supply wiring overlaps the fourth active region in a planar view. This allows the power supply wiring formed in the first back wiring layer to be arranged so as to overlap the active regions in a planar view. Therefore, the wiring width of the power supply wiring in the first back wiring layer can be increased, reducing the wiring resistance of the power supply wiring and thereby preventing a decrease in the operating speed of the semiconductor memory device.

[0011] Furthermore, since it is not necessary to form power supply wiring for supplying the first and second power supply voltages to the metal wiring layer, the wiring width of the first and second wirings corresponding to the first and second bit lines, respectively, can be increased, thereby suppressing the wiring resistance of the bit lines and preventing a decrease in the operating speed of the semiconductor memory device.

[0012] Furthermore, by forming wiring equivalent to word lines in the upper layer of the metal wiring layer, a connection section for connecting the wiring on the back side of the transistor with the wiring on the surface side (upper layer of the transistor) is not required, so it is possible to prevent a decrease in the operating speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0013] A second aspect of the present disclosure is a semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the second node, and a gate connected to the second node; a fourth transistor connected to a source, the drain of which is connected to the second node and the gate of which is connected to the first node; a fifth transistor connected to a source of a first bit line, the drain of which is connected to the first node and the gate of which is connected to a word line; and a sixth transistor connected to a source of a second bit line forming a complementary bit line pair with the first bit line, the drain of which is connected to the second node and the gate of which is connected to the word line; the first bit line is formed in a metal wiring layer above the first to sixth transistors, and includes a first wiring extending in a first direction; the line includes a second wiring formed in the metal wiring layer and extending in the first direction, and the SRAM cell includes a third active region constituting a channel, a source, and a drain of the third transistor, the channel of which includes a nanosheet extending in the first direction; a fourth active region constituting a channel, a source, and a drain of the fourth transistor, the channel of which includes a nanosheet extending in the first direction; a first power supply wiring formed in the metal wiring layer, extending in the first direction, and connected to the first power supply; a second power supply wiring formed in a first back wiring layer on the back side of the first to sixth transistors, extending in the first direction, overlapping with the third active region in a plan view, and connected to the second power supply; a third power supply wiring formed in the first back wiring layer, extending in the first direction, overlapping with the fourth active region in a plan view, and connected to the second power supply; and a third via formed at a position where a third region constituting a source of the third active region and the second power supply wiring overlap, connecting the third region to the second power supply wiring.a fourth via formed at a position where a fourth region constituting a source in the fourth active region and the third power supply wiring overlap, and connecting the fourth region and the third power supply wiring;

[0014] According to the present disclosure, second and third power supply wirings for supplying a second power supply voltage are formed in a first back wiring layer, which is a wiring layer on the back surface of the transistors. First and second wirings corresponding to the first and second bit lines, respectively, and a first power supply wiring for supplying the first power supply voltage are formed in a metal wiring layer above the first to sixth transistors. This leaves only the power supply wiring for supplying the second power supply voltage as the wiring formed in the first back wiring layer. Therefore, the wiring width of the power supply wiring in the first back wiring layer can be increased, and the wiring resistance of the power supply wiring can be obtained, thereby preventing a decrease in the operating speed of the semiconductor memory device.

[0015] Furthermore, since there is no need to form a power supply wiring for supplying the second power supply voltage to the metal wiring layer, the wiring width of the first wiring can be increased, which reduces the wiring resistance of the bit line and prevents a decrease in the operating speed of the semiconductor memory device.

[0016] Furthermore, by forming the power supply wiring that supplies the first power supply voltage between wiring 71 and wiring 72, crosstalk noise between the first and second wirings is suppressed, thereby preventing deterioration in performance and reliability of the semiconductor memory device.

[0017] Furthermore, by forming wiring equivalent to word lines in the upper layer of the metal wiring layer, a connection section for connecting the wiring on the back side of the transistor with the wiring on the surface side (upper layer of the transistor) is not required, so it is possible to prevent a decrease in the operating speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0018] According to the present disclosure, in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor, it is possible to prevent a decrease in the operating speed of a semiconductor memory device while preventing an increase in the area of ​​the semiconductor memory device.

[0019] 1 is a plan view showing an example of a layout structure of an SRAM cell according to the first embodiment; 2 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment; 3 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment; 4 is a circuit diagram showing a configuration of an SRAM cell according to the first embodiment; 5 is another configuration example of a semiconductor integrated circuit device according to the first embodiment; 6 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment; 7 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment; 8 is a plan view showing an example of a layout of a circuit block included in the semiconductor integrated circuit device according to the first embodiment; 9 is a plan view showing another example of a layout of a circuit block included in the semiconductor integrated circuit device according to the first embodiment; 10 is a plan view showing an example of a layout structure of an SRAM cell according to the second embodiment;

[0020] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells, and at least some of the plurality of SRAM cells include nanosheet FETs. A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which a current flows. The nanosheet is formed of, for example, silicon. In the present disclosure, the transistor included in the SRAM cell is not limited to a nanosheet FET.

[0021] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0022] (First Embodiment) (Configuration of SRAM Cell) Figures 1 to 3 show an example of the layout structure of an SRAM cell according to the first embodiment, with Figures 1(a) and 1(b) being plan views, and Figures 2(a) to 2(c) and 3(a) and 3(b) being cross-sectional views in the horizontal direction in a plan view. Specifically, Figure 1(a) shows the upper part of the cell, which is the M1 and M2 wiring layers, and Figure 1(b) shows the lower part of the cell, which is a layer below the M1 and M2 wiring layers and includes a nanosheet FET. Figure 2(a) is a cross-section along line X1-X1', Figure 2(b) is a cross-section along line X2-X2', Figure 2(c) is a cross-section along line X3-X3', Figure 3(a) is a cross-section along line X4-X4', and Figure 3(b) is a cross-section along line X5-X5'.

[0023] In the following description, in plan views such as FIG. 1, the vertical direction of the drawing is the Y direction (first direction), the horizontal direction of the drawing (second direction) is the X direction, and the direction perpendicular to the substrate surface is the Z direction.

[0024] 4 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. As shown in FIG. 4, the SRAM cell includes an SRAM circuit made up of load transistors PU1 and PU2, drive transistors PD1 and PD2, and access transistors PG1 and PG2. The load transistors PU1 and PU2 are P-type FETs, and the drive transistors PD1 and PD2 and the access transistors PG1 and PG2 are N-type FETs.

[0025] The load transistor PU1 is provided between the power supply VDD and a first node NA, and the drive transistor PD1 is provided between the first node NA and a power supply VSS. The gates of the load transistor PU1 and the drive transistor PD1 are connected to a second node NB, and they form an inverter INV1. The load transistor PU2 is provided between the power supply VDD and the second node NB, and the drive transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the load transistor PU2 and the drive transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0026] The access transistor PG1 is provided between the bit line BL and a first node NA, and has its gate connected to the word line WL. The access transistor PG2 is provided between the bit line BLB and a second node NB, and has its gate connected to the word line WL. The bit lines BL and BLB form a complementary bit line pair.

[0027] In an SRAM circuit, when the bit lines BL and BLB constituting a complementary bit line pair are driven to a high level and a low level, respectively, and the word line WL is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the bit lines BL and BLB are driven to a low level and a high level, respectively, and the word line WL is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the word line WL is driven to a low level while data is written to the first and second nodes NA and NB, respectively, the latch state is established and the data written to the first and second nodes NA and NB is held.

[0028] Furthermore, when the bit lines BL and BLB are precharged to a high level and the word line WL is driven to a high level, the states of the bit lines BL and BLB are determined according to the data written to the first and second nodes NA and NB, respectively, and data can be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the bit line BL is held at a high level and the bit line BLB is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the bit line BL is discharged to a low level and the bit line BLB is held at a high level.

[0029] As described above, the SRAM cell has the functions of writing data to the SRAM cell, holding data, and reading data from the SRAM cell by controlling the bit lines BL, BLB and word lines WL.

[0030] In the following description, the solid lines running vertically and horizontally in plan views such as FIG. 1 and the solid lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0031] 1 and other plan views, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. The SRAM cell is arranged so that the cell frame is in contact with the cell frame of an adjacent cell in the X or Y direction.

[0032] 1 and the like, an SRAM cell is arranged on each side of the SRAM cell in the X direction, with the SRAM cell inverted in the X direction, and an SRAM cell is arranged on each side of the SRAM cell in the Y direction, with the SRAM cell inverted in the Y direction.

[0033] As shown in Figure 1B, the backside of the semiconductor chip on which the transistors are formed has wiring layers, BM0 (Backside Metal 0) and BM1 (Backside Metal 1). The BM1 wiring layer is located below the BM0 wiring layer, i.e., farther from the transistors. The BM0 wiring layer corresponds to the first backside wiring layer, and the BM1 wiring layer corresponds to the second backside wiring layer.

[0034] The BM0 wiring layer is formed with power supply wirings 11 to 13 extending in the Y direction from both the top and bottom of the cell. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wirings 12 and 13 supply a power supply voltage VSS.

[0035] The BM1 wiring layer is formed with a power supply wiring 121 extending in the X direction from both the left and right ends of the cell. The power supply wiring 121 supplies a power supply voltage VSS. The power supply wiring 121 is connected to the power supply wiring 12 through a via 131 and to the power supply wiring 13 through a via 132.

[0036] A plurality of active regions constituting the channel, source, and drain of the N-type transistor are formed in an N-type transistor region on a P-type substrate (PSub) (not shown). Specifically, active regions N1 and N2 are formed in the N-type transistor region. The active regions N1 and N2 overlap with power supply wiring 12 and 13, respectively, in a plan view.

[0037] In the N-type transistor region, an access transistor PG2, a drive transistor PD1, a drive transistor PD2, and an access transistor PG1 are formed. The access transistor PG2, the drive transistor PD1, the drive transistor PD2, and the access transistor PG1 each have a channel made of three overlapping sheet structures in a plan view, and each have nanosheets 21 to 24 extending in the Y direction. In other words, the access transistor PG2, the drive transistor PD1, the drive transistor PD2, and the access transistor PG1 are nanosheet FETs.

[0038] In the active region N1, a portion (region 42) that serves as the source of the drive transistor PD2 is connected to the power supply wiring 12 through a via 111 that is provided at a position that overlaps the power supply wiring 12 in a plan view. In the active region N2, a portion (region 43) that serves as the source of the drive transistor PD1 is connected to the power supply wiring 13 through a via 112 that is provided at a position that overlaps the power supply wiring 13 in a plan view.

[0039] A plurality of active regions constituting the channel, source, and drain of the P-type transistor are formed in a P-type transistor region on an N-type well (NWell). Specifically, active regions P1 and P2 are formed in the P-type transistor region. The active regions P1 and P2 overlap with the power supply wiring 11 in plan view.

[0040] Load transistors PU1 and PU2 are formed in the P-type transistor region. The load transistors PU1 and PU2 each have a channel made of three overlapping sheets in a plan view, with nanosheets 25 and 26 extending in the Y direction. In other words, the load transistors PU1 and PU2 are nanosheet FETs. The width in the X direction of the nanosheets 21 to 24 is twice the width in the X direction of the nanosheets 25 and 26.

[0041] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0042] In the active region P1, the portion (region 46) that will become the source of the load transistor PU1 is connected to the power supply wiring 11 through a via 113 that is provided at a position that overlaps the power supply wiring 11 in a planar view. In the active region P2, the portion (region 49) that will become the source of the load transistor PU2 is connected to the power supply wiring 11 through a via 114 that is provided at a position that overlaps the power supply wiring 11 in a planar view.

[0043] As shown in FIG. 1B, gate wirings (Gate) 31 to 34 are formed extending in the X direction. The gate wiring 31 surrounds the outer periphery of the nanosheet 21 in the X and Z directions. The gate wiring 32 surrounds the outer periphery of the nanosheets 25 and 22 in the X and Z directions. The gate wiring 33 surrounds the outer periphery of the nanosheets 23 and 26 in the X and Z directions. The gate wiring 34 surrounds the outer periphery of the nanosheet 24 in the X and Z directions. The gate wiring 31 corresponds to the gate of the access transistor PG2. The gate wiring 32 corresponds to the gates of the load transistor PU1 and the drive transistor PD1. The gate wiring 33 corresponds to the gates of the drive transistor PD2 and the load transistor PU2. The gate wiring 34 corresponds to the gate of the access transistor PG1.

[0044] In the local wiring layer, local wirings 51 to 58 extending in the X direction are formed. Local wiring 51 is connected to region 40 in active region N1. Local wiring 52 is connected to region 46 in active region P1. Local wiring 53 is connected to region 43 in active region N2. Local wiring 54 is connected to region 41 in active region N1 and region 48 in active region P2. Local wiring 55 is connected to region 47 in active region P1 and region 44 in active region N2. Local wiring 56 is connected to region 42 in active region N1. Local wiring 57 is connected to region 49 in active region P2. Local wiring 58 is connected to region 45 in active region N2.

[0045] Region 40 is a portion of active region N1 that will become the source of access transistor PG2. Region 41 is a portion of active region N1 that will become the drain of access transistor PG2 and the drain of drive transistor PD2. Region 42 is a portion of active region N1 that will become the source of drive transistor PD2. Region 43 is a portion of active region N2 that will become the source of drive transistor PD1. Region 44 is a portion of active region N2 that will become the drain of drive transistor PD1 and the drain of access transistor PG1. Region 45 is a portion of active region N2 that will become the source of access transistor PG1. Region 46 is a portion of active region P1 that will become the source of load transistor PU1. Region 47 is a portion of active region P1 that will become the drain of load transistor PU1. Region 48 is a portion of active region P2 that will become the drain of load transistor PU2. Region 49 is a portion of active region P2 that will become the source of load transistor PU2.

[0046] The local wiring 54 is connected to the gate wiring 32 via a shared contact 61. The local wiring 55 is connected to the gate wiring 33 via a shared contact 62. The gate wiring 33, the local wiring 55, and the shared contact 62 correspond to a first node NA. The gate wiring 32, the local wiring 54, and the shared contact 61 correspond to a second node NB.

[0047] As shown in FIG. 1A, wires 71 and 72 extending in the Y direction from the top to the bottom of the cell are formed in the M1 wiring layer, which is a metal wiring layer above the local wiring layer. Wires 73 and 74 are also formed. Wires 71 and 72 correspond to bit lines BLB and BL. Wire 71 overlaps with active region N1 and power supply wire 12 in a plan view. Wire 72 overlaps with active region N2 and power supply wire 13 in a plan view.

[0048] The wiring 71 is connected to the local wiring 51 through a via 81. The wiring 72 is connected to the local wiring 58 through a via 82. The wiring 73 is connected to the gate wiring 31 through a contact (gate-contact) 83. The wiring 74 is connected to the gate wiring 34 through a contact 84.

[0049] In the M2 wiring layer, which is the layer above the M1 wiring layer, a wiring 91 is formed, which extends in the X direction from both the left and right ends of the cell in the drawing. The wiring 91 corresponds to a word line WL. The wiring 91 is connected to the wiring 73 through a via 101 and to the wiring 74 through a via 102.

[0050] With the above configuration, a power supply wiring 11 that supplies a power supply voltage VDD and power supply wirings 12 and 13 that supply a power supply voltage VSS are formed in the BM0 wiring layer, which is a wiring layer on the back surface of the transistor. Wirings 71 and 72 corresponding to the bit lines BLB and BL, respectively, are formed in the M1 wiring layer, which is a metal wiring layer above the transistor. As a result, the only wiring formed in the BM0 wiring layer is the power supply wiring that supplies the power supply voltages VDD and VSS. Therefore, the wiring width of the power supply wirings 11 to 13 that supply the power supply voltages VDD and VSS formed in the BM0 wiring layer can be increased, thereby reducing the wiring resistance of the power supply wiring. Furthermore, the power supply wiring 11 overlaps the active regions P1 and P2 in a planar view and is connected to each other by vias 113 and 114 provided in the overlapping region. The power supply wiring 12 overlaps the active region N1 in a planar view and is connected to each other by a via 111 provided in the overlapping region. The power supply wiring 13 overlaps the active region N2 in a plan view and is connected to the active region N2 through a via 112 provided in the overlapping region. Therefore, the resistance value of the power supply path for the power supply voltages VDD and VSS to the active region can be suppressed. From the above, it is possible to suppress a decrease in the operating speed of the semiconductor memory device and improve the stability of the operation. Furthermore, since it is no longer necessary to form power supply wiring for supplying the power supply wiring VDD and VSS in the M1 wiring layer, the wiring widths of the wirings 71 and 72 corresponding to the bit lines BLB and BL, respectively, can be increased. This suppresses the wiring resistance of the bit lines, thereby suppressing a decrease in the operating speed of the semiconductor memory device.

[0051] Furthermore, wiring 91 corresponding to the word line WL is formed in the M2 wiring layer, which is the layer above the M1 wiring layer. This eliminates the need for a connection portion for connecting the wiring on the back side of the transistor with the wiring on the front side (the layer above the transistor), thereby preventing a decrease in the operating speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0052] The power supply wiring formed on the back surface side of the transistor may be formed using a semiconductor chip separate from the semiconductor chip on which the transistor is formed.

[0053] Fig. 5(a) shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 200 shown in Fig. 5(a) is configured by stacking a first semiconductor chip 201 (chip A) and a second semiconductor chip 202 (chip B). Chip A has the SRAM cells and the like arranged therein. Chip B has power wiring formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps and the like.

[0054] 5B shows a cross section of the SRAM cell of FIG. 1 taken along line X1-X1' in this configuration example. As shown in FIG. 5B, a wiring layer provided on the surface of chip B has a power supply wiring 11 that supplies VDD and power supply wirings 12 and 13 that supply VSS formed therein. The power supply wiring 11 is connected to region 46 of chip A through a via 113 provided at a position overlapping the power supply wiring 11 in a planar view. The power supply wiring 13 is connected to region 43 of chip A through a via 112 provided at a position overlapping the power supply wiring 13 in a planar view. Although not shown, the power supply wiring 12 is connected to region 42 of chip A through a via 111 provided at a position overlapping the power supply wiring 12 in a planar view.

[0055] (Modification 1) Fig. 6 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 6 shows the lower part of the cell. Note that the upper part of the cell in Fig. 6 is the same as Fig. 1(a).

[0056] 6, compared to FIG. 1, a power supply wiring 122 extending in the X direction is formed in the BM0 wiring layer instead of the power supply wiring 121. The power supply wiring 122 supplies a power supply voltage VDD. The power supply wiring 122 is connected to the power supply wiring 11 through a via 133.

[0057] 6 makes it possible to strengthen the power supply voltage VDD supplied to the SRAM cells, and also to obtain the same effects as those in FIG.

[0058] (Modification 2) Fig. 7 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 7 shows the lower part of the cell. Note that the upper part of the cell in Fig. 7 is the same as Fig. 1(a).

[0059] 7, compared to FIG. 1, power supply wiring 121 is replaced with power supply wiring 123 and 124 extending in the X direction formed in the BM0 wiring layer. Power supply wiring 123 is formed at the top of the drawing and supplies power supply voltage VDD. Power supply wiring 124 is formed at the bottom of the drawing and supplies power supply voltage VSS. Power supply wiring 123 is connected to power supply wiring 11 via via 134. Power supply wiring 124 is connected to power supply wiring 12 via via 135 and to power supply wiring 13 via via 136.

[0060] 7 makes it possible to strengthen the power supply voltages VDD and VSS supplied to the SRAM cells, and also to obtain the same effects as those in FIG.

[0061] 8 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to an embodiment. Note that in FIG. 8, only the cell frame of the SRAM cell, the power supply wiring formed in the BM0 wiring layer and the BM1 wiring layer, and the vias connecting the power supply wiring are shown, and the internal structure of the SRAM cell and the wiring between the SRAM cells are not shown.

[0062] The block layout of Fig. 8 includes a memory cell array A1. In the memory cell array A1, cell rows CR1 and cell rows CR2 are alternately arranged in the Y direction. The cell row CR1 is made up of a plurality of SRAM cells C1 arranged in the X direction. The cell row CR2 is made up of a plurality of SRAM cells C2 arranged in the X direction. The SRAM cell C1 is the SRAM cell of Fig. 1. The SRAM cell C2 is the SRAM cell of Fig. 6 inverted in the Y direction.

[0063] As shown in FIG. 8 , in the BM0 wiring layer, the SRAM cells C1 and C2 arranged side by side in the Y direction extend in the Y direction and are commonly connected to a power supply wiring 12 (13) that supplies a power supply voltage VSS. In the BM0 wiring layer, the SRAM cells C1 and C2 arranged side by side in the Y direction extend in the Y direction and are commonly connected to a power supply wiring 11 that supplies a power supply voltage VDD. The power supply wiring 12 (13) that supplies the power supply voltage VSS and the power supply wiring 11 that supplies the power supply voltage VDD are alternately arranged in the X direction. Also, in the BM1 wiring layer, the SRAM cells C1 arranged in the cell column CR1 extend in the X direction and are commonly connected to a power supply wiring 121 that supplies the power supply voltage VSS. In the BM1 wiring layer, the SRAM cells C2 arranged in the cell column CR2 extend in the X direction and are commonly connected to a power supply wiring 122 that supplies the power supply voltage VDD. The power supply wiring 121 that supplies the power supply voltage VSS and the power supply wiring 122 that supplies the power supply voltage VDD are alternately arranged in the Y direction. That is, in the BM0 wiring layer and the BM1 wiring layer, power supply wiring that supplies power supply voltages VDD and VSS is formed in a mesh pattern, so that the wiring resistance of the wiring that supplies the power supply voltage is reduced and fluctuations in the power supply voltage are suppressed, thereby suppressing a decrease in the operating speed of the semiconductor memory device and improving the stability of operation.

[0064] 8, the cell rows CR1 and the cell rows CR2 are alternately arranged in the Y direction, but this is not limiting. For example, the cell row CR2 may be arranged for every N (N is an integer of 3 or more) cell rows CR1 in the Y direction.

[0065] In the example of FIG. 8, eight SRAM cells are arranged in the X direction and eight SRAM cells are arranged in the Y direction, but the number of SRAM cells arranged in the X and Y directions is not limited to this.

[0066] 9 is a plan view showing another example of the layout of a circuit block included in a semiconductor integrated circuit device according to the embodiment. Similar to FIG. 8, FIG. 9 shows only the cell frame of the SRAM cell, the power supply wiring formed in the BM0 wiring layer and the BM1 wiring layer, and the vias connecting the power supply wiring, and does not show the internal structure of the SRAM cell or the wiring between the SRAM cells.

[0067] 9, a memory cell array A2 is formed. In the memory cell array A2, a plurality of cell rows CR1 are arranged in the Y direction. The cell row CR1 is composed of a plurality of SRAM cells C1 arranged in the X direction. The SRAM cells C1 are the SRAM cells of FIG. 1.

[0068] 9, in the BM1 wiring layer in the memory cell array A2, the SRAM cells C1 arranged in the cell column CR1 extend in the X direction and are commonly connected to a power supply wiring 121 that supplies the power supply voltage VSS. A plurality of power supply wirings 121 are arranged side by side in the X direction. As a result, only the power supply wiring that supplies the power supply voltage VSS is formed in the BM1 wiring layer in the memory cell array A2.

[0069] Furthermore, power supply wiring 125 extending in the X direction is formed outside the memory cell array A2 (e.g., in a well tap region, a dummy memory region, etc.). The power supply wiring 125 is formed in the BM1 wiring layer and supplies a power supply voltage VDD. In the example of FIG. 9 , the power supply wiring 125 is formed above the cell row CR1 formed at the top end of the drawing and below the cell row CR1 formed at the bottom end of the drawing. The power supply wiring 125 is connected to each power supply wiring 11 extending in the Y direction through vias 137.

[0070] According to the modified example, power supply wiring for supplying power supply voltages VSS and VDD is formed in a mesh pattern in the BM0 wiring layer and the BM1 wiring layer, thereby reducing the wiring resistance of the wiring for supplying the power supply voltage and suppressing fluctuations in the power supply voltage, thereby suppressing a decrease in the operating speed of the semiconductor memory device and improving the stability of operation.

[0071] Second Embodiment Fig. 10 is a plan view showing an example of a layout structure of an SRAM cell according to a second embodiment. Specifically, Fig. 10(a) shows the upper part of the cell, and Fig. 10(b) shows the lower part of the cell. In Fig. 10, compared to Fig. 1, the power supply wiring 11 in the BM0 wiring layer is omitted, and a power supply wiring 75 is formed in the M1 wiring layer.

[0072] Specifically, a power supply wiring 75 is formed in the M1 wiring layer, extending in the Y direction from the upper to the lower ends of the cell. The power supply wiring 75 supplies a power supply voltage VDD. The power supply wiring 75 is formed between the wiring 71 and the wiring 72.

[0073] The power supply wiring 75 is connected to a portion (region 46) that will become the source of the load transistor PU1 through a via 85 that is provided at a position that overlaps the power supply wiring 75 in a plan view. The power supply wiring 75 is also connected to a portion (region 49) that will become the source of the load transistor PU2 through a via 86 that is provided at a position that overlaps the power supply wiring 75 in a plan view.

[0074] According to the above configuration, power supply wirings 12 and 13 that supply a power supply voltage VSS are formed in the BM0 wiring layer, which is a wiring layer on the back surface of the transistor. Wirings 71 and 72 corresponding to the bit lines BLB and BL, respectively, and a power supply wiring 75 that supplies a power supply voltage VDD are formed in the M1 wiring layer, which is a metal wiring layer above the transistor. As a result, the only wiring formed in the BM0 wiring layer is the power supply wiring that supplies the power supply voltage VSS. Therefore, the wiring width of the power supply wirings (power supply wirings 12 and 13) that supply the power supply voltage VSS in the BM0 wiring layer can be increased, the wiring resistance of the power supply wiring can be reduced, and fluctuations in the power supply voltage can be suppressed. This makes it possible to suppress a decrease in the operating speed of the semiconductor memory device and improve the stability of operation.

[0075] Furthermore, since it is not necessary to form a power supply wiring for supplying the power supply wiring VSS to the M1 wiring layer, it is possible to increase the wiring width of the wirings 71 and 72 corresponding to the bit lines BLB and BL, respectively, thereby suppressing the wiring resistance of the bit lines and preventing a decrease in the operating speed of the semiconductor memory device.

[0076] Furthermore, a power supply wiring 75 that supplies a power supply voltage VDD is formed between the wiring 71 and the wiring 72. This suppresses crosstalk noise between the wirings 71 and 72 that correspond to the bit lines BLB and BL, respectively, and thus makes it possible to prevent deterioration in the performance and reliability of the semiconductor memory device.

[0077] Furthermore, wiring 91 corresponding to the word line WL is formed in the M2 wiring layer, which is the layer above the M1 wiring layer. This eliminates the need for a connection portion for connecting the wiring on the back side of the transistor with the wiring on the front side (the layer above the transistor), thereby preventing a decrease in the operating speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0078] In addition, the same effects as those in FIG. 1 can be obtained.

[0079] 11 is a plan view showing another example of the layout structure of the SRAM cell according to the second embodiment. Specifically, FIG. 11(a) shows the upper part of the cell, and FIG. 11(b) shows the lower part of the cell. In FIG. 11, compared to FIG. 10, power supply wiring 14 is formed in the BM0 wiring layer.

[0080] Specifically, a power supply wiring 14 is formed in the BM0 wiring layer, extending in the Y direction from the top to the bottom of the cell in the drawing. The power supply wiring 14 supplies a power supply voltage VDD. The power supply wiring 14 is formed between the power supply wiring 12 and the power supply wiring 13. The power supply wiring 14 overlaps with the active regions P1 and P2 and the power supply wiring 75 in a plan view.

[0081] The power supply wiring 14 is connected to a portion (region 46) that will become the source of the load transistor PU1 through a via 115 that is provided at a position that overlaps the power supply wiring 14 in a plan view. The power supply wiring 14 is also connected to a portion (region 49) that will become the source of the load transistor PU2 through a via 116 that is provided at a position that overlaps the power supply wiring 14 in a plan view.

[0082] According to the modified example, the power supply wiring 14 that supplies the power supply voltage VDD is formed in the BM0 wiring layer, which is the wiring layer on the back surface of the transistor. This allows the wiring width of the power supply wiring 75 that is formed in the M1 wiring layer and supplies the power supply voltage VDD to be reduced, so that the wiring width of the wirings 71 and 72 that correspond to the bit lines BLB and BL, respectively, can be increased while suppressing crosstalk noise between them.

[0083] Furthermore, since the power supply wiring for supplying the power supply voltage VDD is formed in the M1 wiring layer and the BM0 wiring layer, it is possible to reduce the wiring width of the power supply wiring 14 formed in the BM0 wiring layer. This allows the wiring width of the power supply wirings 12 and 13 for supplying the power supply voltage VSS to be increased, the wiring resistance of the power supply wiring can be reduced, and fluctuations in the power supply voltage can be suppressed, so that a decrease in the operating speed of the semiconductor memory device can be suppressed and the stability of operation can be improved.

[0084] In addition, the same effects as those in FIG. 10 can be obtained.

[0085] In this modification, the power supply wiring 121 that supplies the power supply voltage VSS is formed in the BM1 wiring layer, but this is not limited to this. For example, instead of the power supply wiring 121, a power supply wiring that supplies the power supply voltage VDD may be formed in the BM1 wiring layer. In this case, similar to FIG. 6 , this power supply wiring may be connected to the power supply wiring 14 in the BM0 wiring layer. Furthermore, in addition to the power supply wiring 121, power supply wiring that supplies the power supply voltage VDD and the power supply voltage VSS may be formed in the BM1 wiring layer. In this case, similar to FIG. 7 , the power supply wiring that supplies the power supply voltage VDD may be connected to the power supply wiring 14, and the power supply wiring that supplies the power supply voltage VSS may be connected to the power supply wiring 12 and 13.

[0086] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0087] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0088] In addition, in the above-described embodiments and modifications, the width in the X direction of the nanosheets 21 to 24 is twice the width in the X direction of the nanosheets 25 and 26, but this is not limited to this. The width in the X direction of each of the nanosheets 21 to 26 may be determined taking into consideration the operational stability of the SRAM circuit, etc.

[0089] In addition, in each of the above-described embodiments and modifications, the shared contacts 61 and 62 may be manufactured in the same process as the contacts (gate contacts) and local wiring, or may be manufactured in a separate process.

[0090] Furthermore, in each of the above-described embodiments and modified examples, the power supply that supplies the power supply voltage VDD to the sources (regions 46, 49) of the load transistors PU1, PU2 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit or a power supply generated inside the semiconductor memory device.

[0091] According to the present disclosure, in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor, it is possible to suppress a decrease in the operating speed of a semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0092] 11-14, 75 Power supply wiring 111-116 Vias 21-26 Nanosheets 31-34 Gate wiring 40-49 Areas 71, 72 Wiring PU1, PU2 Load transistors PD1, PD2 Drive transistors PG1, PG2 Access transistors BL, BLB Bit lines WL Word lines

Claims

1. A semiconductor memory device including an SRAM cell, the SRAM cell comprising: a first transistor having a source connected to a first power supply supplying a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply supplying a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, the first bit line is formed in a metal wiring layer above the first to sixth transistors and includes a first wiring extending in a first direction; the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction; the SRAM cell includes: a first active region constituting a channel, source, and drain of the first transistor and including a nanosheet extending in the first direction as the channel; a second active region constituting the channel, source, and drain of the second transistor and including a nanosheet extending in the first direction as the channel; a third active region constituting the channel, source, and drain of the third transistor and including a nanosheet extending in the first direction as the channel; a fourth active region constituting the channel, source, and drain of the fourth transistor and including a nanosheet extending in the first direction as the channel; a first power supply wiring formed in a first back wiring layer on the back side of the first to sixth transistors, extending in the first direction, overlapping with the first and second active regions in a plan view, and connected to the first power supply;a second power supply wiring formed in the first backside wiring layer, extending in the first direction, overlapping with the third active region in a planar view, and connected to the second power supply; a third power supply wiring formed in the first backside wiring layer, extending in the first direction, overlapping with the fourth active region in a planar view, and connected to the second power supply; a first via formed at a position where a first region constituting a source in the first active region and the first power supply wiring overlap, and connecting the first region and the first power supply wiring; a second via formed at a position where a second region constituting a source in the second active region and the first power supply wiring overlap, and connecting the second region and the first power supply wiring; a third via formed at a position where a third region constituting a source in the third active region and the second power supply wiring overlap, and connecting the third region and the second power supply wiring; and a fourth via formed at a position where a fourth region constituting a source in the fourth active region and the third power supply wiring overlap, and connecting the fourth region and the third power supply wiring.

2. A semiconductor memory device according to claim 1, wherein the SRAM cell is formed in a second back wiring layer below the first back wiring layer, and further comprises a fifth power supply wiring extending in a second direction perpendicular to the first direction.

3. A semiconductor memory device according to claim 2, wherein the fifth power supply wiring is connected to the second power supply wiring and the third power supply wiring.

4. A semiconductor memory device according to claim 3, wherein the SRAM cell further comprises a sixth power supply wiring formed in the second backside wiring layer, extending in the second direction, and connected to the first power supply wiring.

5. A semiconductor memory device according to claim 2, wherein the fifth power supply wiring is connected to the first power supply wiring.

6. A semiconductor memory device according to claim 1, comprising a plurality of said SRAM cells, said plurality of SRAM cells being arranged side by side in said first direction and a second direction perpendicular to said first direction, and said SRAM cells arranged side by side in said first direction being commonly connected to the same said first power supply wiring and commonly connected to the same said second power supply wiring.

7. A semiconductor memory device according to claim 6, wherein the plurality of SRAM cells comprise: a first SRAM cell; a second SRAM cell; a plurality of fifth power supply wirings formed in a second back wiring layer below the first back wiring layer, extending in the second direction and connected to the second power supply; and a plurality of sixth power supply wirings formed in the second back wiring layer, extending in the second direction and connected to the first power supply; a first cell row including a plurality of the first SRAM cells aligned in the second direction and a second cell row including a plurality of the second SRAM cells aligned in the second direction are alternately arranged in the first direction; in the first cell row, the second power supply wirings in the plurality of first SRAM cells are commonly connected to the same fifth power supply wiring; and in the second cell row, the first power supply wirings in the plurality of second SRAM cells are commonly connected to the same sixth power supply wiring.

8. A semiconductor memory device according to claim 6, wherein the plurality of SRAM cells are provided with a plurality of fifth power supply wirings formed in a second back wiring layer below the first back wiring layer, extending in the second direction and connected to the second power supply; a plurality of third cell columns each including a plurality of the SRAM cells lined up in the second direction are arranged side by side in the first direction, and in the third cell column, the second power supply wirings in the plurality of SRAM cells are commonly connected to the same fifth power supply wiring; the second power supply wirings in the plurality of SRAM cells are formed in the second back wiring layer, extend in the second direction and are connected to a sixth power supply wiring connected to the first power supply; and the sixth power supply wiring is arranged outside the plurality of SRAM cells in a planar view.

9. A semiconductor memory device including an SRAM cell, the SRAM cell comprising: a first transistor having a source connected to a first power supply supplying a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply supplying a second power supply voltage different from the first power supply voltage, a drain connected to the second node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, the first bit line is formed in a metal wiring layer above the first to sixth transistors and includes a first wiring extending in a first direction; the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction; the SRAM cell includes: a third active region constituting a channel, a source, and a drain of the third transistor and including a nanosheet extending in the first direction as the channel; a fourth active region constituting a channel, a source, and a drain of the fourth transistor and including a nanosheet extending in the first direction as the channel; a first power supply wiring formed in the metal wiring layer, extending in the first direction, and connected to the first power supply; a second power supply wiring formed in a first backside wiring layer on the backside of the first to sixth transistors, extending in the first direction, overlapping with the third active region in a plan view, and connected to the second power supply; and a third power supply wiring formed in the first backside wiring layer, extending in the first direction, overlapping with the fourth active region in a plan view, and connected to the second power supply.a third via formed at a position where a third region constituting a source in the third active region and the second power supply wiring overlap, connecting the third region and the second power supply wiring; and a fourth via formed at a position where a fourth region constituting a source in the fourth active region and the third power supply wiring overlap, connecting the fourth region and the third power supply wiring.

10. A semiconductor memory device according to claim 9, wherein the SRAM cell is formed in a second back wiring layer below the first back wiring layer, extends in a second direction perpendicular to the first direction, and further comprises a fifth power supply wiring connected to the second power supply wiring and the third power supply wiring.

11. A semiconductor memory device according to claim 10, wherein the SRAM cell further comprises: a first active region constituting the channel, source and drain of the first transistor, the channel being a nanosheet extending in the first direction; a second active region constituting the channel, source and drain of the second transistor, the channel being a nanosheet extending in the first direction; a fourth power supply wiring formed in the first backside wiring layer, extending in the first direction, overlapping with the first and second active regions in a planar view, and connected to the first power supply; a first via formed at a position where the first region constituting the source in the first active region and the fourth power supply wiring overlap, connecting the first region and the fourth power supply wiring; and a second via formed at a position where the second region constituting the source in the second active region and the fourth power supply wiring overlap, connecting the second region and the fourth power supply wiring.

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