Semiconductor memory device

Abstract

Wires (11, 12) respectively corresponding to bit lines BLB, BL are formed in a BM0 wiring layer, which is a wiring layer on the back surface of a transistor. Power supply wires (72, 73) for supplying a power supply voltage VSS are formed in a metal wiring layer. An SRAM cell is provided with: an active region (N1) that overlaps the wire (11) in a plan view and is connected to the wire (11); and an active region (N2) that overlaps the wire (12) in a plan view and is connected to the wire (12).

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device, and in particular to a layout structure of a static random access memory (SRAM) cell (hereinafter, also simply referred to as a cell, as appropriate).

[0002] SRAMs are widely used in semiconductor integrated circuits.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltage, and improved operating speed through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. One example of a three-dimensional transistor is the nanosheet FET (Field Effect Transistor).

[0004] Patent Document 1 discloses a technique for providing word lines on the back surface of the substrate directly below the transistors in order to achieve even higher integration.

[0005] US Patent Application Publication No. 2022 / 0336474

[0006] In the technology of Patent Document 1, the bit lines and power supply lines are provided in the same wiring layer, so the wiring width of the bit lines cannot be increased. This increases the wiring resistance of the bit lines and reduces the operating speed of the semiconductor memory device. Furthermore, since the bit lines and power supply lines are provided in the same wiring layer, the wiring width of the power supply lines cannot be increased. This increases the wiring resistance of the power supply lines and increases the power supply voltage drop, reducing the operating speed of the semiconductor memory device. Furthermore, the distance between the bit lines and power supply lines is short, so parasitic capacitance increases and the operating speed of the semiconductor memory device is reduced.

[0007] Furthermore, since the word lines are provided on the back side of the substrate, in order to connect the word lines to the wiring on the front side of the substrate in the peripheral circuit, a connection part for connecting the wiring on the back side and the wiring on the front side is required, which increases the area of ​​the semiconductor memory device and reduces the operating speed of the semiconductor memory device due to the resistance of the connection part.

[0008] The present disclosure aims to prevent an increase in the area of ​​a semiconductor memory device while preventing a decrease in the operating speed of the semiconductor memory device in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor.

[0009] The present disclosure provides a semiconductor memory device including an SRAM cell, the SRAM cell comprising: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line that forms a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, the first bit line being connected to a first backside arrangement on the backside of the first to sixth transistors. the second bit line is formed in the first backside wiring layer and includes a second wiring extending in the first direction; the SRAM cell comprises: a first active region constituting the channel, source, and drain of the fifth transistor, the channel including a nanosheet extending in the first direction; a second active region constituting the channel, source, and drain of the sixth transistor, the channel including a nanosheet extending in the first direction; a first via formed at a position where the first region constituting the source in the first active region and the first wiring overlap, connecting the first region and the first wiring; a second via formed at a position where the second region constituting the source in the second active region and the second wiring overlap, connecting the second region and the second wiring; and a first power supply wiring formed in a metal wiring layer above the first to sixth transistors, extending in the first direction, and connected to the second power supply.

[0010] According to the present disclosure, first and second wirings corresponding to the first and second bit lines, respectively, are formed in a first back wiring layer, which is a wiring layer on the back side of the transistor. A first power supply wiring for supplying a second power supply voltage is formed in a metal wiring layer above the transistor. As a result, only the first and second bit lines are formed in the first back wiring layer. Therefore, the wiring widths of the first and second wirings formed in the first back wiring layer can be increased, thereby reducing the wiring resistance of the bit lines. Furthermore, the first wirings overlap the first active region in a planar view and are connected to each other by a first via provided in the overlapping region. The second wirings overlap the second active region in a planar view and are connected to each other by a second via provided in the overlapping region. Therefore, the resistance from the bit lines to the active region can be reduced. These features can prevent a decrease in the operating speed of the semiconductor memory device.

[0011] Furthermore, since it is not necessary to form wiring corresponding to the first and second bit lines in the metal wiring layer, the wiring width of the first power supply wiring for supplying the second power supply voltage in the metal wiring layer can be increased, which reduces the wiring resistance of the power supply wiring, thereby suppressing fluctuations in the power supply voltage, preventing a decrease in the operating speed of the semiconductor memory device, and improving the stability of operation.

[0012] Furthermore, by forming wiring equivalent to word lines in the upper layer of the metal wiring layer, a connection section for connecting the wiring on the back side of the transistor with the wiring on the surface side (upper layer of the transistor) is not required, so it is possible to prevent a decrease in the operating speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0013] According to the present disclosure, in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor, it is possible to prevent a decrease in the operating speed of a semiconductor memory device while preventing an increase in the area of ​​the semiconductor memory device.

[0014] 1 is a plan view showing an example of a layout structure of an SRAM cell according to the first embodiment. 2 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment. 3 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment. 4 is a circuit diagram showing a configuration of an SRAM cell according to the first embodiment. 5 is another configuration example of a semiconductor integrated circuit device according to the first embodiment. 6 is a plan view showing an example of a layout structure of an SRAM cell according to the second embodiment. 7 is a plan view showing another example of a layout structure of an SRAM cell according to the second embodiment. 8 is a plan view showing another example of a layout structure of an SRAM cell according to the second embodiment. 9 is a cross-sectional view showing another example of a layout structure of an SRAM cell according to the second embodiment. 10 is a plan view showing an example of a layout of a circuit block included in a semiconductor memory device according to a third embodiment. 11 is a plan view showing an example of a layout of a circuit block included in a semiconductor memory device according to the third embodiment. 12 is a circuit diagram showing a configuration of a memory cell array according to the third embodiment. 13 is a circuit diagram showing a configuration of a read / write circuit according to the third embodiment.

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells, and at least some of the plurality of SRAM cells include nanosheet FETs. A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which a current flows. The nanosheet is formed of, for example, silicon. In the present disclosure, the transistor included in the SRAM cell is not limited to a nanosheet FET.

[0016] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0017] 1 to 3 show an example of the layout structure of an SRAM cell according to the first embodiment, with FIGS. 1(a) and 1(b) being plan views, and FIGS. 2(a) to 2(c) and 3(a) and 3(b) being cross-sectional views in the horizontal direction in a plan view. Specifically, FIG. 1(a) shows the upper part of the cell, which is the M1 and M2 wiring layers, and FIG. 1(b) shows the lower part of the cell, which is a layer below the M1 and M2 wiring layers and includes a nanosheet FET. FIG. 2(a) shows a cross section along line X1-X1', FIG. 2(b) shows a cross section along line X2-X2', FIG. 2(c) shows a cross section along line X3-X3', FIG. 3(a) shows a cross section along line X4-X4', and FIG. 3(b) shows a cross section along line X5-X5'.

[0018] In the following description, in plan views such as Figure 1, the vertical direction of the drawing is the Y direction (corresponding to the first direction), the horizontal direction of the drawing (corresponding to the second direction) is the X direction, and the direction perpendicular to the substrate surface is the Z direction.

[0019] 4 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. As shown in FIG. 4, the SRAM cell includes an SRAM circuit made up of load transistors PU1 and PU2, drive transistors PD1 and PD2, and access transistors PG1 and PG2. The load transistors PU1 and PU2 are P-type FETs, and the drive transistors PD1 and PD2 and the access transistors PG1 and PG2 are N-type FETs.

[0020] The load transistor PU1 is provided between the power supply VDD and a first node NA, and the drive transistor PD1 is provided between the first node NA and a power supply VSS. The gates of the load transistor PU1 and the drive transistor PD1 are connected to a second node NB, and they form an inverter INV1. The load transistor PU2 is provided between the power supply VDD and the second node NB, and the drive transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the load transistor PU2 and the drive transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0021] The access transistor PG1 is provided between the bit line BL and a first node NA, and has its gate connected to the word line WL. The access transistor PG2 is provided between the bit line BLB and a second node NB, and has its gate connected to the word line WL. The bit lines BL and BLB form a complementary bit line pair.

[0022] In an SRAM circuit, when the bit lines BL and BLB constituting a complementary bit line pair are driven to a high level and a low level, respectively, and the word line WL is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the bit lines BL and BLB are driven to a low level and a high level, respectively, and the word line WL is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the word line WL is driven to a low level while data is written to the first and second nodes NA and NB, respectively, the latch state is established and the data written to the first and second nodes NA and NB is held.

[0023] Furthermore, when the bit lines BL and BLB are precharged to a high level and the word line WL is driven to a high level, the states of the bit lines BL and BLB are determined according to the data written to the first and second nodes NA and NB, respectively, and data can be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the bit line BL is held at a high level and the bit line BLB is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the bit line BL is discharged to a low level and the bit line BLB is held at a high level.

[0024] As described above, the SRAM cell has the functions of writing data to the SRAM cell, holding data, and reading data from the SRAM cell by controlling the bit lines BL, BLB and word lines WL.

[0025] In the following description, the solid lines running vertically and horizontally in plan views such as FIG. 1 and the solid lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid. However, from the perspective of suppressing manufacturing variations, it is preferable to arrange the components on a grid.

[0026] 1 and other plan views, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. The SRAM cell is arranged so that the cell frame is in contact with the cell frame of an adjacent cell in the X or Y direction.

[0027] 1 and the like, an SRAM cell is arranged on each side of the SRAM cell in the X direction, with the SRAM cell inverted in the X direction, and an SRAM cell is arranged on each side of the SRAM cell in the Y direction, with the SRAM cell inverted in the Y direction.

[0028] As shown in Figure 1B, wiring lines 11 and 12 extending in the Y direction from the top to the bottom of the cell are formed in a BM0 (Backside Metal 0) wiring layer provided on the backside of the semiconductor chip on which the transistor is formed. The wiring lines 11 and 12 correspond to bit lines BLB and BL, respectively. The BM0 wiring layer corresponds to the first backside wiring layer.

[0029] A plurality of active regions constituting the channel, source, and drain of the N-type transistor are formed in an N-type transistor region on a P-type substrate (PSub) (not shown). Specifically, active regions N1 and N2 are formed in the N-type transistor region. The active regions N1 and N2 overlap with wirings 11 and 12, respectively, in a plan view.

[0030] In the N-type transistor region, an access transistor PG2, a drive transistor PD1, a drive transistor PD2, and an access transistor PG1 are formed. The access transistor PG2, the drive transistor PD1, the drive transistor PD2, and the access transistor PG1 each have a channel made of three overlapping sheet structures in a plan view, and each have nanosheets 21 to 24 extending in the Y direction. In other words, the access transistor PG2, the drive transistor PD1, the drive transistor PD2, and the access transistor PG1 are nanosheet FETs.

[0031] In the active region N1, a portion (region 40) that serves as the source of the access transistor PG2 is connected to the wiring 11 through a via 111 that is provided at a position that overlaps the wiring 11 in a plan view. In the active region N2, a portion (region 45) that serves as the source of the access transistor PG1 is connected to the wiring 12 through a via 112 that is provided at a position that overlaps the wiring 12 in a plan view.

[0032] A plurality of active regions constituting the channel, source, and drain of the P-type transistor are formed in a P-type transistor region on an N-type well (NWell) (not shown). Specifically, active regions P1 and P2 are formed in the P-type transistor region.

[0033] Load transistors PU1 and PU2 are formed in the P-type transistor region. The load transistors PU1 and PU2 each have a channel made of three overlapping sheets in a plan view, with nanosheets 25 and 26 extending in the Y direction. In other words, the load transistors PU1 and PU2 are nanosheet FETs. The width in the X direction of the nanosheets 21 to 24 is twice the width in the X direction of the nanosheets 25 and 26.

[0034] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0035] As shown in FIG. 1B, gate wirings (Gate) 31 to 34 are formed extending in the X direction. The gate wiring 31 surrounds the outer periphery of the nanosheet 21 in the X and Z directions. The gate wiring 32 surrounds the outer periphery of the nanosheets 25 and 22 in the X and Z directions. The gate wiring 33 surrounds the outer periphery of the nanosheets 23 and 26 in the X and Z directions. The gate wiring 34 surrounds the outer periphery of the nanosheet 24 in the X and Z directions. The gate wiring 31 corresponds to the gate of the access transistor PG2. The gate wiring 32 corresponds to the gates of the load transistor PU1 and the drive transistor PD1. The gate wiring 33 corresponds to the gates of the drive transistor PD2 and the load transistor PU2. The gate wiring 34 corresponds to the gate of the access transistor PG1.

[0036] In the local wiring layer, local wirings 51 to 58 extending in the X direction are formed. Local wiring 51 is connected to region 40 in active region N1. Local wiring 52 is connected to region 46 in active region P1. Local wiring 53 is connected to region 43 in active region N2. Local wiring 54 is connected to region 41 in active region N1 and region 48 in active region P2. Local wiring 55 is connected to region 47 in active region P1 and region 44 in active region N2. Local wiring 56 is connected to region 42 in active region N1. Local wiring 57 is connected to region 49 in active region P2. Local wiring 58 is connected to region 45 in active region N2.

[0037] Region 40 is a portion of active region N1 that will become the source of access transistor PG2. Region 41 is a portion of active region N1 that will become the drain of access transistor PG2 and the drain of drive transistor PD2. Region 42 is a portion of active region N1 that will become the source of drive transistor PD2. Region 43 is a portion of active region N2 that will become the source of drive transistor PD1. Region 44 is a portion of active region N2 that will become the drain of drive transistor PD1 and the drain of access transistor PG1. Region 45 is a portion of active region N2 that will become the source of access transistor PG1. Region 46 is a portion of active region P1 that will become the source of load transistor PU1. Region 47 is a portion of active region P1 that will become the drain of load transistor PU1. Region 48 is a portion of active region P2 that will become the drain of load transistor PU2. Region 49 is a portion of active region P2 that will become the source of load transistor PU2.

[0038] The local wiring 54 is connected to the gate wiring 32 via a shared contact 61. The local wiring 55 is connected to the gate wiring 33 via a shared contact 62. The gate wiring 33, the local wiring 55, and the shared contact 62 correspond to a first node NA. The gate wiring 32, the local wiring 54, and the shared contact 61 correspond to a second node NB.

[0039] As shown in FIG. 1A, power supply wirings 71 to 73 extending in the Y direction from the top to the bottom of the cell are formed in the M1 wiring layer, which is a metal wiring layer above the local wiring layer. Wires 74 and 75 are also formed. The power supply wiring 71 supplies a power supply voltage VDD. The power supply wirings 72 and 73 supply a power supply voltage VSS. The power supply wiring 71 overlaps with the active regions P1 and P2 in a planar view. The power supply wiring 72 overlaps with the active region N1 and wiring 11 in a planar view. The power supply wiring 73 overlaps with the active region N2 and wiring 12 in a planar view.

[0040] The power supply wiring 71 is connected to the local wiring 52 through a via 81, and is connected to the local wiring 57 through a via 82. The power supply wiring 72 is connected to the local wiring 56 through a via 83. The power supply wiring 73 is connected to the local wiring 53 through a via 84. The wiring 74 is connected to the gate wiring 31 through a via (gate-contact) 85. The wiring 75 is connected to the gate wiring 34 through a via 86.

[0041] In the M2 wiring layer, which is the layer above the M1 wiring layer, a wiring 91 is formed, which extends in the X direction from both the left and right ends of the cell in the drawing. The wiring 91 corresponds to the word line WL. The wiring 91 is connected to the wiring 74 via a contact 101 and to the wiring 75 via a contact 102.

[0042] With the above configuration, wirings 11 and 12 corresponding to bit lines BLB and BL, respectively, are formed in the BM0 wiring layer, which is the wiring layer on the back surface of the transistor. A power supply wiring 71 that supplies power supply voltage VDD and power supply wirings 72 and 73 that supply power supply voltage VSS are formed in the M1 wiring layer, which is the metal wiring layer above the transistor. As a result, the only wirings formed in the BM0 wiring layer are the bit lines BLB and BL. Therefore, the wiring width of the wirings (wirings 11 and 12) corresponding to bit lines BL and BLB formed in the BM0 wiring layer can be increased, thereby reducing the wiring resistance of the bit lines. Furthermore, wiring 11 overlaps with active region N1 in a planar view and is connected to each other by a via provided in the overlapping region. Wiring 12 overlaps with active region N2 in a planar view and is connected to each other by a via provided in the overlapping region. Therefore, the resistance from the bit lines to the active region can be reduced. These features prevent a decrease in the operating speed of the semiconductor memory device.

[0043] Furthermore, since it is not necessary to form wiring corresponding to the bit lines BLB and BL in the M1 wiring layer, the wiring width of the power supply wiring 71 that supplies the power supply voltage VDD and the power supply wirings 72 and 73 that supply the power supply voltage VSS in the M1 wiring layer can be increased. This reduces the wiring resistance of the power supply wiring, thereby suppressing fluctuations in the power supply voltage, preventing a decrease in the operating speed of the semiconductor memory device, and improving the stability of operation.

[0044] Furthermore, wiring 91 corresponding to the word line WL is formed in the M2 wiring layer, which is the layer above the M1 wiring layer. This eliminates the need for a connection portion for connecting the wiring on the back side of the transistor with the wiring on the front side (the layer above the transistor), thereby preventing a decrease in the operating speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0045] In addition, wirings corresponding to the bit lines BL and BLB may be further provided in the BM1 wiring layer below the BM0 wiring layer, i.e., the layer farther from the transistors, and extending in the Y direction. These wirings may be connected to the wirings 11 and 12.

[0046] The bit lines formed on the back side of the transistors may be formed using a semiconductor chip separate from the semiconductor chip on which the transistors are formed.

[0047] Fig. 5(a) shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 200 shown in Fig. 5(a) is configured by stacking a first semiconductor chip 201 (chip A) and a second semiconductor chip 202 (chip B). Chip A has the SRAM cells and the like arranged therein. Chip B has bit lines formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps and the like.

[0048] 5B shows a cross section of the SRAM cell of FIG. 1 taken along line X1-X1' in this configuration example. As shown in FIG. 5B, a wiring layer provided on the surface of chip B has wiring 11 corresponding to bit line BLB and wiring 12 corresponding to bit line BL formed therein. Wiring 11 is connected to region 40 of chip A via via 111 provided at a position overlapping wiring 11 in a planar view. Although not shown, wiring 12 is connected to region 45 of chip A via via 112 provided at a position overlapping wiring 11 in a planar view.

[0049] Second Embodiment Figure 6 is a plan view showing an example of the layout structure of an SRAM cell according to a second embodiment. Specifically, Figure 6(a) shows the upper part of the cell, and Figure 6(b) shows the lower part of the cell. In Figure 6, compared to Figure 1, the power supply wiring 71 in the M1 wiring layer is omitted, and the power supply wiring 13 is formed in the BM0 wiring layer. Accordingly, the wiring width of the power supply wirings 72 and 73 in the M1 wiring layer is wider.

[0050] Specifically, a power supply wiring 13 is formed in the BM0 wiring layer, extending in the Y direction from both the top and bottom of the cell. The power supply wiring 13 supplies a power supply voltage VDD. The power supply wiring 13 is formed between the wiring 11 and the wiring 12. The power supply wiring 13 overlaps with the active regions P1 and P2 in plan view.

[0051] The power supply wiring 13 is connected to a portion (region 46) that will become the source of the load transistor PU1 through a via 113 that is provided at a position that overlaps the power supply wiring 13 in a plan view. The power supply wiring 13 is also connected to a portion (region 49) that will become the source of the load transistor PU2 through a via 114 that is provided at a position that overlaps the power supply wiring 13 in a plan view.

[0052] With the above configuration, the wiring 11 and 12 corresponding to the bit lines BLB and BL, respectively, and the power supply wiring 13 for supplying the power supply voltage VDD are formed in the BM0 wiring layer, which is the wiring layer on the back surface of the transistor. Only the power supply wiring 72 and 73 for supplying the power supply voltage VSS are formed in the M1 wiring layer, which is the metal wiring layer above the transistor. This allows the wiring width of the power supply wiring 72 and 73 for supplying the power supply voltage VSS in the M1 wiring layer to be increased. This reduces the wiring resistance of the power supply wiring, thereby suppressing fluctuations in the power supply voltage, preventing a decrease in the operating speed of the semiconductor memory device, and improving operational stability.

[0053] Furthermore, a power supply wiring 13 that supplies a power supply voltage VDD is formed between the wiring 11 and the wiring 12. This suppresses crosstalk noise between the wirings 11 and 12 that correspond to the bit lines BLB and BL, respectively, and therefore prevents deterioration in performance and reliability of the semiconductor memory device.

[0054] Furthermore, wiring 91 corresponding to the word line WL is formed in the M2 wiring layer, which is the layer above the M1 wiring layer. This eliminates the need for a connection portion for connecting the wiring on the back side of the transistor with the wiring on the front side (the layer above the transistor), thereby preventing a decrease in the operating speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0055] In addition, the same effects as those in FIG. 1 can be obtained.

[0056] In addition, wirings corresponding to the bit lines BL and BLB, which extend in the Y direction, may be further provided in the BM1 wiring layer below the BM0 wiring layer. These wirings may be connected to the wirings 11 and 12.

[0057] 7A and 7B are plan views showing another example of the layout structure of the SRAM cell according to the second embodiment. Specifically, FIG. 7A shows the upper part of the cell, and FIG. 7B shows the lower part of the cell. In FIG. 7, compared to FIG. 6, a power supply wiring 76 is formed in the M1 wiring layer.

[0058] Specifically, a power supply wiring 76 is formed in the M1 wiring layer, extending in the Y direction from the top to the bottom of the cell in the drawing. The power supply wiring 76 supplies a power supply voltage VDD. The power supply wiring 76 is formed between the power supply wiring 72 and the power supply wiring 73. The power supply wiring 76 overlaps with the active regions P1 and P2 and the power supply wiring 13 in a plan view.

[0059] The power supply wiring 76 is connected to the portion (region 46) that will become the source of the active region P1 through a via 87 that is provided at a position that overlaps the power supply wiring 76 in a planar view. The power supply wiring 76 is also connected to the portion (region 49) that will become the source of the active region P2 through a via 88 that is provided at a position that overlaps the power supply wiring 76 in a planar view.

[0060] According to the first modification, a power supply line 76 for supplying a power supply voltage VDD is formed in the M1 wiring layer, which is a metal wiring layer. This allows the width of the power supply line 13 formed in the BM0 wiring layer for supplying the power supply voltage VDD to be reduced, thereby increasing the width of the lines 11 and 12 while suppressing crosstalk noise between the lines 11 and 12 corresponding to the bit lines BLB and BL, respectively.

[0061] Furthermore, since the power supply wiring 13 that supplies the power supply voltage VDD is also formed in the BM0 wiring layer, the wiring width of the power supply wiring 76 that supplies the power supply voltage VDD, formed in the M1 wiring layer, can be reduced. This allows the wiring width of the power supply wirings 72 and 73 that supply the power supply voltage VSS in the M1 wiring layer to be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, which suppresses fluctuations in the power supply voltage, making it possible to prevent a decrease in the operating speed of the semiconductor memory device and improve operational stability.

[0062] In addition, the same effects as those in FIG. 6 can be obtained.

[0063] (Variation 2) Figures 8 and 9 show another example of the layout structure of the SRAM cell according to the second embodiment, with Figure 8 being a plan view and Figure 9 being a cross-sectional view in the horizontal direction in a plan view. Specifically, Figure 8 shows the lower part of the cell, and Figure 9 is a cross-section taken along line X6-X6'. The upper part of the cell in Figures 8 and 9 is the same as Figure 6(a).

[0064] 8 and 9, compared to FIG. 6, power supply wiring 121 is formed in the BM1 (Backside Metal 1) wiring layer. The BM1 wiring layer is a wiring layer provided on the backside of the semiconductor chip on which the transistors are formed, and is a layer below the BM0 wiring layer, i.e., the layer farther from the transistors. The BM1 wiring layer corresponds to the second backside wiring layer.

[0065] Specifically, a power supply wiring 121 is formed in the BM1 wiring layer, extending in the X direction from both the left and right ends of the cell in the drawing. The power supply wiring 121 supplies a power supply voltage VDD. The power supply wiring 121 is connected to the power supply wiring 13 in the BM0 wiring layer through a via 131.

[0066] According to the second modification, a power supply wiring 121 that supplies a power supply voltage VDD is formed in a layer below the BM0 wiring layer. The power supply wiring 121 is connected to the power supply wiring 13 in the BM0 wiring layer through a via 131. This reduces the wiring resistance of the power supply wiring that supplies the power supply voltage VDD, thereby suppressing fluctuations in the power supply voltage, preventing a decrease in the operating speed of the semiconductor memory device, and improving operational stability.

[0067] In addition, the same effects as those in FIG. 6 can be obtained.

[0068] 10 and 11 are plan views showing an example of the layout of a circuit block included in a semiconductor memory device according to a third embodiment. Note that only the cell frame of the SRAM cell, the frames of each circuit constituting the semiconductor memory device, and the bit lines (wires 11 and 12) in the BM0 wiring layer are shown in FIG. 10. Also, in FIG. 10, the memory cells MC arranged in the odd-numbered columns (first and third columns) from the left side of the drawing are horizontally inverted versions of the memory cells MC arranged in the even-numbered columns (second and fourth columns) from the left side of the drawing.

[0069] The semiconductor memory device according to the third embodiment includes a memory cell array A1 and a read / write circuit A2.

[0070] Fig. 12 is a circuit diagram showing the configuration of a memory cell array according to the third embodiment. As shown in Fig. 12, the memory cell array A1 includes a plurality of memory cells MC arranged in an array of m rows (m is a natural number) by n columns (n ​​is a natural number). In Fig. 12, the SRAM cells of Fig. 1 are arranged as the memory cells MC.

[0071] The memory cell array A1 includes a plurality of word lines WL (m in FIG. 12) arranged corresponding to the rows of the memory cells MC, and a plurality of bit line pairs BLT (n in FIG. 12) arranged corresponding to the columns of the memory cells MC. The bit line pair BLT is composed of a pair of bit lines BL and BLB. The word lines WL extend in the X direction. The bit lines BL and BLB extend in the Y direction. Each memory cell MC is connected to the word line WL of the row and the bit line pair BLT (bit lines BL and BLB) of the column corresponding to its arrangement position. The bit line pair BLT is connected to the read / write circuit A2 of FIG. 13.

[0072] 13 is a circuit diagram showing the configuration of a read / write circuit according to the third embodiment. In FIG. 13, one read / write circuit A2 is provided for every two columns. Specifically, the first column connected to the bit line pair BLT[0] and the second column connected to the bit line pair BLT[1] are connected to the read / write circuit A2.

[0073] The read / write circuit A2 includes two level-holding circuits A11 corresponding to the bit line pair BLT[0], BLT[1], two precharge circuits A12, and two column selectors A13. The read / write circuit A2 further includes one sense amplifier circuit A14.

[0074] When one of the bit lines BL and BLB goes low, the level-holding circuit A11 holds the other of the bit lines BL and BLB at high. The level-holding circuit A11 includes transistors Q11 and Q12 (Q21 and Q22).

[0075] The precharge circuit A12 precharges the bit line pair BLT (BL, BLB) based on a precharge signal PCG. The precharge circuit A12 includes transistors Q13 to Q15 (Q23 to Q25).

[0076] The column selector A13 selects whether to write or read data from the first column or the second column based on a column selection signal NCOL[1:0]. The column selector A13 includes transistors Q16 to Q19 (Q26 to Q29).

[0077] The sense amplifier circuit A14 amplifies a desired signal selected from two bit line pairs BLT[1:0] by a column selection signal NCOL[1:0] based on a sense amplifier enable signal NSAE, and outputs the amplified signal to a read data line pair RD[0], NRD[0]. The sense amplifier circuit A14 includes transistors Q31 to Q35.

[0078] Here, the bit line BL is connected to the gate of the transistor Q12 (Q22), and the bit line BLB is connected to the gate of the transistor Q11 (Q21). Except for the connections to the gates of the above transistors, the bit lines BL and BLB are connected only to the sources and drains of the transistors that make up the level-holding circuit A11, the precharge circuit A12, and the column selector A13.

[0079] The drains of the transistors Q16 and Q26 are connected to the gates of the transistors Q33 and Q34, and the drains of the transistors Q17 and Q27 are connected to the gates of the transistors Q31 and Q32.

[0080] As shown in FIG. 10, wirings 11 and 12 are formed in the BM0 wiring layer so as to extend linearly in the Y direction from the memory cell array A1 to the level hold circuit A11, precharge circuit A12, and column selector A13 that constitute the read / write circuit A2.

[0081] 11, the wiring 11 and wiring 12 extending in the Y direction are formed in the BM0 wiring layer. As described above, the wirings 11 and 12 correspond to the bit lines BLB and BL, respectively.

[0082] Active regions N3 and N4 are formed in the N-type transistor region. Active regions P3 to P7 are formed in the P-type transistor region. Wiring 11 overlaps with active regions P4, P7, P6, and N4 in plan view. Wiring 12 overlaps with active regions P3, P5, and N3 in plan view.

[0083] Transistors Q11 and Q12 of the level-holding circuit A11 are formed in active regions P3 and P4, respectively. Transistors Q13 to Q15 of the precharge circuit A12 are formed in active regions P3 and P7. Transistors Q16 and Q17 of the column selector A13 are formed in active regions P5 and P6, respectively. Transistors Q18 and Q19 of the column selector A13 are formed in active regions N3 and N4, respectively.

[0084] Region 40a is the portion that will become the drain of transistor Q11 in active region P3. Region 40b is the portion that will become the drain of transistor Q12 in active region P4. Region 40c is the portion that will become the source of transistor Q16 in active region P5. Region 40d is the portion that will become the drain of transistor Q16 in active region P5. Region 40e is the portion that will become the source of transistor Q17 in active region P6. Region 40f is the portion that will become the drain of transistor Q17 in active region P6. Region 40g is the portion that will become the drain of transistor Q13 and the source of transistor Q15 in active region P3. Region 40h is the portion that will become the drain of transistor Q14 and the drain of transistor Q15 in active region P7. Region 40i is the portion that will become the drain of transistor Q18 in active region N3. Region 40j is the portion that will become the drain of transistor Q19 in active region N4.

[0085] The regions 40a to 40j are connected to local wirings 50a to 50j, respectively.

[0086] The gate wirings 35 and 36 correspond to the gates of the transistors Q11 and Q12, respectively.

[0087] Gate wiring 35 is connected to wiring 11 via shared contact 64, local wiring 50b, region 40b, and via 116. Gate wiring 36 is connected to wiring 12 via shared contact 63, local wiring 50a, region 40a, and via 115. Via 115 is provided in a region where the portion (region 40a) of active region P3 that will become the drain of transistor Q11 and wiring 12 overlap in a planar view. Via 116 is provided in a region where the portion (region 40b) of active region P4 that will become the drain of transistor Q12 and wiring 11 overlap in a planar view. That is, the gates of transistors Q11 and Q12 are connected to bit lines BLB and BL via the drains of transistors Q12 and Q11, respectively. Similarly, the gates of transistors Q21 and Q22 are connected to bit lines BLB and BL (wirings 11 and 12) via the drains of transistors Q22 and Q21, respectively.

[0088] Region 40c is connected to interconnect 12 through via 117, which is provided at a position overlapping interconnect 12 in a planar view. Region 40d is connected to interconnect (not shown) formed in a metal interconnect layer (e.g., M1 interconnect layer, M2 interconnect layer) through local interconnect 50d and via 89. Region 40d is connected to the gates of transistors Q33 and Q34 through this interconnect. Region 40e is connected to interconnect 11 through via 118, which is provided at a position overlapping interconnect 11 in a planar view. Region 40f is connected to interconnect (not shown) formed in a metal interconnect layer (e.g., M1 interconnect layer, M2 interconnect layer) through local interconnect 50f and via 90. Region 40f is connected to the gates of transistors Q31 and Q32 through this interconnect. Via 117 is provided in a region where the portion (region 40c) that serves as the source of transistor Q16 in active region P5 and interconnect 12 overlap in a planar view. Via 118 is provided in a region where the portion of active region P6 that serves as the source of transistor Q17 (region 40e) overlaps with interconnect 11 in plan view. That is, transistor Q16 has its source connected to interconnect 12 and its drain connected to the gates of transistors Q33 and Q34. Transistor Q17 has its source connected to interconnect 11 and its drain connected to the gates of transistors Q31 and Q32. Similarly, transistor Q26 has its source connected to interconnect 12 and its drain connected to the gates of transistors Q33 and Q34. Transistor Q27 has its source connected to interconnect 11 and its drain connected to the gates of transistors Q31 and Q32.

[0089] Region 40g is connected to wiring 12 via via 118 provided at a position overlapping wiring 12 in a plan view. Region 40h is connected to wiring 11 via via 119 provided at a position overlapping wiring 11 in a plan view. Region 40i is connected to wiring 12 via via 120 provided at a position overlapping wiring 12 in a plan view. Region 40j is connected to wiring 12 via via 120a provided at a position overlapping wiring 11 in a plan view.

[0090] As described above, in the active area of ​​FIG. 11, the portions corresponding to the source and drain of each transistor constituting the level hold circuit A11, the precharge circuit A12, and the column selector A13 are connected to the wirings 11 and 12 (bit lines BLB and BL) to realize the circuit of FIG. 13.

[0091] Here, it is difficult to connect the wiring layers (BM0 wiring layer, BM1 wiring layer, etc.) provided on the back surface of the semiconductor chip to the gates (gate wiring) of each transistor through vias from the back surface side. Even if the connection were possible, it would be necessary to connect the gates through vias from both the front surface side and the back surface side, which would complicate the manufacturing process and increase manufacturing costs.

[0092] Therefore, in this embodiment, the gates of transistors Q11 and Q12 (gate wirings 35 and 36) are connected to wirings 11 and 12 (bit lines BLB and BL) formed in the BM0 wiring layer via the drains of transistors Q12 and Q11, respectively. This eliminates the need for a connection section for connecting the bit lines BLB and BL formed in the BM0 wiring layer to a metal wiring layer in order to connect to the gates of transistors Q11 and Q12, thereby preventing an increase in the area of ​​the semiconductor memory device.

[0093] Furthermore, the wirings 11 and 12 are connected to portions corresponding to the source and drain of each transistor constituting the level-holding circuit A11, the precharge circuit A12, and the column selector A13, so as to realize the circuit shown in Fig. 13. As shown in Fig. 13, the bit lines BL and BLB are connected only to the sources and drains of each transistor constituting the level-holding circuit A11, the precharge circuit A12, and the column selector A13, except for the gates of the transistors Q11 and Q12. The connections to the sources and drains of each transistor constituting the level-holding circuit A11, the precharge circuit A12, and the column selector A13 can be realized simply by connecting the wirings 11 and 12 to the portions of each transistor in the active region that will become the source and drain, and by forming vias located at positions that overlap the wirings (wirings 11 and 12) in a plan view, thereby suppressing an increase in the area of ​​the semiconductor memory device.

[0094] Furthermore, the source of transistor Q16 is connected to interconnect 12 formed in the BM0 wiring layer, and the drain is connected to the gates of transistors Q33 and Q34 via interconnects formed in the M1 wiring layer. The source of transistor Q17 is connected to interconnect 11 formed in the BM0 wiring layer, and the drain is connected to the gates of transistors Q31 and Q32 via interconnects formed in the M1 wiring layer. This allows the sources and drains of transistors Q16 and Q17 to be switched from the interconnect layers (BM0 wiring layer, BM1 wiring layer, etc.) provided on the back surface of the semiconductor chip to the interconnect layers (M1 wiring layer, M2 wiring layer) provided on the surface of the semiconductor chip. This eliminates the need for a connection from the interconnect layers provided on the back surface of the semiconductor chip to the interconnect layers provided on the surface, thereby suppressing an increase in the area of ​​the semiconductor memory device.

[0095] 10 and 11 are examples of the arrangement of the transistors that make up the level-holding circuit A11, the precharge circuit A12, and the column selector A13. For example, the transistors that make up the level-holding circuit A11, the precharge circuit A12, and the column selector A13 may be appropriately interchanged in the Y direction.

[0096] In addition, in FIG. 12, the SRAM cells of FIG. 1 are arranged as the memory cells MC, but this is not limitative, and the SRAM cells of FIGS. 6 to 8 may also be arranged.

[0097] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0098] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0099] In addition, in the above-described embodiments and modifications, the width in the X direction of nanosheets 21 to 24 is twice the width in the X direction of nanosheets 25 and 26, but is not limited to this. The width in the X direction of each of nanosheets 21 to 26 (i.e., the gate width of each transistor) may be determined taking into consideration the operational stability of the SRAM circuit, etc.

[0100] In addition, in each of the above-described embodiments and modifications, the shared contacts 61 to 64 may be manufactured in the same process as the contacts (gate contacts) and local wiring, or may be manufactured in a separate process.

[0101] Furthermore, in each of the above-described embodiments and modified examples, the power supply that supplies the power supply voltage VDD to the sources (regions 46, 49) of the load transistors PU1, PU2 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit or a power supply generated inside the semiconductor memory device.

[0102] According to the present disclosure, in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor, it is possible to prevent a decrease in the operating speed of a semiconductor memory device while preventing an increase in the area of ​​the semiconductor memory device.

[0103] 11, 12 Wiring 13, 71 to 73, 76 Power supply wiring 21 to 26 Nanosheet 31 to 36 Gate wiring 40 to 49, 40a to 40f Area PU1, PU2 Load transistor PD1, PD2 Drive transistor PG1, PG2 Access transistor BL, BLB Bit line WL Word line

Claims

1. A semiconductor memory device including an SRAM cell, the SRAM cell comprising: a first transistor having a source connected to a first power supply supplying a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply supplying a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, the first bit line is formed in a first back wiring layer on the back side of the first to sixth transistors and includes a first wiring extending in a first direction; the second bit line is formed in the first back wiring layer and includes a second wiring extending in the first direction; the SRAM cell comprises: a first active region constituting the channel, source, and drain of the fifth transistor and including a nanosheet extending in the first direction as the channel; a second active region constituting the channel, source, and drain of the sixth transistor and including a nanosheet extending in the first direction as the channel; a first via formed at a position where the first region constituting the source in the first active region and the first wiring overlap, connecting the first region and the first wiring; and a second via formed at a position where the second region constituting the source in the second active region and the second wiring overlap, connecting the second region and the second wiring. a first power supply wiring formed in a metal wiring layer above the first to sixth transistors, extending in the first direction, and connected to the second power supply.

2. A semiconductor memory device according to claim 1, wherein the SRAM cell further comprises a second power supply wiring formed in the metal wiring layer, extending in the first direction, and connected to the first power supply.

3. A semiconductor memory device according to claim 1, wherein the SRAM cell further comprises: a third power supply wiring formed in the first backside wiring layer, extending in the first direction and connected to the first power supply; a third active region constituting the channel, source and drain of the first transistor and including a nanosheet extending in the first direction as the channel; a fourth active region constituting the channel, source and drain of the second transistor and including a nanosheet extending in the first direction as the channel; a third via formed at a position where the third region constituting the source in the third active region and the third power supply wiring overlap and connecting the third region and the third power supply wiring; and a fourth via formed at a position where the fourth region constituting the source in the fourth active region and the third power supply wiring overlap and connecting the fourth region and the third power supply wiring.

4. A semiconductor memory device according to claim 3, wherein the SRAM cell further comprises a fourth power supply wiring formed in the metal wiring layer, extending in the first direction, and connected to the first power supply.

5. A semiconductor memory device according to claim 3, wherein the SRAM cell is formed in a second back wiring layer below the first back wiring layer, and further comprises a fifth power supply wiring extending in a second direction perpendicular to the first direction.

6. A semiconductor memory device including an SRAM cell and a level holding circuit, wherein the SRAM cell comprises: a fifth transistor having a source connected to a first bit line; and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line; the first bit line is formed in a first back wiring layer on the back side of the fifth and sixth transistors and includes a first wiring extending in a first direction; the second bit line is formed in the first back wiring layer and includes a second wiring extending in the first direction; and the SRAM cell comprises: a first active region forming the channel, source and drain of the fifth transistor and including a nanosheet extending in the first direction as the channel; a second active region forming the channel, source and drain of the sixth transistor and including a nanosheet extending in the first direction as the channel; a first via formed at a position where a first region forming the source in the first active region and the first wiring overlap, connecting the first region and the first wiring; a second via formed at a position where a second region constituting a source in the second active region and the second wiring overlap, connecting the second region and the second wiring; and the level holding circuit comprises: a seventh transistor; an eighth transistor having a drain connected to a gate of the seventh transistor and a gate connected to the drain of the seventh transistor; a fifth active region constituting the channel, source and drain of the seventh transistor and including a nanosheet extending in the first direction as the channel; a fifth via formed at a position where a fifth region constituting a drain in the fifth active region and the first wiring overlap, connecting the fifth region and the first wiring; and a third wiring formed on the surface side of the fifth region and connecting the fifth region and the gate of the eighth transistor.

7. A semiconductor memory device according to claim 6, wherein the level holding circuit further comprises: a sixth active region which constitutes the channel, source and drain of the eighth transistor and includes a nanosheet extending in the first direction as the channel; a sixth via which the sixth region constituting the drain in the sixth active region and the second wiring overlap, connecting the sixth region and the second wiring; and a fourth wiring which is formed on the surface side of the sixth region and connects the sixth region and the gate of the seventh transistor.

8. A semiconductor memory device according to claim 6, wherein said first wiring is formed linearly in said first direction from said SRAM cell to said level holding circuit.

9. A semiconductor memory device including an SRAM cell, a column selector, and a sense amplifier, wherein the SRAM cell comprises: a fifth transistor having a source connected to a first bit line; and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line; the first bit line is formed in a first back wiring layer on the back side of the fifth and sixth transistors and includes a first wiring extending in a first direction; the second bit line is formed in the first back wiring layer and includes a second wiring extending in the first direction; and the SRAM cell comprises: a first active region forming a channel, source, and drain of the fifth transistor and including a nanosheet extending in the first direction as the channel; a second active region forming a channel, source, and drain of the sixth transistor and including a nanosheet extending in the first direction as the channel; a first via formed at a position where a first region forming one node in the first active region and the first wiring overlap, connecting the first region and the first wiring; the column selector comprises: a ninth transistor having a source connected to the first bit line; a tenth transistor having a source connected to the second bit line; a seventh active region constituting the channel, source and drain of the ninth transistor, the channel including a nanosheet extending in the first direction; and a seventh via formed at a position where the seventh region constituting the source in the seventh active region and the first wiring overlap, the seventh region connecting the seventh region to the first wiring; an eighth region constituting the drain in the seventh active region is connected to a fifth wiring formed on a surface side of the eighth region; and the sense amplifier comprises: an eleventh transistor having a gate connected to the drain of the ninth transistor via the fifth wiring; and a twelfth transistor having a gate connected to the drain of the ninth transistor via the fifth wiring.A semiconductor memory device comprising:

10. A semiconductor memory device according to claim 9, wherein the column selector further comprises: an eighth active region constituting the channel, source and drain of the tenth transistor, the channel including a nanosheet extending in the first direction; and an eighth via formed at a position where a ninth region constituting the source in the eighth active region and the second wiring overlap, connecting the ninth region and the second wiring; the tenth region constituting the drain in the eighth active region is connected to a sixth wiring formed on the surface side of the tenth region; and the sense amplifier comprises: a thirteenth transistor having a gate connected to the drain of the tenth transistor via the sixth wiring; and a fourteenth transistor having a gate connected to the drain of the tenth transistor via the sixth wiring.

11. A semiconductor memory device according to claim 9, wherein the first wiring is formed linearly in the first direction from the SRAM cell to the column selector.

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