Control method for high-gain image sensor

Abstract

Provided in the present invention is a control method for a high-gain image sensor. A column bias current source and a column PMOS amplifier tube are provided in a column signal readout unit, wherein the column bias current source is connected to a current output connection line that is shared by a column, a drain electrode of the column PMOS amplifier tube is connected to a current input connection line that is shared by the column, a gate electrode of the column PMOS amplifier tube is directly connected or is connected, by means of a capacitor, to the current output connection line that is shared by the column, and an amplified signal of a floating diffusion region of a readout row of pixel units can be obtained on the current input connection line that is shared by the column, such that an ultrahigh conversion gain is achieved, and a dynamic range in a low-light scenario is expanded. The dimensions of device structures in the column signal readout unit can be much greater than the dimensions of transistors in pixels, such that better process consistency is achieved, and a conversion gain can be adjusted more flexibly. Switching between an SHCG mode and an STD mode is implemented by means of driving a switch module in the column signal readout unit, resulting in a smaller impact being made on a power supply and the ground during operation, thereby improving the stability of a circuit.

Description

Control method of high-gain image sensor

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 4, 2023, with application number 202310816052.5 and invention name “Control Method of High Gain Image Sensor”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The invention relates to a control method for a high-gain image sensor. Background Art

[0003] Standard image sensors have a limited dynamic range of approximately 60dB to 70dB. However, the dynamic range of real-world brightness is much greater. Natural scenes often span a range of 90dB and above. Image sensors require single-frame high dynamic range (HDR) capabilities in certain applications, such as capturing moving objects or capturing scenes with high frame rates.

[0004] In current CMOS image sensors, 3T or 4T pixel structures are commonly used (Figure 1 shows a traditional 4T pixel as an example). The main reason is that the amplifier tube M3 in the pixel is a source follower (SF) structure, which has a wide range of pixel output voltages and a high degree of freedom in reset voltage. Its conversion gain is approximately inversely proportional to the capacitance C of the FD node (the gate of the M3 tube). FD To achieve better noise performance under low illumination, another approach currently in the industry is to modify the amplifier tube in the pixel to operate in a common-source amplifier structure, known as a capacitor feedback transimpedance amplifier (CTIA) pixel structure (as shown in Figure 2). Its conversion gain is approximately inversely proportional to the capacitance C between the gate and drain of the M3 tube. GD Since C GD <<C FD CTIA pixels can achieve higher conversion gain than traditional 4T pixels. However, the main drawbacks of CTIA pixels are their narrow operating range, the need for a more precise reset voltage, poor PVT robustness, and the susceptibility of output voltage saturation due to charge injection.

[0005] To combine the advantages of the above two structures, patent US10277848B2 proposes a hybrid pixel structure that combines the two structures. By switching peripheral circuits, the pixel can switch between SF and CTIA modes. However, it requires an additional reference voltage and still cannot solve the problems existing in the CTIA pixel itself. Patent CN110537366A proposes a differential pixel structure that can improve the problems existing in the single-ended CTIA pixel to a certain extent. However, the operation process and timing of the differential structure are relatively complex, and the power consumption is also significantly increased, which will be limited in application. Patent CN107770461 proposes a dual-gain output pixel structure, combining amplifiers in the pixel and column circuit to achieve signal output in both SF and CTIA modes. However, this structure requires adding capacitors and transistors in the pixel and additional signal output lines, which increases the complexity of the pixel. The amplifier in the column circuit also increases the overall power consumption.

[0006] Summary of the Invention

[0007] The object of the present invention is to provide a control method for a high-gain image sensor, which can achieve higher conversion gain through simple structural improvement and lower power consumption cost based on a traditional pixel structure.

[0008] Based on the above considerations, the present invention provides a control method for a high-gain image sensor, wherein the image sensor includes multiple columns of pixel units arranged in an array, each column of pixel units having a column-common current input connection and a column-common current output connection, the gate of the source-follower transistor of each pixel unit in each column is connected to its respective floating diffusion region, the drain of the source-follower transistor is connected to the column-common current input connection, and the source of the source-follower transistor is connected to the column-common current output connection directly or through its respective row select transistor; the column-common current input connection and the column-common current output connection are connected to a column signal readout unit; the column signal readout unit includes a column bias current source and a column PMOS amplifier tube, the column bias current source is connected to the column-common current output connection, the drain of the column PMOS amplifier tube is connected to the column-common current input connection, and the gate of the column PMOS amplifier tube is connected to the column-common current output connection directly or through a capacitor, so that an amplified signal of the floating diffusion region of the pixel unit in the row can be obtained on the column-common current input connection.

[0009] Preferably, when the gate of the column PMOS amplifier tube is connected to the current output connection shared by the column through a first capacitor, a second capacitor is set between the gate and the drain of the column PMOS amplifier tube, and by changing the ratio of the first capacitor to the second capacitor, the amplification factor of the signal of the floating diffusion area of ​​the row pixel unit read out by the column signal readout unit on the current input connection shared by the column is changed.

[0010] Preferably, the column signal readout unit further includes a correlated power supply generation module, which latches the first bias voltage and outputs the column second power supply voltage to the source of the column PMOS amplifier tube, so that the power supply of the column signal readout unit has correlation when sampling the reference signal and sampling the image signal, thereby eliminating the influence of power supply noise on correlated double sampling.

[0011] Preferably, the related power generation module includes at least one source follower transistor, the drain of the source follower transistor of the related power generation module is connected to the first power supply voltage, the source is connected to the column second power supply voltage output terminal, and the gate samples and latches the first bias voltage before sampling the reference signal, thereby generating the column second power supply voltage required by the column signal readout unit that is correlated when sampling the reference signal and sampling the image signal.

[0012] Preferably, the gate of the source follower transistor of the relevant power generation module samples the first bias voltage through a seventh switch and holds it on a third capacitor, and performs sampling and holding on a row-by-row or frame-by-frame basis before sampling the reference signal.

[0013] Preferably, the column signal readout unit further includes a noise compensation module, which senses fluctuations in the first power supply voltage or the column second power supply voltage and generates a negative feedback signal to act on the column second power supply voltage to suppress fluctuations in the column second power supply voltage.

[0014] Preferably, the noise compensation module includes a current mirror unit, a bias terminal of the current mirror unit is connected to the first power supply voltage output terminal via a fourth capacitor, and a drain of the current mirror unit is connected to the column second power supply voltage output terminal.

[0015] Preferably, the bias end of the current mirror unit further samples the second bias voltage through an eighth switch and holds the second bias voltage on a fifth capacitor, so as to perform sampling and holding on a row-by-row or frame-by-frame basis.

[0016] Preferably, the current mirror unit is a cascode current mirror.

[0017] Preferably, the noise compensation module includes an amplifying transistor, the gate of which is connected to the second power supply voltage output terminal of the column through a sixth capacitor, the drain of which is connected to the current source, and is connected to the gate of the source follower transistor of the relevant power supply generating circuit through a seventh capacitor. A ninth switch is connected between the gate and the drain of the amplifying transistor, and the DC bias of the amplifying transistor can be achieved by closing the ninth switch row by row or frame by frame.

[0018] Preferably, the column signal readout unit further comprises a clamping module, and before sampling the reference signal and sampling the image signal, the voltage of the drain of the source follower transistor of the pixel unit is clamped to the same level by the clamping module respectively.

[0019] Preferably, the clamping module includes a clamping transistor, the source of the clamping transistor is connected to the column second power supply voltage, the gate and the drain are connected to each other, and the drain is connected to the drain of the source follower transistor of the pixel unit through a tenth switch.

[0020] Preferably, the size of the clamping transistor is a fixed size or an array-adjustable size.

[0021] Preferably, each of the column signal readout units corresponds to a related power generation module, or a plurality of the column signal readout units correspond to a related power generation module.

[0022] Preferably, each of the column signal readout units corresponds to a noise compensation module, or a plurality of the column signal readout units correspond to a noise compensation module.

[0023] Preferably, each of the column signal readout units corresponds to a clamping module, or a plurality of the column signal readout units correspond to a clamping module.

[0024] Preferably, the control method of the high-gain image sensor includes: sampling the first reference signal output from the source of the source follower transistor of the pixel unit to the column signal readout unit; sampling the second reference signal output from the drain of the source follower transistor of the pixel unit to the column signal readout unit; turning on the transfer transistor of the pixel unit and sampling the image signal output from the pixel unit to the column signal readout unit.

[0025] Preferably, the step of sampling the image signal output by the pixel unit to the column signal readout unit includes: making a judgment based on the voltage signal read out from the pixel unit; if the judgment result is a high illumination condition, sampling the first image signal output from the source of the source follower transistor of the pixel unit to the column signal readout unit, and the pixel unit has a first conversion gain; if the judgment result is a low illumination condition, sampling the second image signal output from the drain of the source follower transistor of the pixel unit to the column signal readout unit, and the pixel unit has a second conversion gain; the second conversion gain is higher than the first conversion gain.

[0026] Preferably, the step of judging based on the voltage signal read from the pixel unit includes: comparing the change amplitude of the voltage signal read from the pixel unit before and after the transfer transistor is turned on with the threshold voltage; if the change amplitude is less than or equal to the threshold voltage, it is a low illumination condition; if the change amplitude is greater than the threshold voltage, it is a high illumination condition.

[0027] Preferably, the falling interval of the ramp voltage obtained by analog-to-digital conversion is used as the threshold voltage.

[0028] Preferably, the step of sampling the image signal output by the pixel unit to the column signal readout unit includes: sampling the second image signal output by the drain of the source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a second conversion gain; sampling the first image signal output by the source of the source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a first conversion gain; the second conversion gain is higher than the first conversion gain.

[0029] Preferably, when the source of the source follower transistor of the pixel unit is output to the column signal readout unit, the first conversion gain is adjusted by the dual conversion gain control transistor of the pixel unit.

[0030] Preferably, the step of adjusting the first conversion gain through the dual conversion gain control transistor of the pixel unit includes: turning on the dual conversion gain control transistor to obtain a relatively low first conversion gain, or turning off the dual conversion gain control transistor to obtain a relatively high first conversion gain.

[0031] Preferably, the source or drain of the source follower transistor of the pixel unit is controlled by a switch module to output to the column signal readout unit.

[0032] Compared with the prior art, the internal structure of the pixel unit of the high-gain image sensor of the present invention is consistent with that of traditional 3T or 4T pixels, with good process compatibility. By simply improving the circuit structure and connection method of the column signal readout unit, super high conversion gain (SHCG) can be achieved, expanding the dynamic range in low-light scenes without introducing additional reference voltages or the power consumption caused by additional amplification circuits. The device structure size in the column signal readout unit can be much larger than the transistor in the pixel, improving process consistency and allowing more flexible adjustment of the conversion gain. Switching between SHCG mode and STD mode (standard mode, i.e., traditional source follower mode) can be achieved by driving the switch module in the column signal readout unit without driving the signal in the pixel array. This reduces the impact on the power supply and ground during operation and improves circuit stability.

[0033] Preferably, the first bias voltage is latched by a correlated power generation module and the column second power supply voltage is output to the source of the column PMOS amplifier tube, so that the power supply of the column signal readout unit is correlated when sampling the reference signal and sampling the image signal, thereby eliminating the influence of power supply noise on correlated double sampling and improving imaging quality; the noise compensation module senses the fluctuation of the first power supply voltage or the column second power supply voltage and generates a negative feedback signal to act on the column second power supply voltage to suppress the fluctuation of the column second power supply voltage and further reduce power supply noise; before sampling the reference signal and sampling the image signal, the voltage of the drain of the source follower transistor of the pixel unit is clamped to the same level by a clamping module, respectively, to accelerate the signal stabilization speed, improve the consistency of establishing the reference signal and the image signal, and improve image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments when read with reference to the accompanying drawings.

[0035] FIG1 is a circuit diagram of a 4T pixel structure image sensor in the prior art;

[0036] FIG2 is a circuit diagram of a CTIA pixel structure image sensor in the prior art;

[0037] FIG3 is a schematic diagram of a high-gain image sensor system according to the present invention;

[0038] FIG4 is a circuit diagram of a 4T pixel unit in a high-gain image sensor according to the present invention;

[0039] FIG5 is a circuit diagram of a high-gain image sensor according to a first embodiment of the present invention;

[0040] FIG6 is an equivalent circuit diagram of the high-gain image sensor of FIG5 in the STD mode;

[0041] FIG7 is a signal timing diagram of the high-gain image sensor of FIG5 in the STD mode;

[0042] FIG8 is an equivalent circuit diagram of the high-gain image sensor of FIG5 in SHCG mode;

[0043] FIG9 is a signal timing diagram of the high-gain image sensor of FIG5 in the SHCG mode;

[0044] FIG10 is a conversion gain curve diagram of the high-gain image sensor in two modes of FIG5 ;

[0045] FIG11 is a circuit diagram of a high-gain image sensor according to a second embodiment of the present invention;

[0046] FIG12 is a circuit diagram of a high-gain image sensor according to a third embodiment of the present invention;

[0047] FIG13 is a schematic flow chart of a method for controlling the high-gain image sensor of FIG12 ;

[0048] FIG14 is a signal timing diagram of the control method of FIG13 under high illumination conditions;

[0049] FIG15 is a signal timing diagram of the control method of FIG13 under low illumination conditions;

[0050] FIG16 is another schematic flow chart of the control method of the high-gain image sensor of FIG12;

[0051] FIG17 is a signal timing diagram of the control method of FIG16;

[0052] FIG18 is a circuit diagram of a high-gain image sensor according to a fourth embodiment of the present invention;

[0053] FIG19 is a circuit diagram of a related power generation module and a noise compensation module in the high-gain image sensor of FIG18 ;

[0054] FIG20 is another circuit diagram of the relevant power generation module and noise compensation module in the high-gain image sensor of FIG18;

[0055] FIG21 is a signal timing diagram of the power generation module and the noise compensation module related to FIG20;

[0056] FIG22 is a circuit diagram of a clamping module in the high-gain image sensor of FIG18 ;

[0057] FIG23 is a signal timing diagram of the high-gain image sensor of FIG22 in the SHCG mode.

[0058] In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout different drawings. DETAILED DESCRIPTION

[0059] To address the above-mentioned problems in the prior art, the present invention provides a control method for a high-gain image sensor. A column bias current source and a column PMOS amplifier are provided in a column signal readout unit. The column bias current source is connected to a column-shared current output line, the drain of the column PMOS amplifier is connected to a column-shared current input line, and the gate of the column PMOS amplifier is connected to the column-shared current output line directly or through a capacitor. Thus, an amplified signal from a floating diffusion region of a row pixel unit can be obtained on the column-shared current input line.

[0060] In the following detailed description of preferred embodiments, reference will be made to the accompanying drawings, which form a part of the present invention. The accompanying drawings illustrate, by way of example, specific embodiments that can implement the present invention. The illustrative embodiments are not intended to be exhaustive of all embodiments according to the present invention. It will be understood that other embodiments may be utilized, and structural or logical modifications may be made, without departing from the scope of the present invention. Therefore, the following detailed description is not restrictive, and the scope of the present invention is defined by the appended claims.

[0061] The following describes it in detail with reference to specific embodiments.

[0062] As shown in FIG3, FIG4, and FIG5, the high-gain image sensor according to the first embodiment of the present invention includes a plurality of columns of pixel units 101 arranged in an array and a plurality of column signal readout units 201. Each column signal readout unit 201 corresponds to one or more columns of pixel units 101 in the pixel array 100 and is configured to read an output voltage signal from the corresponding column of pixel units 101 (FIG. 5 shows a pixel unit P in the Mth column of pixel units). <n>and the specific circuit of the corresponding column signal readout unit M are taken as examples).

[0063] Specifically, each pixel unit 101 includes a photodiode PD and multiple pixel transistors, namely, a transfer transistor M1, a reset transistor M2, a source follower transistor M3, and a row select transistor M4. The photodiode PD is used to perform photoelectric conversion on incident light to obtain corresponding charges. The transfer transistor M1 is used to transfer the charge accumulated in the photodiode PD to the floating diffusion area FD. The reset transistor M2 is used to reset the potential of the floating diffusion area FD. The source follower transistor M3 is used to convert the charge in the floating diffusion area FD into a corresponding voltage signal. The row select transistor M4 is used to output the voltage signal to the corresponding column signal readout unit 201.

[0064] Each column of pixel cells 101 has a column-common current input connection 112 and a column-common current output connection 111. The gate of the source-follower transistor M3 of each pixel cell 101 in each column is connected to its respective floating diffusion region FD, the drain of the source-follower transistor M3 is connected to the column-common current input connection 112, and the source of the source-follower transistor M3 is connected to the column-common current output connection 111 via its respective row select transistor M4. It should be noted that in the 4T pixel structure shown in Figures 4 and 5, the row select transistor M4 is connected between the source of the source-follower transistor M3 and the column-common current output connection 111. In other 4T pixel structures not shown, the row select transistor M4 may also be connected between the drain of the source-follower transistor M3 and the column-common current input connection 112. In the 3T pixel structure, the row select transistor M4 may also be omitted, and the source of the source-follower transistor M3 is directly connected to the column-common current output connection 111.

[0065] The column-common current input line 112 and the column-common current output line 111 are connected to corresponding column signal readout units 201. The column signal readout unit 201 includes a column bias current source CS and a column PMOS amplifier M5. A single column PMOS amplifier M5 is shown as an example. Those skilled in the art will appreciate that, in other embodiments not shown, multiple column PMOS amplifiers M5 may be provided. The column bias current source CS is connected to the column-common current output line 111. The drain of the column PMOS amplifier M5 is connected to the column-common current input line 112, and the gate of the column PMOS amplifier M5 is connected to the column-common current output line 111. An amplified signal from the floating diffusion region of a row of pixel cells is obtained on the column-common current input line 112. Furthermore, the source of the column PMOS transistor M5 is connected to a first power supply voltage VDD1 to provide a power supply voltage for the column PMOS transistor M5. By adopting the column PMOS amplifier tube M5 to amplify the signal of the floating diffusion area of ​​the readout row pixel unit, the method has the advantages of simple structure, low noise, large voltage margin, etc.

[0066] Preferably, when the gate of the column PMOS amplifier M5 is connected to the column-common current output connection 111 via the first capacitor C1, a second capacitor C2 is provided between the gate and drain of the column PMOS amplifier M5. Specifically, the column-common current output connection 111 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2 and the gate of the column PMOS amplifier M5, and the second end of the second capacitor C2 and the drain of the column PMOS amplifier M5 are connected to the column-common current input connection 112. The second capacitor C2 can be a parasitic capacitor of the column PMOS amplifier M5, or, like the first capacitor C1, an independent capacitor device. The first capacitor C1 and the second capacitor C2 can be fixed capacitors or a variable capacitor array. By changing the ratio of the first capacitor C1 to the second capacitor C2, the amplification factor of the floating diffusion region signal of the row pixel unit readout by the column signal readout unit 201 on the column-common current input connection 112 can be changed, thereby flexibly adjusting the conversion gain of the pixel unit. Preferably, the column signal readout unit 201 further includes a first switch S4 connected in parallel with the second capacitor C2, for performing a self-clearing operation on the column PMOS amplifier tube M5.

[0067] Based on the above structure, the column signal readout unit 201 can read the voltage signal VHG from the drain of the source-follower transistor M3. The transconductance Gm of the first capacitor C1, the second capacitor C2, and the column PMOS amplifier M5, as well as the load, provide a gain from the floating diffusion FD to the output node VHG, thereby achieving a higher conversion gain than the standard mode (STD mode, i.e., the traditional source-follower mode). This is referred to as the Super High Conversion Gain (SHCG) mode. Because the first capacitor C1, the second capacitor C2, and the column PMOS amplifier M5 are all located in the peripheral circuitry and can be much larger than the in-pixel transistor M3, the process consistency is better than that of the traditional CTIA pixel structure, and the conversion gain can be adjusted more flexibly.

[0068] Further preferably, the switch module can be used to control the source or drain of the source follower transistor M3 of the pixel unit 101 to output to the column signal reading unit 201, thereby achieving switching between the SHCG mode and the STD mode. Specifically, the column signal reading unit 201 further includes a first switch S1, a second switch S2, and a third switch S3. The column-shared current output connection 111 is connected to the first end of the first capacitor C1 via the first switch S1, and the second end of the second capacitor C2 and the drain of the column PMOS amplifier M5 are connected to the column-shared current input connection 112 via the second switch S2. The column-shared current input connection 112 is connected to the first power supply voltage VDD1 via the third switch S3.

[0069] Therefore, when the third switch S3 is closed, the first switch S1 and the second switch S2 are opened, the equivalent circuit of the image sensor working in the STD mode is shown in FIG6 , and the signal timing is shown in FIG7 . In this mode, the post-stage readout circuit 207 reads the first voltage signal VSF from the source of the source follower transistor M3, which is equivalent to the traditional source follower mode.

[0070] When the third switch S3 is opened, the first switch S1 and the second switch S2 are closed, the equivalent circuit of the image sensor working in the SHCG mode is shown in FIG8 , and the signal timing is shown in FIG9

[0071] The conversion gain curves in the two modes are shown in Figure 10.

[0072] As shown in FIG11 , in another preferred embodiment of the image sensor of the present invention, the first capacitor C1, the second capacitor C2, and the fourth switch S4 can also be omitted. In other words, the gate of the column PMOS amplifier M5 is directly connected to the column-shared current output line 111. It should be noted that when this capacitor-omitted structure is adopted, the drain of the reset transistor M2 in the pixel unit 101 must be connected to the drain of the source-follower transistor M3 (different from the drain of the reset transistor M2 connected to the third power supply voltage VDD3 in the first embodiment) to achieve self-clearing through the pixel unit.

[0073] Further preferably, the column signal readout unit 201 further includes a fifth switch S5 and a sixth switch S6, the column-common current output connection 111 is connected to the gate of the column PMOS amplifier tube M5 through the fifth switch S5, and the gate of the column PMOS amplifier tube M5 is also connected to the ground voltage through the sixth switch S6.

[0074] Therefore, when the sixth switch S6 is closed and the fifth switch S5 is opened, the column PMOS amplifier tube M5 is turned on as a switch, the image sensor operates in the STD mode, and the post-stage readout circuit 207 reads the first voltage signal VSF from the source of the source follower transistor M3, which is equivalent to the traditional source follower mode. At this time, the first conversion gain CG1 is relatively low.

[0075] When the sixth switch S6 is opened and the fifth switch S5 is closed, the column PMOS amplifier tube M5 serves as an amplification unit, the image sensor operates in the SHCG mode, and the post-stage readout circuit 207 reads the second voltage signal VHG from the drain of the source follower transistor M3. At this time, the second conversion gain CG2 is relatively high.

[0076] In addition, existing variable conversion gain image sensors often use a dual conversion gain (DCG) design. This design introduces an external capacitor and adds a control switch, such as a metal oxide semiconductor field effect transistor (MOSFET). When a higher signal strength needs to be read, the switch is turned on, connecting the FD to the capacitor to help extract charge. At this time, the conversion gain is low (LCG mode); when a lower signal strength needs to be read, the switch is turned off to obtain a higher conversion gain (HCG mode), thereby improving the readout signal-to-noise ratio. This solution performs well in existing pixel designs and can effectively expand the dynamic range without changing the PD design.

[0077] The readout operation of an existing row-controlled dual-conversion-gain (row-DCG) image sensor includes four stages: sampling the LCG reference signal, sampling the HCG reference signal, sampling the HCG image signal, and sampling the LCG image signal (i.e., LCG ref, HCG ref, HCG sig, and LCG sig). This requires quantizing and storing the image signals output by the pixel units under the two conversion gains, respectively, which is not conducive to high-speed operation. During the readout operation of an existing column-controlled dual-conversion-gain (col-DCG) image sensor, the readout circuit of each column adjusts the conversion gain of the pixel unit according to the bit line voltage. However, since the control signal of each column of pixel units is shared, the column control circuit is overloaded, resulting in a problem of excessive power supply impact when the control signal is flipped.

[0078] The high-gain image sensor of the present invention can be multiplexed with the traditional DCG scheme. For example, in extremely dark scenes, the drain output of the source follower transistor M3 is used (SHCG mode, second conversion gain CG2), and in darker or brighter scenes, the source output of the source follower transistor M3 is used (STD mode, first conversion gain CG1). In the STD mode, the row control circuit further adjusts the first conversion gain CG1 by turning on or off the DCG transistor according to the application scenario. Specifically, by turning on the DCG transistor to obtain a relatively low first conversion gain (Low-CG1), or turning off the DCG transistor to obtain a relatively high first conversion gain (High-CG1), a relatively high HCG or a relatively low LCG readout mode is selected to further expand the dynamic range.

[0079] Based on the circuit structure of Figure 12, the following describes in detail how to use the control method of the high-gain image sensor of the present invention to achieve a high dynamic range by adjusting the conversion gain of the pixel unit while reducing the impact of the switching operation, improving circuit stability, and improving reading efficiency.

[0080] The floating diffusion region FD is connected to a DCG control transistor M0. The equivalent capacitance at the FD point is different when the DCG control transistor M0 is on and off. When M0 is on, the FD capacitance increases, allowing more electrons to be collected from the PD tube, thereby expanding the dynamic range. The connection methods for the other transistors are all conventional and will not be described in detail. The third switch S3 is controlled by the signal SHCG_ENB, while the first and second switches S1 and S2 are controlled by the signal SHCG_EN. A high level indicates that the switch is closed, and a low level indicates that the switch is open. The signals SHCG_EN and SHCG_ENB are inverse digital control signals, which are automatically output by the subsequent readout circuit 207 based on the input signal level.

[0081] As shown in FIG13 , a process of a conversion gain control method of a high-gain image sensor according to the present invention includes:

[0082] Step S11: sampling a first reference signal output from the source of the source follower transistor of the pixel unit to the column signal reading unit;

[0083] Step S12: sampling a second reference signal outputted from the drain of the source follower transistor of the pixel unit to the column signal reading unit;

[0084] Step S13: turning on the transfer transistor of the pixel unit;

[0085] Step S14: determining the light intensity of the pixel unit according to the voltage signal read from the pixel unit;

[0086] Step S15: Based on the judgment result, sample the image signal output by the pixel unit to the column signal reading unit (step S151: under high illumination conditions, the source of the source follower transistor of the sampling pixel unit is output to the first image signal of the column signal reading unit; or step S152: under low illumination conditions, the drain of the source follower transistor of the sampling pixel unit is output to the second image signal of the column signal reading unit).

[0087] Specifically, FIG14 is a timing diagram of the embodiment shown in FIG13 under high illumination conditions, which includes four stages:

[0088] (1) STD_ref stage

[0089] The SHCG_EN signal is at a low level, the third switch S3 is closed, and the first switch S1 and the second switch S2 are opened. At this time, the column PMOS amplifier tube M5 is not connected to the pixel circuit, and the VHG voltage is connected to the first power supply voltage VDD1 through the third switch S3. The column signal reading unit 201 is in STD mode. In this mode, the output node of the pixel unit 101 is the source of the source follower transistor M3, and the voltage VSF is the valid signal input to the subsequent readout circuit 207. In the pixel unit 101, SEL becomes high to select this row, and the DCG and RST signals are high at the same time, resetting the FD point in the pixel unit 101. After that, the RST signal becomes low, and DCG has two states, remaining high or becoming low, which respectively represent that the STD mode can support the LCG mode or the HCG mode, and more flexibly select the dynamic range; the post-stage readout circuit 207 quantizes the VSF voltage to read the STD_ref reset information, that is, completes the step of sampling the source of the source follower transistor M3 of the pixel unit 101 to output the first reference signal STD_ref to the column signal reading unit 201.

[0090] (2) SHCG_ref stage

[0091] When the SHCG_EN signal goes high, the third switch S3 opens, and the first and second switches S1 and S2 close. At this point, the column PMOS amplifier M5 is connected to the pixel circuit, forming a closed loop. The VSF voltage is disconnected from the post-stage readout circuit 207, and the column signal readout unit 201 is in SHCG mode. In this mode, the output node of the pixel cell 101 is the drain of the source-follower transistor M3, and the voltage VHG is the effective signal input to the post-stage readout circuit 207. Because the column PMOS amplifier M5 has a negative gain of -AV, the Miller effect causes most of the electrons flowing out of the PD transistor in the pixel cell 101 to flow to the capacitor CGD, thereby achieving a higher conversion gain than in the STD mode. The post-stage readout circuit 207 quantizes the VHG voltage and reads the SHCG_ref reset information, completing the step of sampling the second reference signal SHCG_ref output from the drain of the source-follower transistor M3 of the pixel cell 101 to the column signal readout unit 201.

[0092] (3) Flag judgment stage

[0093] The circuit is still in the SHCG mode, the TX signal in the pixel unit 101 becomes high level, the electrons in the PD tube flow out through the turned-on transfer transistor M1, and the VHG signal generates a corresponding voltage according to the number of electrons.

[0094] Next, a judgment is made based on the voltage signal read from the pixel unit. A reference threshold voltage Vflag is required to determine the intensity of light. This Vflag voltage can be designed to have an adjustable amplitude to achieve the best image effect. In this embodiment, the falling interval of the ramp voltage (Vramp) of the analog-to-digital conversion is used as the threshold voltage Vflag. In other embodiments not shown, a new threshold voltage can also be introduced. The change amplitude of the voltage signal VHG read from the pixel unit 101 before and after the transfer transistor M1 is turned on is compared with the threshold voltage Vflag. If the change amplitude of VHG is less than or equal to the threshold voltage Vflag, it is a low illumination condition. If the change amplitude of VHG is greater than the threshold voltage Vflag, it is a high illumination condition.

[0095] Taking the judgment result of high illumination condition as an example, a relatively low conversion gain can be selected, and then the STD_sig stage is entered.

[0096] (4) STD_sig stage

[0097] The SHCG_EN signal becomes low, the circuit switches to STD mode, the VHG signal is connected to VDD1, and the post-stage readout circuit 207 quantizes the VSF signal readout and the image information related to the light intensity, that is, the source of the source follower transistor M4 of the sampled pixel unit is output to the first image signal STD_sig of the column signal reading unit 201. According to the first image signal STD_sig and the first reference signal STD_ref, the pixel unit 101 has a first conversion gain CG1.

[0098] FIG15 is a timing diagram of the embodiment shown in FIG13 under low illumination conditions, which also includes four stages, wherein the first two stages are the same as FIG14 , and the difference lies in the last two stages:

[0099] (3) Flag judgment stage

[0100] The circuit is still in the SHCG mode, the TX signal in the pixel unit 101 becomes high level, the electrons in the PD tube flow out through the turned-on transfer transistor M1, and the VHG signal generates a corresponding voltage according to the number of electrons.

[0101] Next, a judgment is made based on the voltage signal read from the pixel unit. The falling range of the ramp voltage (Vramp) obtained by analog-to-digital conversion is used as the threshold voltage Vflag. The change in the voltage signal VHG read from the pixel unit 101 before and after the transfer transistor M1 is turned on is compared with the threshold voltage Vflag. If the change in VHG is less than or equal to the threshold voltage Vflag, the judgment result is that the illumination condition is low and a higher conversion gain is required to obtain good image quality, so the SHCG_sig stage is entered.

[0102] (4) SHCG_sig stage

[0103] The SHCG_EN signal remains at a high level, and the circuit is still in the SHCG mode. The post-stage readout circuit 207 quantizes the VHG signal to read out image information related to light intensity, that is, it samples the drain of the source follower transistor M3 of the pixel unit and outputs the second image signal SHCG_sig to the column signal reading unit 201. According to the second image signal SHCG_sig and the second reference signal SHCG_ref, the pixel unit 101 has a second conversion gain CG2, and the second conversion gain CG2 is greater than the first conversion gain CG1.

[0104] As shown in Figures 13-15, in the above embodiments, the first reference signal STD_ref outputted from the source of the source-follower transistor of the pixel cell to the column signal reading unit and the second reference signal SHCG_ref outputted from the drain of the source-follower transistor to the column signal reading unit are sampled. Then, based on the voltage signal read from the pixel cell, the light intensity of the pixel cell is determined. The appropriate readout architecture is then automatically selected to sample either the second image signal SHCG_sig outputted from the drain of the source-follower transistor or the first image signal STD_sig outputted from the source. This adaptively adjusts the conversion gain of the image sensor to achieve a high dynamic range. In particular, the SHCG readout mode outputted from the drain of the source-follower transistor can extend the dynamic range in low-light scenes. Furthermore, adjusting the conversion gain of the pixel cell does not require driving signals in the pixel array; only the switching module within the column signal reading unit needs to be driven. This reduces the impact on the power supply and ground during switching operations, thereby improving circuit stability. Furthermore, during each pixel cell readout cycle, only the reference signal ref needs to be read twice and the image signal sig needs to be read once, which improves readout efficiency and enables the generation of HDR images at a higher frame rate.

[0105] In addition, the SHCG_EN signal of the high-gain image sensor of the present invention can also be switched to global control of the column circuit, and then read out in conjunction with the row control signal, which can support the readout timing as shown in Figure 17, and sequentially perform the four processes of STD ref, SHCG ref, SHCG sig, and STD sig to generate an HDR image. As shown in Figure 15, another process of the conversion gain control method of the high-gain image sensor of the present invention includes:

[0106] Step S21: sampling the first reference signal outputted from the source of the source follower transistor of the pixel unit to the column signal reading unit (STD_ref stage);

[0107] Step S22: sampling the second reference signal outputted from the drain of the source follower transistor of the pixel unit to the column signal reading unit (SHCG_ref stage);

[0108] Step S23: turning on the transfer transistor of the pixel unit;

[0109] Step S24: sampling the second image signal output from the drain of the source follower transistor of the pixel unit to the column signal reading unit, wherein the pixel unit has a second conversion gain (SHCG_sig stage);

[0110] Step S25: sampling the first image signal output from the source of the source follower transistor of the pixel unit to the column signal reading unit, wherein the pixel unit has a first conversion gain, and the second conversion gain is higher than the first conversion gain (STD_sig stage).

[0111] The circuit principle and switching process of each stage are similar to those of the above embodiment and will not be described in detail here.

[0112] It should be noted that the specific circuits and signal timings of the various embodiments of the present invention are merely examples, and technicians can make other modifications or have other implementation methods based on the common knowledge in the field. For example, by controlling the source or drain of the source follower transistor of the pixel unit to be output to the column signal reading unit through other forms of switching modules, as long as the first reference signal output from the source of the source follower transistor of the pixel unit to the column signal reading unit and the second reference signal output from the drain of the source follower transistor to the column signal reading unit are sampled respectively, and then the image signal output from the pixel unit to the column signal reading unit is sampled as needed, so as to achieve a high dynamic range by adjusting the conversion gain of the pixel unit, which can be used to achieve the purpose of the present invention and should be included in the scope of protection of the present invention.

[0113] Furthermore, the introduction of the column PMOS amplifier M5 in the column signal readout unit increases reliance on a low-noise analog power supply. In practical image sensors, most employ a column readout circuit structure and share the analog power supply VDD1. However, during the quantization process, image signals from each column vary in magnitude, flip points, and dynamic current, leading to varying durations and amplitudes of power supply surges. The resulting fluctuations in power supply surges can in turn affect column signal quantization. Furthermore, power supply input noise can couple into the readout circuit, affecting the correlated double sampling quantization results and causing various image anomalies such as horizontal streaks and smearing.

[0114] Furthermore, because the output impedance of VHG in SHCG mode is greater than that of VSF in STD mode, the VHG signal setup time is relatively slow. Excessive setup time can affect the image sensor's readout frame rate and image quality. Before reading the ref signal, S4 switches, causing channel charge injection and clock feedthrough to cause the gate voltage of column PMOS amplifier M5 to fluctuate, leading to fluctuations in the VHG voltage on the column-shared current input connection 112. Furthermore, before reading the sig signal, the switching action of the transfer transistor M1 within the pixel also causes fluctuations in the voltage at the pixel's FD point, which in turn causes fluctuations in the VHG voltage.

[0115] To further address the above-mentioned problem, the inventors of the present application have discovered through research that, in accordance with another preferred embodiment shown in FIG. 18 , a correlated power supply generation module 205 can be added to the column signal readout unit 201. The correlated power supply generation module 205 latches the first bias voltage Vbias and outputs the column second power supply voltage VDD2 to the column PMOS amplifier M5. This allows the power supply of the column PMOS amplifier M5 to be correlated when sampling the reference signal and the image signal, thereby eliminating the influence of power supply noise on correlated double sampling and improving imaging quality.

[0116] Preferably, a noise compensation module 206 may be further added to the column signal readout unit 201. The noise compensation module 206 senses fluctuations in the first power supply voltage VDD1 or the column second power supply voltage VDD2 and generates a negative feedback signal to act on the column second power supply voltage VDD2, thereby suppressing fluctuations in the column second power supply voltage VDD2 and further reducing power supply noise.

[0117] Preferably, a clamping module 203 may be added to the column signal readout unit 201. Before sampling the reference signal and sampling the image signal, the voltage of the drain of the source follower transistor M3 of the pixel unit is clamped to the same level by the clamping module 203, thereby accelerating the signal stabilization speed, improving the consistency of the reference signal and the image signal, and improving the image quality.

[0118] Specifically, FIG19 is a circuit diagram of the relevant power generation module 205 and the noise compensation module 206 in the high-gain image sensor of FIG18.

[0119] The relevant power generation module 205 includes a source-follower transistor M7. The drain of the source-follower transistor M7 is connected to the first power supply voltage VDD1, the source is connected to the column second power supply voltage output terminal VDD2, and the gate samples and latches the first bias voltage Vbias before sampling the reference signal, thereby generating the column second power supply voltage VDD2 required by the column signal readout unit and having correlation when sampling the reference signal and the image signal. In other embodiments not shown, those skilled in the art may also choose to use a combination of multiple source-follower transistors as a source follower as needed to implement the functions of the relevant power generation module 205. The relevant power generation circuit 205 is implemented using source-follower transistors, which has a simple circuit structure, consumes little area, and has an easily programmable and controllable output voltage.

[0120] Preferably, the gate of the source follower transistor M7 of the related power generation module 205 samples the first bias voltage Vbias through the seventh switch S7 and holds it on the third capacitor C3, performing row-by-row or frame-by-frame sampling and holding before sampling the reference signal.

[0121] The noise compensation module 206 includes a current mirror unit 208 with feedback. The bias terminal of the current mirror unit 208 is connected to the output terminal of the first power supply voltage VDD1 via a fourth capacitor C4, and the drain of the current mirror unit 208 is connected to the output terminal of the column second power supply voltage VDD2. The operating principle is that the bias terminal of the current mirror unit 208 receives fluctuations in the first power supply voltage VDD1 to change the current flowing out of the column second power supply voltage VDD2, thereby affecting the voltage fluctuation of the column second power supply voltage VDD2, thereby forming negative feedback compensation.

[0122] Preferably, the current mirror unit 208 in this embodiment is a cascode current mirror, comprising NMOS transistors M8 and M9. Common-gate transistor M9 increases the output resistance of the current mirror unit and reduces the impact of drain voltage variations on the current of the current mirror unit. The gate Vnbin of amplifier transistor M8 is connected to the second bias voltage Nbias via an eighth switch S8. S8 is activated once per row or frame to sample the second bias voltage Nbias and store it on a fifth capacitor C5. Vnbin is also coupled to the first power supply voltage VDD1 via a fourth capacitor C4. When there is an upward disturbance on the input first power supply voltage VDD1, there will also be an upward disturbance on the second column power supply voltage VDD2. However, through the processing of the related power generation module 205, the amplitude of the disturbance on the second column power supply voltage VDD2 will be greatly attenuated. The Vnbin voltage will rise accordingly due to coupling with the first power supply voltage VDD1 by the fourth capacitor C4. The current of the amplifier tube M8 controlled by Vnbin will increase accordingly, and the current flowing out of the node VDD2 will increase, causing the voltage of VDD2 to drop accordingly. This forms a negative feedback compensation, further suppressing slight disturbances on VDD2. The reverse is also true.

[0123] FIG. 20 is another circuit diagram of the related power generation module 205 and the noise compensation module 206 in the high-gain image sensor of FIG. 18 .

[0124] In this embodiment, the structure of the relevant power generation module 205 is the same as that of FIG19 . The difference is that the noise compensation circuit 206 includes an amplifier transistor M10, capacitors C6 and C7, a switch S9, and a current source CS2. Its operating timing is shown in FIG21 . The gate of the amplifier transistor M10 is connected to the output terminal of the column second power supply voltage VDD2 via a sixth capacitor C6, the drain is connected to the current source CS2, and is connected to the gate of the source-follower transistor M7 of the relevant power generation circuit via a seventh capacitor C7. A ninth switch S9 is connected between the gate and drain of the amplifier transistor M10. The ninth switch S9 can be closed row by row or frame by frame to provide a DC bias for the amplifier transistor M10.

[0125] As shown in FIG21 , the gate voltage of the source-follower transistor M7 in the relevant power generation module 205 is sampled when the seventh switch S7 is turned on. The ninth switch S9 in the noise compensation circuit 206 samples the first bias voltage Vbias during the time period t1′ to t2′. Simultaneously, the amplifier transistor M10 performs a reset operation. The sixth capacitor C6 and the seventh capacitor C7 have a voltage DC blocking function, which allows the gate of the amplifier transistor M10 to be at an appropriate voltage bias. After time t2′, the seventh switch S7 is turned off, and the gate voltage of the M7 transistor is sampled. Then, after time t3′, the ninth switch S9 is turned off, and the closed-loop negative feedback circuit formed by the M7 and M10 transistors operates. Under the action of the voltage negative feedback, the output impedance of the second column power supply voltage node VDD2 is significantly reduced, further reducing the impact of power supply noise on the second column power supply voltage node VDD2.

[0126] Figure 22 is a schematic circuit diagram of a clamping module in the high-gain image sensor of Figure 18. In this embodiment, the clamping module 203 includes a clamping transistor M6 and a tenth switch S10. The source of the clamping transistor M6 is connected to the column second power supply voltage VDD2; the gate and drain are connected together, and the drain is connected to the column-common current input connection 112 (VHG) for the drain of the source-follower transistor of the pixel unit through the tenth switch S10. The clamping transistor M6 can be of a fixed size or a variable array with adjustable array size.

[0127] Fig. 23 is a signal timing diagram of the high-gain image sensor in the SHCG mode of Fig. 22. First, it is explained that in the timing diagram of Fig. 23, the first switch S1 is always on, and the third switch S3 is always off.

[0128] During the time period t1 to t2, the reset transistor M2 in the pixel unit 101 is turned on to reset the FD to the first power supply voltage VDD1, and the fourth switch S4 of the column amplifier PMOS transistor M5 is turned on to reset the column amplifier PMOS transistor M5;

[0129] During the time period from t2 to t3, the column amplifier PMOS transistor M5 is reset, and the fourth switch S4 is disconnected after t3;

[0130] During the time period t3 to t4, switch S10 is turned on and switch S2 is turned off. Clamping module 203 clamps the voltage VHG at the drain of the source-follower transistor of the pixel unit to a predetermined fixed voltage. After t4, clamping is completed, switch S10 is turned off, switch S2 is turned on, and the column-common current input line 112 (VHG) establishes the reset signal ref for the SHCG mode.

[0131] During the time period from t4 to t7, the ref signal of the SHCG mode is sampled and quantized;

[0132] During the time period t8 to t10, the transfer transistor M1 in the pixel unit 101 is turned on and then turned off. Similarly, at this time, the clamping module 203 clamps VHG to the same preset fixed voltage.

[0133] During the time period t11 to t12, the SIG signal of the SHCG mode is quantified.

[0134] Therefore, before sampling the reference signal and sampling the image signal, the voltage of the source follower transistor drain of the pixel unit is clamped to the same level by the clamping module respectively, which can speed up the signal stabilization speed, improve the consistency of the reference signal and the image signal, and improve the image quality.

[0135] It should be noted that in the above embodiments, each column signal readout unit corresponds to a related power supply generation module, each column signal readout unit corresponds to a noise compensation module, and each column signal readout unit corresponds to a clamping module. In other embodiments not shown, those skilled in the art can select an appropriate number of column signal readout units to correspond to a related power supply generation module, a plurality of column signal readout units to correspond to a noise compensation module, and a plurality of column signal readout units to correspond to a clamping module as needed.

[0136] In summary, the internal structure of the pixel unit of the high-gain image sensor of the present invention is consistent with that of traditional 3T or 4T pixels, and has good process compatibility. By simply improving the circuit structure and connection method of the column signal readout unit, ultra-high conversion gain can be achieved, expanding the dynamic range in low-light scenes without introducing additional reference voltages or the power consumption caused by additional amplification circuits. The device structure size in the column signal readout unit can be much larger than the transistor in the pixel, which improves process consistency and allows for more flexible adjustment of the conversion gain. Switching between SHCG mode and STD mode can be achieved by driving the switch module in the column signal readout unit without driving the signal in the pixel array, which reduces the impact on the power supply and ground during operation and improves circuit stability.

[0137] Preferably, a related power generation module latches the first bias voltage and outputs the column second power supply voltage to the source of the column PMOS amplifier tube, so that the power supply of the column signal readout unit is correlated when sampling the reference signal and the image signal, thereby eliminating the impact of power supply noise on correlated double sampling and improving imaging quality. A noise compensation module senses fluctuations in the first power supply voltage or the column second power supply voltage and generates a negative feedback signal to act on the column second power supply voltage to suppress fluctuations in the column second power supply voltage, further reducing power supply noise. Before sampling the reference signal and the image signal, the voltage of the source follower transistor drain of the pixel unit is clamped to the same level by a clamping module, respectively, to accelerate signal stabilization, improve the consistency of the reference signal and the image signal, and improve image quality.

[0138] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and non-restrictive in all respects. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude plural references. Multiple elements recited in a device claim may also be implemented by a single element. Terms such as first and second are used to indicate names and do not imply any particular order.< / n>

Claims

1. A control method for a high-gain image sensor, characterized in that: The image sensor comprises a plurality of columns of pixel units arranged in an array, each column of pixel units having a column-common current input connection and a column-common current output connection, the gate of the source follower transistor of each pixel unit in each column is connected to the respective floating diffusion region, the drain of the source follower transistor is connected to the column-common current input connection, and the source of the source follower transistor is connected to the column-common current output connection directly or through the respective row selection transistors; The column-common current input connection and the column-common current output connection are connected to a column signal readout unit; The column signal readout unit includes a column bias current source and a column PMOS amplifier tube, wherein the column bias current source is connected to the common current output connection of the column, the drain of the column PMOS amplifier tube is connected to the common current input connection of the column, and the gate of the column PMOS amplifier tube is directly or through a capacitor connected to the common current output connection of the column, so that an amplified signal of the floating diffusion area of ​​the readout row pixel unit can be obtained on the common current input connection of the column.

2. The control method of the high gain image sensor according to claim 1, characterized in that: When the gate of the column PMOS amplifier tube is connected to the current output connection shared by the column through the first capacitor, a second capacitor is set between the gate and the drain of the column PMOS amplifier tube. By changing the ratio of the first capacitor to the second capacitor, the amplification factor of the floating diffusion area signal of the readout row pixel unit on the current input connection shared by the column by the column signal readout unit is changed.

3. The control method of the high gain image sensor according to claim 1, characterized in that: The column signal readout unit also includes a correlation power supply generation module, through which the first bias voltage is latched and the column second power supply voltage is output to the source of the column PMOS amplifier tube, so that the power supply of the column signal readout unit has correlation when sampling the reference signal and sampling the image signal, thereby eliminating the influence of power supply noise on the correlated double sampling.

4. The control method of the high gain image sensor according to claim 3, characterized in that: The related power generation module includes at least one source follower transistor, the drain of the source follower transistor of the related power generation module is connected to the first power supply voltage, the source is connected to the column second power supply voltage output terminal, and the gate samples and latches the first bias voltage before sampling the reference signal, thereby generating the column second power supply voltage required by the column signal readout unit and having correlation when sampling the reference signal and sampling the image signal.

5. The control method of the high-gain image sensor according to claim 4, characterized in that: The gate of the source follower transistor of the related power generation module samples the first bias voltage through the seventh switch and holds it on the third capacitor, and performs sampling and holding on a row-by-row or frame-by-frame basis before sampling the reference signal.

6. The control method of the high gain image sensor according to claim 4, characterized in that: The column signal readout unit further includes a noise compensation module, which senses fluctuations of the first power supply voltage or the column second power supply voltage and generates a negative feedback signal to act on the column second power supply voltage to suppress fluctuations of the column second power supply voltage.

7. The control method of the high gain image sensor according to claim 6, characterized in that: The noise compensation module comprises a current mirror unit, a bias terminal of the current mirror unit is connected to the first power supply voltage output terminal via a fourth capacitor, and a drain of the current mirror unit is connected to the second power supply voltage output terminal of the column.

8. The control method of the high-gain image sensor according to claim 7, characterized in that: The bias end of the current mirror unit also samples the second bias voltage through the eighth switch and holds it on the fifth capacitor to perform row-by-row or frame-by-frame sampling and holding.

9. The control method of the high-gain image sensor according to claim 7, characterized in that: The current mirror unit is a cascode current mirror.

10. The control method of the high gain image sensor according to claim 6, characterized in that: The noise compensation module includes an amplifier transistor, the gate of the amplifier transistor is connected to the second power supply voltage output terminal of the column through a sixth capacitor, the drain is connected to a current source, and is connected to the gate of a source follower transistor of the relevant power supply generating circuit through a seventh capacitor. A ninth switch is connected between the gate and the drain of the amplifier transistor, and a DC bias of the amplifier transistor can be achieved by closing the ninth switch row by row or frame by frame.

11. The control method of the high gain image sensor according to claim 1, characterized in that: The column signal readout unit further comprises a clamping module, and before sampling the reference signal and sampling the image signal, the voltage of the drain of the source follower transistor of the pixel unit is clamped to the same level by the clamping module respectively.

12. The control method of the high gain image sensor according to claim 11, characterized in that: The clamping module comprises a clamping transistor, a source of the clamping transistor is connected to a second power supply voltage, a gate and a drain are connected to each other, and the drain is connected to the drain of the source follower transistor of the pixel unit through a tenth switch.

13. The control method of the high gain image sensor according to claim 12, characterized in that: The size of the clamp transistor is a fixed size or an array adjustable size.

14. The control method of the high gain image sensor according to claim 3, characterized in that: Each of the column signal readout units corresponds to a related power generation module, or a plurality of the column signal readout units correspond to a related power generation module.

15. The control method of the high gain image sensor according to claim 6, characterized in that: Each of the column signal readout units corresponds to a noise compensation module, or a plurality of the column signal readout units correspond to a noise compensation module.

16. The control method of the high gain image sensor according to claim 11, characterized in that: Each of the column signal readout units corresponds to a clamping module, or a plurality of the column signal readout units correspond to a clamping module.

17. The control method of the high gain image sensor according to claim 1, characterized in that: include: sampling a first reference signal outputted from a source of a source follower transistor of the pixel unit to the column signal readout unit; sampling a second reference signal outputted from the drain of the source follower transistor of the pixel unit to the column signal readout unit; The transfer transistor of the pixel unit is turned on, and the image signal outputted from the pixel unit to the column signal readout unit is sampled.

18. The control method of the high gain image sensor according to claim 17, characterized in that: The step of sampling the image signal output by the pixel unit to the column signal readout unit comprises: Making a judgment according to a voltage signal read from the pixel unit; If the judgment result is a high illumination condition, sampling the first image signal output from the source of the source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a first conversion gain; If the judgment result is a low illumination condition, sampling the second image signal outputted from the drain of the source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a second conversion gain; The second conversion gain is higher than the first conversion gain.

19. The control method of the high gain image sensor according to claim 18, characterized in that: The step of judging according to the voltage signal read from the pixel unit comprises: The change amplitude of the voltage signal read from the pixel unit before and after the transfer transistor is turned on is compared with the threshold voltage. If the change amplitude is less than or equal to the threshold voltage, it is a low illumination condition; if the change amplitude is greater than the threshold voltage, it is a high illumination condition.

20. The control method of the high gain image sensor according to claim 19, characterized in that: The falling interval of the ramp voltage converted by analog to digital conversion is used as the threshold voltage.

21. The control method of the high gain image sensor according to claim 17, characterized in that: The step of sampling the image signal output by the pixel unit to the column signal readout unit comprises: sampling a second image signal outputted from a drain of a source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a second conversion gain; sampling a first image signal outputted from a source electrode of a source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a first conversion gain; The second conversion gain is higher than the first conversion gain.

22. The control method of the high gain image sensor according to claim 18 or 21, characterized in that: When the source of the source follower transistor of the pixel unit is output to the column signal readout unit, the first conversion gain is adjusted by the dual conversion gain control transistor of the pixel unit.

23. The control method of the high gain image sensor according to claim 22, characterized in that: The step of adjusting the first conversion gain by the dual conversion gain control transistor of the pixel unit comprises: The dual conversion gain control transistor is turned on to obtain a relatively low first conversion gain, or the dual conversion gain control transistor is turned off to obtain a relatively high first conversion gain.

24. The control method of the high-gain image sensor according to claim 17, characterized in that: The source or drain of the source follower transistor of the pixel unit is controlled by a switch module to be output to the column signal readout unit.

Images