Semiconductor device and manufacturing method therefor

Abstract

A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a magnetic material layer, comprising a magnetic tunnel junction or a magnetic spin valve; a first electrode, directly or indirectly arranged on a first surface of the magnetic material layer; a second electrode, directly or indirectly arranged on a second surface opposite to the first surface of the magnetic material layer; and a first stress layer, covering the side wall of an integral structure formed by at least the magnetic material layer, the first electrode and the second electrode, wherein the first stress layer is an insulating stress layer. According to the semiconductor device and the manufacturing method therefor, the technical problem of having difficulty in maintaining relatively stable stress when scaling of semiconductor devices is carried out is solved, and the performance and stability of key parameters of semiconductor devices are improved.

Description

Semiconductor device and method for manufacturing the same Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Magnetic multilayer films, such as magnetic tunnel junctions or magnetic spin valves, have been widely used in semiconductor devices such as magnetic sensors and magnetic random access memories. Key parameters such as giant magnetoresistance (GMR) / tunneling magnetoresistance (TMR), perpendicular magnetic anisotropy, and voltage-controlled magnetic anisotropy (VCMA) are crucial for improving the performance of semiconductor devices. In particular, the extended operating life of semiconductor devices and device scaling inevitably impact performance such as write voltage and energy consumption.

[0003] Summary of the Invention

[0004] In order to solve the technical problem in the prior art that it is difficult to improve the key performance of magnetic semiconductor devices, the present invention provides a semiconductor device and a method for preparing the same.

[0005] A first aspect of the present invention provides a semiconductor device, comprising:

[0006] Magnetic tunnel junction or magnetic spin valve;

[0007] a first electrode, the first electrode being directly or indirectly disposed on a first surface of the magnetic material layer;

[0008] a second electrode, the second electrode being directly or indirectly disposed on a second surface opposite to the first surface of the magnetic material layer;

[0009] a first stress layer, the first stress layer covering a side wall of an overall structure consisting of at least the magnetic material layer, the first electrode, and the second electrode;

[0010] The first stress layer is an insulating stress layer.

[0011] In some embodiments, the semiconductor device includes a second stressor layer;

[0012] The second stress layer is located on an upper wall or a lower wall of the overall structure formed by the magnetic material layer, the first electrode, and the second electrode;

[0013] Alternatively, the second stress layer is located between the first surface of the magnetic material layer and the first electrode, and / or the second stress layer is located between the magnetic material layer, the second surface, and the second electrode;

[0014] The second stress layer is a conductive stress layer.

[0015] In some embodiments, the thickness of the first stress layer is greater than half of the radius or semi-minor axis of the overall structure formed by the magnetic material layer, the first electrode, and the second electrode.

[0016] In some embodiments, a gap between two adjacent integral structures consisting of at least the magnetic material layer, the first electrode, and the second electrode is filled with the first stress layer;

[0017] Alternatively, a gap between two adjacent integral structures at least formed by the magnetic material layer, the first electrode, and the second electrode is filled by the first stress layer and the insulating isolation layer.

[0018] In some embodiments, the thickness of the first stress layer is determined according to the induced stress of the semiconductor device, and / or the gap of the overall structure is determined to be filled by the first stress layer or the gap of the overall structure is filled by the first stress layer and the insulating isolation layer according to the induced stress of the semiconductor device;

[0019] The introduced stress is determined according to a combination of one or more parameters of the semiconductor material, including perpendicular magnetic anisotropy, damping factor, voltage-controlled magnetic anisotropy coefficient, and tunnel magnetoresistance / giant magnetoresistance.

[0020] In some embodiments, the first stress layer includes silicon nitride; and the insulating isolation layer includes silicon oxide.

[0021] In some embodiments, the second stress layer and the first electrode are in the same layer, and / or the second stress layer and the second electrode are in the same layer.

[0022] A second invention of the present invention provides a method for preparing a semiconductor device, which comprises:

[0023] forming an integral structure consisting of at least the magnetic material layer, the first electrode, and the second electrode;

[0024] A first stress layer is formed on the sidewalls of the overall structure.

[0025] In some embodiments, after forming a first stress layer on the sidewalls of the integral structure, an insulating isolation layer is filled in gaps between the plurality of integral structures covered with the first stress layer.

[0026] In some embodiments, during the process of manufacturing the semiconductor device, the stress of the first stress layer is adjusted by a combination of one or more of the following methods:

[0027] Substrate temperature;

[0028] the gas flow, pressure, and type within the cavity forming the first stress layer;

[0029] a component forming a first stress layer;

[0030] Sedimentation rate;

[0031] The geometric distribution of the substrate and target in the cavity forming the first stress layer;

[0032] The thickness of the first stress layer formed by deposition.

[0033] The present invention solves the technical problem of difficulty in maintaining relatively stable stress during miniaturization of semiconductor devices, thereby improving the performance and stability of key parameters of semiconductor devices.

[0034] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0036] FIG1 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0037] FIG2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;

[0038] FIG3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;

[0039] FIG4 is a cross-sectional view of a semiconductor device according to some other embodiments of the present invention;

[0040] FIG5 is a cross-sectional view of a semiconductor device according to some other embodiments of the present invention;

[0041] 6 is a cross-sectional view of a semiconductor device according to some other embodiments of the present invention;

[0042] 7 is a cross-sectional view of a semiconductor device according to some other embodiments of the present invention;

[0043] FIG8 is a cross-sectional view of a semiconductor device according to some further embodiments of the present invention;

[0044] FIG9 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present invention;

[0045] FIG10 is a flow chart of a method for preparing an overall structure of a semiconductor device according to some embodiments of the present invention;

[0046] FIG11 is a cross-sectional view of a method for manufacturing a semiconductor device according to some embodiments of the present invention;

[0047] FIG12 is a cross-sectional view of a method for manufacturing a semiconductor device according to some embodiments of the present invention;

[0048] FIG13 is a cross-sectional view of a method for manufacturing a semiconductor device according to some embodiments of the present invention;

[0049] FIG14 is a cross-sectional view of a method for manufacturing a semiconductor device according to some embodiments of the present invention;

[0050] FIG. 15 is a cross-sectional view of a method for fabricating a semiconductor device according to some embodiments of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0053] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0054] Spin valve or magnetic tunnel junction structures have been widely used in semiconductor devices such as magnetic sensors and magnetic random access memories (MRAMs). Key parameters such as giant magnetoresistance (GMR) / tunneling magnetoresistance (TMR) and perpendicular magnetic anisotropy have a crucial impact on device performance. During MRAM operation, the GMR / TMR ratio determines the speed at which information can be read from the MRAM cell. Therefore, increasing the TMR ratio is crucial for improving read tolerance and speed. The GMR / TMR ratio also determines the sensitivity of the magnetic sensor. Perpendicular magnetic anisotropy is a key indicator of information retention time. For the same device size, stronger perpendicular magnetic anisotropy increases the device's thermal stability and the longer the information is retained in the medium. Therefore, improving these performance indicators is crucial to enhancing the performance of magnetic sensors and MRAMs. Furthermore, for voltage-controlled magnetic random access memory (VC-MRAM), the voltage-controlled magnetic anisotropy (VCMA) coefficient is a key parameter, determining the device's write voltage and energy consumption.

[0055] Introducing stress is a good way to optimize the above key parameters. For example, different substrates can be used to apply stress, thereby changing the perpendicular magnetic anisotropy and TMR of the material. Piezoelectric materials, such as PMN-PT, are used as substrates, and a magnetic multilayer film structure is grown on it. Different voltages are applied to the substrate to cause the piezoelectric material to generate stress and act on the magnetic film / device, thereby regulating its perpendicular magnetic anisotropy. In addition, flexible substrates can also be used to apply stress to the magnetic film / device and regulate its TMR coefficient. For the VCMA coefficient, it has been found that lattice adaptation can be introduced by using methods such as molecular beam epitaxy and low-temperature cooling, thereby introducing stress. This stress can regulate the VCMA coefficient of the sample.

[0056] However, all of these methods have drawbacks. While using PMN-PT and flexible substrates allows for continuous stress adjustment, their incompatibility with CMOS processes has limited their commercialization. Furthermore, PMN-PT contains toxic lead, posing a threat to the environment and human health. Due to the slow growth rate of molecular beam epitaxy (MBE) thin films, the method of introducing stress at the interface by lattice mismatch during MBE growth of magnetic films is unsuitable for large-scale production. Furthermore, none of these methods consider the impact of stress as the device scales, making it difficult to maintain stable device performance.

[0057] In light of this, the present invention provides a semiconductor device and a method for fabricating the same, which can effectively enhance the device's sensitivity and storage performance. The present invention applies a wider range of stress than the aforementioned method. Furthermore, the stress film disclosed in the present invention is CMOS process-compatible, making it suitable for large-scale production. Furthermore, the stress applied by the present invention does not decrease as the magnetic tunnel junction device is miniaturized. Compared to conductor stress layers, the residual stress in the present method does not change over time, maintaining stable device performance.

[0058] Figure 1 is a schematic diagram of the structure of a semiconductor device according to some embodiments of the present invention. Referring to Figure 1 , the semiconductor device may include a magnetic material layer 1, a first electrode 2 located on the lower surface of the magnetic material layer 1, a second electrode 3 located on the upper surface of the magnetic material layer 1, and a first stressor layer 4 covering the sidewalls of the overall structure consisting of the magnetic material layer 1, the first electrode 2, and the second electrode 3. The magnetic material layer is a magnetic tunnel junction or a magnetic spin valve, and the first stressor layer 4 is an insulating stressor layer.

[0059] The first electrode 2 can be made of a conductive material such as titanium nitride, tantalum nitride, etc., and its surface should be flat in order to facilitate the growth of a high-quality magnetic film thereon.

[0060] The material of the second electrode 3 can also be used as a hard mask material for etching the magnetic thin film, and a magnetic tunnel junction or magnetic spin valve structure can be formed by exposure and etching. The hard mask material can be TiN. The magnetic tunnel junction or magnetic spin valve structure can be a cylinder or an elliptical cylinder.

[0061] The magnetic material layer 1 is a thin film structure based on a magnetic tunnel junction or spin valve structure. Semiconductor structures based on magnetic tunnel junctions or spin valve structures can be used as magnetic memories or magnetic sensors. Typical magnetic memories include magnetic field reversal magnetic memory (MRAM), spin-transfer torque magnetic memory (STT-MRAM), spin-orbit torque magnetic memory (SOT-MRAM), and voltage-controlled magnetic memory (VC-MRAM). Typical magnetic sensors include tunneling magnetoresistance (TMR) sensors and giant magnetoresistance (GMR) sensors.

[0062] It is understood that the stress generated by the first stress layer 4 can be tensile stress or compressive stress. Generally, the stress generated by the first stress layer 4 should be greater than 500 MPa. The first stress layer 4 can be prepared using a thin film deposition method such as CVD, so that it is coated on the sidewalls of the overall structure composed of the magnetic material layer 1, the first electrode 2, and the second electrode 3.

[0063] In this embodiment, the first stressor layer 4 includes sidewalls that fully enclose the integral structure formed by the magnetic material layer 1, the first electrode 2, and the second electrode 3, and connects the gap between two adjacent integral structures formed by the magnetic material layer 1, the first electrode 2, and the second electrode 3. Referring to FIG1 , the first stressor layer 4 provided in this embodiment does not completely fill the gap between two adjacent integral structures formed by the magnetic material layer 1, the first electrode 2, and the second electrode 3. The degree to which the first stressor layer fills the gap between the adjacent integral structures can be adjusted by adjusting the deposition time or other control factors.

[0064] The first stress layer 4 of the semiconductor device provided in this embodiment is coated on the side surface of the overall structure and integrally covers a portion of the gap in the overall structure formed by the magnetic material layer 1, the first electrode 2, and the second electrode 3. When the magnetic tunnel junction or the spin valve in the overall structure is miniaturized, the first stress layer 4 can utilize the slight deformation of the overall structure to provide the stress required by the semiconductor device. It is not affected by the deformation of the overall structure caused by changes in operation time, and the device performance remains stable, especially the key parameters in the device performance that affect the storage write voltage and energy consumption, such as giant magnetoresistance (GMR) / tunneling magnetoresistance (TMR), perpendicular magnetic anisotropy, and voltage-controlled magnetic anisotropy (VCMA).

[0065] Figures 2 and 3 are schematic diagrams of semiconductor structures according to other embodiments of the present invention. Referring to Figure 2 , based on the above embodiment, this embodiment differs from the above embodiment in that plug structures for connection are further provided on the upper and lower walls of the overall structure consisting of the magnetic material layer 1 covering the first stress layer 4, the first electrode 2, and the second electrode 3.

[0066] Further referring to FIG. 2 , a first plug 5 is formed on the lower wall of the first electrode 2, and a second plug 6 is formed on the upper wall of the second electrode 3. The diameters of the first plug 5 and the second plug 6 can be greater than or equal to the diameter of the magnetic material layer 1. In order to further introduce stress into the upper wall of the overall structure formed by the second electrode 3, the diameters of the first plug 5 and the second plug 6 can be smaller than the size of the magnetic material layer 1. When the magnetic tunnel junction or spin valve structure is a cylindrical structure, the radius of the first plug 5 and the second plug 6 is smaller than the radius of the magnetic tunnel junction or spin valve structure; when the magnetic tunnel junction or spin valve structure is an elliptical cylinder structure, the radius of the first plug 5 and the second plug 6 is less than half the short axis of the magnetic tunnel junction or spin valve structure.

[0067] In a further embodiment, the plug structure may include a barrier layer, a liner layer, and a filling layer. The barrier layer may be made of Ti, the liner layer may be made of TiN, and the filling layer may be made of W.

[0068] In embodiments not shown, the plug structure may be provided only on the upper wall or only on the lower wall of the overall structure. Furthermore, in embodiments where the first plug 5 is provided only on the lower wall of the first electrode 2 of the overall structure, a second electrode 3 thicker than the first electrode 2 may be used to replace the second plug 6 in terms of connection function. Similarly, in embodiments where the second plug 6 is provided only on the upper wall of the second electrode 3 of the overall structure, a first electrode 2 thicker than the second electrode 3 may be used to replace the first plug 5 in terms of connection function.

[0069] 3 , in some embodiments, the first stress layer 4 extends to the upper surface of the second electrode 3 and covers the sidewalls of the lower half of the second plug 6. Although not shown, the first stress layer 4 may also extend to the lower surface of the first electrode 2 and cover the sidewalls of the upper half of the first plug 5; or the first stress layer 4 may also extend to the upper surface of the second electrode 3 and the lower surface of the first electrode 2, and cover the sidewalls of the lower half of the second plug 6 and the sidewalls of the upper half of the first plug 5.

[0070] When the first stress layer 4 extends to the upper surface of the second electrode 3 and covers the side wall of the lower half of the second plug 6, the insulating isolation layer filling the gap between two adjacent integral structures consisting of the magnetic material layer 1, the first electrode 2, the first plug 5, the second electrode 3, and the second plug 6 maintains the same height as the upper surface of the first stress layer 4; when the first stress layer 4 extends to the lower surface of the first electrode 4 and covers the side wall of the lower half of the first plug 5, the insulating isolation layer filling the gap between two adjacent integral structures consisting of the magnetic material layer 1, the first electrode 2, the first plug 5, the second electrode 3, and the second plug 6 maintains the same height as the lower surface of the first stress layer 4.

[0071] Other technical features of the embodiments shown in FIG. 2 and FIG. 3 are the same as those of the non-exclusive embodiments that can be implemented with reference to the drawings and are not described in detail.

[0072] 4 to 7 are schematic structural diagrams of semiconductor structures according to some further embodiments. Based on the above embodiment, the present embodiment differs from the above embodiment in that the semiconductor structure further includes a second stress layer 7, which is a conductive stress layer.

[0073] Referring to the embodiment shown in FIG. 4 , the second stress layer 7 is located on the upper wall of the overall structure formed by the magnetic material layer 1 , the first electrode 2 , and the second electrode 3 .

[0074] Specifically, the semiconductor device shown in FIG4 may include a magnetic material layer 1, a first electrode 2 located on the lower surface of the magnetic material layer 1, a second stressor layer 7 located on the upper surface of the magnetic material layer 1, a second electrode 3 located on the upper surface of the second stressor layer 7, and a first stressor layer 4 covering the sidewalls of the overall structure consisting of the magnetic material layer 1, the first electrode 2, the second stressor layer 7, and the second electrode 3. The magnetic material layer is a magnetic tunnel junction or a magnetic spin valve, the first stressor layer 4 is an insulating stressor layer, and the second stressor layer 7 is a conductive stressor layer.

[0075] Referring to the embodiment shown in FIG. 5 , the second stress layer 7 is located on the bottom wall of the overall structure formed by the magnetic material layer 1 , the first electrode 2 , and the second electrode 3 .

[0076] Specifically, the semiconductor device shown in FIG5 may include a magnetic material layer 1, a first electrode 2 located on the lower surface of the magnetic material layer 1, a second electrode 3 located on the upper surface of the magnetic material layer 1, a second stressor layer 7 located on the upper surface of the second electrode 3, and a first stressor layer 4 covering the sidewalls of the overall structure consisting of the magnetic material layer 1, the first electrode 2, the second electrode 3, and the second stressor layer 7. The magnetic material layer is a magnetic tunnel junction or a magnetic spin valve, the first stressor layer 4 is an insulating stressor layer, and the second stressor layer 7 is a conductive stressor layer.

[0077] Referring to the embodiment shown in FIG. 6 , the second stress layer 7 is located between the lower surface of the magnetic material layer 1 and the first electrode 2 .

[0078] Specifically, the semiconductor device shown in FIG6 may include a magnetic material layer 1, a first electrode 2 located on the lower surface of the magnetic material layer 1, a second stressor layer 7 located on the lower surface of the first electrode 2, a second electrode 3 located on the upper surface of the magnetic material layer 1, and a first stressor layer 4 covering the sidewalls of the overall structure consisting of the magnetic material layer 1, the second stressor layer 7, the first electrode 2, and the second electrode 3. The magnetic material layer is a magnetic tunnel junction or a magnetic spin valve, the first stressor layer 4 is an insulating stressor layer, and the second stressor layer 7 is a conductive stressor layer.

[0079] Referring to the embodiment shown in FIG. 7 , the second stress layer 7 is located between the upper surface of the magnetic material layer 1 and the second electrode 3 .

[0080] Specifically, the semiconductor device shown in FIG7 may include a magnetic material layer 1, a second stressor layer 7 located on the lower surface of the magnetic material layer 1, a first electrode 2 located on the lower surface of the second stressor layer 7, a second electrode 3 located on the upper surface of the magnetic material layer 1, and a first stressor layer 4 covering the sidewalls of the overall structure consisting of the magnetic material layer 1, the second stressor layer 7, the first electrode 2, and the second electrode 3. The magnetic material layer is a magnetic tunnel junction or a magnetic spin valve, the first stressor layer 4 is an insulating stressor layer, and the second stressor layer 7 is a conductive stressor layer.

[0081] Furthermore, in the embodiments shown in Figures 4 to 7, the second stress layer 7 can be a material that inherently has stress, such as TiN, TaN, or can be a material that generates stress due to lattice mismatch between different materials, or can be other reasonable methods and materials that can still apply stress to the device after the device is manufactured. Similarly, the stress generated by the second stress layer 7 can be tensile stress or compressive stress. By adjusting the thickness of the second stress layer 7, the stress that the second stress layer 7 can apply to the device can be adjusted. The second stress layer 7 and the first stress layer 4 can also cooperate. During the semiconductor miniaturization process, the first stress layer 4 covers the second stress layer 4 so that it can apply sufficient stress to avoid deformation of the first stress layer 4 caused by semiconductor deformation, which may result in insufficient stress provided by the first stress layer 4. Therefore, the stress applied when designing the first stress layer 4 should meet the lateral stress required during semiconductor miniaturization and the stress required by the second stress layer 7 during the deformation process.

[0082] It is understood that, as in the embodiments of Figures 4 to 7, there may be multiple second stress layers 7, that is, there may be two second stress layers 7, located on the upper surface of the magnetic material layer 1 and the lower surface of the magnetic material layer 1, respectively; or there may be two second stress layers 7, located on the lower surface of the first electrode 2 and the upper surface of the second electrode 3, respectively; or there may be two second stress layers 7, one located on the upper surface of the magnetic material layer 1 and the other located on the lower surface of the first electrode 2; or there may be two second stress layers 7, one located on the lower surface of the magnetic material layer 1 and the other located on the lower surface of the second electrode 3. Other embodiments in which multiple second stress layers 7 are disposed at any spaced positions between the second electrode 3, the magnetic material layer 1, and the first electrode 2 are understood to fall within the scope of this embodiment.

[0083] Other technical features of the embodiments shown in FIG. 4 to FIG. 7 are the same as those of the non-exclusive embodiments that can be implemented with reference to FIG. 1 to FIG. 3 , and are not described in detail.

[0084] FIG8 is a schematic structural diagram of a semiconductor structure according to some further embodiments. Based on the above embodiment, this embodiment provides different filling methods for the gap between two adjacent integral structures composed of at least the magnetic material layer, the first electrode, and the second electrode.

[0085] Specifically, the gap between two adjacent integral structures composed of at least the magnetic material layer 1 , the first electrode 2 , and the second electrode 3 is filled by the first stress layer 4 , or by both the first stress layer 4 and the insulating isolation layer 8 .

[0086] For example, in the embodiment shown in FIG. 1 , the gap between two adjacent integral structures composed of at least the magnetic material layer 1 , the first electrode 2 , and the second electrode 3 is filled by the first stress layer 4 and the insulating isolation layer 8 .

[0087] Specifically, the gap between two adjacent structures composed of the magnetic material layer 1, the first electrode 2, and the second electrode 3 that are not filled by the first stress layer 4 is filled with an insulating material to ensure the mutual independence between the devices and avoid the occurrence of short circuits. The insulating material can be SiO2.

[0088] For another example, in the embodiment shown in FIG. 8 , the gap between two adjacent integral structures composed of at least the magnetic material layer 1 , the first electrode 2 , and the second electrode 3 is filled with the first stress layer 4 .

[0089] Specifically, the first stress layer 4 fully fills the gap between two adjacent integral structures composed of the magnetic material layer 1, the first electrode 2, and the second electrode 3, so that the first stress layer 4 can apply greater stress than the first stress layer 4 in the embodiment in which the gap of the integral structure is not fully filled.

[0090] Other technical features of the semiconductor device shown in FIG8 are the same as those of the non-exclusive practicable embodiments shown in FIG1 to FIG3 . A second stress layer 7 made of a conductive material may also be introduced with reference to FIG4 to FIG7 , and details thereof will not be repeated.

[0091] 1 to 8 , the thickness of the first stress layer 4 affects the stress applied to the overall structure composed of the magnetic material layer 1 , the first electrode 2 , and the second electrode 3 .

[0092] To ensure that the first stressor layer 4 applies sufficient stress to the overall structure comprised of the magnetic material layer 1, the first electrode 2, and the second electrode 3, the following limits are imposed on the minimum thickness of the first stressor layer 4 at its thinnest point: when the magnetic tunnel junction or spin valve structure is cylindrical, the thickness of the first stressor layer 4 at its thinnest point should be greater than the radius of the magnetic tunnel junction or spin valve structure; when the magnetic tunnel junction or spin valve structure is an elliptical cylinder, the thickness of the first stressor layer 4 at its thinnest point should be greater than half the minor axis of the magnetic tunnel junction or spin valve structure. In addition to the thickness of the first stressor layer 4 at its thinnest point, adjusting the material composition and growth conditions of the first stressor layer 4 also contributes to adjusting its ability to apply stress, ensuring that the first stressor layer can apply the desired stress.

[0093] The foregoing is a detailed introduction to the semiconductor device provided in the present application, corresponding to the aforementioned semiconductor device embodiments. The following will focus on the preparation method of the semiconductor device provided in the present application.

[0094] FIG9 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments, and FIG10 is a flow chart of a method for manufacturing an overall structure of a semiconductor device according to some embodiments of the present invention. Referring to FIG9 , it includes:

[0095] S901 , forming an integral structure consisting of at least a magnetic material layer, a first electrode, and a second electrode.

[0096] Referring to FIG. 10 , a method for preparing the overall structure of a semiconductor device includes:

[0097] S1001 : growing a first electrode 2 on the substrate 10 .

[0098] The material forming the first electrode 2 includes but is not limited to metal materials such as tantalum, titanium, platinum, ruthenium, or metal nitrides such as titanium nitride, tantalum nitride, and tungsten nitride.

[0099] The process for growing the first electrode 2 may be a sputtering process (DC Sputtering, Magnetron Sputtering), a thermal evaporation process (E-beam Evaporation), a chemical vapor deposition process (CVD, PECVD, LPCVD, etc.), an atomic layer deposition (ALD) process, or a molecular beam epitaxy (MBE) process.

[0100] If the surface of the first electrode 2 formed after growth is not flat, a process flow for flattening it should be provided. Typical flattening process flows include dry etching or chemical mechanical polishing.

[0101] The first plug 5 may include a barrier layer, a liner layer, and a filling layer. The barrier layer may be made of Ti, the liner layer may be made of TiN, and the filling layer may be made of W.

[0102] S1002: growing a magnetic material layer 1 on the first electrode 2. The magnetic material layer 1 includes a magnetic tunnel junction or a magnetic spin valve.

[0103] Specifically, magnetic material layer 1 can be a composite layer structure, comprising a magnetic or non-magnetic layer structure, such as a buffer layer or seed layer, a free layer, a non-magnetic intermediate layer, a reference layer, an antiferromagnetic coupling layer, and a pinned layer, with no restrictions on the order or number of layers. When the non-magnetic intermediate layer is a metal material, such as copper, magnetic material layer 1 is a spin valve thin film system; when the non-magnetic intermediate layer is an insulating material, such as magnesium oxide, magnetic material layer 1 is a magnetic tunnel junction thin film system.

[0104] Optionally, the method for preparing a semiconductor device provided in this embodiment may further include preparing a second stress layer 7 serving as a conductive stress layer before or after forming the magnetic material layer 1 .

[0105] The material of the second stress layer 7 includes but is not limited to TiN, TaN, WN, etc.

[0106] In some embodiments, the minimum stress required for the second stress layer 7 is determined based on parameters such as perpendicular magnetic anisotropy, damping factor, voltage-controlled magnetic anisotropy coefficient, and tunnel magnetoresistance / giant magnetoresistance. The thickness and material ratio of the deposited second stress layer are preliminarily determined, and this is achieved by introducing the aforementioned types of gases into the chamber. During the preparation of the second stress layer 7, the substrate temperature, gas flow rate within the chamber where the second stress layer is formed, gas pressure, deposition rate, and the geometric distribution of the substrate and target material within the chamber where the second stress layer 7 is formed are further adjusted to ensure that the formed second stress layer 7 can exert sufficient stress.

[0107] S1003 : growing the second electrode 3 on the magnetic material layer 1 .

[0108] The material forming the second electrode 3 includes, but is not limited to, metal nitrides, such as titanium nitride, tantalum nitride, and tungsten nitride.

[0109] The upper surface after growing the second electrode 3 should be kept flat, and the process may be a sputtering process (DC Sputtering, Magnetron Sputtering), a thermal evaporation process (E-beam Evaporation), a chemical vapor deposition process (CVD, PECVD, LPCVD, etc.), an atomic layer deposition (ALD) process or a molecular beam epitaxy process (MBE).

[0110] It should be noted that the material of the second electrode 3 can also be used as a hard mask material for etching a magnetic thin film to form a magnetic tunnel junction or a magnetic spin valve structure by exposure and etching. The hard mask material can be TiN, for example.

[0111] S1004 is etching to form an overall structure consisting of the first electrode 2 , the magnetic material layer 1 and the second electrode 3 .

[0112] S902 , forming a first stress layer on the sidewall of the overall structure.

[0113] It is understood that the methods for forming the first stress material layer 4 include, but are not limited to, sputtering (DC sputtering, magnetron sputtering), thermal evaporation (E-beam evaporation), chemical vapor deposition (CVD, PECVD, LPCVD, etc.), atomic layer deposition (ALD), molecular beam epitaxy (MBE), and various oxidation and diffusion processes.

[0114] FIG. 11 illustrates a method for fabricating a semiconductor device according to some embodiments.

[0115] FIG. 11 shows a first plug 55 formed on a substrate 50 . Please refer to FIG. 11 .

[0116] Optionally, the substrate may also be a wafer with transistor switching elements. Devices that can be used as switching elements include planar transistors (Planer FET), fin transistors (Fin FET), nanowire or nanosheet transistors (Nano wire or Nano Sheet FET), etc. or a combination thereof. Taking a transistor as an example, the source region, drain region, and the area above the drain region of the transistor are connected to the first plug 55 formed between the metal wire layer. The device of the present invention relates to a transistor back-end process, that is, the device can be placed between any two adjacent metal interconnect layers of the back-end.

[0117] The formation process of the first plug 55 involves an exposure process combined with an etching process, a thin film deposition process, and a planarization process. Optionally, the photolithography process includes but is not limited to i-line, G-line, DUV, EUV, multi-patterning, etc., the etching process includes but is not limited to wet etching, RIE, ICP-RIE, IBE, etc., the deposition process includes but is not limited to various sputtering processes (DC Sputtering, Magnetron Sputtering), various evaporation processes (Thermal Evaporation, E-beam Evaporation), various chemical vapor deposition processes (CVD, PECVD, LPCVD, etc.), atomic layer epitaxy (ALD) process or molecular beam epitaxy (MBE), etc., and the planarization process includes but is not limited to RIE, ICP-RIE, CMP, etc.

[0118] The material of the first plug 55 includes tungsten / titanium / titanium nitride, cobalt, and ruthenium. In some embodiments, the first plug 55 includes a barrier layer, a liner layer, and a filling layer. The barrier layer may include Ti, the liner layer may include TiN, and the filling layer may include W.

[0119] The upper surface of the first plug 55 is coplanar with the upper surface of the insulating portion 50 on the substrate.

[0120] FIG. 12 shows a hierarchical structure in which a semiconductor device is further formed on the first plug 55 . Please refer to FIG. 12 .

[0121] The first electrode 52, the magnetic material layer 51 and the second electrode 53 are sequentially grown on the first plug 55, as shown in FIG9. Specifically, the method may include:

[0122] The first electrode 52 is grown on the first plug 55 .

[0123] The material forming the first electrode 52 includes, but is not limited to, metal materials such as tantalum, titanium, platinum, ruthenium, or metal nitrides such as titanium nitride, tantalum nitride, and tungsten nitride.

[0124] The first electrode 52 is grown using processes such as sputtering (DC sputtering, magnetron sputtering), thermal evaporation (E-beam evaporation), chemical vapor deposition (CVD, PECVD, LPCVD, etc.), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). Its top surface should be flat, with a roughness of less than 0.5 angstroms. This requirement can be achieved using processes such as CMP.

[0125] A magnetic material layer 51 is grown on the first electrode 52. The magnetic material layer 51 includes a magnetic tunnel junction or a magnetic spin valve.

[0126] Specifically, magnetic material layer 51 can be a composite layer structure, comprising a magnetic or non-magnetic layer structure, such as a buffer layer or seed layer, a free layer, a non-magnetic intermediate layer, a reference layer, an antiferromagnetic coupling layer, and a pinned layer, with no restrictions on the order or number of layers. When the non-magnetic intermediate layer is a metal material, such as copper, magnetic material layer 51 is a spin valve thin film system. When the non-magnetic intermediate layer is an insulating material, such as magnesium oxide, magnetic material layer 51 is a magnetic tunnel junction thin film system.

[0127] Optionally, the method for manufacturing a semiconductor device provided in this embodiment may further include preparing a second stress layer 57 serving as a conductive stress layer before or after forming the magnetic material layer 51 .

[0128] The material of the second stress layer 57 includes but is not limited to TiN, TaN, WN, etc.

[0129] In some embodiments, the minimum stress required for the second stress layer is determined based on parameters such as perpendicular magnetic anisotropy, damping factor, voltage-controlled magnetic anisotropy coefficient, and tunnel magnetoresistance / giant magnetoresistance. The thickness and material ratio of the deposited second stress layer are preliminarily determined, and this is achieved by introducing the aforementioned types of gases into the chamber. During the preparation of the second stress layer 57, the substrate temperature, the gas flow rate within the chamber where the second stress layer is formed, the deposition rate, and the geometric distribution of the substrate and target material within the chamber where the second stress layer 57 is formed are further adjusted to ensure that the formed second stress layer 57 exerts sufficient stress.

[0130] The second electrode 53 is grown on the magnetic material layer 51 .

[0131] The material forming the second electrode 53 includes, but is not limited to, metal nitrides, such as titanium nitride, tantalum nitride, tungsten nitride, and metal materials.

[0132] The upper surface after the second electrode 53 is grown should be kept flat, and the process may be a sputtering process (DC Sputtering, Magnetron Sputtering), an evaporation process (Thermal Evaporation, E-beam Evaporation), a chemical vapor deposition process (CVD, PECVD, LPCVD, etc.), an atomic layer deposition (ALD) process or a molecular beam epitaxy process (MBE).

[0133] It should be noted that the material of the second electrode 53 can also be used as a hard mask material for etching a magnetic thin film to form a magnetic tunnel junction or a magnetic spin valve structure by exposure and etching. The hard mask material may be TiN, for example.

[0134] FIG13 shows an overall structure formed by etching the first electrode 52 , the magnetic material layer 51 and the second electrode 53 . Please refer to FIG13 .

[0135] A magnetic tunnel junction or a magnetic spin valve structure is formed above the first plug using a photolithography process in combination with an etching process, wherein the photolithography process includes but is not limited to i-line, G-line, DUV, EUV, multi-patterning, and nanoimprinting, and the etching process includes but is not limited to wet etching, RIE, ICP-RIE, IBE, etc. The morphology of the formed magnetic storage device includes but is not limited to a cylinder or an elliptical cylinder. In some embodiments, the device can be formed in the form of a photoresist as an etch barrier layer. In other embodiments, a metal hard mask method is also required to form the device through exposure and etching processes. In some embodiments, the conductive stress material and the second electrode can serve as or partially serve as a metal hard mask material.

[0136] FIG14 shows a first stress material layer 54 coated on the outer side of the overall structure consisting of the first electrode 52 , the magnetic material layer 51 and the second electrode 53 . Please refer to FIG14 .

[0137] It is understood that the methods for forming the first stress material layer 54 include, but are not limited to, sputtering (DC sputtering, magnetron sputtering), evaporation (thermal evaporation, E-beam evaporation), chemical vapor deposition (CVD, PECVD, LPCVD, etc.), atomic layer deposition (ALD), molecular beam epitaxy (MBE), and various oxidation and diffusion processes.

[0138] Similar to the second stress layer 57, the minimum stress required for the second stress layer can be determined based on parameters such as perpendicular magnetic anisotropy, damping factor, voltage-controlled magnetic anisotropy coefficient, tunnel magnetoresistance / giant magnetoresistance, and the thickness and material ratio of the deposited second stress layer can be preliminarily determined. This can be achieved by introducing the aforementioned types of gases into the chamber. During the preparation of the first stress material layer 54, the substrate temperature, gas flow rate within the chamber where the second stress layer is formed, gas pressure, deposition rate, and the geometric distribution of the substrate and target within the chamber where the first stress material layer 54 is formed can be adjusted to further ensure that the first stress material layer 54 exerts sufficient stress.

[0139] Depositing an insulating isolation layer. This layer is deposited in the gaps between the components to isolate them from each other and prevent short circuits.

[0140] After depositing the insulating layer, the device surface is flattened through a flattening process such as CMP. In some embodiments, an in-situ stressor layer is grown in a vacuum environment after device formation to protect the device from damage due to oxidation or water absorption. It is understood that the time between device formation and deposition of the insulating stressor layer must be strictly controlled to protect the magnetic device from oxidation and water absorption.

[0141] FIG. 15 shows the formation of a second plug 56 and further provision of insulation protection. Please refer to FIG. 15 .

[0142] The second plug 56 is formed by using an exposure process combined with an etching process, a deposition process, and a planarization process above the second electrode. The exposure process includes, but is not limited to, i-line, G-line, DUV, EUV, and multi-patterning. The etching process includes, but is not limited to, wet etching, RIE, ICP-RIE, and IBE. The deposition process includes, but is not limited to, sputtering (DC sputtering, magnetron sputtering), thermal evaporation (E-beam evaporation), various chemical vapor deposition processes (CVD, PECVD, LPCVD, etc.), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). The planarization process includes, but is not limited to, RIE, ICP-RIE, and CMP. The materials of the second plug structure include, but are not limited to, tungsten / titanium / titanium nitride (W / Ti / TiN), cobalt (Co), and ruthenium (Ru).

[0143] Similar to the first plug 55, the second plug 56 may include a barrier layer, a liner layer, and a filling layer. The barrier layer may be made of Ti, the liner layer may be made of TiN, and the filling layer may be made of W.

[0144] An insulating isolation layer is deposited and a planarization process is used to remove excess material and keep the surface flat, so that the upper surface of the second plug 56 is parallel to the insulating isolation layer, that is, there is no step difference between the substrate insulating layer and the upper surface of the second plug 56 .

[0145] After the deposition of the insulating isolation layer 58, the device has achieved further protection.

[0146] The steps of forming the first plug 55 and the second plug 56 are not essential steps of this embodiment. The first plug 55 may be replaced by depositing a thicker first electrode 52 , or the second plug 56 may be replaced by depositing a thicker second electrode 53 .

[0147] This embodiment provides a method for preparing a semiconductor device. After forming an integral structure consisting of a magnetic material layer, a first electrode, and a second electrode, a first stress layer is disposed to cover the side surfaces of the integral structure and integrally cover all or part of the gaps in the integral structure. When a magnetic tunnel junction or a spin valve in the integral structure is miniaturized, the first stress layer can utilize the slight deformation of the integral structure to provide the stress required by the semiconductor device. The device is not affected by the deformation of the integral structure over time, and the device performance remains stable, especially key parameters in the device performance that affect storage write voltage and energy consumption, such as giant magnetoresistance (GMR) / tunneling magnetoresistance (TMR), perpendicular magnetic anisotropy, and voltage-controlled magnetic anisotropy (VCMA).

[0148] It should be understood that the film thickness in the figure is only a schematic diagram and does not represent the actual thickness and proportion.

[0149] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present invention, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A magnetic material layer, wherein the magnetic material layer includes a magnetic tunnel junction or a magnetic spin valve; A first electrode, the first electrode is directly or indirectly disposed on a first surface of the magnetic material layer; a second electrode, the second electrode being directly or indirectly disposed on a second surface opposite to the first surface of the magnetic material layer; a first stress layer, wherein the first stress layer covers a side wall of an overall structure consisting of at least the magnetic material layer, the first electrode, and the second electrode; The first stress layer is an insulating stress layer.

2. The semiconductor device according to claim 1, wherein: The semiconductor device comprises a second stress layer; The second stress layer is located on an upper wall or a lower wall of an overall structure formed by the magnetic material layer, the first electrode, and the second electrode; Or, the second stress layer is located between the first surface of the magnetic material layer and the first electrode, and / or, the second stress layer is located between the magnetic material layer and the second surface and the second electrode; The second stress layer is a conductive stress layer.

3. The semiconductor device according to claim 1, wherein: The thickness of the first stress layer is greater than half of the radius or semi-minor axis of the overall structure formed by the magnetic material layer, the first electrode, and the second electrode.

4. The semiconductor device according to claim 1, wherein: The filling method of the gap between two adjacent integral structures composed of at least the magnetic material layer, the first electrode, and the second electrode includes: filling with the first stress layer; filling with the first stress layer and the insulating isolation layer together.

5. The semiconductor device according to claim 4, characterized in that The thickness of the first stress layer is determined by the induced stress of the semiconductor device; and / or, The filling method of the gap of the overall structure is determined by the induced stress of the semiconductor device; The introduced stress is determined according to a combination of one or more parameters of the perpendicular magnetic anisotropy, damping factor, voltage-controlled magnetic anisotropy coefficient, and tunnel magnetoresistance / giant magnetoresistance of the semiconductor material.

6. The semiconductor device according to claim 4, characterized in that The first stress layer includes silicon nitride; and the insulating isolation layer includes silicon oxide.

7. The semiconductor device according to claim 2, characterized in that The second stress layer and the first electrode are in the same layer, and / or the second stress layer and the second electrode are in the same layer.

8. A method for preparing a semiconductor device, characterized in that: The method of preparing a semiconductor device as claimed in any one of claims 1 to 7 comprises: forming an integral structure consisting of at least the magnetic material layer, the first electrode, and the second electrode; A first stress layer is formed by coating the sidewalls of the overall structure.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: After the sidewalls of the integral structure are coated with a first stress layer, an insulating isolation layer is filled in the gaps between the plurality of integral structures coated with the first stress layer.

10. The method for preparing a semiconductor device according to claim 8, characterized in that: In the process of preparing the semiconductor device, the stress of the first stress layer is adjusted by a combination of one or more of the following methods: Substrate temperature; The gas flow, pressure and type in the cavity forming the first stress layer; A component forming a first stress layer; Sedimentation rate; The geometric distribution of the substrate and the target in the cavity for forming the first stress layer; The thickness of the first stress layer formed by deposition is

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