Method and apparatus for generating low-power qubit control signal for superconducting quantum computer control

Abstract

Disclosed are a method and an apparatus for generating a qubit control signal, wherein a main pulse and a DRAG pulse used to control a superconducting quantum computer are generated with low power and without a memory. The method comprises the steps of: generating a first sine curve having a first phase obtained by multiplying an angular velocity by a predetermined time of each period, the angular velocity being obtained by adding a first angular velocity of a center frequency and a second angular velocity at a predetermined time of each period; and generating a second sine curve having a second phase obtained by multiplying an angular velocity by a predetermined time, the angular velocity being obtained by subtracting the second angular velocity from the first angular velocity. The DRAG pulse is generated through an operation of adding the first sine curve and the second sine curve.

Description

Method and device for generating low-power qubit control signals for controlling superconducting quantum computers

[0001] The present invention relates to a qubit control signal generation technology for a superconducting quantum computer, and more particularly, to a qubit control signal generation method and device for generating a main pulse and a drag (DRAG: derivative removal by adiabatic gate) pulse used for controlling a superconducting quantum computer at low power without memory.

[0002] Superconducting quantum computers are currently controlled using radio frequency (RF) signals and phases. Transmon qubits, the basic data processing units of superconducting quantum computers, have shorter coherence times (i.e., the time during which information is retained) than other qubits. Google and IBM, which are developing superconducting quantum computers, are working to reduce the length of control signals to perform many calculations within the limited coherence time.

[0003] Qubits utilize quantum properties to have a unique frequency corresponding to each energy state. The frequencies used in basic quantum computer operations are The frequency of the energy band corresponding to and the frequency used to create quantum entanglement are is the frequency of the energy band corresponding to . Usually, the energy (ω) required to go from the ground state to the first excited state 01 ) corresponding to the frequency (f 01 ) is between 5-7 GHz, and the energy (ω) to go from the first excited state to the second excited state 12 ) corresponding to the frequency (f 12 ) is the frequency (f) of the above 01 ) refers to a frequency that is approximately 150-350 MHz lower than the reference frequency.

[0004] As the length of the RF signal for qubit control becomes shorter, the frequency spectrum becomes wider. This generates noise in the frequency range surrounding the center frequency of the qubit. That is, if a short pulse width of, for example, less than 30 ns is used considering the limited coherence time, the frequency power becomes spread around the center frequency. This is because the center frequency (f) of the qubit 01 ) is located approximately 150 to 350 MHz to the left of the second frequency (f 12 ) generates unwanted changes in energy states, i.e. noise. This becomes a major source of error in quantum computing.

[0005] To address these error factors, i.e., to minimize frequency spread, techniques have been proposed that use Gaussian shapes, sine shapes, or raised cosine shapes instead of rectangular pulse shapes.

[0006] However, although the above-mentioned conventional technique can reduce the frequency spread more than the rectangular shape, as the length of the control pulse becomes increasingly shorter, the pulse shape alone cannot achieve the desired level of low noise at the second frequency.

[0007] Another prior art technique proposed a method of reducing noise at a second frequency by adding a DRAG (derivative removal by adiabatic gate) pulse to the main pulse, which has the shape of the original signal, i.e., the main pulse, and has a phase difference of 90° from the frequency of the main pulse, and is currently used in most superconducting quantum computer operations.

[0008] This method of generating a qubit control pulse using a DRAG pulse plays a significant role in reducing noise at the second frequency, but it significantly increases the complexity of the circuit in the process of generating a DRAG pulse, which is a high-frequency signal with a 90° phase difference and a derivative pulse shape.

[0009] In addition, the DRAG pulse is originally used like a main pulse, and it functions to give the characteristic that the frequency power is reduced on the left side of the center frequency and increased on the right side based on the center frequency. One of the other conventional techniques that overcomes the shortcomings of the DRAG pulse by utilizing this characteristic is to control the frequency and phase through a single side band (SSB) synthesis method, and in the process, use a memory to create a pulse shape that reduces noise at a second frequency located to the left of the center frequency.

[0010] However, the conventional method described above requires a high digital system frequency, for example, a frequency of 1 GHz or higher, due to the characteristics of qubits, and must have a high resolution, so there is a problem that the number of required bits increases. In particular, memory is absolutely necessary to create a Gaussian pulse shape and a pulse shape of a DRAG pulse that is differentiated from it, and since all qubits have unique frequency characteristics and cannot share memory, a lot of memory is required to store values ​​for each qubit.

[0011] Specifically, the problem with the aforementioned prior art lies in the fact that the DRAG pulse differs in phase and shape from the main control signal. Therefore, in order to control the frequency and phase through the SSB method using the local oscillator (LO) frequency and the intermediate frequency (IF), the shape of the DRAG pulse is generated by multiplying the amplitude of the main control signal stored in the memory when creating the intermediate frequency.

[0012] That is, when using the above method, the qubit has a basis energy (ω 01 ) and the first state energy (ω 12 ) have different frequencies, so the main pulse and DRAG signals must be stored using different memories. In addition, high signal quality requires a high clock sampling rate and a high DAC (digital analog convertor) bit resolution, which requires a very large memory capacity.

[0013] Furthermore, the conventional qubit generation method described above may not pose a significant problem when the number of qubits is small. However, practical superconducting quantum computers require thousands or tens of thousands of qubits, and controlling them all would require thousands or tens of thousands of RF cables connected to cryogenic or cooling devices, which is practically impossible.

[0014] In other words, the qubit control circuit must operate at low power to maintain the ultra-low temperature of 4K within the cryostat. Furthermore, as the number of qubits increases, more memory is required to generate the corresponding number of DRAG pulses. This increases the number of memory transfer lines and the power required for memory operation, making scalability in the 4K range difficult.

[0015] Thus, the existing qubit control signal generation method that uses memory to store data and generate DRAG pulses is not suitable for practical use of quantum computers, and therefore, a new qubit control signal generation method is required to effectively control quantum computers.

[0016] The present invention has been derived to meet the needs of the prior art as described above, and the purpose of the present invention is to provide a qubit control signal generation device for controlling a superconducting quantum computer, which can generate a main pulse of radio frequency and a DRAG (derivative removal by adiabatic gate) pulse having a shape differentiated therefrom at low power without memory.

[0017] Another object of the present invention is to provide a method and device for generating a qubit control signal for controlling a superconducting quantum computer, which can generate a sine shape pulse and a raised cosine shape pulse, i.e., a main pulse, without using a memory, i.e., without an additional part for amplitude change, and in a similar manner, can generate a DRAG pulse for a sine pulse shape or a raised cosine pulse shape at low power without using a memory.

[0018] According to one aspect of the present invention for solving the above technical problem, a method for generating a qubit control signal for controlling a quantum computer includes the steps of: generating a first sine curve having a first phase obtained by multiplying an angular velocity obtained by adding a first angular velocity of a center frequency to a second angular velocity of a second frequency located to the left of the center frequency by an arbitrary time of each cycle; and generating a second sine curve having a second phase obtained by multiplying an angular velocity obtained by subtracting the second angular velocity from the first angular velocity by the arbitrary time. A DRAG (derivative removal by adiabatic gate) pulse for a qubit control signal can be generated through an operation of adding the first sine curve and the second sine curve.

[0019] The method for generating the qubit control signal further includes the steps of generating a third sine curve having a third phase obtained by multiplying the angular velocity obtained by adding the first angular velocity and the second angular velocity by the arbitrary time; and the step of generating a fourth sine curve having a fourth phase obtained by multiplying the angular velocity obtained by subtracting the second angular velocity from the first angular velocity by the arbitrary time. A main pulse of the qubit control signal can be generated through an operation of subtracting the fourth sine curve from the third sine curve.

[0020] The above qubit control signal generation method may further include a step of setting the current bias of the first sine curve and the second sine curve so that the DRAG pulse is multiplied by a scale factor.

[0021] The above scale factor can be any real value selected from 0 or more and less than 1.

[0022] The above qubit control signal generation method may further include a step of synthesizing the first to fourth sine curves to generate a qubit control pulse synthesized from the main pulse and the DRAG pulse.

[0023] The above qubit control signal generation method may further include a step of converting the qubit control pulse into a radio frequency output signal in addition to the main frequency of the phase-locked circuit according to a plurality of phase signals of the phase-locked circuit applied to the mixer.

[0024] The above qubit control signal generation method may further include a step of specifying an initial phase for generation of each of the first sine curve, the second sine curve, the third sine curve, and the fourth sine curve.

[0025] Each of the steps of generating the first sine curve, the second sine curve, the third sine curve, and the fourth sine curve may include: a step of repeatedly accumulating a frequency codeword (FCW) within a range from 0 to a preset upper limit from a predetermined initial phase; a step of inverting even-numbered rising cycles of the repeated accumulated values ​​obtained in the accumulating step to convert the accumulated values ​​into a triangle wave shape or a sine wave shape; a step of converting a certain upper bit of the accumulated values ​​converted into a sine wave shape into a first analog signal; a step of converting a certain lower bit of the accumulated values ​​converted into a sine wave shape into a second analog signal; and a step of interpolating the first analog signal by adding the second analog signal to the first analog signal.

[0026] The above qubit control signal generation method may further include a step of aligning the processing timing of data or signals input to each of the four controllers by four clock calculators coupled to the four controllers, each of which supplies a phase signal and a frequency codeword (FCW) for determining an initial phase of each of the first to fourth phases to generate the first sine curve, the second sine curve, the third sine curve, and the fourth sine curve, respectively.

[0027] The above qubit control signal generation method may further include a step of dividing a reference clock supplied from an external source of a qubit control signal generation device into n (n is 8 or 16) sub-clocks and transmitting some of them to each of the four clock calculators.

[0028] The above qubit control signal generation method may further include: a step of determining a first main frequency according to the reference clock, and generating a first phase signal and a first clock signal based on the first main frequency; a step of determining a second main frequency different from the first main frequency according to the reference clock, and generating a second phase signal and a second clock signal based on the second main frequency; and a step of selecting one of the first phase signal and the second phase signal and providing the selected one to first to fourth frequency generators that generate the first sine curve, the second sine curve, the third sine curve, and the fourth sine curve, respectively.

[0029] The above qubit control signal generation method may further include a step of distributing data signals and control signals input from the outside of the dilution refrigeration device and supplying them to the four controllers by a main controller connected to the four controllers.

[0030] According to an aspect of the present invention for solving the above technical problem, a qubit control signal generating device for controlling a quantum computer includes: a first frequency generator for generating a first sine curve having a first phase obtained by multiplying an angular velocity obtained by adding a first angular velocity of a center frequency to a second angular velocity of a second frequency located to the left of the center frequency by an arbitrary time of each cycle; and a second frequency generator for generating a second sine curve having a second phase obtained by multiplying an angular velocity obtained by subtracting the second angular velocity from the first angular velocity by the arbitrary time. A DRAG (derivative removal by adiabatic gate) pulse for a qubit control signal can be generated through a process of adding the first sine curve and the second sine curve.

[0031] The qubit control signal generating device may further include a third frequency generator that generates a third sine curve having a third phase obtained by multiplying an angular velocity obtained by adding the first angular velocity and the second angular velocity by the arbitrary time; and a fourth frequency generator that generates a fourth sine curve having a fourth phase obtained by multiplying an angular velocity obtained by subtracting the second angular velocity from the first angular velocity by the arbitrary time. A main pulse for the qubit control signal may be generated through a process of subtracting the fourth sine curve from the third sine curve.

[0032] The above qubit control signal generating device can generate a qubit control pulse synthesized from the first to fourth sine curves by performing an operation of subtracting the fourth sine curve from the third sine curve and an operation of adding the first sine curve and the second sine curve, in order to generate a qubit control pulse synthesized from the main pulse corresponding to the first term of the right side of Equation 3 and the DRAG pulse corresponding to the second term of the right side.

[0033] The above qubit control signal generating device may further include a mixer that converts the qubit control pulse into a radio frequency output signal in addition to the main frequency of the phase-locked circuit according to a plurality of phase signals of the phase-locked circuit.

[0034] The third frequency generator and the fourth frequency generator may each have third and fourth current biases that supply power at a reference level for operation of the third frequency generator and operation of the fourth frequency generator, respectively.

[0035] The first frequency generator and the second frequency generator may each have first and second current biases that supply a power level that is a scale factor multiplied by the reference level for operation of the first frequency generator and operation of the second frequency generator, respectively.

[0036] Each of the first to fourth frequency generators may include: a controller that outputs a frequency codeword (FCW), a phase signal specifying an initial phase, and an enable signal; a repetitive phase accumulator that repeatedly accumulates the frequency codeword in a range from 0 to a preset upper limit from an initial phase determined by the phase signal; a waveform converter that inverts even rising cycles of the repetitive accumulated values ​​obtained from the repetitive phase accumulator to convert the repetitive accumulated values ​​into a triangle wave shape or a sine wave shape; a nonlinear differential digital analog convertor (DAC) that converts a certain upper bit of the accumulated values ​​converted into a sine wave shape into a first analog signal; an interpolation DAC that converts a certain lower bit of the accumulated values ​​converted into a sine wave shape into a second analog signal; and an addition circuit that interpolates the first analog signal by adding the second analog signal to the first analog signal.

[0037] Each of the first to fourth frequency generators may further include a clock calculator that matches the processing timing of a data signal or control signal input to the controller.

[0038] The qubit control signal generating device may further include a first phase-locked circuit that determines a first main frequency according to a reference clock and generates a first phase signal and a first clock signal based on the first main frequency; a second phase-locked circuit that determines a second main frequency different from the first main frequency according to the reference clock and generates a second phase signal and a second clock signal based on the second main frequency; a clock selector that selects one of the first phase signal and the second phase signal and provides the selected one to first to fourth frequency generators; and a main controller that is connected to four controllers of the first to fourth frequency generators and distributes data signals and control signals input from the outside of the dilution refrigeration device and supplies the data signals and control signals to the four controllers.

[0039] According to the present invention, the main pulse and the drag (DRAG: derivative removal by adiabatic gate) pulse of the qubit control signal for controlling a superconducting quantum computer can be generated at low power without memory, thereby contributing to the increase in qubits for practical use of quantum computers.

[0040] In addition, according to the present invention, a drag signal generation device can be provided that can efficiently operate a control circuit of a quantum computer with low power without using memory, and has scalable characteristics in an ultra-low temperature range of 4K.

[0041] In addition, according to the present invention, a method and device for generating a qubit control signal that can be effectively expanded as the number of qubits increases can be provided.

[0042] Figure 1 is a schematic diagram of a circuit and energy levels of a transmon qubit, a type of superconducting qubit.

[0043] Figure 2 is a graph illustrating the degree of spread of the frequency spectrum according to the type of main pulse that can be used for the qubit control pulse.

[0044] Figure 3 is a graph illustrating the extent to which the frequency spectrum spreads when the main pulse shape is fixed to a sine shape and the pulse length is changed.

[0045] Figure 4 is a graph illustrating how the frequency spectrum distribution changes when using a main pulse and a drag (DRAG: derivative removal by adiabatic gate) pulse.

[0046] FIG. 5 is a graph illustrating the main features of a low-power qubit control signal generation method for controlling a superconducting quantum computer according to an embodiment of the present invention.

[0047] FIG. 6 is a circuit diagram of a qubit control signal generation device for controlling a superconducting quantum computer according to the first embodiment of the present invention.

[0048] FIG. 7 is a circuit diagram of a qubit control signal generation device for controlling a superconducting quantum computer according to a second embodiment of the present invention.

[0049] FIG. 8 is a circuit diagram of a qubit control signal generation device for controlling a superconducting quantum computer according to a third embodiment of the present invention.

[0050] FIG. 9 is a circuit diagram of a qubit control signal generation device for controlling a superconducting quantum computer according to the fourth embodiment of the present invention.

[0051] FIG. 10 is a block diagram for explaining a component that divides a digital code into 4-bit MSB and 4-bit LSB in the frequency generator of the qubit control signal generation device of FIG. 9.

[0052] Figures 11 to 13 are exemplary diagrams for explaining the digital code processing process of the frequency generator of Figure 10.

[0053] Fig. 14 is a block diagram for explaining a component for nonlinear processing and interpolation in the frequency generator of the qubit control signal generation device of Fig. 9.

[0054] Fig. 15 is a circuit diagram of a detailed structure that can be employed in a component for nonlinear processing and interpolation in the frequency generator of the qubit control signal generation device of Fig. 9.

[0055] Fig. 16 is a graph for explaining the nonlinear sine mapping process by the interpolation DAC (digital analog convertor) of the frequency generator of Fig. 15.

[0056] Fig. 17 is a graph showing a 5.56 GHz 5 ns sine shape pulse measured at 4K using a chip implementing the qubit control signal generation device of Fig. 9.

[0057] Fig. 18 is a graph showing a 5.56㎓ 10㎱ sine shape pulse generated using an intermediate frequency of ±50㎒ in the sine shape pulse of Fig. 17.

[0058] Fig. 19 is a graph showing the result of generating a signal having multiple frequency components simultaneously as frequency signals at 20 MHz intervals by generating independent frequency and phase signals from each of the four frequency generators of the qubit control signal generation device of Fig. 9.

[0059] Fig. 20 is a graph showing the result of generating a signal having multiple frequency components simultaneously as frequency signals at 100 MHz intervals by generating independent frequency and phase signals from each of the four frequency generators of the qubit control signal generation device of Fig. 9.

[0060] Figures 21 to 23 show the qubit control signal generation device of Figure 9 operating in the 4K region, setting the frequency and phase to match the desired DRAG pulse in four frequency generators, and the scale factor (q). scale ) are graphs showing the results of measuring the change in the distribution of the frequency spectrum.

[0061] Fig. 24 shows a microscopic photograph of a chip implementing a qubit control signal generation device according to the present embodiment.

[0062] Fig. 25 is an enlarged microscopic photograph of the frequency generator portion of the qubit control signal generation device of Fig. 24.

[0063] The present invention is susceptible to various modifications and embodiments. Specific embodiments are illustrated and described in detail in the drawings. However, this is not intended to limit the present invention to specific embodiments, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present invention.

[0064] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0065] In the embodiments of the present application, 'at least one of A and B' may mean 'at least one of A or B' or 'at least one of combinations of one or more of A and B'. Furthermore, in the embodiments of the present application, 'at least one of A and B' may mean 'at least one of A or B' or 'at least one of combinations of one or more of A and B'.

[0066] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components in between.

[0067] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprises" or "has" are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0068] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0069] Hereinafter, with reference to the attached drawings, preferred embodiments of the present invention will be described in more detail. In order to facilitate an overall understanding in describing the present invention, identical reference numerals will be used for identical components in the drawings, and redundant descriptions of identical components will be omitted.

[0070] Figure 1 is a schematic diagram of a circuit and energy levels of a transmon qubit, a type of superconducting qubit.

[0071] Referring to Fig. 1, a transmon qubit can be expressed in the form of an isolated superconducting island region consisting of a capacitance and a Josephson junction inductance (indicated by X) between two nodes or two conductors, as shown in the circuit schematic diagram (10). The number of Cooper pairs existing in the superconducting island region, i.e., the amount of charge, can correspond to one of specific energy levels (|0>, |1>, |2>) on a curve (12) representing the potential energy of the qubit. The Josephson junction acts as a valve that supplies Cooper pairs to the superconducting island region.

[0072] The energy levels of the transmon qubit have a shape that spreads out from the center to both sides of the curve as the energy level increases due to the nonlinear characteristics of the Josephson junction, unlike the curve shape of a quadratic function. Accordingly, as the energy level increases, the gap between the energy levels narrows. According to this characteristic, the energy of the ground state (E0), the energy of the first excited state (E1), and the energy of the second excited state (E2) can be clearly distinguished, so the energy level of the ground state (|0>) and the energy level of the first excited state (|1>) can be used as qubits in a quantum computer.

[0073] When a transmon qubit is in a simple harmonic atmosphere, the energy level (ω) for going from the first excited state to the second excited state 12 ) is the energy level (ω) for going from the ground state to the first excited state. 01 ) can be expressed in the form of adding a certain energy (α). Here, the certain energy is the energy level of the first excited state (ω 12 ) when representing the qubit frequency (ω0 or f 01 ) may correspond to an anharmonicity value added to it.

[0074] The qubit frequency (f) is a radio frequency (RF) 01 ) can be used for rotation control of the qubit, and the rotation angle (θ) of the qubit can be controlled with the RF pulse energy of the qubit frequency, and the rotation state of the rotation axis (φ) of the qubit can be controlled with the RF phase of the qubit frequency.

[0075] Qubit frequency (f 01 ) is 5 to 7 GHz, and the second frequency (f) located to the left of the qubit frequency 12) can be 150 to 350 MHz. The second frequency (f 12 ) is the frequency at which the corresponding power is to be reduced in the qubit control pulse. The coherence time between the qubit frequency and the second frequency with respect to the qubit control signal is typically less than 100 μs. In the following description, the qubit frequency is also referred to as the center frequency for brevity.

[0076] The aforementioned qubits have different characteristics depending on the type of qubit, and the energy (ω) to go to the first excited state 01 ) (hereinafter referred to as 'base energy') and the energy (ω) for going from the first excited state to the second excited state. 12 ) (hereinafter referred to as the 'first state energy') are also all different. Therefore, the RF signals for controlling the qubits can all have different amplitudes, lengths, shapes, phases, and frequencies.

[0077] Fig. 2 is a graph illustrating the degree of spread of the power spectrum according to the type of main pulse that can be used for the qubit control pulse. Fig. 3 is a graph illustrating the degree of spread of the power spectrum when the main pulse shape is fixed to a sine shape and the pulse length is changed. And Fig. 4 is a graph illustrating how the distribution of the power spectrum changes when the main pulse and the DRAG (derivative removal by adiabatic gate) pulse are used.

[0078] Referring to Fig. 2, the length or pulse width of the main pulse for qubit control can be approximately 30 ns in the case of a rectangular-shaped pulse. A rectangular-shaped pulse has a shape that is relatively widened to both sides from the center frequency, and this shape is a major factor in reducing single-gate fidelity in quantum computing.

[0079] That is, in the qubit control signal for a quantum computer, the second frequency (f 12 ) is usually the center frequency (f 01 ) is 150 to 350 MHz smaller than the qubit design. This may vary depending on the qubit design, but when controlling the qubit, the center frequency (f 01 ) is always located to the left of the second frequency (f 12 ) has the problem of reducing single-gate fidelity due to spectral leakage exceeding a certain standard.

[0080] Meanwhile, it can be seen that each of the Gaussian, raised-cosine, and sine-shaped pulses that can be generated by pulse shaping from a rectangular-shaped pulse produces a relatively smaller spread than the rectangular-shaped pulse. That is, the second frequency (f) of each pulse 12 ) can be confirmed that the power spectrum leakage is reduced compared to the second frequency of the rectangular pulse.

[0081] In addition, as shown in Fig. 3, when the pulse shape is fixed to a sine-shaped shape and the pulse length is changed, that is, when a pulse with a reduced pulse width is generated to have a pulse length more suitable for qubit control, it can be seen that as the pulse length becomes shorter, the degree of spreading of the power spectrum on both sides of the center frequency becomes more severe. This means that as the pulse length becomes shorter, the second frequency (f 12 ) requires more power, which increases noise at the second frequency, which may cause errors in qubit operation.

[0082] In the current research on quantum computers, the DRAG (derivative removal by adiabatic gate) pulse, as shown in Fig. 4, is used considering the conditions mentioned above. Fig. 4 shows the power spectrum distribution when the DRAG pulse is added to a sine-shaped main pulse with a length of 10 ns. That is, the DRAG pulse is added to the sine-shaped pulse, and the scale factor (q) of the DRAG pulse is scale ) can be varied from 0.0 to 0.4 to check the distribution of the frequency spectrum. In this way, it can be seen that using the DRAG pulse can reduce the power at the second frequency.

[0083] That is, when using DRAG pulse, the center frequency (f 01 ) can create a pulse shape in which the left part of the energy or power decreases and the right part increases. The second frequency (f 12 ) is the center frequency (f 01 ), the power of the second frequency part can be reduced by using the DRAG pulse, and the second frequency with the largest reduction can be set differently depending on the scale factor. This is due to the center frequency (f ) that varies depending on the design of the qubit. 01 ) and the second frequency (f 12 ) can be used to maximize the effect by using an appropriate scale factor depending on the difference value. By adding the DRAG pulse described above, asymmetry of the frequency spectrum can be induced, and a second frequency (f 12 ) can reduce leakage.

[0084] The aforementioned main pulse is a radio frequency signal for qubit control and may have a sine-shaped or cosine-shaped shape. The DRAG pulse has a shape that is a derivative of the shape of the main pulse and may have a phase difference of 90° from the phase of the main pulse. The DRAG pulse has a scale factor (q) of the main pulse. scale ) has a multiplied shape. The scale factor is a value related to the qubit characteristics, and is the energy of the second excited state (ω 12 )(second state energy) of the first excited state (ω 01 )(first state energy) can be expressed as energy minus or its equivalent value.

[0085] Additionally, the frequency of the main pulse of the qubit control signal is typically designed to be 5 to 7 GHz, and each qubit control signal can have a different unique frequency within the range of tens to hundreds of megahertz (MHz). In addition to frequency, the phase of the RF signal is also an important factor in qubit control.

[0086] Therefore, in order to effectively generate qubit control signals, the single side band (SSB) method is usually used. The SSB method is a method of creating an LO+IF frequency or LO-IF frequency signal by combining a relatively low intermediate frequency (IF) signal of several hundred MHz with a local oscillator (LO) signal of several GHz. Using this, multiple qubit control RF signals can be created by adding or subtracting a relatively low intermediate frequency (IF) to or from a relatively high local oscillator (LO) frequency, while also freely changing the phase.

[0087] However, in the qubit control signal generation method of the comparative example described above, a linear digital-to-analog converter (linear DAC) must be used to generate an IF signal. That is, sine wave data must be passed to the linear DAC to generate an intermediate frequency (IF) signal. In particular, generating a high-resolution IF signal of several hundred MHz requires a relatively large amount of data, which leads to the need for larger memory. Moreover, the larger the memory, the more power consumed.

[0088] Furthermore, to generate a DRAG pulse, the pulse shape must be freely created. For example, a Gaussian shape and its derivative are each stored by multiplying by the IF signal transmitted to the DAC. Since each qubit has a different frequency, the memory required for this cannot be shared. Therefore, to generate a DRAG pulse, memory is required to separately generate and store the main pulse and the DRAG pulse, and since this cannot be shared with other qubits, more memory is required as the number of qubits increases.

[0089] Accordingly, in this embodiment, a method for generating a main pulse and a DRAG pulse without using memory is proposed to solve the problem of a significant increase in the required memory capacity as the number of qubits increases to tens, hundreds, thousands, or tens of thousands or more.

[0090] FIG. 5 is a graph illustrating the main features of a low-power qubit control signal generation method for controlling a superconducting quantum computer according to an embodiment of the present invention.

[0091] Referring to FIG. 5, a qubit control signal generation method is configured to generate a main pulse and a DRAG pulse using a sine-shaped pulse and a rising cosine-shaped pulse without using a square-shaped pulse.

[0092] In the unit pulse shape of the qubit control signal, the sine shape or the raised cosine shape has similar properties to the Gaussian shape, but has a slight difference in frequency spread. Therefore, in this embodiment, a desired RF pulse is generated by using trigonometric synthesis for the sine shape and the raised cosine shape. For example, by adding or subtracting an intermediate frequency (IF) from the main frequency corresponding to the local generator (LO) frequency, a signal (hereinafter referred to as the "third signal") obtained by multiplying the main frequency and the intermediate frequency can be obtained. At this time, if the third signal can be appropriately processed, an RF pulse having a sine shape can be arbitrarily generated.

[0093] To be more specific, since the intermediate frequency (IF) signal determines the frequency of the main pulse of the sine shape, the pulse width of the main pulse can be adjusted by changing the frequency of the IF signal, and the phase of the main frequency signal can be changed by changing the phase of the two signals generated. In addition, a raised cosine signal can be generated by adding a rectangular pulse of the main frequency to a sine signal. Using this method, the main pulse can be generated using two sine-shaped frequency signals without additional circuitry or memory.

[0094] Moreover, the sine shape and the raised cosine shape have the cosine shape and the sine shape respectively as their derivative values. This means that the DRAG pulse can be generated in the same way as the main pulse is generated. That is, since the DRAG pulse has a phase difference of 90° from the main pulse, the phases of the two frequency signals can be appropriately controlled to generate the DRAG pulse corresponding to the main pulse. In addition, the amplitude or shape of each frequency signal generated can be adjusted by multiplying the scale factor.

[0095] In this way, in this embodiment, the main pulse and the DRAG pulse for qubit control without memory can be generated using only sine-shaped pulses and / or cosine-shaped pulses.

[0096] The aforementioned main pulse (main pulse, 20) can be expressed as in the following mathematical expression 1.

[0097]

[0098] In mathematical equation 1, is the main pulse of sine shape at time (t), Each represents an on-time pulse of the circuit for frequency generation.

[0099] As shown in mathematical expression 1, the main pulse of the sine shape can be expressed in the form of a product of a sine function and a rising cosine function. Furthermore, by expanding the sine function formula, the main pulse (20) of the sine shape can be synthesized by subtracting two sine curves. In trigonometric functions, the subtraction operation can correspond to the operation of flipping a sine curve by 180 degrees and adding it.

[0100] Similar to the generation process of the main pulse above, the DRAG pulse (22) can be expressed as in the following mathematical expression 2.

[0101]

[0102] In mathematical expression 2, is the DRAG pulse at time (t), q scale is the scale factor, Each represents an on-time pulse of the circuit for frequency generation.

[0103] As shown in mathematical expression 2, the DRAG pulse having a phase difference of 90 degrees from the main pulse can be expressed in the form of a product of a scale factor and a cosine function and a sine function. Here, the cosine function corresponds to the differentiation of the sine function of the main function, and the sine function corresponds to the differentiation of the cosine function of the main function. In addition, when expanded using the sine function formula, the cosine function and the product of the sine function of the DRAG pulse can be expressed in a form synthesized by adding two sine curves. In other words, the DRAG pulse having a rising cosine shape can be generated in a form synthesized by adding two sine curves.

[0104] Using the aforementioned main pulse and DRAG pulse, the qubit control pulse ( ) can be expressed as in the following mathematical expression 3. The qubit control pulse can also be referred to as a qubit-driving pulse.

[0105]

[0106] In mathematical formula 3 is a qubit control pulse, is the on-time pulse of the circuit for frequency generation, q scale is the scale factor, is the phase angle at any time (t) of the qubit basis state, Each represents the phase angle of the qubit at any time (t).

[0107] As shown in Equation 3, a qubit control pulse can be simply synthesized by adding four sine curves. Two of the four sine curves are used to generate a main pulse, and the remaining two are used to generate a DRAG pulse. Thus, according to the present embodiment, a main pulse and a DRAG pulse for qubit control can be generated without memory.

[0108] The qubit control pulses generated using the four sine curves described above can be used to control ultra-low-temperature quantum computers. That is, they can effectively generate qubit control pulses for quantum computers operating in the ultra-low-temperature environment of a dilution refrigerator or in the 4K region (stage).

[0109] FIG. 6 is a circuit diagram of a qubit control signal generation device for controlling a superconducting quantum computer according to the first embodiment of the present invention.

[0110] Referring to FIG. 6, the qubit control signal generation device includes at least one driver (100) to generate a qubit control signal, and each driver (100) may include first to fourth frequency generators (310, 320, 330, 340), a waveform shaping circuit (350), a mixer (370), and an output terminal (390). The frequency generator may be referred to as a frequency generation block.

[0111] Each frequency generator may include a controller, a clock calculator, a rotational phase accumulator, a triangular transform unit, a current bias, a non-linear differential digital-to-analog converter (DAC), an interpolating DAC, and a synthesis unit. The detailed configuration of the aforementioned frequency generator will be described in detail in the description with reference to FIG. 9.

[0112] Among the first to fourth frequency generators (310, 320, 330, 340), two frequency generators may be used to generate two sine functions for the main pulse, respectively, and the remaining two frequency generators may be used to generate two sine functions for the DRAG pulse, respectively.

[0113] That is, if the four sine functions are appropriately synthesized as shown in the mathematical expression 3 above, in other words, two of the four sine functions can be operated according to the subtraction operation of the trigonometric function to form the main pulse portion, and the remaining two sine functions can be processed according to the addition operation of the trigonometric function while applying a preset scale factor to form the DRAG pulse portion. In this way, according to the present embodiment, a qubit control pulse can be simply generated by synthesizing four sine curves.

[0114] Qubit control pulses generated from each of the four frequency generators (310, 320, 330, 340) can be combined into a rising cosine shape by a waveform shaping circuit (350) and combined with an intermediate frequency by a mixer (370) to be output as a single RF signal.

[0115] Here, the mixer (370) can be configured to output an RF signal having a frequency that combines a relatively fast second frequency pulse with a relatively slow first frequency pulse through an output circuit (390) through a plurality of pairs of switches that are turned on / off by control signals having a Q component (Q) of the main frequency, which is the LO (local oscilator) frequency, an inverted component (Qb) of the Q component, and an I component (I) of the main frequency, and an inverted component (Ib) of the I component.

[0116] The output circuit (390) may have a structure of an insulated converter and may be configured to output an RF signal based on an internal power supply voltage (VDD). The RF signal (RF out) output through the output circuit (390) may have a form in which a plurality of qubit control pulses or tones are listed according to a frequency (read frequency) used for qubit readout, a predetermined digital clock, and pulse spacing of the DAC. Here, the read frequency may be 8 GHz, the digital clock may be 2 GHz, and the pulse spacing of the DAC may be several tens of MHz. The read frequency may be different from the frequency used for qubit control or qubit write.

[0117] In the present embodiment, the frequency generators (310, 320, 330, 340), the waveform shaping circuit (350), and the mixer (370) of the qubit control signal generation device may receive a data signal, a first control signal, and a second control signal through a plurality of cables connected to the outside of the refrigeration device. A portion (E1) of the data signal and the first control signal may include a frequency codeword (FCW), a clock (CLK), an enable (EN) signal, and the like, and the remaining portion (E2) of the data signal and the first control signal may include a reference signal, a clock signal, a phase signal, and the like. The reference signal or the clock signal may be referred to as a reference clock. In addition, the second control signal transmitted to the waveform shaping circuit (350) may include two main control signals (mc1, mc2).

[0118] Here, the frequency codeword (FCW) is composed of digital bits, and some of the bits are used to control the digital preprocessing unit for generating the main pulse in the frequency generator, and the remaining bits can be used to control the analog processing unit for generating the DRAG pulse in the frequency generator. The clock can have the same frequency as the data signal for synchronous processing of the data signal composed of digital bits. The enable signal can be used to determine the on / off or active / inactive state of each component such as the controller, the iterative phase accumulator, etc. The reference clock is for operating the phase-locked circuit, and can be a clock that is much faster and cleaner than the clock having the same frequency as the data signal. The phase signal can be used to specify the initial phase position of the iterative phase accumulator and can be used to control the operation of the switch pairs in the mixer (370). In addition, the main control signals (mc1, mc2) can be used to control the operation of the waveform shaping circuit (350).

[0119] The clock signal of the above-mentioned reference clock may include a 1 / 8 clock obtained by dividing the main clock into 8 parts or a 1 / 16 clock obtained by dividing the main clock into 16 parts, and such clock signal may be applied to each of the frequency generators (310, 320, 330, 340). In addition, the above-mentioned phase signal may include four signals of 1 / 2 phase obtained by dividing the main phase determined by the reference clock into 2 parts. Such phase signal may be applied to the control terminal of each switch of the four switch pairs of the mixer (370) as an in-phase signal, a quadrature-phase signal, an in-phase inverted signal, and a quadrature-phase inverted signal.

[0120] Meanwhile, in order to individually transmit data signals and control signals to the qubit control signal generating device from outside the cryostat or refrigeration device while the qubit control signal generating device is installed inside the cryostat or refrigeration device and has multiple drivers (100) each having four frequency generators, each signal must be transmitted through multiple cables, the number of which is 16 times the number of drivers. Therefore, in order to avoid using such multiple cables, a main controller may be installed and used in the qubit control signal generating device.

[0121] FIG. 7 is a circuit diagram of a qubit control signal generation device for controlling a superconducting quantum computer according to a second embodiment of the present invention.

[0122] Referring to FIG. 7, the qubit control signal generation device may include a main controller (60) and at least one driver (100). The driver (100) may include four frequency generators (310, 320, 330, 340), a waveform shaping circuit (350), a mixer (370), and an output circuit (390), as described above with reference to FIG. 6.

[0123] By using the main controller (60), data signals and control signals received from an external source can be copied and individually provided to four frequency generators (310, 320, 330, 340) included in at least one driver (100), so that direct cable connection between an external computing device and each frequency generation block can be omitted.

[0124] By using the main controller (60), the operation of the waveform shaping circuit (350) having a variable capacitor and a variable switch connected in parallel between four frequency generators (310, 320, 330, 340) and the mixer (370) can be controlled through the self-generated main control signal (mc1, mc2). In addition, by using the waveform shaping circuit (350), the signals that are respectively combined into two pairs among the four frequency generators (310, 320, 330, 340) and transmitted to the mixer (370) can be selectively shaped into a raised cosine shape and transmitted.

[0125] Meanwhile, clock signals divided into 1 / 8 or 1 / 16 are applied to four frequency generators (310, 320, 330, 340) of each driver (100), and a plurality of phase signals, i.e., four phase signals of half phase (1 / 2 phase), are applied to the mixer (370). The number of these clock signals and phase signals increases as the number of qubits increases, and therefore, when the number of qubits is more than a predetermined number, the second frequency (f) located to the left of the center frequency of the qubit control signal 12 ) causes power to be concentrated, which generates a large amount of noise at the second frequency. To prevent qubit control errors caused by such noise generation, in the present embodiment, multiple phase-locked circuits can be installed in the qubit control signal generation device.

[0126] FIG. 8 is a circuit diagram of a qubit control signal generation device for controlling a superconducting quantum computer according to a third embodiment of the present invention.

[0127] Referring to FIG. 8, the qubit control signal generation device may include a main controller (60), a first phase-locked circuit (PLL1, 70), a second phase-locked circuit (PLL2, 80), a clock selector (clock selector, 90), and at least one driver (driver, 100). Each driver (100) may include four frequency generators (310, 320, 330, 340), a waveform shaping circuit (350), a mixer (370), and an output circuit (390), as described above with reference to FIG. 6.

[0128] The first phase-locked circuit (70) can generate a first output signal based on a reference signal. The first phase-locked circuit (70) controls the first output signal by using a phase difference between the reference signal and a signal fed back from the first output signal. The first phase-locked circuit (70) can adjust the frequency of the first output signal according to the reference signal. The frequency of the first output signal can include a first LO frequency for qubit control. The first LO frequency can be any one frequency selected from 10 GHz to 13 GHz and can be referred to as a first main frequency.

[0129] The second phase-locked circuit (80) can generate a second output signal based on a reference signal. The second phase-locked circuit (80) controls the second output signal by using the phase difference between the reference signal and a signal fed back from the second output signal. The second phase-locked circuit (80) can adjust the frequency of the second output signal according to the reference signal. The frequency of the second output signal can include a second LO frequency for qubit readout. The second LO frequency can be any one frequency selected from 14 GHz to 16 GHz and can be referred to as a second main frequency.

[0130] The first phase-locked circuit (70) may be configured to output, as a first output signal, a 1 / n clock of 1 / n main frequencies obtained by dividing the first main frequency into multiple (n) parts, rather than outputting the clock of the first main frequency as it is. In the present embodiment, a 1 / 8 clock of 1 / 8 main frequencies obtained by dividing the first main frequency into 8 parts may be output. Similarly, the second phase-locked circuit (80) may be configured to output, as a second output signal, a 1 / n clock of 1 / n frequencies obtained by dividing the second main frequency into multiple (n) parts, rather than outputting the clock of the second main frequency as it is. In the present embodiment, a 1 / 8 clock of 1 / 8 frequencies obtained by dividing the second main frequency into 8 parts may be output.

[0131] In addition, the first phase-locked circuit (70) may be configured to output, as another first output signal, a signal of 1 / n phase (1 / n phase) obtained by dividing the main phase into multiple (n) parts, rather than outputting the signal having the initial phase or main phase of the first main frequency as it is. In the present embodiment, the first phase-locked circuit (70) may output four signals of 1 / 2 phase (1 / 2 4-phase signals) as the phase signal. Similarly, the second phase-locked circuit (80) may be configured to output, as another second output signal, a signal of 1 / n phase (1 / n phase) obtained by dividing the main phase into multiple (n) parts, rather than outputting the signal having the initial phase or main phase of the second main frequency as it is. In the present embodiment, the second phase-locked circuit (80) may output four signals of 1 / 2 phase as the phase signal.

[0132] In this way, in the present embodiment, in order to prevent excessive power consumption and resulting large noise at a specific second frequency when producing the clock required for at least one driver (100), multiple phase-locked circuits may be used. The multiple phase-locked circuits may be configured to divide the entire frequency band to be supported by each driver into multiple parts, each responsible for its own operation.

[0133] The clock selector (90) may be configured to receive phase signals and clock signals from a plurality of phase-synchronous circuits, respectively, and to select one of the received phase signals and one of the clock signals and transmit them to each driver. For example, the clock selector may be configured to receive a first phase signal and a first clock signal from a first phase-synchronous circuit (70), receive a second phase signal and a second clock signal from a second phase-synchronous circuit (80), and then select and output one of the first and second phase signals and one of the first and second clock signals. This clock selector (90) may be configured to include a first switch for selecting one of the first clock signal and the second clock signal, and a second switch for selecting one of the first phase signal and the second phase signal.

[0134] By using the first phase-locked circuit (70), the second phase-locked circuit (80), and the clock selector (90), the operation timing or synchronous timing of the four frequency generators (310, 320, 330, 340) of each driver (100) can be effectively provided through the clock signal selected by the clock selector (90), and the operation of the mixer (370) can be controlled through the phase signal selected by the clock selector (90) to load a plurality of qubit control pulses at a preset read frequency and transmit them to the output circuit (390).

[0135] Meanwhile, although this embodiment exemplifies the use of two phase-locked circuits, the present invention is not limited to such a configuration, and may be configured to use three or more or dozens or more phase-locked circuits depending on the number of qubits.

[0136] FIG. 9 is a circuit diagram of a qubit control signal generating device for controlling a superconducting quantum computer according to another embodiment of the present invention. FIG. 10 is a block diagram for explaining a component that divides a digital code into a 4-bit MSB and a 4-bit LSB in the frequency generator of the qubit control signal generating device of FIG. 9. FIGS. 11 to 13 are exemplary diagrams for explaining a digital code processing process of the frequency generator of FIG. 10. In addition, FIG. 14 is a block diagram for explaining a component for nonlinear processing and interpolation in the frequency generator of the qubit control signal generating device of FIG. 9. FIG. 15 is a circuit diagram for a detailed structure that can be employed in the component for nonlinear processing and interpolation in the frequency generator of the qubit control signal generating device of FIG. 9. FIG. 16 is a graph for explaining a nonlinear sine mapping process by an interpolation DAC (digital analog convertor) of the frequency generator of FIG. 15.

[0137] Referring to FIG. 9, the qubit control signal generation device may include a main controller (60), a first phase-locked circuit (PLL1, 70), a second phase-locked circuit (PLL2, 80), a clock selector (90), and at least one driver (100).

[0138] A qubit control signal generation device may be installed inside a dilution refrigeration device. The qubit control signal generation device may be configured to receive only data signals transmitted to the main controller (60), control signals such as clock signals and enable signals, and reference signals transmitted to phase-locked circuits (70, 80) from a computing device, an external control device, an external measurement device, or a combination thereof located outside the dilution refrigeration device through four channels (E1) and one channel (E4).

[0139] The main controller (60) can store information for generating a qubit control pulse, such as a frequency codeword (FCW), a phase, a pulse width, a pulse shape, and single side band (SSB) selection information. All or part of this information may be preset by an external computing device or external management and control equipment, or may be input during the operation process. Of course, at least part of the information may be preset during the manufacturing of the qubit control signal generation device.

[0140] The main controller (60) can transmit data signals, reference signals, synchronization signals, and other control signals to the first phase-synchronous circuit (70), the second phase-synchronous circuit (80), and at least one driver (100). For example, the main controller (60) can copy at least some of the data signals and control signals received from the outside and transmit them to the first to fourth controllers (C1 to C4), the first phase-synchronous circuit (70), and the second phase-synchronous circuit (80), respectively.

[0141] Detailed descriptions of the main controller (60), the first phase-synchronous circuit (70), the second phase-synchronous circuit (80), and the clock selector (90) are replaced with the descriptions given above with reference to FIGS. 7 and 8.

[0142] The driver (100) may include a digital part and an analog part. The digital part may be referred to as a digital preprocessing unit, and the analog part may be referred to as an analog processing unit.

[0143] The digital part may include first to fourth controllers (C1 to C4), first to fourth clock calculators, first to fourth repeating phase accumulators (A1 to A4), and first to fourth waveform converters (T1 to T4). In addition, the analog part may include first to fourth current biases (B1 to B4), first to fourth nonlinear differential DACs (dDAC1 to dDAC4), first to fourth interpolating DACs (DAC1 to DAC4), an adding circuit (260), a waveform shaping circuit (350), a mixer (370), and an output circuit (390).

[0144] In the digital part, each of the first to fourth controllers (C1 to C4) may be briefly referred to as a controller (controller, 110). Each of the first to fourth clock calculators respectively coupled to each controller (110) may be briefly referred to as a clock calculator (CLK cal., 112). Each of the first to fourth repetition phase accumulators (A1 to A4) may be briefly referred to as a repetition phase accumulator (rotational phase accumulator, 120). And each of the first to fourth waveform converters (T1 to T4) may be briefly referred to as a waveform converter (triangular transform unit, 130).

[0145] In the analog part, each of the first to fourth current biases (B1 to B4) may be briefly referred to as a current bias (210). Each of the first to fourth nonlinear differential DACs (dDAC1 to dDAC4) may be briefly referred to as a nonlinear differential DAC (non-linear differential digital analog convertor, 230). And each of the first to fourth interpolating DACs (DAC1 to DAC4) may be briefly referred to as an interpolating DAC (250).

[0146] The qubit control signal generation device has independent frequency generators (frequency generation units) that generate four intermediate frequency signals, as mentioned in the mathematical expression 3 above, and each of the main pulse and DRAG pulse generated by the plurality of generated IF signals can be combined with a signal of a phase-locked circuit through a mixer (mixer, 370).

[0147] In this embodiment, the independent frequency generators may include first to fourth frequency generators (see 310, 320, 330, and 340 of FIGS. 6 to 8). Four intermediate frequency signals generated from the four frequency generators may be combined with a signal from a phase-locked circuit via a mixer (370). The signal from the phase-locked circuit may be a signal having a local osillator (LO) frequency and a fundamental phase, a signal having a 1 / n frequency obtained by dividing the LO frequency into multiple parts, or a signal having a 1 / n phase obtained by dividing the fundamental phase into multiple parts. The LO frequency may be referred to as a fundamental frequency.

[0148] To explain the frequency generation units in more detail, each frequency generation unit may be configured to include a controller (110), a clock calculator (112), a repeating phase accumulator (120), a waveform converter (T1, 130), a current bias (210), a nonlinear differential DAC (230), and an interpolation DAC (250), as shown in FIGS. 9, 10, and 14.

[0149] The controller (110) can receive data signals and control signals from the main controller (60), and based on these, transmit a frequency codeword (FCW), a phase signal, and an enable signal to the repeating phase accumulator (120). The controller (110) can hold information on the operation of the nonlinear waveform differential DAC, such as frequency codeword (FCW), phase, pulse width, pulse shape, and single side band (SSB) selection information, for the frequency generation operation of the corresponding frequency generator.

[0150] Here, FCW may be a frequency-related signal set or input from a user device, an external computing device, an external management and measurement device, etc. to determine the frequency generated from each frequency generator of the driver (100). FCW may include a value input by the user.

[0151] A phase signal is a signal used to determine the phase of a frequency generated by a frequency generator. The phase signal can be configured to specify the starting position of the phase of an FCW stored in a specific memory when generating an FCW by adding or accumulating FCW values ​​to that memory.

[0152] The enable signal is a signal for selecting the operation mode of on / off, enable and disable, active and inactive of a component or unit inside the driver (100). The enable signal may have a first signal level corresponding to on, enable or active, and a second signal level corresponding to off, disable or inactive. The first signal level may be a first level corresponding to 1, and the second signal level may be a second level corresponding to 0, or vice versa. This enable signal may be applied to the repeating phase accumulator (120), the current bias (210), and the nonlinear differential DAC (230).

[0153] Referring again to FIGS. 9 and 10, the clock calculator (CLK cal., 112) can function to synchronize the timing in data processing or signal processing in the controller (110) with the operations of other controllers. The clock calculator (112) can synchronize all clocks input to each controller to prevent clock delays from occurring in signal processing of each controller due to the physical arrangement relationship between the main controller (60) and each of the first to fourth controllers (C1 to C4), the length of the wiring connecting them, etc.

[0154] The repeating phase accumulator (120) receives an initial phase value (initial phase, ) is received, and then the initial phase value ( ) reads the frequency codeword (FCW) from the storage means and continuously adds and accumulates it.

[0155] For reference, FCW is an element that determines the frequency of a nonlinear waveform. The accumulation of FCW is repeated until the accumulated value reaches a certain upper limit. When the accumulated value reaches the upper limit, the iterative phase accumulator (120) can subtract the upper limit from the accumulated value and continue to accumulate FCW from the remaining value. In this way, the accumulated value can be accumulated by repeating the process of increasing only from 0 or a value close to it to the upper limit and then being reset. The accumulated value that is repeatedly increased only up to the upper limit can be referred to as a 'repeated accumulated value'. Here, the size of the repeated accumulated value is related to the phase of the pulse generated by the frequency generator, and the upper limit of the repeated accumulated value can correspond to 1 / 2 of the phase variation range of the generated pulse.

[0156] In this embodiment, the upper limit of the repeated accumulation value is π, and the repeated accumulation value can be set to repeat an increase from 0 to π. The phase of the [π, 2π] section corresponding to the remainder of one cycle of the sine wave can be obtained by a symmetry transform of the waveform converter (130) described below.

[0157] The waveform converter (triangular transform, T1, 130), as illustrated in FIG. 12, can receive the iterated accumulation value from the iterated phase accumulator (120) and perform a symmetrical transformation on a portion of the received iterated accumulation value. The symmetrical transformation can include an operation that inverts the iterated accumulation value at every interleaved period. In the present embodiment, the symmetrical transformation can be configured to leave the iterated accumulation value of odd rising periods as it is, and invert only the iterated accumulation value of even rising periods based on π, which is the midpoint between the maximum and minimum values. Accordingly, the symmetrical transformed value output by the waveform converter (130) in the even rising period of the iterated accumulation value shows a waveform that falls from π to 0. That is, the output signal of the iterated phase accumulator (120), which had an overall shape similar to a sawtooth wave, can have an overall waveform similar to a triangular wave through the symmetrical transformation.

[0158] In addition, the waveform converter (130), as illustrated in Fig. 13, can transfer the four bits located at the far left in the time flow from left to right among the digital code composed of the symmetrical transformation values, that is, the most significant bits (MSBs), to the nonlinear differential DAC (230) as a linear data signal to be converted into an analog signal. In addition, the waveform converter (130) can transfer the least significant bits of the symmetrical transformation values ​​as a residual data signal to the interpolating DAC (230).

[0159] In a digital preprocessing unit having the aforementioned controller (110), clock calculator (112), repeating phase accumulator (120) and waveform converter (130), an initial phase value () provided from the controller (110) to the repeating phase accumulator (120) ) may have a length of a predetermined number of bits, for example, 14 bits. In this case, the FCW transmitted from the controller (110) to the repeating phase accumulator (120) for each clock cycle and accumulated may have a smaller number of bits than the initial phase value. For example, each FCW may have a length of 13 bits or less.

[0160] Meanwhile, in order to simplify the configuration of the analog processing unit, in this embodiment, the iterative phase accumulator (120) may be configured to transmit only the upper 8 bits of the 14-bit iterative accumulation value to the waveform converter (130) and discard the lower 6 bits. Here, a certain number of bits used by the iterative phase accumulator (120) and the waveform converter (130) may be referred to as a 'valid input signal'. The specific number of bits mentioned above is exemplary and the present invention is not limited thereto.

[0161] In this embodiment, the extraction of the upper 4 bits of the valid input signal symmetrically transformed by the waveform converter (130) as a linear data signal for conversion into an analog signal can be viewed as a result of a type of quantization. In addition, the lower 4 bits of the valid input signal, i.e., the residual data signal, correspond to the difference between the valid input signal and the linear data signal, and can be viewed as representing the residue or error after quantization.

[0162] The following will describe the analog processing unit in detail with reference to FIGS. 9, 14, and 16.

[0163] First, the current bias (210) may have a circuit configuration including an on / off switch and a variable current source (also referred to as a first current source), as illustrated in FIGS. 9, 14, and 15. The current bias (210) may receive an enable signal for on / off control of the current bias unit from the controller (110) and a control signal of a predetermined bit for controlling the level of the variable current source. Here, the enable signal may be referred to as an on / off signal applied to the control terminal of the on / off switch, and the control signal may be an 8-bit signal. In addition, a current of a predetermined intensity output from the current bias (210) may be supplied as a current source of the nonlinear differential DAC (230).

[0164] The nonlinear differential DAC (230) may include a plurality of sub-converters connected in parallel, as illustrated in FIG. 15. The plurality of sub-converters operate to convert a digital code or binary code of a predetermined number of MSBs received from the waveform converter (130) into a thermometer code. The thermometer code may have a value or number expressed, for example, depending on the number of 1s in the digital code.

[0165] Additionally, a plurality of sub-converters may be configured to supply a replication current source to the interpolating DAC (250) in response to an enable signal of the controller (110). The enable signal may be referred to as an interpolating choice signal for selecting an interpolation operation mode of the interpolating DAC (250).

[0166] The aforementioned nonlinear differential DAC (230) may include multiple sub-converters in the form of differential circuits that separately calculate an in-phase signal (I-signal) and a quadrature-phase signal (Q-signal). Half of the multiple sub-converters may be in-phase DACs, and the remaining half may be quadrature-phase DACs. They may have the same configuration as the quadrature-phase DAC and the in-phase DAC, and may be arranged to form two pairs among the multiple sub-converters.

[0167] In a plurality of sub-converters, each sub-converter may have a first mirror, a second mirror, and a second current source. Here, the first mirror may receive a digital code of a predetermined number of MSBs from a waveform converter (130). In the present embodiment, the MSBs digital code may be 4 bits, and the thermometer code may be 16 bits. The second mirror may supply a current source to the interpolation DAC (250) according to an interpolation selection signal. In addition, the second current source may be configured with a transistor connected to the first current source, and may be configured to distribute a predetermined level of output current of the current source of the current bias (210) and determine a current level of each sub-converter according to the received level.

[0168] Additionally, each sub-converter may include 16 second current sources, each of whose gates is connected to the drains of the first current sources of the current bias through which the reference current flows. Each source of the 16 second current sources is connected to ground, and the drains are connected to the output terminal or the inverting output terminal through the first switch of the first mirror and the second switch of the second mirror.

[0169] The second current sources may correspond to constant current power sources capable of supplying currents corresponding to levels denoted as Δ1 to Δ16, respectively. The levels may be referred to as grayscales. The levels may correspond to incremental amplitudes of a sine wave for a one-step phase change of π / 16. In the present embodiment, this incremental amplitude may be different for each second current source. That is, although the first current source, which is the reference current source in FIGS. 15 and 16, and the 16 second current sources are connected in a form similar to current mirrors, the magnitude of the current supplied by all or at least some of the 16 second current sources may be different from that of the other current sources. For example, as can be inferred from the horizontal auxiliary line density in FIG. 13, the second current sources located near the middle may supply a larger current than the other four or so second current sources located at either end. Such operating characteristics can be implemented by mapping the current values ​​of each of the second current sources to a linear input and a nonlinear input at the design stage so that the nonlinear differential DAC (230) has the desired nonlinear characteristics, determining the current values ​​of each of the second current sources to match the nonlinear mapping results, and then varying the sizes of the transistors constituting the second current sources, for example, the aspect ratio of the channel.

[0170] The first terminal of the first switch described above may be connected to an output terminal of a nonlinear differential DAC (230), the second terminal may be connected to an inverting output terminal of the nonlinear differential DAC (230), and the common terminal may be connected to the first terminal of the second switch. In addition, the second terminal of the second switch may be connected to an input terminal of an interpolation DAC (250), and the common terminal may be connected to a drain of a second current source, respectively.

[0171] The interpolation DAC (250) comprises four pairs of transistors, each of which constitutes a pass transistor. The gate of each pair of transistors is supplied with a residual data signal, that is, one of the four lower bits (LSBs) of the valid input signal after symmetry transformation and its inverted value. In each pair of transistors, the first terminal of the transistor to which the valid input signal bit is supplied to the gate is connected to the inverting output terminal, and the first terminal of the remaining transistor is connected to the output terminal. The second terminal of each transistor forming the transistor pairs is connected to the output terminal of the interpolation DAC (250). In addition, the interpolation DAC (250) may be configured such that the second terminal of each transistor is connected to the source of each of the transistors of the second switch, the first terminal of each transistor is connected to the inverting output terminal, and the control terminal of each transistor is connected to a dummy transistor that applies a bias voltage (VDD).

[0172] In this way, each bit of the thermometer code for the upper 4 bits (MSBs) of the linear data signal, i.e., the valid input signal after symmetry transformation, is supplied as a switching control signal to the first switches of the nonlinear differential DAC (230). The switching of each of the first switches is controlled by the corresponding bit of the thermometer code. For example, when the thermometer code has a value of '0000000000000011', two second current sources supply current through the output terminal, 13 second current sources supply current through the inverting output terminal, and the remaining one second current source can supply current to the output terminal and the inverting output terminal through the interpolation DAC (250).

[0173] That is, the interpolation DAC (250) can perform non-linear sine mapping, as illustrated in FIG. 16. Non-linear sine mapping converts a digital code expressed as the sum of a non-linear MSB and a linearly interpolated LSB into analog through digital-to-analog conversion. For example, the interpolation DAC (250) can output an interpolation value through a pass transistor structure of four transistor pairs for the 4-bit LSBs received from the waveform converter (130). The output interpolation value can be added to the output value of the non-linear differential DAC (230). The interpolation operation by at least one interpolation value, as non-linear sine mapping, can be added to the MSB values ​​sequentially output from a plurality of sub-converters of the non-linear differential DAC (230) to partially fill in the gap between two MSB values ​​sequentially output from two adjacent sub-converters.

[0174] In other words, the interpolation DAC (230a) complements the output resolution of the nonlinear differential DAC (230) by interpolating the output current. For example, when generating the waveform illustrated in Fig. 16, assuming that only two secondary current sources are connected to the output terminals and that a current of Δ1+Δ2, which is the sum of the currents supplied by each secondary current source, flows, there will be a significant error between the amount of current that should be generated and the actual amount of current. At this time, if only the relevant section is considered, it is assumed that the change in the amount of current does not significantly deviate from the linear change trend over time, and interpolation can be performed as in the second term on the right side of the following mathematical expression 7.

[0175] The entire signals (output) output for nonlinear sine mapping in the interpolation DAC (250) can be expressed as a formula in the following mathematical formula 4.

[0176]

[0177] In mathematical expression 4, n represents the MSB code, a represents the LSB code, and 16 represents the sum of the MSB bits and the LSB bits, respectively. In addition, the first term on the right side of mathematical expression 4 represents non-linear values ​​(Δ1 to Δ16) that can be sequentially displayed in a predetermined curve shape between 0 and π, and the second term on the right side can represent interpolating values ​​that are filled in between the non-linear values.

[0178] The aforementioned interpolation DAC (250) can output the current flowing through each transistor pair and dummy transistor through the output node of the circuit according to the residual data signal. The output node of the interpolation DAC (250) can be connected to only one of the second current sources of the nonlinear differential DAC (230). The second current source connected to the output node of the interpolation DAC (250) is a current source corresponding to the least significant bit having a bit value of '0' in the thermometer code (hereinafter referred to as the 'third current source'). According to this configuration, the currents flowing through the transistor pairs and dummy transistors of the interpolation DAC (250) flow through the third current source, and the current flowing through the third current source is divided to interpolate the output current of the nonlinear differential DAC (230).

[0179] When using this type of interpolation, the error caused by the linear interpolation method does not occur significantly in the part where the sine wave changes most rapidly because the amount of slope change is not large. On the other hand, in the part where the amount of slope change is the largest, the error that occurs is not large because the actual output change amount is small. Therefore, when the nonlinear differential DAC (230) and the interpolation DAC (250) are combined and used, high resolution can be obtained using a minimum number of input bits, and there can also be a benefit in operating speed. Moreover, since the interpolation DAC (250) acts on only one section or one stage of the second current sources of the nonlinear differential DAC (230), the interpolation circuit does not substantially increase the complexity of the overall device structure, and the effect of system complexity on the operating speed is minimal or almost nonexistent.

[0180] According to the above-described configuration, in the drain signal generation device, pulses generated by two frequency generators among the four frequency generators of the driver (100) (see 310, 320, 330 and 340 of FIGS. 6, 7 and 8) can be added and interpolated by the addition circuit (260).

[0181] As described above, the interpolated main pulse can be expressed as a formula in the following mathematical expression 5.

[0182]

[0183] In mathematical expression 5, can be arbitrarily set for each qubit control signal output from one driver (100) as a value determined by FCW.

[0184] Pulses generated by the remaining two frequency generators among the four frequency generators of the aforementioned driver (100) can be interpolated by the addition circuit (260).

[0185] As described above, the interpolated DRAG pulse can be expressed as a formula in the following mathematical expression 6.

[0186]

[0187] In mathematical expression 6, the scale factor ( ) can be determined according to the current level of the current bias (210).

[0188] The qubit control signal generated by the four frequency generators of the driver (100) described above can be expressed in a formula as shown in the following mathematical expression 7.

[0189]

[0190] In this way, according to the present embodiment, a qubit control signal can be generated without memory by the four frequency generators of the driver (100).

[0191] The waveform shaping circuit (350) can shape the analog signal output by the four frequency generators for better spectral separation between pulses. In the present embodiment, the waveform shaping circuit (350) can perform shunt-based amplitude shaping to approximate the LO frequency of the phase-locked circuit to simplify circuit implementation. This waveform shaping circuit (350) can include a capacitor and a transistor connected in parallel between the I-signal output terminal and the inverting output terminal to convert the output signal into a rising cosine shape.

[0192] The mixer (370) is connected to the I-signal output terminal and the inverting output terminal and the Q-signal output terminal and the inverting output terminal of the analog processing unit. Transistor pairs for mixing LO signals are arranged between the I-signal output terminal and the I-signal inverting output terminal. Transistor pairs for mixing LO signals are also arranged between the Q-signal output terminal and the Q-signal inverting output terminal. The transistor pairs can frequency-modulate the LO signal according to the output signal of the analog processing unit and transmit a nonlinear high-frequency signal to the output circuit (390).

[0193] By using the mixer (370), the gap between the I-signal and the inverted I-signal is reduced, and as the size of the I-signal decreases, the envelope of the waveform shaping signal output from the waveform shaping circuit (350) narrows and widens repeatedly.

[0194] The output circuit (390) can filter the waveform-shaped analog signal and output the output voltage, which is a radio frequency output (RF OUT), as a qubit control signal, which is a nonlinear waveform signal. The output circuit (390) includes a primary winding and a secondary winding that are magnetically coupled. The inductors and variable capacitors of the primary winding form a filter to exclude unnecessary sidebands of the local oscillation signal and allow only the intended sidebands to pass.

[0195] In the example of the circuit shown (see FIG. 9), a bias voltage (VDD) is applied to the center tap of the primary winding, which can be configured to bias the second current sources of the nonlinear differential DAC (230) through the I-signal and Q-signal output terminals and the inverting output terminal. Meanwhile, in the present embodiment, a resistor is placed instead of the magnetically coupled primary and secondary windings, and the voltage drop across the resistor can be used as the output voltage.

[0196] According to the aforementioned qubit control signal generation device, a main pulse and a DRAG pulse can be generated without using memory using four independent frequency generators, and a qubit control signal can be generated by combining them. This enables the perfect generation of qubit control signals in an ultra-low temperature superconducting computing device without memory, enabling low-power operation and effectively expanding the number of qubit control signals as the number of qubits increases.

[0197] In particular, the importance of low-power operation without memory lies in the unique characteristics of superconducting quantum computers. Superconducting quantum computers operate at extremely low temperatures, down to 10 mK absolute zero, and therefore require the use of cryogenic refrigeration. Therefore, if externally generated radio frequency (RF) signals for qubit control are required, high-speed RF signals must be fed into the refrigeration system. However, since these RF signals increase in proportion to the number of qubits, they must be physically connected via thousands or tens of thousands of channels or cables, which is not very efficient in practice. Therefore, research is being conducted to generate qubit control signals within the 4K region within the refrigeration system, limiting the control chip's ability to operate within the limited cooling power of the 4K region. However, existing methods proposed to date have not been able to generate DRAG pulses for controlling a large number of qubits in the 4K region. However, according to the method and device of the present embodiment, a qubit control signal comprising a main pulse, a DRAG pulse, or a combination of a main pulse and a DRAG pulse can be generated simply and effectively without memory, for controlling a large number of qubits.

[0198] Fig. 17 is a graph showing a 5.56 GHz 5 ns sine shape pulse measured at 4K using a chip implementing the qubit control signal generation device of Fig. 9. Fig. 18 is a graph showing a 5.56 GHz 10 ns sine shape pulse generated using an intermediate frequency of ±50 MHz of the sine shape pulse of Fig. 17.

[0199] Referring to FIG. 17, the drag signal generation device can generate a sine-shaped pulse of 5㎱ pulse as a main pulse by using two frequency generators that generate a frequency of 5.56㎓ + 100㎒ and a frequency of 5.56㎓ - 100㎒, respectively, through a local oscillator (LO) of a phase-locked circuit having a frequency of 5.66㎓.

[0200] Also, referring to FIG. 18, the drag signal generation device can generate a sine-shaped pulse of 10㎱ pulse as a main pulse by using two frequency generators that generate a frequency of 5.56㎓ + 50㎒ and a frequency of 5.56㎓ - 50㎒, respectively, through a local oscillator (LO) of a phase-locked circuit that generates a frequency signal of 5.66㎓.

[0201] Fig. 19 is a graph showing the results of generating a signal having multiple frequency components simultaneously as frequency signals at 20 MHz intervals by generating independent frequency and phase signals from each of the four frequency generators of the qubit control signal generation device of Fig. 9. Fig. 20 is a graph showing the results of generating a signal having multiple frequency components simultaneously as frequency signals at 100 MHz intervals by generating independent frequency and phase signals from each of the four frequency generators of the qubit control signal generation device of Fig. 9.

[0202] As shown in Fig. 19, it can be confirmed that the qubit control signal generation device of the present embodiment can generate a qubit control signal of four tones simultaneously. The radio frequency signal readout from the qubit control signal generation device can have the characteristics of an LO frequency of 8 GHz, a digital clock of 2 GHz, a DAC spacing of 20 MHz, and a center frequency of 7.62 GHz.

[0203] In addition, as shown in Fig. 20, it can be confirmed that the qubit control signal generation device of the present embodiment can generate a qubit control signal of four tones simultaneously. The radio frequency signal readout from the qubit control signal generation device can have the characteristics of an LO frequency of 8 GHz, a digital clock of 2 GHz, and a DAC spacing of 100 MHz.

[0204] In this way, each of the four frequency generators can operate independently and simultaneously.

[0205] Figures 21 to 23 show the qubit control signal generation device of Figure 9 operating in the 4K region, setting the frequency and phase to match the desired DRAG pulse in four frequency generators, and the scale factor (q). scale ) are graphs showing the results of measuring the change in the distribution of the frequency spectrum.

[0206] Referring to FIG. 21, the qubit control signal generation device generates a qubit control signal having an output frequency of 5.46 GHz, a pulse width of 5 ns, and a second frequency (f) through first and third frequency generators using LO frequency 5.56 GHz and frequency 5.46 GHz + 20 MHz, and second and fourth frequency generators using frequency 5.46 GHz - 20 MHz. 12) can generate a DRAG pulse with a leakage suppression of at least 15 dB or more. Depending on the value of the scale factor (scare factor, qscale), that is, when the scaling factor is not applied (0.0), 0.1 to 0.4 is applied, the second frequency (f 12 ) can generate DRAG pulses of 15 dB, 16 dB, 18 dB, 22 dB, and 28 dB in the order described.

[0207] Referring to FIG. 22, the qubit control signal generation device generates a qubit control signal having an output frequency of 5.46 GHz, a pulse width of 10 ns, and a second frequency (f) through first and third frequency generators using LO frequency 5.56 GHz and frequency 5.46 GHz + 50 MHz, and second and fourth frequency generators using frequency 5.46 GHz - 50 MHz. 12 ) can generate a DRAG pulse with a leakage suppression of at least 11 dB or more. Depending on the value of the scale factor, that is, when the scaling factor is not applied (0.0), 0.1 to 0.4 is applied, the second frequency (f 12 ) can generate DRAG pulses of 11 dB, 14 dB, 16 dB, 19 dB, and 26 dB in the order described.

[0208] Referring to FIG. 23, the qubit control signal generation device generates a qubit control signal having an output frequency of 5.56 GHz, a pulse width of 15 ns, and a second frequency (f) through first and third frequency generators using LO frequency 5.56 GHz, frequency 5.56 GHz + 33 MHz, and second and fourth frequency generators using frequency 5.56 GHz - 33 MHz. 12 ) can generate a DRAG pulse with a leakage suppression of at least 32 dB or more. Depending on the size of the scale factor, that is, when the scaling factor is not applied (0.0), 0.1 to 0.4 is applied, the second frequency (f 12) can generate DRAG pulses of 32 dB, 33 dB, 34 dB, 35 dB, and 37 dB in the order described.

[0209] Fig. 24 shows a microscopic photograph of a chip implementing a qubit control signal generation device according to the present embodiment. Fig. 25 is an enlarged microscopic photograph of the frequency generator portion of the qubit control signal generation device of Fig. 24.

[0210] Referring to FIG. 24, each frequency generator of the qubit control signal generation device may be in the form of an integrated circuit (IC) including a controller, two phase-locked loops (PLLs), and four drivers. The size of the IC may be 1.65 mm wide and 2.3 mm high. In addition, referring to FIG. 25, each driver may be manufactured in a bulk CMOS (complementary metal oxide semiconductor) form using a 40 nm process, and may have a size of 0.55 mm wide and 0.65 mm high. The driver may include four digital parts for a controller, a clock calculator, an iterative phase accumulator, and a waveform converter, multiple DACs for a nonlinear differential DAC and an interpolation DAC, a filter for waveform shaping, a mixer, and a radio frequency (RF) output terminal.

[0211] According to the above-described configuration, a qubit control pulse using a DRAG pulse for superconducting qubits can be efficiently synthesized by generating four sine waves. At this time, no memory or lookup table (LUT) is required for generating the qubit control pulse. Furthermore, it was demonstrated that qubit control pulses can be simultaneously generated in four channels for frequency division multiplexing (FDM). It was confirmed that the power consumption per qubit was 7.2 mW in readout pulse generation mode, indicating that it can be efficiently applied to low-power quantum computers.

[0212] In this way, a sine-shaped pulse and a raised cosine-shaped pulse, i.e., a main pulse, can be generated without using memory, i.e., without an additional part for amplitude variation, and in a similar manner, a DRAG pulse for a sine pulse shape or a raised cosine pulse shape can be generated at low power without using memory. In addition, a signal capable of simultaneously reading four qubits can be generated at low power using frequency generators for four independent intermediate frequencies. In other words, a method and device for generating four different frequency signals at once can be provided.

[0213] In addition, it is possible to provide a method of having a phase-locked loop (PLL) for generating an LO frequency inside, dividing the frequency generated from the PLL into, for example, 1 / 8 or 1 / 16 and using it simultaneously for a digital system clock, and using this to precisely align and control the phase of an intermediate frequency (IF) signal generated using an LO signal and a digital block.

[0214] Furthermore, considering that a phase error may occur due to a delay in the system clock when the same system clock is used in multiple frequency generators, this can be compensated for by adding a phase when generating an internal frequency, thereby ensuring reliability and stability in the operation of the device.

[0215] The aforementioned qubit control signal generation device can be configured around two frequency generators for generating a drag signal in a narrow sense, and in that case, it can be referred to as a drag signal generation device.

[0216] Although the present invention has been described with reference to the above embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. A method for generating a qubit control signal for controlling a quantum computer, A step of generating a first sine curve having a first phase obtained by multiplying an angular velocity obtained by adding a first angular velocity of a center frequency and a second angular velocity of a second frequency located to the left of the center frequency by an arbitrary time of each cycle; and A step of generating a second sine curve having a second phase obtained by multiplying an angular velocity obtained by subtracting the second angular velocity from the first angular velocity and the arbitrary time; Including, A method for generating a qubit control signal, wherein a DRAG (derivative removal by adiabatic gate) pulse for a qubit control signal is generated through an operation of adding the first sine curve and the second sine curve.

2. In claim 1, A step of generating a third sine curve having a third phase obtained by multiplying the angular velocity obtained by adding the first angular velocity and the second angular velocity by the arbitrary time; and A step of generating a fourth sine curve having a fourth phase obtained by multiplying the angular velocity obtained by subtracting the second angular velocity from the first angular velocity and the arbitrary time; Including, A method for generating a qubit control signal, wherein a main pulse of a qubit control signal is generated through an operation of subtracting the fourth sine curve from the third sine curve.

3. In claim 2, A method for generating a qubit control signal further comprising the step of setting the current bias of the first sinusoid and the second sinusoid so that the DRAG pulse is multiplied by a scale factor.

4. In claim 3, A method for generating a qubit control signal, wherein the above scale factor is any one real value selected from 0 or more and less than 1.

5. In claim 3, A method for generating a qubit control signal, further comprising the step of synthesizing the main pulse and the DRAG pulse to generate a qubit control pulse by synthesizing the first to fourth sine curves together.

6. In claim 5, A method for generating a qubit control signal, further comprising a step of converting the qubit control pulse into a radio frequency output signal in addition to the main frequency of the phase-locked circuit according to a plurality of phase signals of the phase-locked circuit applied to the mixer.

7. In claim 2, A method for generating a qubit control signal, further comprising the step of specifying an initial phase for generating each of the first sine curve, the second sine curve, the third sine curve, and the fourth sine curve.

8. In claim 2, Each of the steps of generating the first sine curve, the second sine curve, the third sine curve, and the fourth sine curve, A step of repeatedly accumulating a frequency codeword (FCW) within a range of a preset upper limit from 0 from a predetermined initial phase; A step of converting the accumulated values ​​into a triangle wave shape or a sine wave shape by reversing the even-numbered rising cycles of the repeated accumulated values ​​obtained in the above-mentioned accumulating step; A step of converting the upper certain bits of the accumulated values ​​converted into the above sine wave shape into a first analog signal; A step of converting a lower certain bit of the accumulated values ​​converted into the sine wave shape into a second analog signal; and A method for generating a qubit control signal, comprising: a step of interpolating the first analog signal by adding the second analog signal to the first analog signal.

9. In claim 2, A method for generating a qubit control signal, further comprising: a step of aligning the processing timing of data or signals input to each of the four controllers by four clock calculators coupled to the four controllers, each of which supplies a phase signal and a frequency codeword (FCW) for determining an initial phase of each of the first to fourth phases to generate the first sine curve, the second sine curve, the third sine curve, and the fourth sine curve, respectively.

10. In claim 9, A method for generating a qubit control signal, further comprising the step of dividing a reference clock supplied from an external source of a qubit control signal generating device into n (n is 8 or 16) sub-clocks and transmitting some of them to each of the four clock calculators.

11. In claim 10, A step of determining a first main frequency according to the above reference clock and generating a first phase signal and a first clock signal based on the first main frequency; A step of determining a second main frequency different from the first main frequency according to the reference clock, and generating a second phase signal and a second clock signal based on the second main frequency; and A step of selecting one of the first phase signal and the second phase signal and providing it to first to fourth frequency generators that generate the first sine curve, the second sine curve, the third sine curve, and the fourth sine curve, respectively; A method for generating a qubit control signal including more.

12. In claim 9, A method for generating a qubit control signal further comprising a step of distributing data signals and control signals input from the outside of the dilution refrigeration device and supplying them to the four controllers by a main controller connected to the four controllers.

13. As a qubit control signal generation device for controlling a quantum computer, A first frequency generator that generates a first sine curve having a first phase obtained by multiplying an angular velocity obtained by adding a first angular velocity of a center frequency to a second angular velocity of a second frequency located to the left of the center frequency by an arbitrary time of each cycle; and A second frequency generator that generates a second sine curve having a second phase obtained by multiplying the angular velocity obtained by subtracting the second angular velocity from the first angular velocity by the arbitrary time; Including, A DRAG (derivative removal by adiabatic gate) pulse for a qubit control signal is generated through the process of adding the first sine curve and the second sine curve. Qubit control signal generator.

14. In claim 13, A third frequency generator that generates a third sine curve having a third phase obtained by multiplying the angular velocity obtained by adding the first angular velocity and the second angular velocity by the arbitrary time; and A fourth frequency generator generating a fourth sine curve having a fourth phase obtained by multiplying the angular velocity obtained by subtracting the second angular velocity from the first angular velocity by the arbitrary time; Including more, A qubit control signal generating device, wherein a main pulse for the qubit control signal is generated through a process of subtracting the fourth sine curve from the third sine curve.

15. In claim 14, In order to generate a qubit control pulse synthesized from the first to fourth sine curves, the main pulse corresponding to the first term of the right side of Equation 3 and the DRAG pulse corresponding to the second term of the right side are synthesized by performing an operation of subtracting the fourth sine curve from the third sine curve and an operation of adding the first sine curve and the second sine curve. [Equation 3] In the above mathematical formula 3 is a qubit control pulse, is the on-time pulse of the circuit for frequency generation, q scale is the scale factor, is the phase angle at any time (t) of the qubit basis state, A qubit control signal generation device, each of which represents a phase angle of a qubit at an arbitrary time (t).

16. In claim 15, A qubit control signal generating device further comprising a mixer that converts the qubit control pulse into a radio frequency output signal in addition to the main frequency of the phase-locked circuit according to a plurality of phase signals of the phase-locked circuit.

17. In claim 15, The third frequency generator and the fourth frequency generator each have third and fourth current biases that supply power at a reference level for the operation of the third frequency generator and the operation of the fourth frequency generator, respectively. The first frequency generator and the second frequency generator each have first and second current biases that supply a power level that is a scale factor multiplied by the reference level for the operation of the first frequency generator and the operation of the second frequency generator, respectively. Qubit control signal generator.

18. In claim 14, Each of the first to fourth frequency generators, A controller that outputs a frequency codeword (FCW), a phase signal specifying an initial phase, and an enable signal; A repeating phase accumulator that repeatedly accumulates the frequency codeword in a range from 0 to a preset upper limit value from an initial phase determined by the phase signal; A waveform converter that converts the repeated accumulated values ​​obtained from the repeated phase accumulator into a triangle wave shape or a sine wave shape by inverting the even-numbered rising cycles of the repeated accumulated values; A nonlinear differential DAC (digital analog convertor) that converts the upper certain bits of the accumulated values ​​converted into the above sine wave shape into a first analog signal; An interpolation DAC that converts a lower certain bit of the accumulated values ​​converted into the sine wave shape into a second analog signal; and A qubit control signal generating device comprising an addition circuit that interpolates the first analog signal by adding the second analog signal to the first analog signal.

19. In claim 18, A qubit control signal generation device, wherein each of the first to fourth frequency generators further includes a clock calculator that matches the processing timing of a data signal or control signal input to the controller.

20. In claim 18, A first phase-locked circuit that determines a first main frequency according to a reference clock and generates a first phase signal and a first clock signal based on the first main frequency; A second phase-locked circuit that determines a second main frequency different from the first main frequency according to the reference clock, and generates a second phase signal and a second clock signal based on the second main frequency; A clock selector for selecting one of the first phase signal and the second phase signal and providing the same to the first to fourth frequency generators; and A qubit control signal generation device further comprising a main controller connected to the four controllers of the first frequency generator to the fourth frequency generator and distributing data signals and control signals input from the outside of the dilution refrigeration device and supplying them to the four controllers.

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