Array substrate and driving method therefor, and display panel and display apparatus

Abstract

An array substrate and a driving method therefor, and a display panel and a display apparatus. The array substrate comprises: a plurality of pixel groups (C), wherein each pixel group (C) comprises two sub-pixels arranged in a column direction (Y), and the pixel groups (C) in each column comprise a plurality of sub-pixels (A1, A2, A3), which are alternately arranged according to a plurality of display colors thereof, the display colors of sub-pixels located in the same row being the same; a plurality of data line groups (D), wherein each data line group (D) comprises a first data line (D1) and a second data line (D2), which extend in the column direction (Y), the pixel groups (C) in each column correspond to one data line group (D), the first data line (D1) and second data line (D2) in each data line group (D) are respectively located on two opposite sides of pixel groups (C) in each column in a row direction (X), the first data line (D1) in each data line group (D) is electrically connected to one sub-pixel of each pixel group (C) in the corresponding column, and the second data line (D2) in the data line group (D) is electrically connected to the other sub-pixel of each pixel group (C) in the corresponding column; and a plurality of rows of scanning lines (G1, G2, G3), wherein the plurality of rows of scanning lines (G1, G2, G3) and the rows of pixel groups (C) are alternately arranged in the column direction (Y), and the scanning lines (G1, G2, G3) are electrically connected to the sub-pixels in the corresponding row.

Description

Array substrate, driving method thereof, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a driving method thereof, a display panel, and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The present disclosure provides an array substrate, a driving method thereof, a display panel, and a display device. The specific solutions are as follows:

[0005] An embodiment of the present disclosure provides an array substrate, comprising:

[0006] A plurality of pixel groups arranged in an array along row and column directions, each pixel group including two sub-pixels arranged along the column direction, each column of the pixel groups including a plurality of sub-pixels alternately arranged in a plurality of display colors, and the sub-pixels in the same row display the same color;

[0007] a plurality of data line groups, each data line group comprising a first data line and a second data line extending along the column direction, each column of the pixel groups corresponding to one data line group, and the first data line and the second data line in each data line group being located on opposite sides of each column of the pixel group in the row direction; wherein the first data line in each data line group is electrically connected to one sub-pixel in each pixel group in the corresponding column, and the second data line in each data line group is electrically connected to another sub-pixel in each pixel group in the corresponding column;

[0008] A plurality of rows of scan lines, wherein the scan lines in each row and the pixel groups in each row are alternately arranged in the column direction, and the scan lines are electrically connected to the sub-pixels in the corresponding row.

[0009] In a possible implementation, in the array substrate provided in the embodiment of the present disclosure, each row of sub-pixels is electrically connected to the scan line most adjacent thereto.

[0010] In one possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, each sub-row sub-pixel in the pixel group located in the Nth row is electrically connected to the scan line most adjacent to it, and the pixel group located in the N+1th row includes a first sub-row sub-pixel and a second sub-row sub-pixel, the first sub-row sub-pixel is electrically connected to the scan line most adjacent to the second sub-row sub-pixel, and the second sub-row sub-pixel is electrically connected to the scan line most adjacent to the first sub-row sub-pixel; wherein N is a positive integer.

[0011] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, two sub-pixels located on both sides of the same scan line and in the most adjacent column are connected to the same data line.

[0012] In a possible implementation, in the array substrate provided by an embodiment of the present disclosure, each row of pixel groups is electrically connected to the same row of scan lines, and different rows of pixel groups are electrically connected to different rows of scan lines.

[0013] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, each column of the pixel group includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially in the column direction, the display color of the first sub-pixel is blue, the display color of the second sub-pixel is green, and the display color of the third sub-pixel is red; wherein,

[0014] Each of the first sub-pixels in the pixel group located in the Mth column is electrically connected alternately to the first data line and the second data line of the corresponding group, and each of the first sub-pixels in the pixel group located in the M+1th column is electrically connected to the first data line of the corresponding group;

[0015] Each of the second sub-pixels in the pixel group located in the Mth column is electrically connected to the second data line of the corresponding group, and each of the second sub-pixels in the pixel group located in the M+1th column is alternately electrically connected to the second data line and the first data line of the corresponding group;

[0016] Each of the third sub-pixels in the pixel group located in the Mth column is electrically connected to the first data line of the corresponding group, and each of the third sub-pixels in the pixel group located in the M+1th column is electrically connected to the second data line of the corresponding group; wherein M is a positive integer.

[0017] In a possible implementation, the array substrate provided in the embodiment of the present disclosure further includes a plurality of rows of common electrode lines, and each row of the common electrode lines is located between two rows of sub-pixels in a corresponding row of the pixel group.

[0018] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the common electrode lines and the scan lines are alternately arranged along the column direction.

[0019] In one possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, a sub-pixel in one of any two adjacent pixel groups in the column direction has the same display color as a sub-pixel in the other group, and the display colors of any two adjacent sub-pixels in the column direction are different.

[0020] In one possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the sub-pixels in each column are divided into a plurality of pixel units arranged in sequence in the column direction, and each of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence in the column direction; the display colors of the first sub-pixel, the second sub-pixel and the third sub-pixel are different.

[0021] In a possible implementation, in the array substrate provided in the embodiment of the present disclosure, the display color of the first sub-pixel is blue, the display color of the second sub-pixel is green, and the display color of the third sub-pixel is red.

[0022] In a possible implementation, in the array substrate provided in an embodiment of the present disclosure, the length of each sub-pixel along the row direction is greater than the length along the column direction.

[0023] In one possible implementation, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the sub-pixel includes a pixel electrode and a thin film transistor, the gate of the transistor is electrically connected to the corresponding scanning line, the first electrode of the transistor is electrically connected to the corresponding data line, and the second electrode of the transistor is electrically connected to the corresponding pixel electrode.

[0024] Correspondingly, an embodiment of the present disclosure further provides a display panel, comprising: the above-mentioned array substrate provided in an embodiment of the present disclosure, and an opposite substrate arranged in a box with the array substrate.

[0025] Correspondingly, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel provided by an embodiment of the present disclosure.

[0026] Accordingly, an embodiment of the present disclosure further provides a driving method for an array substrate, which is used to drive the above-mentioned array substrate provided by an embodiment of the present disclosure. The driving method includes:

[0027] Within one frame time, a scanning voltage is loaded onto the scanning line, and a data voltage is loaded onto the sub-pixels in the corresponding row through the data line group; wherein, the voltage polarities loaded onto the first data line and the second data line in each of the data line groups are opposite, and the voltage polarities loaded onto the two columns of data lines between two adjacent columns of pixel groups are the same.

[0028] In a possible implementation, in the driving method provided in the embodiment of the present disclosure, within one frame time, a scan voltage is applied to the scan lines row by row, or a scan voltage is applied to two adjacent rows of scan lines at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic structural diagram of an array substrate provided in the related art;

[0030] FIG2 is a schematic structural diagram of another array substrate provided in the related art;

[0031] FIG3 is a schematic structural diagram of another array substrate provided in the related art;

[0032] FIG4 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure;

[0033] FIG5 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0034] FIG6 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0035] FIG7 is a timing diagram of the array substrate shown in FIG4 ;

[0036] FIG8 is a schematic diagram showing the effect of a brighter green (G) sub-pixel in the array substrate shown in FIG4 ;

[0037] FIG9 is a schematic diagram showing the effect of brightening the red (R) sub-pixel and the green (G) sub-pixel in the array substrate shown in FIG5 ;

[0038] FIG10 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0039] FIG11 is a schematic diagram of a planar structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0042] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0043] Currently, commonly used pixel architectures include Single Gate (single gate, each row of pixel units is driven by a row of scan lines), Dual Gate (double gate, each row of pixel units is driven by two rows of scan lines), and Triple Gate (each row of pixel units is driven by three rows of scan lines), as shown in Figures 1-3. Figure 1 is a single-gate pixel architecture provided in the relevant art, Figure 2 is a dual-gate pixel architecture provided in the relevant art, and Figure 3 is a triple-gate pixel architecture provided in the relevant art, where G1, G2... are scan lines, D1, D2... are data lines, and each pixel unit includes multiple sub-pixels of different display colors (for example, R, G, B). At the same display panel resolution, different pixel architectures require different numbers of data driver ICs (integrated circuits), which in turn affects the production cost of the display panel. For example, a display panel with a resolution of 1920 x 1080 has 1920 columns of pixels and 1080 rows of pixels. The number of sub-pixels in the row direction is 1920 x 3 = 5760. Assuming a single data driver IC drives 960 data lines, a single-gate pixel architecture requires six data driver ICs, a dual-gate pixel architecture requires three, and a triple-gate pixel architecture requires two. However, this reduction in the number of data driver ICs comes at the expense of shortening the actual charging time per pixel. Assuming the actual charging time per pixel in a single-gate pixel architecture is 1 hour, the actual charging time per pixel in a dual-gate pixel architecture is 1 / 2 hour, and the actual charging time per pixel in a triple-gate pixel architecture is 1 / 3 hour. For ultra-large, high-resolution products, using a dual-gate or triple-gate pixel architecture can reduce data driver IC costs, but the pixel charging time is too short, which can compromise image quality.

[0044] In order to solve the above technical problems, the present disclosure provides an array substrate, as shown in FIG4 to FIG6 , including:

[0045] Multiple pixel groups C are arrayed along the row direction X and the column direction Y, each pixel group C includes two sub-pixels arranged along the column direction Y, and each column of pixel group C includes multiple sub-pixels (A1, A2, A3) arranged alternately in multiple display colors, and the display colors of the sub-pixels in the same row are the same; for example, along the column direction Y, pixel group C may include two sub-pixels A1 and A2, pixel group C may include two sub-pixels A3 and A1, and pixel group C may include two sub-pixels A2 and A3; along the row direction X, for example, the first row is composed entirely of sub-pixels A1, the second row is composed entirely of sub-pixels A2, and the third row is composed entirely of sub-pixels A3, and then A1, A2, and A3 are arranged in a cyclic manner in groups.

[0046] a plurality of data line groups D, each data line group D including a first data line D1 and a second data line D2 extending along a column direction Y, each column of pixel groups C corresponding to one data line group D, and the first data line D1 and the second data line D2 in each data line group D being located on opposite sides of each column of pixel groups C in the row direction X; wherein the first data line D1 in each data line group D is electrically connected to one sub-pixel in each pixel group C in the corresponding column, and the second data line D2 in each data line group D is electrically connected to another sub-pixel in each pixel group C in the corresponding column;

[0047] Multiple rows of scan lines (G1, G2, G3, ...), each row of scan lines (G1, G2, G3, ...) and each row of pixel groups C are alternately arranged in the column direction Y, and the scan lines (G1, G2, G3, ...) are electrically connected to the sub-pixels of the corresponding row.

[0048] The array substrate provided in the embodiments of the present disclosure is designed with a row direction comprising a whole row of sub-pixels of the same color, and a column direction comprising sub-pixels of different colors arranged in a cyclic pattern. Furthermore, a row of scan lines is provided for every two rows of sub-pixels in the column direction, and two data lines are provided between every two adjacent columns of sub-pixels in the row direction. Compared to a single-gate pixel architecture in the related art, the pixel architecture of the present disclosure has 1.5 times the number of scan lines, 2 / 3 the number of data driver ICs, and 2 / 3 the charging time of a single gate. Therefore, compared to a single-gate pixel architecture in the related art, the pixel architecture of the present disclosure can save 1 / 3 the number of data driver ICs at the same resolution. Compared to a dual-gate pixel architecture in the related art, the pixel architecture of the present disclosure has 3 / 4 the number of scan lines, 4 / 3 the number of data driver ICs, and 4 / 3 the charging time of a dual-gate pixel architecture. Therefore, compared to a dual-gate pixel architecture in the related art, the pixel architecture of the present disclosure can reduce the charging time per row of pixels by 1 / 3. Therefore, the array substrate provided by the embodiment of the present disclosure can be used in some ultra-large and high-resolution display panels, which can not only reduce the cost of data driver ICs but also ensure the charging time of pixels, thereby ensuring picture quality.

[0049] Optionally, the array substrate provided by the embodiment of the present disclosure may be applied to liquid crystal display products, but is certainly not limited thereto.

[0050] In a specific implementation, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figures 4 to 6, in any two adjacent pixel groups C in the column direction Y, a sub-pixel in one of the groups has the same display color as a sub-pixel in the other group. For example, taking the first column of pixel groups C as an example, the sub-pixel A1 in the first pixel group C and the sub-pixel A1 in the second pixel group C have the same display color, the sub-pixel A3 in the second pixel group C and the sub-pixel A3 in the third pixel group C have the same display color, and the sub-pixel A2 in the third pixel group C and the sub-pixel A2 in the fourth pixel group C have the same display color; the display colors of any two adjacent sub-pixels in the column direction Y are different.

[0051] In a specific implementation, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figures 4 to 6, each column of sub-pixels is divided into a plurality of pixel units P arranged in sequence in the column direction Y, and each pixel unit P includes a first sub-pixel A1, a second sub-pixel A2 and a third sub-pixel A3 arranged in sequence in the column direction Y, that is, each column of pixel groups includes a first sub-pixel A1, a second sub-pixel A2 and a third sub-pixel A3 arranged in sequence in the column direction Y; wherein the display colors of the first sub-pixel A1, the second sub-pixel A2 and the third sub-pixel A3 are different. Optionally, the display color of the first sub-pixel A1 is blue (B), the display color of the second sub-pixel A2 is green (G), and the display color of the third sub-pixel A3 is red (R), that is, the arrangement order of the sub-pixels in the column direction is BGRBGRBGR…, but not limited to this; for example, the display color of the first sub-pixel A1 can also be red (R), the display color of the second sub-pixel A2 is green (G), and the display color of the third sub-pixel A3 is blue (B), that is, the arrangement order of the sub-pixels in the column direction is RGBRGBRGB…, and the display colors of the first sub-pixel A1, the second sub-pixel A2 and the third sub-pixel A3 can be set according to actual needs.

[0052] In a specific implementation, in the array substrate provided by the embodiments of the present disclosure, as shown in Figures 4-6 , the length of each sub-pixel along the row direction X is greater than the length along the column direction Y. The sub-pixels of the present disclosure are arranged such that the row direction X represents a whole row of sub-pixels of the same color, while the column direction Y is arranged in a BGRBGR cyclic pattern. This reduces the number of data driver ICs by one-third compared to Single Gate at the same resolution, and increases the charging time of each row of pixels by one-third compared to Dual Gate at the same resolution.

[0053] In a specific implementation, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figures 4 to 6, the sub-pixel may include a pixel electrode 10 and a thin film transistor T, the gate of the transistor T is electrically connected to the corresponding scan line, the first electrode of the transistor T is electrically connected to the corresponding data line, and the second electrode of the transistor T is electrically connected to the corresponding pixel electrode 10.

[0054] Optionally, the gate of the transistor T is integrally provided with the scan line, the first electrode of the transistor T is integrally provided with the data line, and the second electrode of the transistor T is partially in contact and electrically connected with the pixel electrode.

[0055] Optionally, the transistor T may be a P-type transistor or an N-type transistor, and the transistor T may be a bottom-gate transistor, a top-gate transistor, or a dual-gate transistor, etc., which are not limited here. In the present disclosure, the first electrode of the transistor T may be a source electrode, and the second electrode may be a drain electrode, or the first electrode of the transistor T may be a drain electrode, and the second electrode may be a source electrode, which are not limited here. The transistor T also includes an active layer, and the material of the active layer may be amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (Oxide, such as indium gallium zinc oxide IGZO), etc. Optionally, a gate insulating layer (GI) may be provided between the layer where the gate of the transistor T is located and the active layer, and the material of the gate insulating layer may be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0056] Optionally, the material of the pixel electrode includes transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0057] Optionally, the material of the scanning line may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc., and the scanning line may be a single-layer structure or a stacked-layer structure, for example, the scanning line is a single-layer structure composed of a molybdenum metal layer.

[0058] Optionally, the material of the data line may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), and the data line may be a single-layer structure or a stacked structure, for example, the data line may be a stacked structure consisting of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0059] In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, as shown in FIG4 , each row of sub-pixels is electrically connected to the scan line most adjacent thereto. A scan line is provided for every two rows of sub-pixels in the column direction Y. For example, the first row of scan line G1 is electrically connected to the first row of sub-pixels, the second row of scan line G2 is electrically connected to the second row of sub-pixels and the third row of sub-pixels, the third row of scan line G3 is electrically connected to the fourth row of sub-pixels and the fifth row of sub-pixels, and so on. Two adjacent data lines are provided between every two adjacent columns of sub-pixels in the row direction X. For example, two adjacent data lines D2 and D1 are provided between the first column of pixel group C and the second column of pixel group C. D2 drives the even-numbered sub-pixels to its left, and D1 drives the odd-numbered sub-pixels to its right. Alternatively, D2 can drive the odd-numbered sub-pixels to its left, and D1 drives the even-numbered sub-pixels to its right. The polarity arrangement of each data line along the row direction X can be "-++--++-" or "+--++--+", and a data line does not switch polarity within a frame. That is, the voltage polarity applied to the first data line D1 and the second data line D2 in each data line group D is opposite, and the voltage polarity applied to the two columns of data lines (D1 and D2) between two adjacent columns of pixel groups C is the same. The pixel architecture design shown in Figure 4 provided by the embodiment of the present disclosure can save 1 / 3 of the number of data driver ICs at the same resolution compared to Single Gate, and can increase the charging time of each row of pixels by 1 / 3 compared to Dual Gate at the same resolution.

[0060] Based on the array substrate shown in Figure 4, during the image quality test, for example, during the red-green (RG) mixed color image quality test, all green (G) sub-pixels will be pre-charged, resulting in a long charging time, and the red (R) sub-pixels will not be pre-charged, resulting in a short charging time. In this way, the green (G) sub-pixels are brighter and the red (R) sub-pixels are darker, which easily leads to color deviation problems. For example, the high level of each row of scan lines will last for 4 hours. Of course, the high level of each row of scan lines can also last for 2 hours / 3 hours / 5 hours / 6 hours / 7 hours / 8 hours, etc. This disclosure takes 4 hours as an example. Combined with the timing diagram shown in Figure 7, the last 1 hour of the high level of the scan signals G1 / G2 / G3 / G4... is the actual data charging time of the sub-pixel, and the previous 3 hours are all pre-charging time. Taking the third row of red (R) sub-pixels and the fifth row of green (G) sub-pixels as an example, since the sub-pixels in the same column and the same data line are electrically connected, when the red (R) sub-pixels are charged, the green (G) sub-pixels are pre-charged. Therefore, the green (G) sub-pixels are brighter and the red (R) sub-pixels are darker, as shown in Figure 8, which is a schematic diagram of the effect of the green (G) sub-pixels being brighter.

[0061] For example, to solve the problem of color shift when testing a red-green (RG) mixed color screen on the array substrate shown in FIG4 , an embodiment of the present disclosure provides another array substrate, as shown in FIG5 , in which each row of pixel groups C is electrically connected to the same row of scan lines, and different rows of pixel groups C are electrically connected to different rows of scan lines. For example, both rows of sub-pixels in the first row of pixel group C are electrically connected to the second row of scan line G2, both rows of sub-pixels in the second row of pixel group C are electrically connected to the third row of scan line G3, and both rows of sub-pixels in the third row of pixel group C are electrically connected to the fourth row of scan line G4…; of course, it is also possible that both rows of sub-pixels in the first row of pixel group C are electrically connected to the first row of scan line G1, both rows of sub-pixels in the second row of pixel group C are electrically connected to the second row of scan line G2, and both rows of sub-pixels in the third row of pixel group C are electrically connected to the third row of scan line G3….

[0062] In a specific implementation, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIG5 , each first sub-pixel A1 in the pixel group C located in the Mth column is alternately electrically connected to the first data line D1 and the second data line D2 of the corresponding group, and each first sub-pixel A1 in the pixel group C located in the M+1th column is electrically connected to the first data line D1 of the corresponding group; wherein M is a positive integer; for example, each first sub-pixel A1 in the pixel group C located in the first column is alternately electrically connected to the first data line D1 and the second data line D2 of the corresponding group, and each first sub-pixel A1 in the pixel group C located in the second column is electrically connected to the first data line D1 of the corresponding group; each first sub-pixel A1 in the pixel group C located in the third column is alternately electrically connected to the first data line D1 and the second data line D2 of the corresponding group, and each first sub-pixel A1 in the pixel group C located in the fourth column is electrically connected to the first data line D1 of the corresponding group; and so on;

[0063] Each second sub-pixel A2 in the pixel group C located in the Mth column is electrically connected to the second data line D2 of the corresponding group, and each second sub-pixel A2 in the pixel group C located in the M+1th column is alternately electrically connected to the second data line D2 and the first data line D1 of the corresponding group; wherein M is a positive integer; for example, each second sub-pixel A2 in the pixel group C located in the first column is electrically connected to the second data line D2 of the corresponding group, and each second sub-pixel A2 in the pixel group C located in the second column is alternately electrically connected to the second data line D2 and the first data line D1 of the corresponding group; each second sub-pixel A2 in the pixel group C located in the third column is electrically connected to the second data line D2 of the corresponding group, and each second sub-pixel A2 in the pixel group C located in the fourth column is alternately electrically connected to the second data line D2 and the first data line D1 of the corresponding group; and so on;

[0064] Each third sub-pixel A3 in the pixel group C located in the Mth column is electrically connected to the first data line D1 of the corresponding group, and each third sub-pixel A3 in the pixel group C located in the M+1th column is electrically connected to the second data line D2 of the corresponding group; wherein M is a positive integer; for example, each third sub-pixel A3 in the pixel group C located in the first column is electrically connected to the first data line D1 of the corresponding group, and each third sub-pixel A3 in the pixel group C located in the second column is electrically connected to the second data line D2 of the corresponding group; each third sub-pixel A3 in the pixel group C located in the third column is electrically connected to the first data line D1 of the corresponding group, and each third sub-pixel A3 in the pixel group C located in the fourth column is electrically connected to the second data line D2 of the corresponding group; and so on.

[0065] In the pixel architecture design shown in FIG5 provided by the embodiment of the present disclosure, during the red-green (RG) color mixing image quality test, when charging the red (R) sub-pixels in the previous row, the red (R) sub-pixels or green (G) sub-pixels in the following row are pre-charged, or when charging the green (G) sub-pixels in the previous row, the green (G) sub-pixels or red (R) sub-pixels in the following row are pre-charged. In this way, half of the green (G) sub-pixels will be brighter and three-quarters of the red (R) sub-pixels will be brighter, as shown in FIG9, which is a schematic diagram of the effect of brighter red (R) and green (G) sub-pixels. This can make the red-green (RG) color mixing more uniform and improve the color cast problem of the picture.

[0066] In a specific implementation, in order to further improve the charging time of each row of pixels of the array substrate provided by the embodiment of the present disclosure, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in Figure 6, each sub-row sub-pixel in the pixel group C located in the Nth row is electrically connected to the scan line most adjacent to it, and the pixel group C located in the N+1th row includes a first sub-row (C1) sub-pixel and a second sub-row (C2) sub-pixel, the first sub-row (C1) sub-pixel is electrically connected to the scan line most adjacent to the second sub-row (C2) sub-pixel, and the second sub-row (C2) sub-pixel is electrically connected to the scan line most adjacent to the first sub-row (C1) sub-pixel; wherein N is a positive integer; for example, the first sub-row sub-pixel in the first row pixel group C is electrically connected to the first row scan line G1 most adjacent to it, the second sub-row sub-pixel in the first row pixel group C is electrically connected to the second row scan line G2 most adjacent to it; the first sub-row (C1) sub-pixel in the second row pixel group C is electrically connected to the third row scan line G3 most adjacent to the second sub-row (C2) sub-pixel, and the second sub-row (C2) sub-pixel in the second row pixel group C is electrically connected to the third row scan line G4 most adjacent to the second sub-row (C4) sub-pixel. The second sub-row (C2) sub-pixels are electrically connected to the second row scan line G2 that is most adjacent to the first sub-row (C1) sub-pixels; the first sub-row sub-pixels in the third row pixel group C are electrically connected to the third row scan line G3 that is most adjacent to it, and the second sub-row sub-pixels in the third row pixel group C are electrically connected to the fourth row scan line G4 that is most adjacent to it; the first sub-row (C1) sub-pixels in the fourth row pixel group C are electrically connected to the fifth row scan line G5 that is most adjacent to the second sub-row (C2) sub-pixels, and the second sub-row (C2) sub-pixels in the fourth row pixel group C are electrically connected to the fourth row scan line G4 that is most adjacent to the first sub-row (C1) sub-pixels….

[0067] In a specific implementation, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figure 6, the two sub-pixels (G and R) located on both sides of the same scan line (for example, G2) and in the same column (for example, the first column) that are most adjacent are connected to the same data line D2, the two sub-pixels (B and G) located on both sides of the same scan line (for example, G3) and in the same column (for example, the second column) that are most adjacent are connected to the same data line D1, and the two sub-pixels (R and B) located on both sides of the same scan line (for example, G4) and in the same column (for example, the third column) that are most adjacent are connected to the same data line D2...

[0068] As shown in Figure 6, for example, two adjacent data lines D2 and D1 between the first and second columns of pixel groups C drive the pixels to its left in the following order: one row of green sub-pixels, two rows of red sub-pixels, two rows of blue sub-pixels, and one row of green sub-pixels, repeating in a repeating cycle. D1 drives the pixels to its right in the following order: two rows of blue sub-pixels, two rows of green sub-pixels, and two rows of red sub-pixels, repeating in a repeating cycle. The data line polarity is arranged as "-++--++-" or "+--++--+," and a data line does not switch polarity within a frame. Because the pixel architecture shown in Figure 6 connects two adjacent sub-pixels on each data line in each column of the same color—for example, the sub-pixels connected to the first data line D1 are BBGGRR..., and the sub-pixels connected to the second data line D2 are GGRRBB...—the pixel architecture shown in Figure 6 can support simultaneous gate opening for two rows of sub-pixels, doubling the pixel charging time and thus improving the charging rate of each row of pixels. Taking the first column data line D1 as an example, when G1 and G2 are turned on at the same time, D1 charges the two blue sub-pixels and does not cause image abnormalities.

[0069] As shown in Table 1 below, Table 1 compares the number of scan lines, the number of data lines, the number of data driver ICs, and the charging time of each row of pixels corresponding to the pixel architecture provided by the embodiment of the present disclosure and several common pixel architectures in the related art, taking the resolution of the display panel as 1920*1080 as an example.

[0070] Table 1

[0071] As can be seen from Table 1, the pixel architecture design of the array substrate provided in the embodiments of the present disclosure, compared to the Single Gate and Dual Gate designs in the related art, has a number of scan lines between those of the Single Gate and Dual Gate designs, a number of data lines between those of the Single Gate and Dual Gate designs, a number of data driver ICs between those of the Single Gate and Dual Gate designs, and a pixel charging time per row between those of the Dual Gate designs. Therefore, the pixel architecture design of the array substrate provided in the embodiments of the present disclosure can reduce the cost of the data driver ICs while ensuring pixel charging time, thereby ensuring image quality.

[0072] In a specific implementation, the array substrate provided in the embodiments of the present disclosure, as shown in Figures 4-6 , further includes multiple rows of common electrode lines Com, each row of common electrode lines Com being located between two rows of sub-pixels in a corresponding row of pixel groups C. For example, a first row of common electrode lines Com is located between two rows of sub-pixels in a first row of pixel groups C, a second row of common electrode lines Com is located between two rows of sub-pixels in a second row of pixel groups C, a third row of common electrode lines Com is located between two rows of sub-pixels in a third row of pixel groups C, and so on. Specifically, the common electrode lines Com and the scan lines (G1, G2, G3, ...) are alternately arranged along the column direction Y. By providing multiple common electrode lines Com throughout the array substrate, uniformity of the common signal can be ensured, thereby improving display uniformity.

[0073] It should be noted that other essential components of the array substrate should be understood by those skilled in the art and will not be described in detail here, nor should they be considered as limitations of the present disclosure.

[0074] Based on the same inventive concept, an embodiment of the present disclosure further provides a driving method for an array substrate, which is used to drive the array substrate provided by the embodiment of the present disclosure. The driving method includes:

[0075] Within one frame time, a scan voltage is applied to the scan line, and a data voltage is applied to the corresponding row of sub-pixels through the data line group; wherein, the voltage polarities applied to the first data line and the second data line in each data line group are opposite, and the voltage polarities applied to the two columns of data lines between two adjacent columns of pixel groups are the same.

[0076] The specific driving distance can be found in the related description of the aforementioned array substrate, which will not be elaborated here.

[0077] In specific implementation, in the above-mentioned driving method provided in the embodiment of the present disclosure, as shown in Figures 4 and 5, within one frame time, the scanning voltage is loaded to the scanning lines row by row; as shown in Figure 6, the scanning voltage is loaded to two adjacent rows of scanning lines at the same time to improve the charging rate of each row of pixels.

[0078] In specific implementation, the array substrate provided in the embodiment of the present disclosure may further include other functional film layers well known to those skilled in the art, which are not listed here one by one.

[0079] Based on the same inventive concept, the present disclosure also provides a display panel, as shown in FIG10 , comprising: the array substrate 001 provided in the present disclosure, and an opposing substrate 002 aligned with the array substrate 001. The principles of solving the problems of this display panel are similar to those of the aforementioned array substrate, so the implementation of this display panel can refer to the implementation of the aforementioned array substrate, and the repeated parts will not be repeated here.

[0080] In specific implementation, the display panel provided in the embodiment of the present disclosure, as shown in FIG10 , further includes: a liquid crystal layer 003 located between the array substrate 001 and the counter substrate 002 , and a backlight module 004 located on the light incident side of the array substrate 001 .

[0081] Specifically, the opposite substrate includes: a blue color filter arranged corresponding to the first sub-pixel, a green color filter arranged corresponding to the second sub-pixel, and a red color filter arranged corresponding to the third sub-pixel.

[0082] In some embodiments, in the above-mentioned display panel provided in the embodiments of the present disclosure, the backlight module 004 can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser and a brightening film stacked on the light-emitting side of the matrix light source, etc., and the reflective sheet includes an opening arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).

[0083] Submillimeter or even micron-scale micro-LEDs are self-luminous devices, just like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, they can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0084] Based on the same inventive concept, the present disclosure also provides a display device comprising the display panel described above. The principles of this display device are similar to those of the aforementioned display panel, so the implementation of this display device can refer to the implementation of the aforementioned display panel, and any repetitions will not be repeated here.

[0085] In a specific implementation, the above-mentioned display device provided in the embodiment of the present disclosure may be a liquid crystal display device, which also includes other necessary components and components, such as a housing, a main circuit board, a power cord, etc. Those skilled in the art may make corresponding supplements based on the specific usage requirements of the display device. These supplements will not be elaborated here and should not be regarded as a limitation to the present disclosure.

[0086] In specific implementation, the above-mentioned display device provided in the embodiment of the present disclosure may be a full-screen display device, or may be a flexible display device, etc., which is not limited here.

[0087] In a specific implementation, the display device provided in the embodiment of the present disclosure may be a full-screen mobile phone as shown in Figure 11. Of course, the display device provided in the embodiment of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0088] The present invention provides an array substrate, a driving method thereof, a display panel, and a display device. The array substrate provided by the present invention is designed to have a whole row of sub-pixels of the same color in the row direction, and to have sub-pixels of different colors arranged in a group in a cyclic manner in the column direction. A row of scan lines is provided for every two rows of sub-pixels in the column direction, and two data lines are provided between every two adjacent columns of sub-pixels in the row direction. Compared with the Single Gate pixel architecture in the related art, the pixel architecture of the present invention has 1.5 times the number of scan lines, 2 / 3 times the number of data driver ICs, and 2 / 3 times the charging time of the Single Gate. Therefore, compared with the Single Gate pixel architecture in the related art, the pixel architecture of the present invention can save 1 / 3 of the number of data driver ICs at the same resolution. Compared with the Dual Gate pixel architecture in the related art, the pixel architecture of the present invention has 3 / 4 times the number of scan lines, 4 / 3 times the number of data driver ICs, and 4 / 3 times the charging time of the Dual Gate. Therefore, compared with the Dual Gate pixel architecture in the related art, the pixel architecture of the present invention has 1.5 times the number of scan lines, 2 / 3 times the number of data driver ICs, and 4 / 3 times the charging time of the Dual Gate. Gate can increase the charging time of each row of pixels by 1 / 3 at the same resolution. Therefore, the array substrate provided by the embodiments of the present disclosure can be used in some ultra-large and high-resolution display panels, reducing the cost of data driver ICs while ensuring pixel charging time, thereby ensuring picture quality.

[0089] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0090] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: A plurality of pixel groups arranged in an array along row and column directions, each of the pixel groups comprising two sub-pixels arranged along the column direction, each column of the pixel groups comprising a plurality of sub-pixels alternately arranged with a plurality of display colors, and the display colors of the sub-pixels in the same row are the same; a plurality of data line groups, each of the data line groups comprising a first data line and a second data line extending along the column direction, each column of the pixel groups corresponding to one of the data line groups, and the first data line and the second data line in each of the data line groups are respectively located at opposite sides of each column of the pixel groups in the row direction; wherein the first data line in each of the data line groups is respectively electrically connected to one of the sub-pixels in each of the pixel groups in the corresponding column, and the second data line in each of the data line groups is respectively electrically connected to another of the sub-pixels in each of the pixel groups in the corresponding column; A plurality of rows of scan lines, each row of the scan lines and each row of the pixel groups are alternately arranged in the column direction, and the scan lines are electrically connected to the sub-pixels in the corresponding row.

2. The array substrate according to claim 1, wherein: Each row of sub-pixels is electrically connected to the scan line most adjacent to it.

3. The array substrate according to claim 1, wherein: Each sub-row sub-pixel in the pixel group located in the Nth row is electrically connected to the scan line most adjacent to it, and the pixel group located in the N+1th row includes a first sub-row sub-pixel and a second sub-row sub-pixel, the first sub-row sub-pixel is electrically connected to the scan line most adjacent to the second sub-row sub-pixel, and the second sub-row sub-pixel is electrically connected to the scan line most adjacent to the first sub-row sub-pixel; wherein N is a positive integer.

4. The array substrate according to claim 3, wherein: Two sub-pixels located at two sides of the same scan line and in the most adjacent column are connected to the same data line.

5. The array substrate according to claim 1, wherein: The pixel groups in each row are electrically connected to the scan lines in the same row, and the pixel groups in different rows are electrically connected to the scan lines in different rows.

6. The array substrate according to claim 5, wherein: Each column of the pixel group includes a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence in the column direction, the display color of the first sub-pixel is blue, the display color of the second sub-pixel is green, and the display color of the third sub-pixel is red; wherein, Each of the first sub-pixels in the pixel group located in the Mth column is electrically connected to the first data line and the second data line of the corresponding group alternately, and each of the first sub-pixels in the pixel group located in the M+1th column is electrically connected to the first data line of the corresponding group; Each of the second sub-pixels in the pixel group located in the Mth column is electrically connected to the second data line of the corresponding group, and each of the second sub-pixels in the pixel group located in the M+1th column is alternately electrically connected to the second data line and the first data line of the corresponding group; Each of the third sub-pixels in the pixel group located in the Mth column is electrically connected to the first data line of the corresponding group, and each of the third sub-pixels in the pixel group located in the M+1th column is electrically connected to the second data line of the corresponding group; wherein M is a positive integer.

7. The array substrate according to any one of claims 1 to 6, wherein: It also includes a plurality of rows of common electrode lines, each row of the common electrode lines is located between two rows of sub-pixels in the corresponding row of the pixel group.

8. The array substrate according to claim 7, wherein: The common electrode lines and the scan lines are alternately arranged along the column direction.

9. The array substrate according to any one of claims 1 to 4, wherein: A sub-pixel in one of any two adjacent pixel groups in the column direction has the same display color as a sub-pixel in the other group, and a sub-pixel in any two adjacent sub-pixels in the column direction has different display colors.

10. The array substrate according to claim 9, wherein: The sub-pixels in each column are divided into a plurality of pixel units arranged sequentially in the column direction, and each of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel arranged sequentially in the column direction; the display colors of the first sub-pixel, the second sub-pixel and the third sub-pixel are different.

11. The array substrate according to claim 10, wherein: The display color of the first sub-pixel is blue, the display color of the second sub-pixel is green, and the display color of the third sub-pixel is red.

12. The array substrate according to any one of claims 1 to 11, wherein: The length of each sub-pixel along the row direction is greater than the length along the column direction.

13. The array substrate according to any one of claims 1 to 12, wherein: The sub-pixel includes a pixel electrode and a thin film transistor, a gate of the transistor is electrically connected to the corresponding scan line, a first electrode of the transistor is electrically connected to the corresponding data line, and a second electrode of the transistor is electrically connected to the corresponding pixel electrode.

14. A display panel, wherein: include: An array substrate as claimed in any one of claims 1 to 13, and a counter substrate arranged in a box with the array substrate.

15. A display device, wherein: Comprising the display panel as claimed in claim 14.

16. A method for driving an array substrate, for driving the array substrate according to any one of claims 1 to 13, wherein: The driving method comprises: Within one frame time, a scan voltage is loaded onto the scan line, and a data voltage is loaded onto the sub-pixels of the corresponding row through the data line group; wherein the voltage polarities loaded onto the first data line and the second data line in each of the data line groups are opposite, and the voltage polarities loaded onto the two columns of data lines between two adjacent columns of the pixel groups are the same.

17. The driving method according to claim 16, wherein: In one frame time, a scan voltage is applied to the scan lines row by row, or a scan voltage is applied to two adjacent rows of scan lines at the same time.

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