Gate driving circuit and display panel

Abstract

A gate driving circuit and a display panel. A gate driving unit in the gate driving circuit comprises a pull-up control module (101), a pull-up node (Q), a pull-down control module (102), a pull-down node (P) and a pull-down module (103), wherein the pull-up control module (101) is electrically connected to the pull-up node (Q); the pull-down control module (102) is electrically connected to the pull-down node (P) and a scanning signal input end (G(N-1)) in the previous stage or a scanning signal input end (G(N-2)) in the stage prior to the previous stage; and the pull-down module (102) is electrically connected to the pull-up node (Q) and the pull-down node (P).

Description

Gate drive circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] Gate-driver on array (GOA) technology utilizes the thin-film transistor array (TFT) manufacturing process to fabricate gate drive circuitry on a TFT array substrate, enabling progressive scanning. The gate drive circuitry consists of multiple cascaded gate drive units.

[0003] The gate drive unit includes a pull-up node and a pull-down node. The pull-up node refers to the gate control point of the output transistor in the GOA. When the potential of the pull-up node is high, the output transistor turns on, and the gate drive unit outputs a drive signal to the corresponding scan line. The pull-down node refers to the gate control point of the pull-down control transistor. When the potential of the pull-down node is high, the pull-down control transistor turns on, and the gate drive unit stops outputting a drive signal to the corresponding scan line.

[0004] In the existing gate drive circuit, the potential of the pull-up node and the potential of the pull-down node affect each other. When the potential of the pull-up node is insufficient to turn on the pull-down control transistor to pull down the high potential of the pull-down node, the potential of the pull-up node is in a conflicting state of being pulled up and pulled down, resulting in a charging delay problem for the pull-up node. SUMMARY OF THE INVENTION

[0005] An object of the embodiments of the present application is to provide a gate driving circuit and a display panel, which can improve the problem of charging delay of a pull-up node.

[0006] On the one hand, an embodiment of the present application provides a gate drive circuit, comprising a multi-stage cascaded gate drive unit, the gate drive unit comprising a pull-up control module, a pull-up node, a pull-down control module, a pull-down node and a pull-down module; the pull-up control module is electrically connected to the pull-up node, and the pull-up control module is used to pull up the potential of the pull-up node; the pull-down control module is not electrically connected to the pull-up node, the pull-down control module is electrically connected to the pull-down node, and the pull-down control module is used to pull down the potential of the pull-down node; the pull-down module is electrically connected to the pull-up node and the pull-down node, and the pull-down module is used to pull down the potential of the pull-up node under the control of the potential of the pull-down node.

[0007] On the other hand, the present application provides a display panel, including a pixel unit and a gate driving circuit, wherein the gate driving circuit is electrically connected to the pixel unit, the gate driving circuit includes a multi-stage cascaded gate driving unit, the gate driving unit including a pull-up control module, a pull-up node, a pull-down control module, a pull-down node and a pull-down module; the pull-up control module is electrically connected to the pull-up node, and the pull-up control module is used to pull up the potential of the pull-up node; the pull-down control module is not electrically connected to the pull-up node, the pull-down control module is electrically connected to the pull-down node, and the pull-down control module is used to pull down the potential of the pull-down node; the pull-down module is electrically connected to the pull-up node and the pull-down node, and the pull-down module is used to pull down the potential of the pull-up node under the control of the potential of the pull-down node. Beneficial effects

[0008] In the gate drive circuit and display panel provided in the embodiments of the present application, the gate drive circuit includes a multi-stage cascaded gate drive unit, the gate drive unit including a pull-up control module, a pull-up node, a pull-down control module, a pull-down node and a pull-down module; the pull-up control module is electrically connected to the previous level scan signal input terminal and the pull-up node, and the pull-up control module is used to pull up the potential of the pull-up node; the pull-down control module is not electrically connected to the pull-up node, the pull-down control module is electrically connected to the pull-down node, and the pull-down control module is used to pull down the potential of the pull-down node; the pull-down module is electrically connected to the pull-up node and the pull-down node, and the pull-down module is used to pull down the potential of the pull-up node under the control of the potential of the pull-down node. The gate drive circuit is electrically connected to the previous level scan signal input terminal or the previous two levels scan signal input terminals by setting a pull-down control module, so that the potential of the pull-down node is controlled by the potential of the scan signal input by the previous level scan signal input terminal or the previous two levels scan signal input terminals, and is not controlled by the potential of the pull-up node, so as to improve the problem of charging delay of the pull-up node caused by the high potential of the pull-down node not being pulled down in time. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG1 is a schematic diagram of a gate drive circuit provided in an embodiment of the present application;

[0010] FIG2 is a schematic diagram of a gate driving unit in the gate driving circuit provided in FIG1 ;

[0011] FIG3 is a schematic diagram of a first partial circuit of the gate driving unit provided in FIG2 ;

[0012] FIG4 is a schematic diagram of a second partial circuit of the gate driving unit provided in FIG2 ;

[0013] FIG5 is a schematic diagram of a third partial circuit of the gate driving unit provided in FIG2 ;

[0014] FIG6 is a comparison diagram of simulation results of the gate driving unit of the present application and the existing gate driving unit;

[0015] FIG7 is a schematic diagram of a fourth partial circuit of the gate driving unit provided in FIG2 ;

[0016] FIG8 is a schematic diagram of a fifth partial circuit of the gate driving unit provided in FIG2 ;

[0017] FIG. 9 is a schematic diagram of a sixth partial circuit of the gate driving unit provided in FIG. 2 . Modes for Carrying Out the Invention

[0018] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. The described embodiments are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0019] The gate drive circuit in an existing display panel charges a pull-up node in a gate drive unit, causing the pull-up node to reach a high potential, thereby turning on a pull-down control transistor and thereby pulling down the high potential of the pull-down node. Because the pull-down control transistor has a threshold voltage (Vth), the pull-down transistor turns on only when the difference between the voltage at the pull-up control transistor's gate (Vg) and the voltage at the pull-down control transistor's source (Vs) is greater than Vth. Therefore, when the pull-up node switches from a low potential to a high potential, if the difference between the potential at the pull-up node and the source of the pull-down control transistor is less than Vth, the pull-down control transistor cannot turn on, and the high potential of the pull-down node cannot be pulled down. As a result, the pull-down transistor, controlled by the potential of the pull-down node, remains on, and the potential of the pull-up node is pulled down through the pull-down transistor. This causes the potential of the pull-up node to rise too slowly. Furthermore, the pull-down transistor remains on while the pull-up node is charging, causing the reference low-level signal terminal and the reference high-level signal terminal to conduct, which can easily lead to short-circuit burns.

[0020] An embodiment of the present application provides a display panel, including a pixel unit and a gate driving circuit, wherein the gate driving circuit is electrically connected to the pixel unit.

[0021] The display panel includes a plurality of pixel units arranged in an array and a plurality of scan lines. Each scan line is electrically connected to a row of pixel units. The gate drive circuit includes a plurality of cascaded gate drive units. Each gate drive unit is electrically connected to a scan line and is configured to provide a drive signal to the corresponding scan line to control the thin film transistors in the corresponding row of pixel units to turn on.

[0022] The gate driving circuit in the display panel provided by the embodiments of the present application can improve the problem of charging delay of the pull-up node caused by the high potential of the pull-down node not being pulled down in time.

[0023] The transistors used in all embodiments of the present application may be thin film transistors or other devices with the same characteristics. In order to distinguish the two poles of the transistor other than the gate, one of the source and the drain is referred to as the first electrode, and the other of the source and the drain is referred to as the second electrode. According to the form in the accompanying drawings, the middle input terminal of the transistor is defined as the gate, the signal input terminal is defined as the first electrode, and the signal output terminal is defined as the second electrode. In addition, the transistors used in the embodiments of the present application are P-type transistors or N-type transistors, wherein the P-type transistor is turned on when the gate is at a low potential and is cut off when the gate is at a high potential; the N-type transistor is turned on when the gate is at a high potential and is cut off when the gate is at a low potential.

[0024] As shown in Figure 1 , the gate drive circuit provided by an embodiment of the present application includes multiple stages of cascaded gate drive units. Figure 1 takes the cascaded gate drive unit GOA(n-1), the gate drive unit GOA(n), and the gate drive unit GOA(n+1) of the N+1 stage as an example.

[0025] The N-1th level gate driving unit GOA(n-1), the Nth level gate driving unit GOA(n) and the N+1th level gate driving unit GOA(n+1) are connected to the scanning lines G(n-1), G(n) and G(n+1) respectively, wherein the Nth level gate driving unit GOA(n) is connected to the level transmission scanning signal ST(n-1) output by the N-1th level gate driving unit GOA(n-1), and correspondingly, the N+1th level gate driving unit GOA(n+1) is connected to the level transmission signal S output by the Nth level gate driving unit GOA(n). T(n), and so on; at the same time, the N-1th gate driving unit GOA(n-1) transmits the scan signal to the scan line G(n-1) connected to the N-1th gate driving unit GOA(n), the Nth-level gate driving unit GOA(n) transmits the scan signal to the scan line G(n) connected to the Nth-level gate driving unit GOA(n), the N+1th-level gate driving unit GOA(n+1) transmits the scan signal to the scan line G(n+1) connected to the N+1th-level gate driving unit GOA(n+1), and so on.

[0026] The first-stage gate driving unit GOA(1) transmits a scan signal to a first scan line G(1) connected to the first-stage gate driving unit GOA(1) in response to a start signal STV, and transmits a stage transmission signal ST(1) to a second-stage gate driving unit GOA(2). It should be noted that the N-th stage gate driving unit (N is a positive integer greater than 1) can transmit a scan signal to the N-th scan line G(n), and transmit a stage transmission signal ST(n) to the N+1-th stage gate driving unit GOA(n+1).

[0027] The scan driving control signal includes a first clock signal CK1 and a second clock signal CK2.

[0028] When the Nth-stage gate driver unit is operating, the scan signal output by the Nth-stage gate driver unit GOA(n) is high, which is used to turn on the transistor switch of each pixel in a row of the display panel and charge the pixel electrode in each pixel through the data signal. The scan signal is used to control the operation of the N+1th-stage gate driver unit. When the N+1th-stage gate driver unit is operating, the scan signal output by the N+1th-stage gate driver unit GOA(n+1) is high, and the scan signal output by the Nth-stage gate driver unit GOA(n) is low.

[0029] As shown in FIG. 2 , the gate driving unit is a non-initial stage gate driving unit, and includes a pull-up control module 101 , a pull-up node Q, a pull-down control module 102 , a pull-down node P, and a pull-down module 103 .

[0030] The pull-up control module 101 is electrically connected to the previous stage scan signal input terminal G(N−1) and the pull-up node Q. The pull-up control module 101 is used to pull up the potential of the pull-up node Q.

[0031] The pull-down control module 102 is not electrically connected to the pull-up node Q. Specifically, the pull-down control module 102 is electrically connected to the previous-stage scan signal input terminal G(N-1) or the previous-stage scan signal input terminal G(N-2). The pull-down control module 102 is also electrically connected to the pull-down node P. The pull-down control module 102 is used to lower the potential of the pull-down node P.

[0032] The pull-down module 103 is electrically connected to the pull-up node Q and the pull-down node P. The pull-down module 103 is configured to pull down the potential of the pull-up node Q under the control of the potential of the pull-down node P.

[0033] The gate drive unit also includes an output control module 104 and an output module 105. Output control module 104 is electrically connected to pull-down node P and is configured to pull up the potential of pull-down node P. Output module 105 is electrically connected to pull-up node Q and is configured to output scan signal G(N). Output module 105 may include an output transistor. Output module 105 and output control module 104 may have the same existing structures.

[0034] The gate drive circuit provided in the embodiment of the present application is electrically connected to the previous level scan signal input terminal G (N-1) or the previous two levels scan signal input terminal G (N-2) by setting a pull-down control module 102, so that the potential of the pull-down node P is controlled by the potential of the scan signal input by the previous level scan signal input terminal G (N-1) or the previous two levels scan signal input terminal G (N-2), and is not controlled by the potential of the pull-up node Q, so as to improve the problem of charging delay of the pull-up node Q caused by the high potential of the pull-down node P not being pulled down in time.

[0035] As shown in Figures 3 and 4, the pull-up control module 101 includes a first transistor T1, a gate of the first transistor T1 is electrically connected to the previous stage scan signal input terminal G(N-1), a first electrode of the first transistor T1 is electrically connected to the reference high level signal input terminal VGH, and a second electrode of the first transistor T1 is electrically connected to the pull-up node Q.

[0036] The pull-down module 103 includes a fifth transistor T5 , a gate of which is electrically connected to the pull-down node P, a first electrode of which is electrically connected to the reference low-level signal input terminal VGL, and a second electrode of which is electrically connected to the pull-up node Q.

[0037] As shown in FIG3 , the pull-down control module 102 includes a second transistor T2 , a gate of the second transistor T2 being electrically connected to the previous-stage scan signal input terminal G(N−1), a first electrode of the second transistor T2 being electrically connected to the reference low-level signal input terminal VGL, and a second electrode of the second transistor T2 being electrically connected to the pull-down node P.

[0038] As shown in FIG4 , the pull-down control module 102 includes a second transistor T2 , a gate of the second transistor T2 being electrically connected to the upper two-stage scan signal input terminal G(N−2), a first electrode of the second transistor T2 being electrically connected to the reference low-level signal input terminal VGL, and a second electrode of the second transistor T2 being electrically connected to the pull-down node P.

[0039] As shown in FIG. 5 , the pull-down control module 102 includes a third transistor T3 , a fourth transistor T4 and a first node K.

[0040] A gate of the third transistor T3 is electrically connected to the first node K, a first electrode of the third transistor T3 is electrically connected to the reference low-level signal input terminal VGL, and a second electrode of the third transistor T3 is electrically connected to the pull-down node P.

[0041] The pull-up control module 101 includes a first transistor T1, a gate of the first transistor T1 is electrically connected to the previous stage scan signal input terminal G(N-1), a first electrode of the first transistor T1 is electrically connected to the reference high level signal input terminal VGH, and a second electrode of the first transistor T1 is electrically connected to the pull-up node Q.

[0042] The pull-down module 103 includes a fifth transistor T5 , a gate of which is electrically connected to the pull-down node P, a first electrode of which is electrically connected to the reference low-level signal input terminal VGL, and a second electrode of which is electrically connected to the pull-up node Q.

[0043] The gate of the fourth transistor T4 is electrically connected to the scan signal input terminal G(N-1) of the previous stage, the first electrode of the fourth transistor T4 is electrically connected to the reference high-level signal input terminal VGH, and the second electrode of the fourth transistor T4 is electrically connected to the first node K. Alternatively, the gate of the fourth transistor T4 is electrically connected to the scan signal input terminal G(N-2) of the previous two stages (not shown in the figure).

[0044] As shown in FIG6 , the potential of the pull-up node Q in the gate drive unit of an existing display panel needs to be pulled up to a point where the potential difference with the source of the pull-down control transistor is greater than the threshold voltage of the pull-down control transistor before the pull-down control transistor can be turned on, thereby pulling down the high potential of the pull-down node P to turn off the pull-down transistor and prevent the low-level signal from lowering the potential of the pull-up node Q through the pull-down transistor. Because the pull-up node Q receives both a high-level signal and a low-level signal during this stage, a charging delay of time t is caused for the pull-up node Q. Correspondingly, the time delay t for the pull-down node P to be pulled down to a preset low potential is such that the pull-up node Q cannot be charged to a preset high potential within the preset time, thereby affecting the display effect of the display panel.

[0045] As shown in Figure 7, the pull-down module 103 includes a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 is electrically connected to the pull-down node P, the first electrode of the fifth transistor T5 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the fifth transistor T5 is electrically connected to the pull-up node Q.

[0046] The gate of the sixth transistor T6 is electrically connected to the next stage scan signal input terminal G(N+1), the first electrode of the sixth transistor T6 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the pull-up node Q.

[0047] The pull-up control module 101 includes a first transistor T1, a gate of the first transistor T1 is electrically connected to the previous stage scan signal input terminal G(N-1), a first electrode of the first transistor T1 is electrically connected to the reference high level signal input terminal VGH, and a second electrode of the first transistor T1 is electrically connected to the pull-up node Q.

[0048] The pull-down control module 102 includes a second transistor T2, a gate of the second transistor T2 being electrically connected to the previous-stage scan signal input terminal G(N-1), a first electrode of the second transistor T2 being electrically connected to the reference low-level signal input terminal VGL, and a second electrode of the second transistor T2 being electrically connected to the pull-down node P. Alternatively, the gate of the second transistor T2 is electrically connected to the previous-stage scan signal input terminal G(N-2) (not shown in the figure).

[0049] The sixth transistor T6 is provided in the gate driving unit except the last-stage gate driving unit, that is, only the last-stage gate driving unit does not include the sixth transistor T6.

[0050] The gate drive circuit provided in the embodiment of the present application can ensure that the potential of the pull-up node Q is promptly lowered when the gate drive unit completes signal output by adding a sixth transistor T6 in at least part of the gate drive unit, thereby avoiding the phenomenon of mischarging of the pixel units in the surface due to the high potential of the pull-up node Q still outputting a signal after the signal output is completed.

[0051] As shown in Figures 8 and 9, the pull-up control module 101 includes a first transistor T1, a gate of the first transistor T1 is electrically connected to the previous stage scan signal input terminal G(N-1), a first electrode of the first transistor T1 is electrically connected to the reference high level signal input terminal VGH, and a second electrode of the first transistor T1 is electrically connected to the pull-up node Q.

[0052] The pull-down control module 102 includes a second transistor T2, wherein the gate of the second transistor T2 is electrically connected to the previous-stage scan signal input terminal G(N-1), the first electrode of the second transistor T2 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the second transistor T2 is electrically connected to the pull-down node P. Alternatively, the gate of the second transistor T2 is electrically connected to the previous-stage scan signal input terminal G(N-2) (not shown in the figure), the first electrode of the second transistor T2 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the second transistor T2 is electrically connected to the pull-down node P.

[0053] The pull-down module 103 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate of the fifth transistor T5 is electrically connected to the pull-down node P, the first electrode of the fifth transistor T5 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the fifth transistor T5 is electrically connected to the pull-up node Q.

[0054] The gate of the sixth transistor T6 is electrically connected to the next stage scan signal input terminal G(N+1), the first electrode of the sixth transistor T6 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the pull-up node Q.

[0055] As shown in FIG8 , the gate of the seventh transistor T7 is electrically connected to the next-stage clock signal input terminal CK(N+1), the first electrode of the seventh transistor T7 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the seventh transistor T7 is electrically connected to the pull-up node Q.

[0056] As shown in FIG9 , the gate of the seventh transistor T7 is electrically connected to the next-stage clock signal input terminal CK(N+1), the first electrode of the seventh transistor T7 is electrically connected to the full-on control signal input terminal GAS, and the second electrode of the seventh transistor T7 is electrically connected to the pull-up node Q.

[0057] The seventh transistor T7 is disposed in the last stage of the gate driving unit.

[0058] The gate drive circuit provided by an embodiment of the present application comprises a seventh transistor T7 added to at least a portion of the gate drive unit, wherein the gate of the seventh transistor T7 is electrically connected to the next-stage clock signal input terminal CK(N+1), which outputs a periodic square wave signal. The signal output period and frequency of the next-stage clock signal input terminal CK(N+1) are the same as the source signal CKN of the output transistor, and the phase of the clock signal input to the next-stage clock signal input terminal CK(N+1) is later than the source signal CKN of the output transistor. After the gate drive unit completes signal output, the next-stage clock signal input terminal CK(N+1) inputs a high-level clock signal, causing the high potential of the pull-up node Q to be pulled down to a low potential. The high-level clock signal input through the next-stage clock signal input terminal CK(N+1) pulls down the potential of the pull-up node Q. At the same time, the seventh transistor T7 can be set to avoid degradation of the pull-down transistor performance in harsh environments or after long-term operation, which leads to a decline in on-state current. The clock signal input to the next-level clock signal input terminal CK (N+1) is a periodic signal. Whenever the amplitude of the clock signal input to the next-level clock signal input terminal CK (N+1) is high, the pull-up node Q is pulled low, thereby achieving multi-pulse output by increasing the number of pull-down times.

[0059] The above is a detailed introduction to a gate driving circuit and a display panel provided in the embodiments of the present application. The description of the above embodiments is only used to help understand the core idea of ​​the present application, and the above description should not be understood as limiting the scope of protection of the present application.

Claims

1. A gate driving circuit, comprising a multi-stage cascaded gate driving unit, wherein the gate driving unit comprises a pull-up control module, a pull-up node, a pull-down control module, a pull-down node and a pull-down module; The pull-up control module is electrically connected to the pull-up node, and the pull-up control module is used to pull up the potential of the pull-up node; The pull-down control module is not electrically connected to the pull-up node, the pull-down control module is electrically connected to the pull-down node, and the pull-down control module is used to pull down the potential of the pull-down node; The pull-down module is electrically connected to the pull-up node and the pull-down node, and the pull-down module is used to pull down the potential of the pull-up node under the control of the potential of the pull-down node.

2. The gate drive circuit according to claim 1, wherein: The pull-up control module includes a first transistor, a gate of the first transistor is electrically connected to the previous level scan signal input terminal, a first electrode of the first transistor is electrically connected to the reference high level signal input terminal, and a second electrode of the first transistor is electrically connected to the pull-up node.

3. The gate driving circuit according to claim 1, wherein: The pull-down control module includes a second transistor, a gate of the second transistor is electrically connected to the previous level scan signal input terminal or the previous two levels scan signal input terminal, a first electrode of the second transistor is electrically connected to the reference low level signal input terminal, and a second electrode of the second transistor is electrically connected to the pull-down node.

4. The gate driving circuit according to claim 1, wherein: The pull-down control module comprises a third transistor and a fourth transistor, a first electrode of the third transistor is electrically connected to the reference low level signal input terminal, and a second electrode of the third transistor is electrically connected to the pull-down node; The gate of the fourth transistor is electrically connected to the previous level scan signal input terminal or the previous two levels scan signal input terminal, the first electrode of the fourth transistor is electrically connected to the reference high level signal input terminal, and the second electrode of the fourth transistor is electrically connected to the gate of the third transistor.

5. The gate driving circuit according to claim 1, wherein: The pull-down module includes a fifth transistor, a gate of the fifth transistor is electrically connected to the pull-down node, a first electrode of the fifth transistor is electrically connected to a reference low-level signal input terminal, and a second electrode of the fifth transistor is electrically connected to the pull-up node.

6. The gate driving circuit according to claim 5, wherein: The pull-down module also includes a sixth transistor, a gate of the sixth transistor is electrically connected to the next level scan signal input terminal, a first electrode of the sixth transistor is electrically connected to the reference low level signal input terminal, and a second electrode of the sixth transistor is electrically connected to the pull-up node.

7. The gate driving circuit according to claim 6, wherein: The sixth transistor is disposed in the gate driving unit except the last stage of the gate driving unit.

8. The gate driving circuit according to claim 5, wherein: The pull-down module also includes a seventh transistor, a gate of the seventh transistor is electrically connected to the next-level clock signal input terminal, a first electrode of the seventh transistor is electrically connected to a reference low-level signal input terminal or a fully-open control signal input terminal, and a second electrode of the seventh transistor is electrically connected to the pull-up node.

9. The gate driving circuit according to claim 8, wherein: The seventh transistor is arranged in the last stage of the gate driving unit.

10. The gate driving circuit according to claim 1, wherein: The gate driving unit further includes an output control module and an output module, wherein the output control module is electrically connected to the pull-down node, and the output control module is used to pull up the potential of the pull-down node; The output module is electrically connected to the pull-up node, and the output module is used to output a scan signal.

11. A display panel, comprising a pixel unit and a gate driving circuit, wherein the gate driving circuit is electrically connected to the pixel unit, the gate driving circuit comprises a multi-stage cascaded gate driving unit, and the gate driving unit comprises a pull-up control module, a pull-up node, a pull-down control module, a pull-down node, and a pull-down module; The pull-up control module is electrically connected to the pull-up node, and the pull-up control module is used to pull up the potential of the pull-up node; The pull-down control module is not electrically connected to the pull-up node, the pull-down control module is electrically connected to the pull-down node, and the pull-down control module is used to pull down the potential of the pull-down node; The pull-down module is electrically connected to the pull-up node and the pull-down node, and the pull-down module is used to pull down the potential of the pull-up node under the control of the potential of the pull-down node.

12. The display panel according to claim 11, wherein: The pull-up control module includes a first transistor, a gate of the first transistor is electrically connected to the previous level scan signal input terminal, a first electrode of the first transistor is electrically connected to the reference high level signal input terminal, and a second electrode of the first transistor is electrically connected to the pull-up node.

13. The display panel according to claim 11, wherein: The pull-down control module includes a second transistor, a gate of the second transistor is electrically connected to the previous level scan signal input terminal or the previous two levels scan signal input terminal, a first electrode of the second transistor is electrically connected to the reference low level signal input terminal, and a second electrode of the second transistor is electrically connected to the pull-down node.

14. The display panel according to claim 11, wherein: The pull-down control module comprises a third transistor and a fourth transistor, a first electrode of the third transistor is electrically connected to the reference low level signal input terminal, and a second electrode of the third transistor is electrically connected to the pull-down node; The gate of the fourth transistor is electrically connected to the previous level scan signal input terminal or the previous two levels scan signal input terminal, the first electrode of the fourth transistor is electrically connected to the reference high level signal input terminal, and the second electrode of the fourth transistor is electrically connected to the gate of the third transistor.

15. The display panel according to claim 11, wherein: The pull-down module includes a fifth transistor, a gate of the fifth transistor is electrically connected to the pull-down node, a first electrode of the fifth transistor is electrically connected to a reference low-level signal input terminal, and a second electrode of the fifth transistor is electrically connected to the pull-up node.

16. The display panel according to claim 15, wherein: The pull-down module also includes a sixth transistor, a gate of the sixth transistor is electrically connected to the next level scan signal input terminal, a first electrode of the sixth transistor is electrically connected to the reference low level signal input terminal, and a second electrode of the sixth transistor is electrically connected to the pull-up node.

17. The display panel according to claim 16, wherein: The sixth transistor is disposed in the gate driving unit except the last stage of the gate driving unit.

18. The display panel according to claim 15, wherein: The pull-down module also includes a seventh transistor, a gate of the seventh transistor is electrically connected to the next-level clock signal input terminal, a first electrode of the seventh transistor is electrically connected to a reference low-level signal input terminal or a fully-open control signal input terminal, and a second electrode of the seventh transistor is electrically connected to the pull-up node.

19. The display panel according to claim 18, wherein: The seventh transistor is arranged in the last stage of the gate driving unit.

20. The display panel according to claim 11, wherein: The gate driving unit further includes an output control module and an output module, wherein the output control module is electrically connected to the pull-down node, and the output control module is used to pull up the potential of the pull-down node; The output module is electrically connected to the pull-up node, and the output module is used to output a scan signal.

Images