Integrated circuit manufacturing method for design layouts with different densities

Abstract

The present invention provides an integrated circuit manufacturing method for design layouts with different densities, comprising: providing design layouts with different pattern densities for different products, a target density value of the pattern density of the design layouts and a process menu corresponding to the target density value, the pattern density being a ratio of the area occupied by patterns in the layouts to the total area of the layouts; adjusting the pattern density of each design layout to the target density value to form a photomask layout for production; and manufacturing a semiconductor device with the photomask layout by using the same process menu. According to the present invention, for the same manufacturing process, the process menu does not need to be readjusted or developed for the design layouts with different pattern densities for different products, and the photomask layouts formed by adjusting the pattern densities for products with different pattern densities of the design layouts and finally used for production have the same pattern density and can be suitable for the same process menu; the speed of new product development and large-scale mass production is increased, the management difficulty and management costs of manufacturing and production are reduced, and the manufacturing capacity is improved.

Description

Integrated circuit manufacturing method with different density design layouts Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing integrated circuits with different density design layouts. Background Art

[0002] Graphic density has a significant impact on lithography critical dimensions, etching critical dimensions, and film formation. Existing layouts usually only control graphic density within a certain range, such as controlling the active area, gate, and metal interconnection between 20-80%.

[0003] Different customer products with the same manufacturing process often have significantly different pattern densities due to different layout designs. Therefore, different process menus must be used for etching and film formation to target different customer designs and products. For new customer products, process menus need to be readjusted or developed based on different pattern densities. Different process menus on the same equipment have different parameter settings. When switching parameters, the equipment needs to be shut down to wait for the switch to complete. After the process parameter switch, it takes a certain amount of time for the equipment state to stabilize and the parameters to be calibrated to ensure that the fluctuations in the new process parameter settings meet the process fluctuation range requirements. Therefore, switching between different process menus on the same equipment, especially frequent switching, will significantly extend the equipment waiting time, greatly reducing the effective utilization rate of the equipment and leading to a decrease in production capacity.

[0004] In order to solve the above problems, it is necessary to propose a new integrated circuit manufacturing method with different density design layouts. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an integrated circuit manufacturing method with different density design layouts, which is used to solve the problem of different customer products with the same manufacturing process in the prior art. Because the layout designs are different, the graphic densities are often very different. Etching and film formation must use different process menus to target different customer designs and products. For new customer products, it is necessary to readjust or develop the process menu according to the different graphic densities. Different process menus for the same equipment have different parameter settings. When switching parameters, the equipment needs to be shut down and wait for the switch to be completed. After the process parameters are switched, it takes a certain amount of time for the equipment state to stabilize and the parameters to be calibrated to ensure that the new process parameter setting fluctuations meet the process fluctuation range requirements. Therefore, switching different process menus on the same equipment, especially frequent switching, will cause the equipment waiting time to be greatly extended, which will greatly reduce the effective utilization rate of the equipment and lead to a decrease in production capacity.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a method for manufacturing integrated circuits with different density design layouts, comprising:

[0007] Step 1: providing design layouts with different graphic densities for different products, target density values ​​for the graphic densities of the design layouts, and corresponding process recipes, where the graphic density is the ratio of the area occupied by the graphic in the layout to the total area of ​​the layout;

[0008] Step 2: adjusting the pattern density of each of the design layouts to the target density value to form a mask layout for production;

[0009] Step 3: Using the mask layout and the same process menu to manufacture semiconductor devices.

[0010] Preferably, the method for obtaining the target density value and the corresponding process menu in step one includes: designing test masks with different graphic densities; adjusting the parameters of the test process menu to perform stability tests on each of the test masks; and selecting the test mask and the test process menu whose stability test results are better than those of other test groups as the target density value and the corresponding process menu.

[0011] Preferably, the parameters of the process recipe corresponding to the target density value in step 1 are within 10% of the maximum variation range of the manufacturing process.

[0012] Preferably, the target density value in step 1 meets the design rules for multi-layer layout superposition.

[0013] Preferably, the method of adjusting the pattern density of the design layout to the target density value to form the mask layout in step 2 includes:

[0014] Determining whether the pattern density of the design layout reaches the target density value;

[0015] If not, filling the design layout with a first dummy pattern so that the pattern density of the design layout is the target density value, and then filling the design layout with a second dummy pattern so that the pattern density of the design layout is the target density value; wherein the first dummy pattern is identical to or similar to the pattern in the design layout, and the second dummy pattern is a pattern used for circuit matching;

[0016] If so, fill the design layout with a second dummy graphic, the size of the second dummy graphic is smaller than the first dummy graphic, so that the graphic density of the design layout is the target density value; wherein the second dummy graphic is a graphic used for circuit matching.

[0017] Preferably, the method of filling the design layout with the first dummy pattern in step 2 includes: determining a pattern period of the first dummy pattern, determining a distance between the first pattern and the design layout, and determining a filling range of the first pattern; filling the first pattern on the design layout, and determining whether its pattern density reaches the target density value;

[0018] If yes, execute the following steps;

[0019] If not, adjust the graphic period of the first dummy graphic, adjust the distance of the first graphic from the design layout, adjust the filling range of the first graphic, and then refill the first graphic on the design layout until its graphic density reaches the target density value.

[0020] Preferably, the cell unit X*Y filling block of the first dummy pattern in step 2 is densely filled with lines and gaps of minimum design rules.

[0021] Preferably, the method of filling the design layout with the second dummy pattern in step 2 includes: determining a pattern period of the second dummy pattern, determining a distance of the second pattern from the design layout, and determining a filling range of the second pattern; filling the second pattern on the design layout, and determining whether its pattern density reaches the target density value;

[0022] If yes, execute the following steps;

[0023] If not, adjust the graphic period of the second dummy graphic, adjust the distance of the second graphic from the design layout, adjust the filling range of the second graphic, and then refill the first graphic on the design layout until its graphic density reaches the target density value.

[0024] Preferably, the cell unit of the second dummy graphic in step 2 is an X*Y rectangle.

[0025] Preferably, the method of adjusting the pattern density of the design layout to the target density value to form the mask layout in step 2 includes:

[0026] Filling a first auxiliary pattern in the cutting path pattern area of ​​the design layout; then determining whether the pattern density reaches the target density value;

[0027] If yes, the layout after filling the first auxiliary pattern is used as the mask layout;

[0028] If not, the blank area in the design layout is filled with the second auxiliary pattern until the mask layout is obtained.

[0029] As described above, the method for manufacturing integrated circuits with different density design layouts of the present invention has the following beneficial effects:

[0030] The present invention does not require readjustment or development of a process menu for a design layout with different graphic densities for different products having the same manufacturing process. Products with different graphic densities in the design layout, formed after adjusting the graphic density, have the same graphic density in the final mask layout used for production and can be applied to the same process menu, thereby increasing the speed of new product development and large-scale mass production, reducing the management difficulty and cost of manufacturing production, and improving manufacturing capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 shows a schematic diagram of the process flow of the present invention. Implementation Method

[0032] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Referring to FIG. 1 , the present invention provides a method for manufacturing integrated circuits with different density design layouts, comprising:

[0034] Step 1: Provide a design layout, a target density value for the design layout pattern density, and a corresponding process menu. The pattern density is the ratio of the area occupied by the pattern in the layout to the total area of ​​the layout. The design layout is derived from the layouts of different customer products, and their pattern densities often vary greatly. In the prior art, filling only controls the pattern density within a certain range, such as controlling the active area, gate, and metal interconnection between 20-80%. The present invention controls the pattern density value to a fixed value.

[0035] In an optional embodiment, the method for obtaining the target density value and its corresponding process menu in step one includes: designing test masks with different graphic densities; adjusting the parameters of the test process menu to perform stability tests on each test mask respectively; and selecting the test mask and test process menu with better stability test results than other test groups as the target density value and its corresponding process menu.

[0036] In an optional embodiment, the parameters of the process recipe corresponding to the target density value in step 1 are within 10% of the maximum variation range of the manufacturing process.

[0037] In an optional embodiment, the target density value in step 1 meets the design rules of multi-layer layout superposition.

[0038] Step 2: Adjust the graphic density of each design layout to the target density value to form a mask layout. This involves inserting other types of graphics, such as dummy graphics, to adjust the graphic density of design layouts with different graphic densities to the target density value of the mask layout. The target density value is a preset fixed value. Manufacturing based on the mask layout does not require redevelopment of the process menu, thereby improving manufacturing capacity. The role of dummy graphics in circuit design, dummy analysis of MOS transistors - KIA MOS transistors. In IC layout design, not only must the circuit logic or function be reflected to ensure correct LVS verification, but also some graphics unrelated to LVS (circuit matching) must be included to reduce deviations in the intermediate process. We usually call these graphics dummy layers.

[0039] In an optional embodiment, the method of adjusting the pattern density of the design layout to the target density value to form the mask layout in step 2 includes:

[0040] Determine whether the graphic density of the design layout reaches the target density value;

[0041] If not, fill the design layout with a first dummy pattern so that the pattern density of the design layout reaches the target density value, and then fill the design layout with a second dummy pattern so that the pattern density of the design layout reaches the target density value; wherein the first dummy pattern is identical to or similar to the pattern in the design layout, and the second dummy pattern is a pattern used for circuit matching;

[0042] If so, the design layout is filled with a second dummy pattern, the size of the second dummy pattern is smaller than the first dummy pattern, so that the pattern density of the design layout is the target density value; wherein the second dummy pattern is a pattern used for circuit matching.

[0043] In an optional embodiment, the method of filling the design layout with the first dummy pattern in step 2 includes: determining a pattern period of the first dummy pattern, determining a distance between the first pattern and the design layout, and determining a filling range of the first pattern; filling the design layout with the first pattern, and determining whether its pattern density reaches a target density value;

[0044] If yes, execute the following steps;

[0045] If not, adjust the graphic period of the first dummy graphic, adjust the distance between the first graphic and the design layout, adjust the filling range of the first graphic, and then refill the first graphic on the design layout until its graphic density reaches the target density value.

[0046] In an optional embodiment, the X*Y filling block of the cell unit of the first dummy pattern in step 2 is densely filled with lines and gaps using minimum design rules.

[0047] In an optional embodiment, the method of filling the design layout with the second dummy pattern in step 2 includes: determining a pattern period of the second dummy pattern, determining a distance between the second pattern and the design layout, and determining a filling range of the second pattern; filling the second pattern on the design layout, and determining whether its pattern density reaches a target density value;

[0048] If yes, execute the following steps;

[0049] If not, adjust the graphic period of the second dummy graphic, adjust the distance between the second graphic and the design layout, adjust the filling range of the second graphic, and then refill the first graphic on the design layout until its graphic density reaches the target density value.

[0050] In an optional implementation, the cell unit of the second dummy graphic in step 2 is an X*Y rectangle.

[0051] In an optional embodiment, the method of adjusting the pattern density of the design layout to the target density value to form the mask layout in step 2 includes:

[0052] Filling a first auxiliary pattern in a cutting path pattern area of ​​a design layout; then determining whether the pattern density reaches a target density value;

[0053] If yes, the layout after filling the first auxiliary pattern is used as the mask layout;

[0054] If not, the blank area in the design layout is filled with the second auxiliary pattern until the mask layout is obtained.

[0055] It should be noted that in step 2, other methods well known to those skilled in the art may be used to adjust the graphic density of the design layout to the target density value to form the mask layout, which is not specifically limited here.

[0056] Step 3: Using the mask layout and the process menu to manufacture semiconductor devices, products with different pattern densities can be applied to the same process menu after adjusting the pattern density, which reduces the difficulty of manufacturing and production management and improves manufacturing capacity.

[0057] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0058] In summary, the present invention eliminates the need to readjust or develop a new process recipe for design layouts with different pattern densities for different products with the same manufacturing process. After adjusting the pattern density, the final mask layouts used for production of products with different pattern densities have the same pattern density and can be applied using the same process recipe. This speeds up new product development and large-scale production, reduces the difficulty and cost of manufacturing management, and increases manufacturing capacity. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial value.

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing integrated circuits with different density design layouts, characterized in that: At least: Step 1: providing design layouts with different graphic densities for different products, target density values ​​of the graphic density of the design layouts and corresponding process menus, wherein the graphic density is the ratio of the area occupied by the graphic in the layout to the total area of ​​the layout; Step 2: adjusting the pattern density of each of the design layouts to the target density value to form a mask layout for production; Step 3: Using the mask pattern and the same process menu to manufacture semiconductor devices.

2. The method for manufacturing integrated circuits with different density design layouts according to claim 1, characterized in that: The method for obtaining the target density value and the corresponding process menu in step one includes: designing test masks with different graphic densities; adjusting the parameters of the test process menu to perform stability tests on each of the test masks; and selecting the test mask and the test process menu whose stability test results are better than those of other test groups as the target density value and the corresponding process menu.

3. The method for manufacturing integrated circuits with different density design layouts according to claim 3, characterized in that: The parameters of the process menu corresponding to the target density value in step 1 are within 10% of the maximum variation range of the manufacturing process.

4. The method for manufacturing integrated circuits with different density design layouts according to claim 1, characterized in that: The target density value in step 1 meets the design rules for multi-layer layout overlay.

5. The method for manufacturing integrated circuits with different density design layouts according to claim 1, characterized in that: The method of adjusting the pattern density of the design layout to the target density value to form a mask layout in step 2 includes: Determining whether the pattern density of the design layout reaches the target density value; If not, fill the design layout with a first dummy pattern so that the pattern density of the design layout is the target density value, and then fill the design layout with a second dummy pattern so that the pattern density of the design layout is the target density value; wherein the first dummy pattern is the same as or similar to the pattern in the design layout, and the second dummy pattern is a pattern used for circuit matching; If so, fill the design layout with a second dummy pattern, the size of the second dummy pattern is smaller than the first dummy pattern, so that the pattern density of the design layout is the target density value; wherein the second dummy pattern is a pattern used for circuit matching.

6. The method for manufacturing integrated circuits with different density layout designs according to claim 5, characterized in that: The method of filling the design layout with the first dummy pattern in step 2 includes: determining a pattern period of the first dummy pattern, determining a distance of the first pattern from the design layout, and determining a filling range of the first pattern; filling the first pattern on the design layout, and determining whether its pattern density reaches the target density value, If yes, execute the following steps; If not, adjust the graphic period of the first dummy graphic, adjust the distance of the first graphic from the design layout, adjust the filling range of the first graphic, and then re-fill the first graphic on the design layout until its graphic density reaches the target density value.

7. The method for manufacturing integrated circuits with different density design layouts according to claim 1, characterized in that: The cell unit X*Y filling block of the first dummy pattern in step 2 is densely filled with lines and gaps using minimum design rules.

8. The method for manufacturing integrated circuits with different density design layouts according to claim 5, characterized in that: The method of filling the design layout with the second dummy pattern in step 2 includes: determining a pattern period of the second dummy pattern, determining a distance of the second pattern from the design layout, and determining a filling range of the second pattern; filling the second pattern on the design layout, and determining whether its pattern density reaches the target density value, If yes, execute the following steps; If not, adjust the graphic period of the second dummy graphic, adjust the distance of the second graphic from the design layout, adjust the filling range of the second graphic, and then re-fill the first graphic on the design layout until its graphic density reaches the target density value.

9. The method for manufacturing integrated circuits with different density design layouts according to claim 8, characterized in that: The cell unit of the second dummy figure in step 2 is an X*Y rectangle.

10. The method for manufacturing integrated circuits with different density design layouts according to claim 1, characterized in that: The method of adjusting the pattern density of the design layout to the target density value to form a mask layout in step 2 includes: Filling a first auxiliary pattern in the cutting path pattern area of ​​the design layout; then determining whether the pattern density reaches the target density value; If yes, the layout after filling the first auxiliary pattern is used as the mask layout; If not, the blank area in the design layout is filled with the second auxiliary pattern until the mask layout is obtained.

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