Semiconductor structure, memory cell and manufacturing method therefor, memory, and electronic device

Abstract

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor structure, a memory cell and a manufacturing method therefor, a memory, and an electronic device, which are used for enhancing the gate control capability and improving the storage density. The semiconductor structure comprises an active pillar (2), a first gate (3), and a second gate (4), and the active pillar (2) is located in a substrate (1) and extends in a direction perpendicular to the substrate (1); and the top surface of the active pillar (2) is provided with a first accommodating hole (H1) extending towards the bottom surface in the axial direction of the active pillar (2); the first gate (3) fills the first accommodating hole (H1); and the second gate (4) is located on the outer side wall of the active pillar (2).

Description

Semiconductor structure, memory cell and manufacturing method thereof, memory and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on July 20, 2023, with application number 202310896742.6 and invention name “Semiconductor structure, memory cell and preparation method thereof, memory and electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor structure, a memory cell and a method for manufacturing the same, a memory, and an electronic device. Background Art

[0004] In the field of integrated circuit design and manufacturing technology, how to achieve high-density storage cells has always been a difficult problem in the development of dynamic random access memory (DRAM) technology.

[0005] To increase storage density, researchers have developed vertical channel transistor (VCT) technology. Because VCTs have fewer restrictions on gate length and source-drain contact area, they offer advantages in increasing DRAM cell density. For VCTs, a high on-off ratio and low leakage current have a decisive impact on the operating speed, power consumption, and lifespan of DRAM cells. Therefore, optimizing the on-off ratio and leakage current of VCTs has become a pressing issue.

[0006] Summary of the Invention

[0007] According to various embodiments of the present disclosure, a semiconductor structure, a memory cell and a method for manufacturing the same, a memory, and an electronic device are provided.

[0008] According to some embodiments, one aspect of the present disclosure provides a semiconductor structure, which includes an active pillar, a first gate, and a second gate; the active pillar is located in a substrate and extends in a direction perpendicular to the substrate; the top surface of the active pillar has a first accommodating hole extending along its axial direction toward the bottom surface of the active pillar; the first gate fills the first accommodating hole; the top surface of the first gate is connected to the write transistor; the second gate is located on the outer wall of the active pillar.

[0009] In some embodiments, the active pillars include single crystal silicon pillars.

[0010] In some embodiments, the first gate includes a first sub-gate located in the first receiving hole and a second sub-gate located on a top surface of the first sub-gate; and a top surface of the first sub-gate is flush with a top surface of the active pillar.

[0011] According to some embodiments, another aspect of the present disclosure provides a memory cell, the memory cell including a read transistor and a write transistor; the read transistor including the semiconductor structure of the above embodiment; wherein the bottom surface of the active pillar is connected to the read bit line; the second gate is connected to the read word line; the top surface of the first gate is connected to the write transistor,

[0012] In the memory cell of the above embodiment, the write transistor is connected to the top surface of the first gate, which enables vertical stacking of the read transistor and the write transistor, thereby further improving space utilization and facilitating improvement of device integration and storage density.

[0013] In some embodiments, the write transistor includes a third gate and a semiconductor layer; the semiconductor layer is located on the top surface of the first gate; a gate trench is provided in the semiconductor layer; the semiconductor layer on the sidewall of the gate trench is connected to the write bit line; the third gate fills the gate trench; the top surface of the third gate is connected to the write word line; wherein the semiconductor layer and the third gate are insulated from each other; and the write bit line and the write word line are insulated from each other.

[0014] In some embodiments, the semiconductor layer has an extension portion, which is located on a top surface of the write bit line and extends in a direction away from the third gate.

[0015] In some embodiments, the extending direction of the write bit line is the same as the extending direction of the read word line; the extending direction of the write bit line is the same as or different from the extending direction of the write word line.

[0016] According to some embodiments, another aspect of the present disclosure provides a method for preparing a memory cell. In some embodiments, the method includes:

[0017] A patterned substrate is formed in which at least one active pillar is formed; the active pillar extends in a direction perpendicular to the substrate, and a top surface of the active pillar has a first receiving hole extending along an axis thereof toward a bottom surface of the active pillar;

[0018] forming a first gate in the first receiving hole;

[0019] forming a read bit line on the bottom surface of the active pillar;

[0020] forming a second gate and a read word line connected to the second gate on an outer sidewall of the active pillar;

[0021] forming a write transistor on a top surface of the first gate;

[0022] The memory cell includes a read transistor and a write transistor; the read transistor includes an active column, a first gate and a second gate.

[0023] In some embodiments, patterning a substrate, forming at least one active pillar in the substrate, and forming a first gate in a first receiving hole includes:

[0024] Performing a first patterning on the substrate to form a plurality of first receiving holes distributed in an array in the substrate;

[0025] forming a first gate dielectric layer and a first gate electrode in sequence in the first receiving hole;

[0026] The substrate is patterned for the second time to form a plurality of active pillars distributed in an array in the substrate, and each first receiving hole is located at the axis of the active pillar in a one-to-one correspondence.

[0027] In some embodiments, sequentially forming a first gate dielectric layer and a first gate in the first receiving hole includes:

[0028] A first gate dielectric layer and a first sub-gate are sequentially formed in the first receiving hole; a top surface of the first sub-gate is flush with a top surface of the active pillar;

[0029] After forming a second gate and a read word line connected to the second gate on the outer sidewall of the active pillar, forming a second sub-gate located on the top surface of the first sub-gate;

[0030] The first gate includes a first sub-gate and a second sub-gate.

[0031] In some embodiments, forming a read bit line on a bottom surface of an active pillar includes:

[0032] After the substrate is patterned for the second time, a metal silicidation process is performed on the substrate located at the bottom surface of the active pillars based on the interval between adjacent active pillars to form a read bit line extending along the first direction.

[0033] In some embodiments, forming a second gate and a read word line connected to the second gate on an outer sidewall of the active pillar includes:

[0034] After patterning the substrate for the second time, forming a second gate dielectric layer covering the sidewalls of the active pillars, and an isolation material layer covering the second gate dielectric layer and filling the spaces between adjacent active pillars;

[0035] removing a portion of the isolation material layer between adjacent active pillars in a second direction to form an etching hole exposing a sidewall of the second gate dielectric layer; the second direction intersects the first direction;

[0036] Based on the etched hole, the isolation material layer outside the sidewall of the corresponding active pillar in the first direction is etched back to form a second receiving hole on the outer sidewall of the corresponding active pillar;

[0037] A second gate is formed in the second receiving hole, and a read word line connected to the second gate is formed in the etched hole.

[0038] In some embodiments, forming a write transistor on a top surface of the first gate includes:

[0039] forming an interlayer dielectric layer and a write bit line in sequence on the top surface of the first gate in a direction away from the substrate;

[0040] forming a third receiving hole penetrating the interlayer dielectric layer and the write bit line and exposing the top surface of the first gate;

[0041] A semiconductor layer is formed on the inner wall of the third receiving hole and the top surface of the write bit line; the bottom surface of the semiconductor layer is connected to the top surface of the first gate;

[0042] forming a third gate dielectric layer covering the semiconductor layer;

[0043] forming a third gate electrode covering the third gate dielectric layer and filling the third receiving hole, and a write word line connected to the third gate electrode;

[0044] The write transistor includes a semiconductor layer, a third gate dielectric layer and a third gate.

[0045] According to some embodiments, another aspect of the present disclosure provides a memory including the above-mentioned storage unit.

[0046] According to some embodiments, another aspect of the present disclosure provides an electronic device including the above-mentioned memory.

[0047] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0049] FIG1 is a schematic structural diagram of a vertical gate-all-around transistor provided in the related art;

[0050] FIG2 is a schematic structural diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0051] FIG3 is a graph showing the relationship between the subthreshold swing and the first gate width in a semiconductor structure provided in an embodiment of the present disclosure;

[0052] FIG4 is a graph showing the relationship between the switching ratio and the first gate width in a semiconductor structure provided in an embodiment of the present disclosure;

[0053] FIG5 is a schematic structural diagram of a storage unit provided in one embodiment of the present disclosure;

[0054] FIG6 is an equivalent circuit diagram of a memory cell provided in one embodiment of the present disclosure;

[0055] FIG7 is a schematic flow chart of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0056] FIG8 is a schematic diagram of a structure obtained in step S1111 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0057] FIG9 is a schematic diagram of a structure obtained in step S1112 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0058] FIG10 is a schematic diagram of a structure obtained in step S1113 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0059] FIG11 is a schematic diagram of a structure obtained in step S1114 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0060] FIG12 is a schematic diagram of a structure obtained in step S1115 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0061] FIG13 is a schematic diagram of a structure obtained in step S1116 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0062] FIG14 is a schematic diagram of a structure obtained in step S121 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0063] FIG15 is a schematic diagram of a structure obtained in step S1211 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0064] FIG16 is a schematic diagram of a structure obtained in step S1212 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0065] FIG17 is a schematic diagram of a structure obtained in step S1213 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0066] FIG18 is a schematic diagram of a structure obtained by forming a second mask stack in step S13 in a method for manufacturing a memory cell according to an embodiment of the present disclosure;

[0067] FIG19 is a schematic diagram of a structure obtained by forming an active pillar in step S13 in a method for manufacturing a memory cell according to an embodiment of the present disclosure;

[0068] FIG20 is a schematic diagram of a structure obtained in step S411 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0069] FIG21 is a schematic diagram of a structure obtained in step S31 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0070] FIG22 is a schematic diagram of a structure obtained in step S412 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0071] FIG23 is a schematic diagram of a structure obtained in step S413 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0072] FIG24 (a) is a partial enlarged view of the Z region in FIG23, and FIG24 (b) is a cross-sectional view of FIG24 (a) along the AA' direction;

[0073] FIG25 (a) is a schematic diagram of the structure obtained in step S42 of the method for preparing a memory cell provided in one embodiment of the present disclosure, and FIG25 (b) is a cross-sectional view of FIG25 (a) along the AA' direction;

[0074] FIG26 (a) is a schematic diagram of the structure obtained in step S43 of the method for preparing a memory cell provided in one embodiment of the present disclosure, and FIG26 (b) is a cross-sectional view of FIG26 along the AA′ direction;

[0075] FIG27 (a) is a schematic diagram of the structure obtained in step S44 of the method for preparing a memory cell provided in one embodiment of the present disclosure, and FIG27 (b) is a cross-sectional view of FIG27 (a) along the AA' direction;

[0076] FIG28 is a schematic diagram of a structure obtained in step S1221 of a method for manufacturing a memory cell according to an embodiment of the present disclosure;

[0077] FIG29 is a schematic diagram of a structure obtained in step S1222 of a method for manufacturing a memory cell according to an embodiment of the present disclosure;

[0078] FIG30 is a schematic diagram of a structure obtained by forming a dielectric material layer in a method for preparing a memory cell provided in an embodiment of the present disclosure;

[0079] FIG31 is a schematic diagram of a structure obtained by forming an isolation dielectric layer in a method for preparing a memory cell provided in an embodiment of the present disclosure;

[0080] FIG32 is a schematic diagram of a structure obtained in step S51 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0081] FIG33 is a schematic diagram of a structure obtained in step S52 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0082] FIG34 is a schematic diagram of a structure obtained in step S53 of a method for preparing a memory cell according to an embodiment of the present disclosure;

[0083] FIG35 is a schematic diagram of a structure obtained in step S54 in the method for preparing a memory cell provided in one embodiment of the present disclosure;

[0084] FIG36 is a schematic diagram of the structure obtained in step S55 of the method for preparing a memory cell provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0085] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0086] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0087] The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. Where "include," "have," and "comprises" are used herein, another component may be added unless a clear limiting term, such as "only," "consisting of," or the like, is used. Unless otherwise noted, a term in the singular may include a plural form and is not to be construed as being one.

[0088] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0089] In the description of this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0090] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0091] Referring to Figure 1, vertical gate-all-around transistors have broad application prospects as DRAM conduction control transistors due to their excellent gate control capability and high on-off ratio. However, as feature sizes continue to scale, the gate control capability and on-off ratio of vertical gate-all-around transistors decrease. In traditional vertical gate-all-around transistors, a channel layer made of indium gallium zinc oxide (IGZO) material is typically formed in the active pillar 2, which reduces the memory read speed. In addition, the IGZO material has poor compatibility with the silicon-based semiconductor materials used in peripheral device processes.

[0092] In view of the above-mentioned deficiencies in the prior art, the present application provides a semiconductor structure and a method for manufacturing the same, the details of which will be described in subsequent embodiments.

[0093] According to some embodiments, the present disclosure provides a semiconductor structure.

[0094] As an example, the semiconductor structure described above can be used to form a semiconductor device (e.g., a DRAM). The DRAM may include a transistor structure and an equivalent capacitor connected to the transistor structure. The equivalent capacitor is used to store data, and the transistor structure is used to read data from the equivalent capacitor or write data to the equivalent capacitor. It is understood that the semiconductor structure provided in the embodiment of the present application can be directly used as a transistor structure in a DRAM or as a component of a transistor structure. For example, it can be a transistor in a 2TOC structure, but the present invention is not limited thereto. The semiconductor structure provided in the embodiment of the present application can also be used as other structures.

[0095] Please refer to Figure 2.

[0096] The semiconductor structure includes an active pillar 2, a first gate 3 and a second gate 4; the active pillar 2 is located in the substrate and extends in a direction perpendicular to the substrate; the top surface of the active pillar 2 has a first accommodating hole H1 extending along its axial direction toward the bottom surface of the active pillar 2; the first gate 3 fills the first accommodating hole H1; the second gate 4 is located on the outer wall of the active pillar 2.

[0097] In the semiconductor structure of the above embodiment, a vertical active pillar 2 is formed inside the substrate, and the semiconductor structure is arranged inside the substrate, which is different from the method of forming a transistor on the surface of the substrate through multiple film layers. In addition, by filling the first receiving hole H1 in the active pillar 2 with a first gate 3 and setting the second gate 4 on the outer wall of the active pillar 2, the semiconductor structure has a dual-gate structure, wherein the first gate 3 is used to store or release charge, and the second gate 4 is used to control the on and off of the semiconductor structure. The semiconductor structure with a dual-gate structure is conducive to increasing the contact area between the gate and the channel of the semiconductor structure, thereby enhancing the gate control capability of the gate, thereby reducing the subthreshold swing (SS), improving the switching ratio of the semiconductor structure, and enhancing the electrical performance of the semiconductor structure in the above embodiment.

[0098] It is understood that subthreshold swing is a performance indicator that measures the rate of transition between the on and off states of a semiconductor device. It represents the change in gate voltage required for a tenfold change in source-drain current. In the above embodiment, the subthreshold swing can vary with the width IGL of the first gate 3.

[0099] For example, the width IGL of the first gate 3 may be 1 nm to 3 nm; for example, the width IGL of the first gate 3 may be 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm.

[0100] 2 and 3 , the subthreshold swing can be reduced as the width IGL of the first gate 3 increases. For example, compared with the related art, the subthreshold swing of the semiconductor structure provided in the embodiment of the present application can be reduced by 15%.

[0101] Accordingly, as can be understood from the combination of Figures 2 and 4 , a smaller subthreshold swing means a faster on-off ratio. In other words, the on-off ratio can be improved as the width IGL of the first gate 3 increases. Therefore, the semiconductor structure provided in the above-described embodiment has a higher on-off ratio, which is beneficial for improving the electrical performance of the semiconductor device. For example, compared to related technologies, the semiconductor structure provided in the embodiment of the present application can improve the on-off ratio by an order of magnitude.

[0102] Please continue to refer to Figure 2. An active pillar 2 perpendicular to the substrate and a second gate 4 located on the outer wall of the active pillar 2 are formed in the substrate, so that the semiconductor structure has a vertical channel structure. Therefore, more active pillars 2 can be set while occupying the same substrate area, thereby further improving space utilization, which is conducive to improving device integration and storage density.

[0103] In some embodiments, active pillars 2 include single-crystal silicon pillars. Compared to related technologies using IGZO as the channel material, the use of single-crystal silicon pillars in this embodiment improves compatibility with silicon-based semiconductor materials used in peripheral device processes. Furthermore, semiconductor structures using single-crystal silicon pillars have faster read speeds, which helps improve the read speed of the semiconductor structure.

[0104] In some embodiments, the first gate 3 includes a first sub-gate 31 located within the first receiving hole H1 and a second sub-gate 32 located on top of the first sub-gate 31. The top surface of the first sub-gate 31 is flush with the top surface of the active pillar 2. An isolation dielectric layer is formed around the second sub-gate 32 to prevent leakage of charge stored in the first gate 3 and effectively reduce leakage current.

[0105] In some embodiments, as shown in FIG2(b), the second gate 4 can be disposed around the active pillar 2, i.e., the second gate 4 has a gate-all-around (GAA) structure. This further increases the contact area between the gate and the active pillar 2, further improving gate control capability. Furthermore, the GAA structure helps save structural size, further increasing the distribution density of the semiconductor structure, and thus further improving the storage density of the device.

[0106] According to some embodiments, the present disclosure also provides a storage unit.

[0107] As an example, the above-mentioned memory cell can be used as a component of a transistor structure and an equivalent capacitor in a DRAM, for example, a 2T0C structure, but is not limited to this. The memory cell provided in the embodiment of the present application can also be used as other structures.

[0108] 5 , in some embodiments, a memory cell U includes a read transistor T1 and a write transistor T2. The read transistor T1 includes the semiconductor structure described in the above embodiments. In some embodiments, the memory cell U may have a 2T0C structure composed of the read transistor T1 and the write transistor T2.

[0109] In some embodiments, the bottom surface of the active pillar 2 is connected to the read bit line; the second gate 4 is connected to the read word line; and the top surface of the first gate 3 is connected to the write transistor T2.

[0110] In the memory cell of the above embodiment, the write transistor T2 is connected to the top surface of the first gate 3, which enables vertical stacking of the read transistor T1 and the write transistor T2, thereby further improving space utilization and facilitating improvement of device integration and storage density.

[0111] In some embodiments, the semiconductor structure further includes a first gate dielectric layer 33 . The first gate dielectric layer 33 covers the surface of the first receiving hole H1 and is located between the first sub-gate 31 and the active pillar 2 .

[0112] In some embodiments, the semiconductor structure further includes a second gate dielectric layer 41 . The second gate dielectric layer 41 is located on the sidewall of the active pillar 2 and at least between the second gate 4 and the active pillar 2 .

[0113] In some embodiments, write transistor T2 includes a third gate 5 and a semiconductor layer 6. Semiconductor layer 6 is located on the top surface of first gate 3. Semiconductor layer 6 has a gate trench. The sidewalls of semiconductor layer 6 are connected to write bit line WBL. Third gate 5 fills the gate trench. The top surface of third gate 5 is connected to write word line WWL. Write bit line WBL and write word line WWL are insulated from each other. Third gate 5 is connected to write word line WWL to control the on / off state of write transistor T2. Write bit line WBL is used to write a level signal to memory cell U to store data.

[0114] In some embodiments, the semiconductor structure further includes a third gate dielectric layer 51 , which conformally covers the semiconductor layer 6 . The semiconductor layer 6 and the third gate 5 are insulated from each other by the third gate dielectric layer 51 .

[0115] FIG6 is an equivalent circuit of the semiconductor structure in this embodiment. The memory unit U can be equivalent to a 2T0C memory circuit composed of a read transistor T1 and a write transistor T2. Please understand in conjunction with FIG5 and FIG6 that the first gate 3 can be used to store charge. For example, the first gate 3 and the active pillar 2 and the first gate dielectric layer 33 therebetween can be equivalent to a capacitor. The connection between the first gate 3 and the semiconductor layer 6 corresponds to the storage node SN shown in FIG5. One end of the active pillar 2 is connected to the read bit line RBL, and the other end of the active pillar 2 is applied with a reference voltage Vref. For example, the end of the active pillar 2 away from the write transistor T2 is connected to the read bit line RBL as the source of the read transistor T1, and the other end of the active pillar 2 is applied with a reference voltage Vref as the drain of the read transistor T1.

[0116] For example, when the memory cell U of this embodiment performs a write operation, the write word line WWL applies a control level through the third gate 5, so that the write transistor T2 is turned on. At the same time, the write bit line WBL is used to provide a data level to the memory cell U, which is written into the first gate 3 through the semiconductor layer 6, so that the charge is stored in the first gate 3 to realize the writing of data.

[0117] Accordingly, when the memory cell U of this embodiment performs a read operation, the read word line RWL applies a control voltage level through the second gate 4, turning on the read transistor T1. When charge is stored in the first gate 3, due to the potential difference between the data level stored in the first gate 3 and the reference voltage Vref, the charge stored in the first gate 3 enters the active pillar 2 based on the tunneling effect and other related principles, causing the potential of the end of the active pillar 2 connected to the read bit line RBL to change. This potential change is then detected by the read bit line RBL, thereby enabling data to be read.

[0118] It can be understood that the write operation and the read operation of the storage unit U in the embodiment of the present disclosure can be performed separately.

[0119] Please continue to refer to Figure 5. In some embodiments, the semiconductor layer 6 has an extension portion, which is located on the top surface of the write bit line WBL and extends in a direction away from the third gate 5 to increase the contact area between the semiconductor layer 6 and the write bit line WBL, thereby reducing the contact resistance between the two.

[0120] In some embodiments, the extending direction of the write bit line WBL is the same as the extending direction of the read word line RWL; the extending direction of the write bit line WBL is the same as or different from the extending direction of the write word line WWL.

[0121] Illustratively, the material of the semiconductor layer 6 includes a metal oxide semiconductor of at least one of indium, gallium, zinc or tin, such as indium gallium zinc oxide (IGZO), so as to reduce leakage current of the write transistor T2 and thereby ensure reliability of the write transistor T2.

[0122] In some embodiments, the semiconductor layer 6 can be arranged around the third gate 5, that is, the write transistor T2 can adopt a channel-all-around (CAA) structure, which is beneficial to saving structure size, thereby increasing the distribution density of the storage unit U and thus increasing the storage density of the device.

[0123] According to some embodiments, the present application also provides a method for preparing a memory cell, which is used to prepare the memory cell provided in some of the above embodiments.

[0124] Referring to FIG. 7 , in some embodiments, a method for preparing a memory cell may include the following steps:

[0125] S10: patterning the substrate to form at least one active pillar in the substrate; the active pillar extends in a direction perpendicular to the substrate, and a top surface of the active pillar has a first receiving hole extending along an axis thereof toward a bottom surface of the active pillar;

[0126] S20: forming a first gate in the first receiving hole;

[0127] S30: forming a read bit line on the bottom surface of the active pillar;

[0128] S40: forming a second gate and a read word line connected to the second gate on an outer sidewall of the active pillar;

[0129] S50: forming a write transistor on a top surface of the first gate;

[0130] The memory cell includes a read transistor and a write transistor; the read transistor includes an active column, a first gate and a second gate.

[0131] In the preparation method of the memory cell of the above embodiment, the active column is prepared by patterning the substrate, so that the active column and the first receiving hole therein are both formed inside the substrate. In this way, in the preparation process of the active column in the read transistor, it can be achieved only by patterning the substrate, without the need to form multiple film layers on the substrate, which can simplify the process flow and save production costs. In addition, by forming the first gate in the first receiving hole and forming the second gate on the outer wall of the active column, the read transistor including the active column, the first gate and the second gate has a dual-gate structure. At the same time, the write transistor is formed on the top surface of the first gate, which can realize the vertical stacking of the read transistor and the write transistor.

[0132] In some embodiments, step S10 of patterning the substrate, forming at least one active pillar in the substrate, and forming a first gate in the first receiving hole includes:

[0133] S11: performing a first patterning on the substrate to form a plurality of first receiving holes distributed in an array in the substrate;

[0134] S12: forming a first gate dielectric layer and a first gate in sequence in the first receiving hole;

[0135] S13: performing a second patterning on the substrate to form a plurality of active pillars distributed in an array in the substrate, and making the first receiving holes correspond one to one and be located at the axis of the active pillar.

[0136] In some embodiments, step S12, sequentially forming a first gate dielectric layer and a first gate in the first receiving hole, includes:

[0137] S121: forming a first gate dielectric layer and a first sub-gate in sequence in the first receiving hole; a top surface of the first sub-gate is flush with a top surface of the active pillar;

[0138] S122: After forming a second gate and a read word line connected to the second gate on an outer sidewall of the active pillar, forming a second sub-gate located on a top surface of the first sub-gate;

[0139] The first gate includes a first sub-gate and a second sub-gate.

[0140] In some embodiments, step S30 of forming a read bit line on the bottom surface of the active pillar includes:

[0141] S31: After the substrate is patterned for the second time, a metal silicidation process is performed on the substrate located at the bottom surface of the active pillars based on the interval between adjacent active pillars to form a read bit line extending along the first direction.

[0142] In some embodiments, step S40 of forming a second gate and a read word line connected to the second gate on the outer sidewall of the active pillar includes:

[0143] S41: After patterning the substrate for the second time, forming a second gate dielectric layer covering the sidewalls of the active pillars, and an isolation material layer covering the second gate dielectric layer and filling the spaces between adjacent active pillars;

[0144] S42: removing a portion of the isolation material layer between adjacent active pillars in a second direction to form an etching hole exposing a sidewall of the second gate dielectric layer; the second direction intersects the first direction;

[0145] S43: etching back the isolation material layer outside the sidewall of the corresponding active pillar in the first direction based on the etched hole to form a second receiving hole on the outer sidewall of the corresponding active pillar;

[0146] S44: forming a second gate in the second receiving hole, and forming a read word line connected to the second gate in the etched hole.

[0147] In some embodiments, step S50, forming a write transistor on the top surface of the first gate, includes:

[0148] S51: forming an interlayer dielectric layer and a write bit line in sequence on a top surface of the first gate in a direction away from the substrate;

[0149] S52: forming a third receiving hole penetrating the interlayer dielectric layer and the write bit line and exposing the top surface of the first gate;

[0150] S53: forming a semiconductor layer on the inner wall of the third receiving hole and the top surface of the write bit line; the bottom surface of the semiconductor layer is connected to the top surface of the first gate;

[0151] S54: forming a third gate dielectric layer covering the semiconductor layer;

[0152] S55: forming a third gate electrode covering the third gate dielectric layer and filling the third receiving hole, and a write word line connected to the third gate electrode;

[0153] The write transistor includes a semiconductor layer, a third gate dielectric layer and a third gate.

[0154] It should be understood that, although the various steps in the flowchart of FIG7 are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in FIG7 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0155] In order to more clearly illustrate the preparation methods of the memory cells provided in some of the above embodiments, please refer to Figures 8 to 36 below to understand some embodiments of the present application.

[0156] The embodiments of the present application do not specifically limit the constituent materials of the substrate 1. As an example, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate 1, a silicon germanium (SiGe) substrate 1, a silicon germanium carbon (SiGeC) substrate 1, a silicon carbide (SiC) substrate 1, a gallium arsenide (GaAs) substrate 1, an indium arsenide (InAs) substrate 1, an indium phosphide (InP) substrate 1 or other III / V semiconductor substrate 1 or II / VI semiconductor substrate 1. Alternatively, for example, the substrate 1 can be a layered substrate 1 including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on insulator.

[0157] 8 to 14 , in step S11 , the first patterning of the substrate 1 is not limited to a single patterning process, and the first patterning may include multiple patterning processes. In some embodiments, step S11 may include:

[0158] S111: forming a patterned mask stack on the substrate 1, wherein the patterned mask stack defines a position of the first receiving hole H1;

[0159] S112 : performing a first patterning on the substrate 1 based on the patterned mask stack to form a plurality of first receiving holes H1 distributed in an array in the substrate 1 .

[0160] For example, a self-aligned double patterning (SADP) process may be used to form a patterned mask stack on the substrate 1, specifically comprising:

[0161] S1111: As shown in FIG8 , forming a first mask stack 7 on the surface of the substrate 1; the first mask stack 7 may include a first silicon oxide layer 71, a first polysilicon layer 72, a first silicon oxynitride layer 73, a first spin-on hard mask layer 74, and a second silicon oxynitride layer 75 sequentially deposited on the surface of the substrate 1;

[0162] S1112: As shown in FIG9 , a photoresist (PR) layer is formed on the surface of the first mask stack 7, and the photoresist layer is exposed and developed to form a first pattern in the photoresist layer, thereby forming a first patterned photoresist layer 76;

[0163] S1113: As shown in FIG10 , the first silicon oxynitride layer 73 and the first spin-on hard mask layer 74 are etched based on the first patterned photoresist layer 76 to transfer the first pattern into the first silicon oxynitride layer 73 and the first spin-on hard mask layer 74; the first patterned photoresist layer 76 is removed;

[0164] S1114: As shown in FIG11 , a second silicon oxide layer 77 is deposited on the sidewalls and top of the first silicon oxynitride layer 73 and the first spin-on hard mask layer 74 ;

[0165] S1115: As shown in FIG12 , the structure obtained in step 114 is etched back to remove the first silicon oxynitride layer 73, the first spin-on hard mask layer 74, and a portion of the second silicon oxide layer 77. The remaining second silicon oxide layer 77 has a second pattern. For example, this step can be etched back using anisotropic etching. Anisotropic etching can selectively etch material in a predetermined crystal direction or crystal plane direction, while leaving little or no etching marks in other directions. Using anisotropic etching for etching back in this step can make the morphology of the obtained structure more precise and controllable.

[0166] S1116: As shown in FIG13 , etching the first polysilicon layer 72 and the first silicon oxynitride layer 73 based on the second pattern to form a patterned mask stack;

[0167] As shown in FIG. 14 , in step S112 , the substrate 1 is etched based on the patterned mask stack to form a plurality of first receiving holes H1 distributed in an array in the substrate 1 .

[0168] Here, in some embodiments, it can be understood from FIG. 13 to FIG. 14 that the first silicon oxide layer 71 is etched while the substrate 1 is etched based on the patterned mask stack; and the remaining first silicon oxide layer 71 is removed.

[0169] For example, in step S111, the first spin-on hard mask layer 74 can be formed by a spin coating process; for example, the first spin-on hard mask layer 74 can be an insulating layer of a carbon-hydrogen (CxHy) system, which can include silicon hard mask materials, carbon hard mask materials, and organic hard mask materials, etc.

[0170] Referring to FIG. 15 and FIG. 16 , in step S121 , a first gate dielectric layer 33 and a first sub-gate 31 are sequentially formed in the first receiving hole H1 , specifically including:

[0171] S1211: As shown in FIG15 , forming a first gate dielectric material layer 331 , the first gate dielectric material layer 331 conformally covering the outer surface of the active pillar 2 ;

[0172] S1212: As shown in FIG16 , forming a first conductive layer 311 covering the first gate dielectric material layer 331 and filling the first receiving hole H1;

[0173] S1213: As shown in Figure 17, the first conductive layer 311 and the first gate dielectric material layer 331 are etched back until the top surface of the active pillar 2 is exposed; the remaining first conductive layer 311 serves as the first sub-gate 31, and the top surface of the first sub-gate 31 is flush with the top surface of the active pillar 2; the remaining first gate dielectric material layer 331 serves as the first gate dielectric layer 33.

[0174] 18 and 19 , in step S13 , the second patterning of the substrate 1 is not limited to a single patterning process, and the second patterning may also include multiple patterning processes.

[0175] For example, the substrate 1 may be patterned a second time using a self-aligned double patterning (SADP) process to form a plurality of active pillars 2 distributed in an array in the substrate 1 , and each first receiving hole H1 is located at the axis of the active pillar 2 in a one-to-one correspondence.

[0176] As shown in FIG18 , a second mask stack 8 can be formed on the surface of substrate 1. Second mask stack 8 can include a third silicon oxide layer 81, a second polysilicon layer 82, a third silicon oxynitride layer 83, a second spin-on hard mask layer 84, and a fourth silicon oxynitride layer 85, sequentially deposited on the surface of substrate 1. Substrate 1 can be patterned a second time based on second mask stack 8 using steps identical or similar to steps S111 to S117 to form a plurality of active pillars 2 distributed in an array within substrate 1, as shown in FIG19 . These steps will not be described in detail herein.

[0177] 20 to 23 , in step S41 , after the substrate 1 is patterned for the second time, a second gate dielectric layer 41 covering the sidewalls of the active pillars 2 and an isolation material layer 91 covering the second gate dielectric layer 41 and filling the spaces between adjacent active pillars 2 are formed. This may include:

[0178] S411: As shown in FIG20 , forming a second gate dielectric material layer 411 covering the sidewalls of the active pillar 2;

[0179] S412 : As shown in FIG. 22 , covering the second gate dielectric layer 41 and filling the isolation material layer 91 between adjacent active pillars 2 ;

[0180] S413 : as shown in FIG. 23 , the structure obtained in step 412 is etched back until the top surface of the active pillar 2 is exposed; the remaining second gate dielectric material layer 411 serves as the second gate dielectric layer 41 .

[0181] Referring to FIG. 21 , for example, after step S411 , step S31 may be performed. After the substrate 1 is patterned for the second time, a metal silicidation process is performed on the substrate 1 located at the bottom surface of the active pillars 2 based on the interval between adjacent active pillars 2 to form a read bit line RBL extending along the first direction. Specifically, the process includes:

[0182] S311: etching and removing the second gate dielectric layer 41 at the bottom to expose the substrate 1 thereunder;

[0183] S312: forming a metal layer in the portion of the substrate 1 exposed at the bottom of the second gate dielectric layer 41;

[0184] S313 : performing heat treatment on the metal layer to diffuse the metal layer along the first direction and connect the metal layers to each other, thereby forming a read bit line RBL extending along the first direction.

[0185] For example, the first direction may be the X direction shown in FIG. 21 .

[0186] Figure 24 (a) is a partial enlarged view of the Z region in Figure 23, and Figure 24 (b) is a cross-sectional view of Figure (a) along the AA' direction. The meanings of Figures 25 to 27 are roughly the same as those of Figure 24 and will not be repeated here.

[0187] Please refer to Figures 24 and 25. In step S42, part of the isolation material layer 91 between adjacent active pillars 2 in the second direction is removed to form an etching hole EH exposing the side wall of the second gate dielectric layer 41; the second direction intersects with the first direction; illustratively, the second direction is the Y direction shown in Figure 25.

[0188] For example, the step of forming the etching hole EH may include:

[0189] S421: forming a receiving groove extending along the second direction between adjacent first gates 3, and forming an etch stop layer in the receiving groove; the material of the etch stop layer is different from that of the isolation material layer 91;

[0190] S422 : etching portions of the isolation material layer 91 between adjacent active pillars 2 in the second direction along the first direction to form etching holes EH exposing sidewalls of the second gate dielectric layer 41 .

[0191] 26 , in step S43 , the isolation material layer 91 outside the sidewall of the corresponding active pillar 2 in the first direction is etched back based on the etched hole EH to form a second receiving hole H2 on the outer sidewall of the corresponding active pillar 2 .

[0192] It is worth noting that in step S42 and step S43 , the width of the etched hole EH along the first direction is greater than the width of the active pillar 2 along the first direction, so that the second receiving hole H2 can expose the sidewall of the second gate dielectric layer 41 along the first direction.

[0193] It should be noted that in FIG. 24 ( b ), the orthographic projection shape of the active pillar 2 is only for illustration, and the shape of the active pillar 2 is not limited here. Accordingly, the shape of the etched hole EH is also not limited.

[0194] Referring to FIG. 27 , in step S44 , a second gate 4 is formed in the second receiving hole H2 , and a read word line RWL connected to the second gate 4 is formed in the etched hole EH.

[0195] Here, it can be understood that the second gate 4 and the read word line RWL are an integrated structure and can be simultaneously formed in the etched hole EH and the second receiving hole H2 through a one-time deposition process.

[0196] 28 and 29 , after forming the second gate 4 and the read word line RWL connected to the second gate 4 on the outer wall of the active pillar 2 , step S122 is performed to form the second sub-gate 32 located on the top surface of the first sub-gate 31 , specifically including:

[0197] S1221: As shown in FIG28 , forming a second conductive layer 321 covering the structure obtained in step 40 above;

[0198] S1222 : as shown in FIG. 29 , a portion of the second conductive layer 321 is removed to form a second sub-gate 32 located on the top surface of the first sub-gate 31 .

[0199] For example, the material of the second sub-gate 32 may be the same as or similar to the material of the first sub-gate 31 . The material of the second sub-gate 32 and the material of the first sub-gate 31 include metal, such as tungsten.

[0200] 30 to 31 , a dielectric material layer 921 is formed covering the second sub-gate 32 and the isolation material layer 91 ; the dielectric material layer 921 is etched back until the top surface of the second sub-gate 32 is exposed, and the remaining dielectric material layer serves as the isolation dielectric layer 92 .

[0201] For example, the material of the isolation material layer 91 may include but is not limited to silicon nitride. The material of the isolation dielectric layer 92 may include but is not limited to silicon oxide.

[0202] Referring to FIG. 32 , in step S51 , an interlayer dielectric layer 93 and a write bit line WBL are sequentially formed on the top surface of the first gate 3 in a direction away from the substrate 1 .

[0203] For example, the material of the write bit line WBL may include, but is not limited to, nickel and titanium.

[0204] Referring to FIG. 33 , in step S52 , a third receiving hole H3 is formed that penetrates the interlayer dielectric layer 93 and the write bit line WBL and exposes the top surface of the first gate 3 .

[0205] For example, the material of the interlayer dielectric layer 93 may include but is not limited to silicon oxide.

[0206] 34 , in step S53 , a semiconductor layer 6 is formed on the inner wall of the third receiving hole H3 and the top surface of the write bit line WBL; the bottom surface of the semiconductor layer 6 is connected to the top surface of the first gate 3 .

[0207] Referring to FIG. 35 , in step S54 , a third gate dielectric layer 51 covering the semiconductor layer 6 is formed.

[0208] For example, the material of the third gate dielectric layer 51 may be the same as or similar to the material of the first gate dielectric layer 33 and the material of the second gate dielectric layer 41. For example, the material of the first gate dielectric layer 33, the material of the second gate dielectric layer 41, and the material of the third gate dielectric layer 51 may include at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0209] 36 , in step S55 , a third gate 5 covering the third gate dielectric layer 51 and filling the third receiving hole H3 , and a write word line WWL connected to the third gate 5 are formed.

[0210] Illustratively, the material of the write word line WWL includes metal, such as tungsten.

[0211] In some embodiments, a memory is provided, comprising the above-mentioned storage unit.

[0212] In some embodiments, an electronic device is provided, comprising the above-mentioned memory. Due to the use of a memory with better performance and reliability, the electronic device of this embodiment has more beneficial performance and higher reliability.

[0213] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0214] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0215] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0216] The above embodiments merely illustrate several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, wherein: include: An active column is located in the substrate and extends in a direction perpendicular to the substrate; the top surface of the active column has a first receiving hole extending toward the bottom surface along the axis direction thereof; A first gate, filling the first containing hole; The second gate is located on the outer side wall of the active column.

2. The semiconductor structure according to claim 1, wherein: The active pillars include single crystal silicon pillars.

3. The semiconductor structure according to claim 1 or 2, wherein: The first gate includes a first sub-gate located in the first containing hole and a second sub-gate located on the top surface of the first sub-gate; the top surface of the first sub-gate is flush with the top surface of the active pillar.

4. A storage unit, wherein: It comprises a read transistor and a write transistor; the read transistor comprises a semiconductor structure as described in any one of claims 1 to 3; wherein the bottom surface of the active column is connected to the read bit line; the second gate is connected to the read word line; and the top surface of the first gate is connected to the write transistor.

5. The storage unit according to claim 4, wherein: The write transistor comprises: A semiconductor layer is located on the top surface of the first gate; a gate trench is provided in the semiconductor layer; and the semiconductor layer on the sidewall of the gate trench is connected to a write bit line; A third gate electrode fills the gate trench; a top surface of the third gate electrode is connected to a write word line; The semiconductor layer and the third gate are insulated from each other; the write bit line and the write word line are insulated from each other.

6. The storage unit according to claim 5, wherein: The semiconductor layer has an extension portion, which is located on a top surface of the write bit line and extends in a direction away from the third gate.

7. The storage unit according to claim 5 or 6, wherein: The extending direction of the write bit line is the same as the extending direction of the read word line; An extension direction of the write bit line is the same as or different from an extension direction of the write word line.

8. A method for preparing a storage unit, wherein: The method comprises: A patterned substrate, wherein at least one active column is formed in the substrate; the active column extends in a direction perpendicular to the substrate, and the top surface of the active column has a first receiving hole extending along the axis direction thereof toward the bottom surface of the active column; forming a first gate in the first receiving hole; forming a read bit line on the bottom surface of the active pillar; forming a second gate and a read word line connected to the second gate on an outer sidewall of the active column; forming a write transistor on a top surface of the first gate; Wherein, the storage unit includes a read transistor and the write transistor; the read transistor includes the active column, the first gate and the second gate.

9. The method for preparing a storage unit according to claim 8, wherein: The patterned substrate, forming at least one active pillar in the substrate, and the first gate formed in the first receiving hole, include: Performing a first patterning on the substrate to form a plurality of the first receiving holes distributed in an array in the substrate; forming a first gate dielectric layer and a first gate electrode in the first receiving hole in sequence; The substrate is patterned for the second time to form a plurality of active pillars distributed in an array in the substrate, and each of the first receiving holes is located at the axis of the active pillar in a one-to-one correspondence.

10. The method for preparing a memory cell according to claim 9, wherein: The step of sequentially forming a first gate dielectric layer and a first gate electrode in the first receiving hole comprises: The first gate dielectric layer and the first sub-gate are sequentially formed in the first receiving hole; the top surface of the first sub-gate is flush with the top surface of the active pillar; After forming a second gate and a read word line connected to the second gate on the outer sidewall of the active pillar, forming a second sub-gate located on the top surface of the first sub-gate; Wherein, the first gate includes the first sub-gate and the second sub-gate.

11. The method for preparing a storage unit according to claim 9 or 10, wherein: The forming of a read bit line on the bottom surface of the active pillar comprises: After the substrate is patterned for the second time, a metal silicidation process is performed on the substrate located at the bottom surface of the active pillars based on the interval between adjacent active pillars to form the read bit line extending along the first direction.

12. The method for preparing a storage unit according to any one of claims 9 to 11, wherein: The second gate and the read word line connected to the second gate are formed on the outer sidewall of the active column, comprising: After patterning the substrate for the second time, forming a second gate dielectric layer covering the sidewalls of the active pillars, and an isolation material layer covering the second gate dielectric layer and filling the spaces between adjacent active pillars; removing a portion of the isolation material layer between adjacent active pillars in a second direction to form an etching hole exposing a sidewall of the second gate dielectric layer; the second direction intersects the first direction; Based on the etched hole, the isolation material layer corresponding to the outer side wall of the active column in the first direction is etched back to form a second receiving hole on the outer side wall corresponding to the active column; The second gate is formed in the second receiving hole, and the read word line connected to the second gate is formed in the etched hole.

13. The method for preparing a storage unit according to any one of claims 9 to 12, wherein: The step of forming a write transistor on the top surface of the first gate comprises: forming an interlayer dielectric layer and a write bit line in sequence on the top surface of the first gate in a direction away from the substrate; forming a third receiving hole penetrating the interlayer dielectric layer and the write bit line and exposing the top surface of the first gate; A semiconductor layer is formed on the inner wall of the third receiving hole and the top surface of the write bit line; the bottom surface of the semiconductor layer is connected to the top surface of the first gate; forming a third gate dielectric layer covering the semiconductor layer; forming a third gate electrode covering the third gate dielectric layer and filling the third receiving hole, and a write word line connected to the third gate electrode; Wherein, the write transistor includes the semiconductor layer, the third gate dielectric layer and the third gate.

14. A memory, wherein: include: A storage unit as claimed in any one of claims 4 to 6.

15. An electronic device, wherein: include: The memory as claimed in claim 14.

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