Semiconductor device structure and preparation method therefor, and electronic device

Abstract

The embodiments of the present disclosure relate to a semiconductor device structure and a preparation method therefor, and an electronic device, which relate to the field of semiconductors, and are used for simplifying the preparation process of the semiconductor device structure and improving the space utilization rate. The semiconductor device structure comprises: a substrate (10), a transistor (20) array, and a plurality of capacitors (30). The transistor (20) array is located on the substrate (10), and the transistor (20) array comprises a plurality of transistors (20), wherein the plurality of transistors (20) are arranged at intervals in a first direction, a second direction and a third direction respectively. The first direction is perpendicular to the upper surface of the substrate (10), the second direction and the third direction are both parallel to the upper surface of the substrate (10), and the second direction intersects with the third direction. One electrode of at least one capacitor (30) surrounds one transistor (20).

Description

Semiconductor device structure and manufacturing method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on July 18, 2023, with application number 2023108829958 and invention name “Semiconductor device structure, preparation method thereof, and electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor device structure and a preparation method thereof, and electronic equipment. Background Art

[0004] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0005] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands.

[0006] Summary of the Invention

[0007] An embodiment of the present disclosure provides a semiconductor device structure, including: a substrate, a transistor array, and multiple capacitors, wherein the transistor array is located on the substrate, the transistor array includes multiple transistors, and the multiple transistors are arranged at intervals along a first direction, a second direction, and a third direction, respectively. The first direction is perpendicular to the upper surface of the substrate, the second direction and the third direction are both parallel to the upper surface of the substrate, and the second direction intersects with the third direction; wherein one electrode of at least one capacitor surrounds one transistor.

[0008] In some embodiments, a transistor includes: a gate conductive layer, a gate dielectric layer, and a channel layer. The gate conductive layer extends along a second direction; the gate dielectric layer is located on a surface of the gate conductive layer; the channel layer is located on a surface of the gate dielectric layer away from the gate conductive layer; and one electrode of the capacitor is located on a surface of the channel layer.

[0009] In some embodiments, the channel layer surrounds the gate conductive layer; the capacitor includes a first electrode, a capacitor dielectric layer, and a second electrode stacked sequentially from the inside to the outside; the second electrode of the capacitor surrounds the channel layer, wherein the channel layer also serves as the first electrode of the capacitor.

[0010] In some embodiments, the material of the channel layer includes indium gallium zinc oxide.

[0011] In some embodiments, the semiconductor device structure further includes: a plurality of bit lines, which are stacked and spaced apart along a first direction and extend along a third direction; transistors spaced apart along a second direction are respectively located on opposite sides of the bit lines and in contact with the bit lines located in the same layer.

[0012] In some embodiments, the bit line contacts the channel layers of transistors located at the same layer on both sides of the bit line.

[0013] In the embodiment of the present application, multiple bit lines are stacked and spaced apart along a first direction, and transistors are positioned on opposite sides of the bit lines, contacting the bit lines on the same layer. This facilitates the integrated layout of transistors, capacitors, and bit lines, and increases the density of semiconductor devices per unit wafer area.

[0014] In some embodiments, a plurality of capacitors are disposed corresponding to the transistors and surround the corresponding transistors respectively; and the plurality of capacitors located on the same side of the bit line share a common second electrode.

[0015] In the embodiment of the present application, capacitors are arranged around corresponding transistors, and multiple capacitors on the same side of the bit line share a common second electrode, thereby further improving the device integration of the semiconductor device structure.

[0016] In some embodiments, the semiconductor device structure further includes: an external circuit structure electrically connected to the capacitor.

[0017] In some embodiments, the external circuit structure is electrically connected to the second electrode of the capacitor.

[0018] In some embodiments, the semiconductor device structure further includes a word line extending along the first direction, and the word line is connected to a plurality of gate conductive layers arranged at intervals along the first direction.

[0019] An embodiment of the present disclosure provides a method for preparing a semiconductor device structure, comprising the following steps.

[0020] providing a substrate;

[0021] A plurality of first stacked structures are formed on the upper surface of the substrate; each of the first stacked structures includes a sacrificial layer and a conductive layer alternately stacked in sequence along a first direction; the plurality of first stacked structures are arranged at intervals along a second direction and a third direction, respectively; the first direction is perpendicular to the upper surface of the substrate; the second direction and the third direction are both parallel to the upper surface of the substrate, and the second direction intersects the third direction;

[0022] removing the conductive layer in the first stacked structure to form a first gap;

[0023] forming a transistor in the first gap;

[0024] removing the sacrificial layer in the first stack structure to form a second gap;

[0025] A second electrode of the capacitor is formed at least in the second gap, and the second electrode of the capacitor surrounds the transistor.

[0026] In some embodiments, forming a plurality of first stacked structures on the upper surface of the substrate includes the following steps.

[0027] forming a sacrificial layer and a conductive layer alternately stacked in sequence along a first direction on the upper surface of the substrate;

[0028] The sacrificial layer and the conductive layer are etched to form a first stacked structure.

[0029] In some embodiments, the sacrificial layer and the conductive layer are etched to form the first stacking structure while also forming a second stacking structure, and the second stacking structure extends along a third direction; the conductive layer retained in the second stacking structure forms a bit line, and the sacrificial layer retained in the second stacking structure forms an isolation dielectric layer for adjacent bit lines; the first stacking structures arranged at intervals along the second direction are located on opposite sides of the second stacking structure.

[0030] In some embodiments, after forming a plurality of first stacked structures on the upper surface of the substrate and before removing the conductive layer within the first stacked structures to form the first gap, the preparation method further includes the following steps.

[0031] forming a first isolation layer, wherein the first isolation layer fills the gaps between the first stacked structures spaced apart along the third direction and covers at least the first stacked structures;

[0032] The first isolation layer is etched to expose the conductive layer in the first stacked structure.

[0033] In some embodiments, after forming the transistor in the first gap and before removing the sacrificial layer in the first stacked structure to form the second gap, the preparation method further includes: etching the first isolation layer to form a release gap.

[0034] Correspondingly, removing the sacrificial layer in the first stack structure to form the second gap includes: removing the sacrificial layer in the first stack structure based on the release gap to form the second gap.

[0035] In some embodiments, forming a transistor in the first gap includes the following steps.

[0036] forming a channel layer on a surface of the first gap;

[0037] forming a gate dielectric layer on the surface of the channel layer;

[0038] A gate conductive layer is formed on the surface of the gate dielectric layer.

[0039] In the embodiment of the present application, the gate conductive layer is also used as a component of the transistor (for example, the gate conductive layer), so as to reduce the number of devices in the semiconductor device structure and simplify the preparation process.

[0040] In some embodiments, forming a second electrode of the capacitor at least in the second gap includes the following steps.

[0041] forming a capacitor dielectric layer on the surface of the second gap and the surface of the release gap;

[0042] A second electrode is formed on the surface of the capacitor dielectric layer; and the channel layer of the transistor serves as the first electrode of the capacitor.

[0043] In some embodiments, the capacitor dielectric layer and the second electrode further cover the second stacked structure; after the second electrode is formed on the surface of the capacitor dielectric layer, the preparation method further includes the following steps.

[0044] forming an electrode connection layer on the surface of the second electrode, wherein the electrode connection layer also fills the second gap and the release gap;

[0045] forming a first covering dielectric layer on the upper surface of the electrode connection layer;

[0046] forming an isolation trench in the first cover dielectric layer, the isolation trench penetrating the first cover dielectric layer, the electrode connection layer, the second electrode, and the capacitor dielectric layer along a first direction, and being arranged corresponding to the second stacked structure;

[0047] A second isolation layer is formed in the isolation trench and on the upper surface of the first covering dielectric layer; the second isolation layer insulates and isolates the capacitors on opposite sides of the second stacking structure along the second direction, and allows multiple capacitors on the same side of the second stacking structure to share the second electrode.

[0048] In some embodiments, after forming the second isolation layer in the isolation trench and on the upper surface of the first cover dielectric layer, the preparation method further includes the following steps.

[0049] forming a second covering dielectric layer on the upper surface of the second isolation layer;

[0050] forming a contact hole, the contact hole penetrating the second covering dielectric layer, the second isolation layer and the first covering dielectric layer along a first direction, exposing the electrode connection layer;

[0051] An external circuit structure is formed in the contact hole, and the external circuit structure is in contact with the electrode connection layer.

[0052] An embodiment of the present application also provides an electronic device that adopts the semiconductor device structure described in some of the aforementioned embodiments.

[0053] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without paying any creative work.

[0055] FIG1 is a schematic structural diagram of a semiconductor device structure provided in some embodiments;

[0056] FIG2 is a schematic cross-sectional view of the structure shown in FIG1 along the AA direction;

[0057] FIG3 is another cross-sectional schematic diagram of the structure shown in FIG1 along the AA direction;

[0058] FIG4 is a schematic cross-sectional view of the structure shown in FIG1 along the BB direction;

[0059] FIG5 is a schematic cross-sectional view of the structure shown in FIG1 along the CC direction;

[0060] FIG6 is a schematic cross-sectional view of the structure shown in FIG1 along the DD direction;

[0061] FIG7 is a schematic flow chart of a method for preparing a semiconductor device structure provided in some embodiments;

[0062] FIG8 is a schematic flow chart of another method for preparing a semiconductor device structure provided in some embodiments;

[0063] FIG9 is a schematic flow chart of step S400 provided in some embodiments;

[0064] FIG10 is a schematic flow chart of another method for preparing a semiconductor device structure provided in some embodiments;

[0065] FIG11 is a schematic flow chart of step S600 provided in some embodiments;

[0066] FIG12 is a schematic flow chart of another method for preparing a semiconductor device structure provided in some embodiments;

[0067] FIG13 is a schematic structural diagram of a structure obtained after executing step S210 provided in some embodiments;

[0068] 14 and 15 are schematic diagrams of a structure obtained after performing step S220 in some embodiments; FIG15 is a top view of the structure obtained after step S220, and FIG14 is a front view of the structure obtained after step S220;

[0069] FIG16 and FIG17 are schematic diagrams of a structure obtained after performing step S250 in some embodiments; FIG17 is a top view of the structure obtained after step S250, and FIG16 is a front view of the structure obtained after step S250;

[0070] FIG18 is a schematic top view of a structure obtained after executing step S260 provided in some embodiments;

[0071] FIG19 is a schematic cross-sectional view taken along the AA direction in FIG18 ;

[0072] FIG20 is a schematic cross-sectional view along the BB direction in FIG18;

[0073] FIG21 is a schematic cross-sectional view taken along the CC direction in FIG18 ;

[0074] FIG22 is a schematic cross-sectional view of a structure obtained after executing step S300 along the AA direction in FIG18 , provided in some embodiments;

[0075] FIG23 is a schematic cross-sectional view of a structure obtained after executing step S300 along the CC direction in FIG18 provided in some embodiments;

[0076] FIG24 is a schematic cross-sectional view of a structure obtained after executing step S410 along the AA direction in FIG18 provided in some embodiments;

[0077] FIG25 is a schematic cross-sectional view of a structure obtained after executing step S420 along the AA direction in FIG18 , provided in some embodiments;

[0078] FIG26 is a schematic cross-sectional view of a structure obtained after executing step S430 along the AA direction in FIG18 , provided in some embodiments;

[0079] FIG27 is a schematic cross-sectional view of a structure obtained after executing step S430 along the CC direction in FIG18 provided in some embodiments;

[0080] FIG28 is a schematic top view of a structure obtained after performing step S450 in some embodiments;

[0081] FIG29 is a schematic cross-sectional view along the BB direction in FIG28;

[0082] FIG30 is a schematic cross-sectional view of a structure obtained after performing step S500′ along the AA direction in FIG28 provided in some embodiments;

[0083] FIG31 is a schematic cross-sectional view of a structure obtained after performing step S500′ along the CC direction in FIG28 provided in some embodiments;

[0084] FIG32 is a schematic cross-sectional view of a structure obtained after executing step S610 along the AA direction in FIG28 provided in some embodiments;

[0085] FIG33 is a schematic cross-sectional view of a structure obtained after executing step S610 along the direction BB in FIG28 , provided in some embodiments;

[0086] FIG34 is a schematic cross-sectional view of a structure obtained after executing step S610 along the CC direction in FIG28 , provided in some embodiments;

[0087] FIG35 is a schematic cross-sectional view of a structure obtained after executing step S620 along the AA direction in FIG28 provided in some embodiments;

[0088] FIG36 is a schematic cross-sectional view of a structure obtained after executing step S620 along the direction BB in FIG28 , provided in some embodiments;

[0089] FIG37 is a schematic cross-sectional view of a structure obtained after executing step S620 along the CC direction in FIG28 , provided in some embodiments;

[0090] FIG38 is a schematic cross-sectional view of a structure obtained after executing step S700 along the AA direction in FIG28 provided in some embodiments;

[0091] FIG39 is a schematic cross-sectional view of a structure obtained after executing step S700 along the direction BB in FIG28 provided in some embodiments;

[0092] FIG40 is a schematic cross-sectional view of a structure obtained after executing step S700 along the CC direction in FIG28 provided in some embodiments;

[0093] FIG41 is a schematic cross-sectional view of a structure obtained after executing step S800 along the AA direction in FIG28 provided in some embodiments;

[0094] FIG42 is a schematic cross-sectional view of a structure obtained after executing step S800 along the direction BB in FIG28 provided in some embodiments;

[0095] FIG43 is a schematic cross-sectional view of a structure obtained after executing step S800 along the CC direction in FIG28 provided in some embodiments;

[0096] FIG44 is a schematic cross-sectional view of a structure obtained after executing step S900 along the AA direction in FIG28 provided in some embodiments;

[0097] FIG45 is a schematic cross-sectional view of a structure obtained after executing step S900 along the direction BB in FIG28 , provided in some embodiments;

[0098] FIG46 is a schematic cross-sectional view of a structure obtained after executing step S1000 along the AA direction in FIG28 , provided in some embodiments;

[0099] FIG47 is a schematic cross-sectional view of a structure obtained after executing step S1000 along the direction BB in FIG28 , provided in some embodiments;

[0100] FIG48 is a schematic cross-sectional view of a structure obtained after executing step S1000 along the CC direction in FIG28 provided in some embodiments;

[0101] FIG49 is a schematic cross-sectional view of a structure obtained after executing step S1200 along the AA direction in FIG28 provided in some embodiments;

[0102] FIG50 is a schematic cross-sectional view of a structure obtained after executing step S1200 along the CC direction in FIG28 provided in some embodiments;

[0103] FIG51 is a schematic cross-sectional view of a structure obtained after executing step S1300 along the AA direction in FIG28 provided in some embodiments;

[0104] FIG52 is a schematic cross-sectional view of a structure obtained after executing step S1300 along the CC direction in FIG28 provided in some embodiments. DETAILED DESCRIPTION

[0105] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the embodiments of the present disclosure.

[0106] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0107] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intervening element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc., if there is transmission of electrical signals or data between the connected objects.

[0108] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0109] Please refer to Figures 1 to 6 to understand that in some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes: a substrate 10, a transistor array, and multiple capacitors 30. The transistor array is located on the substrate 10 and includes multiple transistors 20. The multiple transistors 20 are arranged in a first direction, a second direction, and a third direction. The first direction is perpendicular to the upper surface of the substrate 10, and the second direction and the third direction are both parallel to the upper surface of the substrate 10, and the second direction intersects the third direction. At least one electrode of the capacitor 30 surrounds one transistor 20.

[0110] In the embodiment of the present application, by setting the electrode of the capacitor 30 to surround the transistor, the process can be simplified and the size of the semiconductor device structure can be reduced, thereby improving space utilization.

[0111] For example, the first direction is, for example, the Z direction, the second direction is, for example, the X direction, and the third direction is, for example, the Y direction. The first direction (Z direction) is perpendicular to the upper surface of the substrate 10, the second direction (X direction) and the third direction (Y direction) are both parallel to the upper surface of the substrate 10, and the second direction (X direction) intersects the third direction (Y direction). To more clearly illustrate the structure of the semiconductor device provided in this application, the following embodiments and drawings continue the definitions of the first direction, the second direction, and the third direction herein.

[0112] Here, the electrode of the capacitor 30 surrounding the transistor 20 means that at least one electrode of the capacitor 30 surrounds the transistor 20, or the orthographic projection of the transistor 20 on the YZ plane falls within the area enclosed by the orthographic projection of one electrode of the capacitor 30 on the YZ plane. In addition, in some embodiments, one or more electrodes of the capacitor 30 also surround corresponding transistors 20.

[0113] For example, the substrate 10 may be made of, but is not limited to, a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 may be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate. This application is not limited by this specification.

[0114] Continuing with FIG. 2 and FIG. 4 , in some embodiments, the transistor 20 includes a channel layer 201, a gate dielectric layer 202, and a gate conductive layer 203. The gate conductive layer 203 extends along a second direction (e.g., the X direction); the gate dielectric layer 202 is located on a surface of the gate conductive layer 203; the channel layer 201 is located on a surface of the gate dielectric layer 202 away from the gate conductive layer 203; and one electrode of the capacitor 30 is located on a surface of the channel layer 201.

[0115] For example, the material of the gate conductive layer 203 includes one or more of metal tungsten, metal titanium, metal aluminum, metal copper, and metal nickel.

[0116] For example, the gate conductive layer 203 may be a single-layer structure, or may be a multi-layer structure including a plurality of different metal materials.

[0117] For example, the gate dielectric layer 202 covers the surface of the gate conductive layer 203 .

[0118] For example, the material of the gate dielectric layer 202 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium dioxide.

[0119] For example, the channel layer 201 covers a surface of the gate dielectric layer 202 away from the gate conductive layer 203 .

[0120] For example, the material of the channel layer 201 may include: single crystal silicon, polycrystalline silicon, silicon germanium or metal oxide, and the material of the metal oxide may be indium tin zinc oxide or indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0121] It should be noted that a gate conductive layer 203 and its peripheral gate dielectric layer 202 and channel layer 201 may constitute a transistor 20 .

[0122] As an example, referring to Figures 1 to 4, the semiconductor device structure may also include a word line 204 extending along the first direction, and the word line 204 is connected to a plurality of gate conductive layers 203 arranged at intervals along the first direction, that is, one word line 204 is connected to the gate conductive layer 203 of a string of transistors 20.

[0123] For example, the capacitor 30 may include: a first electrode, a capacitor dielectric layer 301 and a second electrode 302 , wherein the capacitor dielectric layer 301 surrounds at least a portion of the circumference of the channel layer 201 ; and the second electrode 302 surrounds the capacitor dielectric layer 301 .

[0124] Here, the channel layer 201 in contact with the capacitor dielectric layer 301 can also serve as one of the electrodes of the capacitor 30 (eg, the first electrode) to improve the integration of the semiconductor device.

[0125] Please refer to Figures 2 and 3 to understand that in some embodiments, the size of the capacitor 30 along the second direction (e.g., the X direction) can also be adjusted, for example, so that the size of the capacitor 30 along the second direction is equal to or greater than the size of the transistor 20 along the second direction, so as to further increase the surface area of ​​the capacitor 30, thereby increasing the capacitance.

[0126] Continuing to refer to Figures 4 and 6, in some embodiments, the semiconductor device structure further includes: a plurality of bit lines 40, which are stacked and spaced apart along a first direction (e.g., the Z direction) and extend along a third direction (e.g., the Y direction); transistors 20 spaced apart along a second direction (e.g., the X direction) are respectively located on opposite sides of the bit lines 40 and in contact with the bit lines 40 located on the same layer.

[0127] For example, the plurality of transistors 20 are respectively located on two opposite sides of the bit line 40 , and the channel layer 201 of the transistor 20 is in contact with the bit line 40 to achieve electrical connection.

[0128] 2 and 5 , in some embodiments, a plurality of capacitors 30 are disposed corresponding to the transistors 20 and surround the corresponding transistors 20 ; the plurality of capacitors 30 located on the same side of the bit line 40 share a second electrode 302 .

[0129] Here, the plurality of capacitors 30 sharing the second electrode 302 means that the second electrodes 302 of the plurality of capacitors 30 are electrically connected together.

[0130] For example, an electrode connection layer 80 may be provided to cover the surfaces of the second electrodes 302 of the plurality of capacitors 30 located on the same side of the bit line 40 , so as to achieve corresponding electrical connections.

[0131] In some embodiments, the semiconductor device structure further includes: an external circuit structure 50 ; the external circuit structure 50 is electrically connected to the capacitor 30 .

[0132] In some embodiments, the external circuit structure 50 is electrically connected to the second electrode 302 of the capacitor 30 .

[0133] For example, the external circuit structure 50 may be a conductive plug, which may lead out the corresponding capacitor 30 to facilitate electrical connection with an external control circuit, thereby realizing functions such as current writing.

[0134] Referring to FIG. 7 , some embodiments of the present application further provide a method for fabricating a semiconductor device structure, for fabricating the semiconductor device structures described in some of the aforementioned embodiments. This method also possesses the technical advantages of the semiconductor device structures described in some of the aforementioned embodiments and will not be further described here. The method includes steps S100 to S600.

[0135] S100 , providing a substrate.

[0136] S200 , forming a plurality of first stacking structures on the upper surface of the substrate; each first stacking structure includes a sacrificial layer and a conductive layer alternately stacked in sequence along a first direction; and the plurality of first stacking structures are spaced apart along a second direction and a third direction, respectively.

[0137] S300 , removing the conductive layer in the first stacked structure to form a first gap.

[0138] S400 , forming a transistor in the first gap.

[0139] S500 , removing the sacrificial layer in the first stacked structure to form a second gap.

[0140] S600 , forming a second electrode of the capacitor at least in the second gap, wherein the second electrode of the capacitor surrounds the transistor.

[0141] Please refer to FIG. 8 , in some embodiments, step S200 may include steps S210 - S220 .

[0142] S210 , forming sacrificial layers and conductive layers alternately stacked in sequence along a first direction on an upper surface of the substrate.

[0143] S220 , etching the sacrificial layer and the conductive layer to form a first stacked structure.

[0144] Continuing to refer to FIG. 8 , in some embodiments, after step S220 and before step S300 , the preparation method further includes steps S250 to S260 .

[0145] S250 , forming a first isolation layer, wherein the first isolation layer fills the gaps between the first stacked structures spaced apart along the third direction and at least covers the first stacked structures.

[0146] S260 , etching the first isolation layer to expose the conductive layer in the first stacked structure.

[0147] It should be noted that, in some embodiments, while executing the aforementioned step S220, a second stacking structure is also synchronously formed, and the second stacking structure extends along a third direction (for example, the Y direction); the conductive layer retained in the second stacking structure forms a bit line, and the sacrificial layer retained in the second stacking structure forms an isolation dielectric layer for adjacent bit lines; the first stacking structures arranged at intervals along the second direction (for example, the X direction) are located on opposite sides of the second stacking structure.

[0148] Correspondingly, in step S250, the first isolation layer also covers the second stack structure; in step S260, the first isolation layer located at one end of the first stack structure away from the second stack structure along the second direction is etched to expose the conductive layer in the first stack structure.

[0149] Please refer to FIG. 9 , in some embodiments, step S400 includes steps S410 - S430 .

[0150] S410 , forming a channel layer on a surface of the first gap.

[0151] S420 , forming a gate dielectric layer on the surface of the channel layer.

[0152] S430 , forming a gate conductive layer on the surface of the gate dielectric layer.

[0153] Here, the gate conductive layer also fills the first gap.

[0154] Referring to FIG. 10 , in some embodiments, after performing step S400 and before performing step S500 , the preparation method further includes:

[0155] S450 , etching the first isolation layer to form a release gap.

[0156] Correspondingly, the preparation method further comprises:

[0157] S500 ′, removing the sacrificial layer in the first stack structure based on the release gap to form a second gap.

[0158] Please refer to FIG. 11 , in some embodiments, step S600 includes steps S610 - S620 .

[0159] S610 , forming a capacitor dielectric layer on a surface of the second gap and a surface of the release gap.

[0160] S620 , forming a second electrode on the surface of the capacitor dielectric layer; the channel layer of the transistor serves as the first electrode of the capacitor.

[0161] Here, the second electrode, the capacitor dielectric layer, and the first electrode (ie, a portion of the channel layer of the transistor) together form a capacitor surrounding the transistor.

[0162] Referring to FIG. 12 , in some embodiments, the capacitor dielectric layer and the second electrode further cover the second stacked structure. After step S600 , the preparation method further includes steps S700 to S1300 .

[0163] S700 , forming an electrode connection layer on the surface of the second electrode, wherein the electrode connection layer also fills the second gap and the release gap.

[0164] S800 , forming a first covering dielectric layer on the upper surface of the electrode connection layer.

[0165] S900 , forming an isolation trench in the first cover dielectric layer, wherein the isolation trench penetrates the first cover dielectric layer, the electrode connection layer, the second electrode, and the capacitor dielectric layer along a third direction and is arranged corresponding to the second stacked structure.

[0166] S1000, forming a second isolation layer in the isolation trench and on the upper surface of the first covering dielectric layer; the second isolation layer insulates and isolates the capacitors on opposite sides of the second stacking structure along the second direction, and allows multiple capacitors on the same side of the second stacking structure to share a second electrode.

[0167] S1100 , forming a second covering dielectric layer on an upper surface of the second isolation layer.

[0168] S1200 , forming a contact hole, wherein the contact hole penetrates the second covering dielectric layer, the second isolation layer, and the first covering dielectric layer along a first direction, exposing the electrode connection layer.

[0169] S1300 , forming an external circuit structure in the contact hole, wherein the external circuit structure is in contact with the electrode connection layer.

[0170] In addition, in the above embodiments of the present application, unless otherwise specified herein, there is no strict order restriction for the execution of the steps in the method, and these steps may not necessarily be executed in the order described, but may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0171] In order to more clearly illustrate the manufacturing methods of the semiconductor device structures in some of the above embodiments, the following embodiments describe in detail the manufacturing methods of some semiconductor device structures with reference to FIG. 12 to FIG. 52 .

[0172] In step S100 , referring to S100 in FIG. 12 and FIG. 13 , a substrate 10 is provided.

[0173] For example, the substrate 10 may be made of, but is not limited to, a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 may be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate. This application is not limited by this specification.

[0174] In step S200, referring to S200 in FIG. 12 and FIG. 13 to FIG. 15 , a plurality of first stacked structures 60A are formed on the upper surface of the substrate 10; each first stacked structure 60A includes a sacrificial layer 61 and a conductive layer 62 alternately stacked in sequence along a first direction (e.g., the Z direction); and the plurality of first stacked structures 60A are respectively arranged at intervals along a second direction (e.g., the X direction) and a third direction (e.g., the Y direction).

[0175] Specifically, some of the plurality of first stacked structures 60A are arranged at intervals along the second direction, and another portion of the first stacked structures 60A are arranged at intervals along the third direction.

[0176] Illustratively, step S200 includes steps S210 to S220.

[0177] In step S210 , referring to S210 in FIG. 8 and FIG. 13 , sacrificial layers 61 and conductive layers 62 are formed on the upper surface of the substrate 10 and are alternately stacked in a first direction (eg, Z direction).

[0178] For example, the material of the sacrificial layer 61 may include, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride.

[0179] For example, the material of the conductive layer 62 may include, but is not limited to, metal tungsten, metal titanium, metal aluminum, metal copper, or metal nickel.

[0180] In one example, the material of the sacrificial layer 61 is, for example, silicon oxide; and the material of the conductive layer 62 is, for example, metal tungsten.

[0181] In step S220 , referring to S220 in FIG. 8 and FIG. 14 to FIG. 15 , the sacrificial layer 61 and the conductive layer 62 are etched to form a first stacked structure 60A.

[0182] Here, while the first stack structure 60A is being formed, the second stack structure 60B may also be formed simultaneously.

[0183] For example, the second stacked structure 60B extends along a third direction (e.g., the Y direction); the conductive layer 62 retained in the second stacked structure 60B forms the bit line 40, and the sacrificial layer 61 retained in the second stacked structure 60B forms an isolation dielectric layer for adjacent bit lines 40; the first stacked structures 60A arranged at intervals along the second direction (e.g., the X direction) are located on opposite sides of the second stacked structure 60B.

[0184] For example, an initial stacking structure consisting of a sacrificial layer 61 and a conductive layer 62 alternately stacked in a first direction (for example, the Z direction) can be formed on the substrate 10, and then the first stacking structure 60A and the second stacking structure 60B can be synchronously obtained by patterning the initial stacking structure; specifically, the first stacking structure 60A and the second stacking structure 60B can be synchronously obtained by etching the initial stacking structure.

[0185] In step S250 , referring to S250 in FIG. 8 and FIG. 16 to FIG. 17 , a first isolation layer 71 is formed. The first isolation layer 71 fills the gaps between the first stacked structures 60A arranged along a third direction (eg, the Y direction) and covers at least the first stacked structures 60A.

[0186] When the second stacked structure 60B is formed, the first isolation layer 71 also covers the second stacked structure 60B.

[0187] For example, a first isolation layer 71 covering the first stacked structure 60A, the second stacked structure 60B and the exposed surface of the substrate 10 can be formed by processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, evaporation growth, molecular beam epitaxy or vapor phase film formation.

[0188] For example, the material of the first isolation layer 71 may include, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride. In one example, the material of the first isolation layer 71 is, for example, silicon nitride.

[0189] In step S260 , referring to S260 in FIG. 8 and FIG. 18 to FIG. 21 , the first isolation layer 71 is etched to expose the conductive layer 62 in the first stacked structure 60A.

[0190] Here, the first isolation layers 71 located on two opposite sides of the first stack structure 60A along the third direction (eg, the Y direction) need to be retained so that subsequent steps can be performed smoothly.

[0191] For example, a photolithography process can be used to form a patterned mask layer on the surface of the first isolation layer 71. The patterned mask layer has an opening pattern that exposes the first stacked structure 60A along the second direction (for example, the X direction) away from one end of the bit line 40. The first isolation layer 71 is etched based on the opening pattern to expose the conductive layer 62 in the first stacked structure 60A.

[0192] In step S300 , referring to S300 in FIG. 12 and FIG. 22 to FIG. 23 , the conductive layer 62 in the first stacked structure 60A is removed to form a first gap G1 .

[0193] For example, a wet etching process may be used to etch away one end of the exposed conductive layer 62 , and parameters such as etching time may be adjusted to facilitate controlling the extension length of the obtained first gap G1 along the second direction (eg, X direction).

[0194] It should be noted that, since this step does not involve further direct processing of the first isolation layer 71 , the cross-sectional schematic diagram of the structure obtained after performing this step along the BB direction can be understood by referring to FIG. 20 .

[0195] In step S400 , referring to S400 in FIG. 12 and FIG. 24 to FIG. 27 , a transistor 20 is formed in the first gap G1 .

[0196] Illustratively, step S400 includes steps S410 to S430.

[0197] In step S410 , referring to S410 in FIG. 9 and FIG. 24 , a channel layer 201 is formed on the surface of the first gap G1 .

[0198] For example, the channel layer 201 may be formed covering the surface of the first gap G1 by using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporative growth, molecular beam epitaxy, or vapor phase film formation.

[0199] For example, the material of the channel layer 201 may include, but is not limited to, single crystal silicon, polycrystalline silicon, silicon germanium, or indium tin zinc oxide. In one example, the material of the channel layer 201 is, for example, indium tin zinc oxide.

[0200] In step S420 , referring to S420 in FIG. 9 and FIG. 25 , a gate dielectric layer 202 is formed on the surface of the channel layer 201 .

[0201] For example, the gate dielectric layer 202 may be formed to cover the surface of the channel layer 201 by using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy, or vapor phase film formation.

[0202] For example, the material of the gate dielectric layer 202 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, or hafnium dioxide.

[0203] In step S430 , referring to S430 in FIG. 9 and FIG. 26 to FIG. 27 , a gate conductive layer 203 is formed on the surface of the gate dielectric layer 202 .

[0204] Here, the gate conductive layer 203 also fills the first gap G1 . The channel layer 201 , the gate dielectric layer 202 and the gate conductive layer 203 together constitute the transistor 20 , wherein the channel layer 201 also serves as the first electrode of the capacitor 30 .

[0205] For example, the gate conductive layer 203 covering the surface of the channel layer 201 and filling the first gap G1 may be formed by using processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or evaporation.

[0206] For example, the material of the gate conductive layer 203 may include, but is not limited to, metal tungsten, metal titanium, metal aluminum, metal copper, or metal nickel.

[0207] It should be noted that, since step S400 (including steps S410 to S430 ) does not involve further direct processing of the first isolation layer 71 , the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can be understood with reference to FIG. 19 .

[0208] It should be further explained that a transistor 20 is formed in a first gap G1 .

[0209] As an example, referring to Figures 1 to 4, the semiconductor device structure may further include a word line 204 extending along the first direction, and the word line 204 is connected to a plurality of gate conductive layers 203 arranged at intervals along the first direction, that is, the gate conductive layers 203 of the plurality of transistors 20 located in the plurality of first gaps G1 share the same word line 204.

[0210] In step S450 , referring to S450 in FIG. 12 and FIG. 28 to FIG. 29 , the first isolation layer 71 is etched to form a release gap G0 .

[0211] Here, it is necessary to etch and remove portions of the first isolation layer 71 located on two opposite sides of the first stacked structure 60A along the third direction (eg, the Y direction).

[0212] For example, a photolithography process can be used to form a patterned mask layer on the surface of the first isolation layer 71. The patterned mask layer has an opening pattern that exposes the first stacked structure 60A on two opposite sides along a third direction (for example, the Y direction). The first isolation layer 71 is etched based on the opening pattern to obtain a release gap G0.

[0213] It should be noted that, since this step does not involve further direct processing of the first stacked structure 60A, the cross-sectional schematic diagram of the structure obtained after executing this step along the AA direction can be understood by referring to FIG. 26 .

[0214] In step S500 ′, referring to S500 ′ in FIG. 12 and FIG. 30 to FIG. 31 , the sacrificial layer 61 in the first stacked structure 60A is removed based on the release gap G0 to form a second gap G2 .

[0215] Here, the second gap G2 also exposes a portion of the surface of the channel layer 201. Optionally, ion implantation may be performed on the exposed surface of the channel layer 201 to further enhance its conductivity, thereby improving the electrical performance of the semiconductor device.

[0216] For example, a wet etching process may be used to etch and remove the exposed sacrificial layer 61 along a third direction (eg, Y direction) based on the release gap G0 to form the second gap G2 .

[0217] For example, the orthographic projection of the second gap G2 on the substrate 10 falls within the orthographic projection of the first gap G1 on the substrate 10 in the same first stacked structure 60A.

[0218] It should be noted that, since this step does not involve further direct processing of the release gap G0, the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can be understood by referring to FIG. 29 .

[0219] In step S600 , the second electrode 302 of the capacitor 30 is formed at least in the second gap G2 . The second electrode 302 of the capacitor 30 surrounds the transistor 20 .

[0220] Illustratively, step S600 includes steps S610 to S620.

[0221] In step S610 , referring to S610 in FIG. 12 and FIG. 32 to FIG. 34 , a capacitor dielectric layer 301 is formed on the surface of the second gap G2 and the surface of the release gap G0 .

[0222] For example, the capacitor dielectric layer 301 may be formed by covering the surface of the second gap G2 and the surface of the release gap G0 using processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy, or vapor phase film formation.

[0223] For example, the capacitor dielectric layer 301 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass.

[0224] In step S620 , referring to S620 in FIG. 12 and FIG. 35 to FIG. 37 , a second electrode 302 is formed on the surface of the capacitor dielectric layer 301 ; the channel layer 201 of the transistor 20 serves as the first electrode of the capacitor 30 .

[0225] Here, the second electrode 302 , the capacitor dielectric layer 301 and the first electrode (ie, a portion of the channel layer 201 of the transistor 20 ) together form a capacitor 30 surrounding the transistor 20 .

[0226] For example, the second electrode 302 covering the surface of the capacitor dielectric layer 301 may be formed by, but not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or evaporation processes.

[0227] For example, the material of the second electrode 302 may include, but is not limited to, metal tungsten, metal titanium, metal aluminum, metal copper, or metal nickel.

[0228] In step S700 , referring to S700 in FIG. 12 and FIG. 38 to FIG. 40 , an electrode connection layer 80 is formed on the surface of the second electrode 302 . The electrode connection layer 80 also fills the second gap G2 and the release gap G0 .

[0229] For example, processes such as, but not limited to, chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporative growth, molecular beam epitaxy, or vapor phase film formation can be used to form an electrode connection layer 80 that covers the surface of the second electrode 302 and fills the second gap G2 and releases the gap G0.

[0230] Here, the electrode connection layer 80 can electrically connect the second electrodes 302 of the plurality of capacitors 30 together, so as to increase the charge capacity and perform subsequent charge and discharge control.

[0231] For example, the material of the electrode connection layer 80 may include, but is not limited to, a metal material or a semiconductor material.

[0232] For example, the material of the electrode connection layer 80 may be doped polysilicon.

[0233] In step S800 , referring to S800 in FIG. 12 and FIG. 41 to FIG. 43 , a first covering dielectric layer 91 is formed on the upper surface of the electrode connection layer 80 .

[0234] Illustratively, the first cover layer 91 may include a single-layer structure or a multi-layer structure.

[0235] For example, the first covering dielectric layer 91 covering the upper surface of the electrode connection layer 80 may be formed by processes such as, but not limited to, chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy, or vapor phase film formation.

[0236] For example, the material of the first cover dielectric layer 91 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass.

[0237] In step S900, referring to S900 in FIG. 12 and FIG. 44 to FIG. 45 , an isolation trench G3 is formed in the first cover dielectric layer 91. The isolation trench G3 also penetrates the first cover dielectric layer 91, the electrode connection layer 80, the second electrode 302, and the capacitor dielectric layer 301 along a first direction (e.g., the Z direction), and is arranged corresponding to the second stacked structure 60B.

[0238] Here, the isolation trench G3 and the second stacked structure 60B are arranged correspondingly, which means that the orthographic projection of the isolation trench G3 on the substrate 10 coincides with or substantially coincides with the orthographic projection of the second stacked structure 60B on the substrate 10 .

[0239] For example, a photolithography process can be used to form a patterned mask layer on the first covering layer 91. The patterned mask layer has an opening pattern that defines the formation position of the isolation groove G3. Based on the opening pattern, the first covering dielectric layer 91, the electrode connection layer 80, the second electrode 302 and the capacitor dielectric layer 301 are etched in sequence, and the first isolation layer 71 is used as an etching stop layer to obtain the isolation groove G3.

[0240] It should be noted that, since this step does not involve further direct processing of the film layer structure located above the first stacked structure 60A, the cross-sectional schematic diagram of the structure obtained after executing this step along the CC direction can be understood by referring to FIG. 43 .

[0241] In step S1000, referring to S1000 in FIG. 12 and FIGS. 46 to 48 , a second isolation layer 72 is formed in the isolation trench G3 and on the upper surface of the first cover dielectric layer 91 . The second isolation layer 72 insulates and isolates the capacitors 30 on opposite sides of the second stacked structure 60B along a second direction (e.g., the X direction), and allows multiple capacitors 30 on the same side of the second stacked structure 60B to share a second electrode 302.

[0242] For example, the second isolation layer 72 filling the isolation groove G3 and covering the upper surface of the first cover dielectric layer 91 can be formed by processes such as but not limited to chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy or vapor phase film formation.

[0243] For example, the material of the second isolation layer 72 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass. In one example, the material of the second isolation layer 72 is, for example, silicon oxide.

[0244] In step S1100 , referring to S1100 in FIG. 12 and FIG. 49 , a second cover dielectric layer 92 is formed on the upper surface of the second isolation layer 72 .

[0245] For example, the second cover dielectric layer 92 may include a single-layer structure or a multi-layer structure.

[0246] For example, the second covering dielectric layer 92 covering the upper surface of the second isolation layer 72 may be formed by processes such as, but not limited to, chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy, or vapor phase film formation.

[0247] For example, the material of the second cover dielectric layer 92 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass. In one example, the material of the second isolation layer 72 is, for example, silicon nitride.

[0248] In step S1200 , referring to S1200 in FIG. 12 and FIG. 49 to FIG. 50 , a contact hole G4 is formed. The contact hole G4 penetrates the second cover dielectric layer 92 , the second isolation layer 72 and the first cover dielectric layer 91 along a first direction (eg, Z direction), exposing the electrode connection layer 80 .

[0249] For example, a photolithography process can be used to form a patterned mask layer on the second covering layer 92. The patterned mask layer has an opening pattern that defines the position where the contact hole G4 is formed. Based on the opening pattern, the second covering dielectric layer 92, the second isolation layer 72 and the first covering dielectric layer 91 are etched in sequence, and the electrode connection layer 80 is used as an etching stop layer to obtain the contact hole G4.

[0250] It should be noted that, since this step does not involve further direct processing of the first isolation layer 71 , the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can be understood by referring to FIG. 47 .

[0251] In step S1300 , referring to S1300 in FIG. 12 and FIG. 51 to FIG. 52 , an external circuit structure 50 is formed in the contact hole G4 , and the external circuit structure 50 is in contact with the electrode connection layer 80 .

[0252] For example, the external circuit structure 50 may be a conductive plug, which may lead out the corresponding capacitor 30 to facilitate electrical connection with an external control circuit, thereby realizing functions such as current writing.

[0253] For example, the material of the external circuit structure 50 may include, but is not limited to, metal tungsten, metal titanium, metal aluminum, metal copper, or metal nickel.

[0254] For example, the external circuit structure 50 may be a single-layer structure or a multi-layer structure.

[0255] It should be noted that, since this step does not involve further direct processing of the first isolation layer 71 , the cross-sectional schematic diagram of the structure obtained after executing this step along the BB direction can be understood by referring to FIG. 47 .

[0256] It should be understood that, unless otherwise expressly stated herein, the steps described are not strictly limited in order of execution, and the steps may be executed in other orders. Furthermore, at least a portion of the steps described may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The sub-steps or stages are not necessarily executed sequentially, but may be executed in rotation or alternation with other steps or at least a portion of the sub-steps or stages of other steps.

[0257] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0258] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0259] The above-described embodiments merely represent several implementation methods of the embodiments of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person skilled in the art can make several modifications and improvements without departing from the concept of the embodiments of the present disclosure, all of which fall within the scope of protection of the embodiments of the present disclosure. Therefore, the scope of protection of the patent for the embodiments of the present disclosure shall be based on the appended claims.

Claims

1. A semiconductor device structure, comprising: substrate; A transistor array is located on the substrate; the transistor array includes a plurality of transistors, and the plurality of transistors are arranged at intervals along a first direction, a second direction, and a third direction; the first direction is perpendicular to the upper surface of the substrate; the second direction and the third direction are both parallel to the upper surface of the substrate, and the second direction intersects the third direction; A plurality of capacitors; wherein an electrode of at least one of the capacitors surrounds one of the transistors.

2. The semiconductor device structure according to claim 1, wherein the transistor comprises: A gate conductive layer extending along the second direction; A gate dielectric layer, located on the surface of the gate conductive layer; A channel layer, located on a surface of the gate dielectric layer away from the gate conductive layer; The one electrode of the capacitor is located on a surface of the channel layer.

3. The semiconductor device structure according to claim 2, wherein the channel layer surrounds the gate conductive layer; the capacitor comprises a first electrode, a capacitor dielectric layer and a second electrode stacked sequentially from the inside to the outside; the second electrode of the capacitor surrounds the channel layer, wherein: The channel layer also serves as the first electrode of the capacitor.

4. The semiconductor device structure according to claim 3, wherein the material of the channel layer comprises: Indium gallium zinc oxide.

5. The semiconductor device structure according to claim 3 or 4, further comprising: a plurality of bit lines, the plurality of bit lines are stacked and spaced apart along the first direction and extend along the third direction; The transistors arranged at intervals along the second direction are respectively located on two opposite sides of the bit line and are in contact with the bit line located in the same layer. 6 . The semiconductor device structure according to claim 5 , wherein the bit line is in contact with the channel layer of the transistor located at the same layer on both sides thereof.

7. According to the semiconductor device structure of claim 5 or 6, a plurality of the capacitors are arranged corresponding to the transistors and respectively surround the corresponding transistors; and a plurality of the capacitors located on the same side of the bit line share the second electrode.

8. The semiconductor device structure according to any one of claims 1 to 7, further comprising: An external circuit structure is electrically connected to the capacitor. 9 . The semiconductor device structure according to claim 8 , wherein the external circuit structure is electrically connected to the second electrode of the capacitor.

10. The semiconductor device structure according to claim 2, characterized in that: It also includes a word line extending along the first direction, wherein the word line is connected to a plurality of the gate conductive layers arranged at intervals along the first direction.

11. A method for preparing a semiconductor device structure, comprising: providing a substrate; forming a plurality of first stacking structures on the upper surface of the substrate; Each of the first stacked structures includes sacrificial layers and conductive layers alternately stacked in sequence along a first direction; The plurality of first stacked structures are arranged at intervals along the second direction and the third direction respectively; the first direction is perpendicular to the upper surface of the substrate; the second direction and the third direction are both parallel to the upper surface of the substrate, and the second direction intersects the third direction; removing the conductive layer in the first stacked structure to form a first gap; forming a transistor in the first gap; removing the sacrificial layer in the first stacked structure to form a second gap; A second electrode of a capacitor is formed at least in the second gap, and the second electrode of the capacitor surrounds the transistor.

12. The method for preparing a semiconductor device structure according to claim 11, wherein forming a plurality of first stacked structures on the upper surface of the substrate comprises: forming a sacrificial layer and a conductive layer alternately stacked in sequence along the first direction on the upper surface of the substrate; The sacrificial layer and the conductive layer are etched to form the first stacked structure.

13. The method for manufacturing a semiconductor device structure according to claim 12, wherein the etching of the sacrificial layer and the conductive layer to form the first stacking structure also forms a second stacking structure, and the second stacking structure extends along the third direction; The conductive layer retained in the second stack structure forms a bit line, and the sacrificial layer retained in the second stack structure forms an isolation dielectric layer adjacent to the bit line; The first stacking structures arranged at intervals along the second direction are located on two opposite sides of the second stacking structure.

14. The method for preparing a semiconductor device structure according to any one of claims 11 to 13, after forming a plurality of first stacked structures on the upper surface of the substrate and before removing the conductive layer in the first stacked structures to form the first gap, the method further comprises: forming a first isolation layer, wherein the first isolation layer fills the gaps between the first stacked structures arranged at intervals along the third direction and at least covers the first stacked structures; The first isolation layer is etched to expose the conductive layer in the first stacked structure.

15. The method for preparing a semiconductor device structure according to claim 14, After forming a transistor in the first gap and before removing the sacrificial layer in the first stacked structure to form a second gap, the method further includes: Etching the first isolation layer to form a release gap; The removing the sacrificial layer in the first stacked structure to form the second gap includes: removing the sacrificial layer in the first stacked structure based on the release gap to form the second gap.

16. The method for manufacturing a semiconductor device structure according to claim 14 or 15, wherein forming a transistor in the first gap comprises: forming a channel layer on a surface of the first gap; forming a gate dielectric layer on a surface of the channel layer; A gate conductive layer is formed on the surface of the gate dielectric layer.

17. The method for manufacturing a semiconductor device structure according to claim 15, wherein forming a second electrode of a capacitor at least in the second gap comprises: forming a capacitor dielectric layer on a surface of the second gap and a surface of the release gap; forming a second electrode on the surface of the capacitor dielectric layer; The channel layer of the transistor serves as a first electrode of the capacitor.

18. The method for preparing a semiconductor device structure according to claim 17, wherein the capacitor dielectric layer and the second electrode also cover the second stacked structure; after forming the second electrode on the surface of the capacitor dielectric layer, the method further comprises: forming an electrode connection layer on the surface of the second electrode, wherein the electrode connection layer also fills the second gap and the release gap; forming a first covering dielectric layer on the upper surface of the electrode connection layer; forming an isolation groove in the first covering dielectric layer, wherein the isolation groove penetrates the first covering dielectric layer, the electrode connecting layer, the second electrode and the capacitor dielectric layer along the first direction and is arranged corresponding to the second stacking structure; forming a second isolation layer in the isolation trench and on the upper surface of the first covering dielectric layer; The second isolation layer insulates and isolates the capacitors on two opposite sides of the second stacking structure along the second direction, and enables a plurality of the capacitors located on the same side of the second stacking structure to share a second electrode.

19. The method for manufacturing a semiconductor device structure according to claim 18, after forming the second isolation layer in the isolation trench and on the upper surface of the first covering dielectric layer, further comprising: forming a second covering dielectric layer on the upper surface of the second isolation layer; forming a contact hole, wherein the contact hole penetrates the second covering dielectric layer, the second isolation layer and the first covering dielectric layer along the first direction to expose the electrode connection layer; An external circuit structure is formed in the contact hole, and the external circuit structure is in contact with the electrode connection layer.

20. An electronic device, comprising: The semiconductor device structure according to any one of claims 1 to 10.

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