Shift register and drive method therefor, and gate drive circuit and display apparatus

Abstract

Provided in the present disclosure are a shift register and a drive method therefor, and a gate drive circuit and a display apparatus. In the shift register, a first holding sub-circuit is coupled to a control signal input end and a first node, and is used for maintaining the voltage of the first node such that same is substantially unchanged in a first operation mode; and a second holding sub-circuit is coupled to the control signal input end and a second node, and is used for maintaining the voltage of the second node such that same is substantially unchanged in the first operation mode.

Description

Shift register and driving method thereof, gate driving circuit, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310897092.7 filed in China on July 20, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0004] With the continuous development of display technology, the application fields of display products are becoming increasingly broad, and users are placing increasingly higher demands on display products. To meet users' demand for narrow bezels in display products, display products can adopt GOA (Gate On Array) technology, which integrates the gate drive circuit on the display product's array substrate.

[0005] The power consumption of display products is mainly generated by two parts: one is the pixel driving circuit part, and the other is the gate driving circuit part. The relevant technology has greatly reduced the power consumption generated by the pixel driving circuit part through corresponding technical means. Therefore, how to reduce the power consumption generated by the gate driving circuit part has become a key issue in reducing the overall power consumption of the display substrate.

[0006] Summary of the Invention

[0007] The present disclosure aims to provide a shift register and a driving method thereof, a gate driving circuit, and a display device.

[0008] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0009] A first aspect of the present disclosure provides a shift register, comprising: a first node, a second node, a first output sub-circuit, and a second output sub-circuit; the shift register further comprises a first holding sub-circuit and / or a second holding sub-circuit;

[0010] The first output sub-circuit is coupled to the first level signal input terminal, the gate drive signal output terminal and the first node respectively, and is used to control the electrical connection between the first level signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the first node;

[0011] The second output sub-circuit is coupled to the first clock signal input terminal, the gate drive signal output terminal and the second node respectively, and is used to control the electrical connection between the first clock signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the second node;

[0012] The first holding subcircuit is coupled to the control signal input terminal and the first node respectively, and is used to keep the voltage of the first node substantially unchanged in the first working mode;

[0013] The second holding subcircuit is coupled to the control signal input terminal and the second node respectively, and is configured to keep the voltage of the second node substantially unchanged in the first working mode.

[0014] Optionally, the shift register further includes a third node, a fourth node, a third node control subcircuit, and a fourth node control subcircuit, wherein the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node;

[0015] The first holding sub-circuit includes a tenth transistor, a gate of the tenth transistor is coupled to the control signal input terminal, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the third node;

[0016] The second holding sub-circuit includes a ninth transistor, a gate of the ninth transistor is coupled to the control signal input terminal, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the fourth node.

[0017] Optionally, the ninth transistor and the tenth transistor include oxide transistors.

[0018] Optionally, the shift register further includes a fourth node and a fourth node control subcircuit, wherein the fourth node control subcircuit is used to control the potential of the fourth node;

[0019] The shift register also includes: a third holding sub-circuit, which is coupled to the second level signal input terminal, the fourth node and the second holding sub-circuit respectively, and is used to control the conduction or disconnection of the electrical connection between the fourth node and the second holding sub-circuit under the control of the second level signal input terminal.

[0020] Optionally, the third holding sub-circuit includes an eighth transistor, the gate of the eighth transistor is coupled to the second level signal input terminal, the first electrode of the eighth transistor is coupled to the second holding sub-circuit, and the second electrode of the eighth transistor is coupled to the fourth node.

[0021] Optionally, the shift register further includes a third node, a fourth node, a third node control subcircuit, and a fourth node control subcircuit, wherein the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node;

[0022] The third node control subcircuit is coupled to the second clock signal input terminal, the second level signal input terminal, the third node and the fourth node respectively, and is used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node under the control of the second clock signal input terminal; and is also used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node under the control of the fourth node.

[0023] Optionally, the third node control subcircuit includes a second transistor and a third transistor;

[0024] The gate of the second transistor is coupled to the fourth node, the first electrode of the second transistor is coupled to the second clock signal input terminal, and the second electrode of the second transistor is coupled to the third node;

[0025] A gate of the third transistor is coupled to the second clock signal input terminal, a first electrode of the third transistor is coupled to the second level signal input terminal, and a second electrode of the third transistor is coupled to the third node.

[0026] Optionally, the shift register further includes a third node, a fourth node, a third node control subcircuit, and a fourth node control subcircuit, wherein the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node;

[0027] The fourth node control subcircuit is coupled to the input signal terminal, the first clock signal input terminal, the second clock signal input terminal, the first level signal input terminal, the third node and the fourth node respectively; and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the fourth node under the control of the second clock signal input terminal; and is also used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the fourth node under the joint control of the third node and the first clock signal input terminal.

[0028] Optionally, the fourth node control subcircuit includes a first transistor, a sixth transistor and a seventh transistor;

[0029] The gate of the first transistor is coupled to the second clock signal input terminal, the first electrode of the first transistor is coupled to the input signal terminal, and the second electrode of the first transistor is coupled to the fourth node;

[0030] The gate of the sixth transistor is coupled to the third node, the first electrode of the sixth transistor is coupled to the first level signal input terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor;

[0031] A gate of the seventh transistor is coupled to the first clock signal input terminal, and a second electrode of the seventh transistor is coupled to the fourth node.

[0032] Optionally, the first output sub-circuit includes a fourth transistor and a first capacitor, wherein a gate of the fourth transistor is coupled to the first node, a first electrode of the fourth transistor is coupled to the first level signal input terminal, and a second electrode of the fourth transistor is coupled to the gate drive signal output terminal; a first terminal of the first capacitor is coupled to the first level signal input terminal, and a second terminal of the first capacitor is coupled to the first node;

[0033] The second output sub-circuit includes a fifth transistor and a second capacitor, the gate of the fifth transistor is coupled to the second node, the first electrode of the fifth transistor is coupled to the first clock signal input terminal, the second electrode of the fifth transistor is coupled to the gate drive signal input terminal, the first terminal of the second capacitor is coupled to the second node, and the second terminal of the second capacitor is coupled to the gate drive signal output terminal.

[0034] Based on the technical solution of the shift register, a second aspect of the present disclosure provides a gate driving circuit comprising a plurality of cascaded shift registers.

[0035] Based on the technical solution of the gate driving circuit, a third aspect of the present disclosure provides a display device including the above-mentioned gate driving circuit.

[0036] Based on the technical solution of the shift register, a fourth aspect of the present disclosure provides a driving method of a shift register, which is used to drive the shift register. The driving method includes multiple driving cycles. In one driving cycle:

[0037] In the holding phase, the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register inputs a first voltage signal;

[0038] Under the control of the first node, the first output sub-circuit controls the electrical connection between the first level signal input terminal and the gate drive signal output terminal; under the control of the second node, the second output sub-circuit controls the electrical connection between the first clock signal input terminal and the gate drive signal output terminal; during at least part of the holding phase, the first holding sub-circuit is in the first operating mode under the control of the control signal input terminal, and keeps the voltage of the first node basically unchanged; the second holding sub-circuit is in the first operating mode under the control of the control signal input terminal, and keeps the voltage of the second node basically unchanged.

[0039] Optionally, the first holding sub-circuit includes a tenth transistor, the second holding sub-circuit includes a ninth transistor, and the ninth transistor and the tenth transistor include oxide transistors;

[0040] During at least a portion of the holding phase, the ninth transistor and the tenth transistor are turned off under the control of the control signal input terminal.

[0041] Optionally, during a drive cycle:

[0042] In the refresh phase, the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register inputs a clock signal; under the control of the control signal input terminal, the ninth transistor and the tenth transistor are turned on. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0044] FIG1 is a schematic diagram of a first sub-circuit of a shift register provided by an embodiment of the present disclosure;

[0045] FIG2 is a schematic diagram of a second sub-circuit of a shift register provided by an embodiment of the present disclosure;

[0046] FIG3 is a first structural diagram of a shift register provided by an embodiment of the present disclosure;

[0047] FIG4 is a second structural diagram of a shift register provided by an embodiment of the present disclosure;

[0048] FIG5 is a timing diagram of various signals connected to the shift register provided by an embodiment of the present disclosure;

[0049] FIG6 is an enlarged schematic diagram of A1 in FIG5 ;

[0050] FIG7 is a third structural diagram of a shift register provided by an embodiment of the present disclosure;

[0051] FIG8 is a fourth structural diagram of a shift register provided in an embodiment of the present disclosure;

[0052] FIG9 is a timing diagram of various signals connected to the shift register provided by an embodiment of the present disclosure;

[0053] FIG10 is an enlarged schematic diagram of A2 in FIG9 . DETAILED DESCRIPTION

[0054] In order to further illustrate the shift register and its driving method, gate driving circuit, and display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0055] Referring to FIG. 1 and FIG. 7 to FIG. 10 , an embodiment of the present disclosure provides a shift register, including: a first node PU, a second node PD, a first output sub-circuit 10 , and a second output sub-circuit 20 ; the shift register further includes a first holding sub-circuit 50 and / or a second holding sub-circuit 60 ;

[0056] The first output sub-circuit 10 is coupled to the first level signal input terminal VGH, the gate drive signal output terminal (such as GOUT_n and GOUT_n+1), and the first node PU, respectively, and is used to control the electrical connection between the first level signal input terminal VGH and the gate drive signal output terminal to be turned on or off under the control of the first node PU;

[0057] The second output sub-circuit 20 is coupled to the first clock signal input terminal (the signal written is GCK or GCB), the gate drive signal output terminal and the second node PD respectively, and is used to control the electrical connection between the first clock signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the second node PD;

[0058] The first holding sub-circuit 50 is coupled to the control signal input terminal Vcon and the first node PU respectively, and is used to keep the voltage of the first node substantially unchanged in the first working mode;

[0059] The second holding sub-circuit 60 is coupled to the control signal input terminal Vcon and the second node PD, respectively, and is configured to keep the voltage of the second node substantially unchanged in the first operating mode.

[0060] Exemplarily, the first node PU includes a pull-up node, and the second node PD includes the following nodes, but is not limited thereto.

[0061] Exemplarily, the first level signal input terminal VGH inputs a high level signal, but is not limited thereto.

[0062] Exemplarily, the shift register further includes a third node N3, a fourth node N4, a third node control module 30, and a fourth node control module 40; the third node control module 30 is coupled to the third node N3 for controlling the potential of the third node N3; the fourth node control module 40 is coupled to the fourth node N4 for controlling the potential of the fourth node N4;

[0063] The first holding sub-circuit 50 is coupled to the control signal input terminal Vcon, the first node PU and the third node N3 respectively, and is used to control the conduction or disconnection of the electrical connection between the first node PU and the third node N3 under the control of the control signal input terminal Vcon.

[0064] The second holding sub-circuit 60 is coupled to the control signal input terminal Vcon, the second node PD and the fourth node N4 respectively, and is used to control the electrical connection between the second node PD and the fourth node N4 to be turned on or off under the control of the control signal input terminal Vcon.

[0065] Exemplarily, the first holding sub-circuit 50 includes a tenth transistor T10, a gate of the tenth transistor T10 coupled to the control signal input terminal Vcon, a first electrode of the tenth transistor T10 coupled to the first node PU, and a second electrode of the tenth transistor T10 coupled to the third node N3. The second holding sub-circuit 60 includes a ninth transistor T9, a gate of the ninth transistor T9 coupled to the control signal input terminal Vcon, a first electrode of the ninth transistor T9 coupled to the second node PD, and a second electrode of the ninth transistor T9 coupled to the fourth node N4.

[0066] Exemplarily, the ninth transistor T9 and the tenth transistor T10 include oxide transistors.

[0067] Exemplarily, the shift register may be applicable to low-frequency driving, but is not limited thereto.

[0068] For example, during low-frequency driving, as shown in FIG10 , in the holding phase P2, the signal input to the first clock signal input terminal and / or the second clock signal input terminal (e.g., GCK / GCB) is set to a high potential for a long time, that is, a first voltage signal is input to replace the original clock signal in the high-frequency hopping mode. At the same time, the control signal input to the control signal input terminal Vcon is adjusted to a low voltage hold, and the ninth transistor T9 and the tenth transistor T10 are controlled to be turned off, so that the first holding sub-circuit 50 and the second holding sub-circuit 60 are both in the first operating mode. By utilizing the low leakage characteristics of the oxide transistor, the voltages of the first node PU and the second node PD remain unchanged, thereby controlling the output signal of the gate drive signal output terminal to maintain a stable voltage. As shown in FIG9 , for comparison, when the control signal is adjusted to a high voltage at 50 ms, it can be found that the voltages of the first node PU and the second node PD gradually shift, which is not conducive to maintaining the output voltage of the gate drive signal output terminal.

[0069] It should be noted that the signal inputted by the first clock signal input terminal and / or the second clock signal input terminal (such as GCK / GCB) is set to a high potential for a long time and enters the holding phase P2. In the holding phase P2, when the control signal inputted by the signal input terminal Vcon is adjusted to low voltage holding, the first holding sub-circuit 50 and the second holding sub-circuit 60 enter the first working mode.

[0070] Exemplarily, the shift register may be used to output a light emitting control signal or a gate scanning signal, but is not limited thereto.

[0071] Based on the problems existing in the background technology, it has been found that, as shown in Figures 3, 4 and 6, when driving at a low frequency (for example, 10 Hz), the gate drive signal output terminal needs to maintain a high voltage output. At this time, the first node PU maintains a low voltage and the second node PD maintains a high voltage. The first clock signal input to the first clock signal input terminal and the second clock signal input to the second clock signal input terminal always maintain a high-frequency jump (toggle) state during the high voltage output stage of the gate drive signal output terminal, which will generate a large amount of power consumption. If the clock signals input to the first clock signal input terminal and the second clock signal input terminal are adjusted to the first voltage signal in the high voltage holding state during the high voltage output stage of the gate drive signal output terminal, the power consumption of the gate drive circuit can be greatly reduced. As shown in Figure 5, this timing setting allows the gate drive signal output terminal to output normally in the initial stage, but as time goes on, the high voltage output of the gate drive signal output terminal begins to be unstable. The reason is that after the clock signal is adjusted to the first voltage signal, the voltages of the first node PU and the second node PD cannot be refreshed by the signal, and become floating state, gradually beginning to drift, thereby making the high voltage output of the gate drive signal output terminal unstable.

[0072] According to the specific structure of the shift register described above, in the shift register provided by the embodiment of the present disclosure, the first holding sub-circuit 50 is coupled to the control signal input terminal and the first node PU, respectively, for keeping the voltage of the first node PU substantially unchanged in the first working mode; the second holding sub-circuit 60 is coupled to the control signal input terminal and the second node PD, respectively, for keeping the voltage of the second node PD substantially unchanged in the first working mode. Therefore, in the shift register provided by the embodiment of the present disclosure, in the holding phase P2, the clock signal input terminal coupled to the shift register is controlled to input a first voltage signal maintaining a fixed potential, and the first holding sub-circuit 50 and the second holding sub-circuit 60 are controlled to be in the first working mode, so as to lock the voltages of the first node PU and the second node PD, thereby ensuring the stability of the signal output by the gate drive signal output terminal.

[0073] According to the specific structure of the above-mentioned shift register, in the shift register provided by the embodiment of the present disclosure, the first holding sub-circuit 50 is set to be able to control the conduction or disconnection of the electrical connection between the first node PU and the third node N3 under the control of the control signal input terminal Vcon; the second holding sub-circuit 60 is able to control the conduction or disconnection of the electrical connection between the second node PD and the fourth node N4 under the control of the control signal input terminal Vcon.

[0074] This configuration allows the shift register to operate in a refresh phase P1 by controlling the clock signal input terminal coupled to the shift register to input a transitioning clock signal, controlling the first holding sub-circuit 50 to connect the first node PU to the third node N3, and controlling the second holding sub-circuit 60 to connect the second node PD to the fourth node N4, thereby achieving the driving function of the shift register. In a hold phase P2, the clock signal input terminal coupled to the shift register is controlled to input a first voltage signal maintaining a fixed potential, controlling the first holding sub-circuit 50 to disconnect the first node PU from the third node N3, and controlling the second holding sub-circuit 60 to disconnect the second node PD from the fourth node N4, thereby locking the voltages of the first node PU and the second node PD, thereby ensuring the stability of the signal output from the gate drive signal output terminal.

[0075] Therefore, in the shift register provided by the embodiment of the present disclosure, the driving function of the shift register is guaranteed in the refresh phase P1. In the hold phase P2, the signal inputted by the clock signal input terminal is switched from a high-frequency jump state to a fixed voltage hold state by controlling the clock signal input terminal, thereby effectively reducing the power consumption of the shift register. At the same time, in the hold phase P2, the voltages of the first node PU and the second node PD are locked by the first hold sub-circuit 50 and the second hold sub-circuit 60, thereby preventing the voltages of the first node PU and the second node PD from shifting at the hold nodes, thereby ensuring the stability of the signal outputted by the gate drive signal output terminal. Therefore, when the shift register provided by the embodiment of the present disclosure is applied to a gate drive circuit, the power consumption generated by the gate drive circuit portion is effectively reduced.

[0076] As shown in Figures 2, 7 and 8, in some embodiments, the shift register further includes: a third holding sub-circuit 70, which is respectively coupled to the second level signal input terminal VGL, the fourth node N4 and the second holding sub-circuit 60, and is used to control the conduction or disconnection of the electrical connection between the fourth node N4 and the second holding sub-circuit 60 under the control of the second level signal input terminal VGL.

[0077] Exemplarily, the third holding sub-circuit 70 includes an eighth transistor T8, a gate of the eighth transistor T8 coupled to the second level signal input terminal VGL, a first electrode of the eighth transistor T8 coupled to the second holding sub-circuit 60, and a second electrode of the eighth transistor T8 coupled to the fourth node N4. The second level signal input terminal VGL controls the on / off state of the eighth transistor T8.

[0078] Exemplarily, the second level signal input terminal VGL inputs a low level signal, but is not limited thereto.

[0079] Exemplarily, the eighth transistor T8 includes a low-temperature polysilicon transistor, but is not limited thereto.

[0080] The third holding sub-circuit 70 can ensure that the drain-source voltage Vds of the first transistor T1 is not particularly large in any phase.

[0081] As shown in Figures 2, 7 and 8, in some embodiments, the third node control sub-circuit 30 is respectively coupled to the second clock signal input terminal, the second level signal input terminal VGL, the third node N3 and the fourth node N4, and is used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node N3 under the control of the second clock signal input terminal; and is also used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node N3 under the control of the fourth node N4.

[0082] Exemplarily, the third node control subcircuit 30 includes a second transistor T2 and a third transistor T3;

[0083] The gate of the second transistor T2 is coupled to the fourth node N4, the first electrode of the second transistor T2 is coupled to the second clock signal input terminal, and the second electrode of the second transistor T2 is coupled to the third node N3; the fourth node N4 controls whether the second transistor T2 is turned on.

[0084] The gate of the third transistor T3 is coupled to the second clock signal input terminal, the first electrode of the third transistor T3 is coupled to the second level signal input terminal VGL, and the second electrode of the third transistor T3 is coupled to the third node N3. The second clock signal input terminal controls whether the third transistor T3 is turned on.

[0085] As shown in Figures 2, 7 and 8, in some embodiments, the fourth node control sub-circuit 40 is respectively coupled to the input signal terminal (such as GOUT_n and GOUT_n-1), the first clock signal input terminal, the second clock signal input terminal, the first level signal input terminal VGH, the third node N3 and the fourth node N4; and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the fourth node N4 under the control of the second clock signal input terminal; and is also used to control the conduction or disconnection of the electrical connection between the first level signal input terminal VGH and the fourth node N4 under the common control of the third node N3 and the first clock signal input terminal.

[0086] Exemplarily, the fourth node control subcircuit 40 includes a first transistor T1, a sixth transistor T6 and a seventh transistor T7;

[0087] The gate of the first transistor T1 is coupled to the second clock signal input terminal, the first electrode of the first transistor T1 is coupled to the input signal terminal, and the second electrode of the first transistor T1 is coupled to the fourth node N4; the second clock signal input terminal is used to control whether the first transistor T1 is turned on.

[0088] The gate of the sixth transistor T6 is coupled to the third node N3, the first electrode of the sixth transistor T6 is coupled to the first level signal input terminal VGH, and the second electrode of the sixth transistor T6 is coupled to the first electrode of the seventh transistor T7; the third node N3 controls whether the sixth transistor T6 is turned on.

[0089] The gate of the seventh transistor T7 is coupled to the first clock signal input terminal, and the second electrode of the seventh transistor T7 is coupled to the fourth node N4. The first clock signal input terminal controls whether the seventh transistor T7 is turned on.

[0090] As shown in Figures 2, 7 and 8, in some embodiments, the first output sub-circuit 10 includes a fourth transistor T4 and a first capacitor C1, the gate of the fourth transistor T4 is coupled to the first node PU, the first electrode of the fourth transistor T4 is coupled to the first level signal input terminal VGH, and the second electrode of the fourth transistor T4 is coupled to the gate drive signal output terminal; the first end of the first capacitor C1 is coupled to the first level signal input terminal VGH, and the second end of the first capacitor C1 is coupled to the first node PU; the first node PU controls whether the fourth transistor T4 is turned on.

[0091] The second output sub-circuit 20 includes a fifth transistor T5 and a second capacitor C2. The gate of the fifth transistor T5 is coupled to the second node PD. A first electrode of the fifth transistor T5 is coupled to the first clock signal input terminal. A second electrode of the fifth transistor T5 is coupled to the gate drive signal input terminal. A first terminal of the second capacitor C2 is coupled to the second node PD. A second terminal of the second capacitor C2 is coupled to the gate drive signal output terminal. The second node PD controls whether the fifth transistor T5 is turned on.

[0092] Exemplarily, in the shift register, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 all include low-temperature polysilicon transistors, and the ninth transistor T9 and the tenth transistor T10 include oxide transistors, but are not limited to this.

[0093] An embodiment of the present disclosure further provides a gate driving circuit, comprising a plurality of cascaded shift registers provided by the above embodiments.

[0094] As shown in FIG. 7 and FIG. 8 , illustratively, in two adjacent stages of shift registers, the gate drive signal output terminal GOUT_n of the upper stage shift register is coupled to the input signal terminal of the lower stage shift register.

[0095] Exemplarily, in two adjacent shift registers, the signal input to the first clock signal input terminal coupled to the upper-stage shift register (e.g., GCB) is the same as the signal input to the second clock signal input terminal coupled to the lower-stage shift register (e.g., GCB), and the signal input to the second clock signal input terminal coupled to the upper-stage shift register (e.g., GCK) is the same as the signal input to the first clock signal input terminal coupled to the lower-stage shift register (e.g., GCK), but is not limited to this.

[0096] It should be noted that FIG9 also illustrates a frame start signal GSTV.

[0097] When the shift register provided by the above embodiment operates, in refresh phase P1, the clock signal input terminal coupled to the shift register is controlled to input a transitional clock signal, the first holding sub-circuit 50 is controlled to establish an electrical connection between the first node PU and the third node N3, and the second holding sub-circuit 60 is controlled to establish an electrical connection between the second node PD and the fourth node N4, thereby achieving the driving function of the shift register. In hold phase P2, the clock signal input terminal coupled to the shift register is controlled to input a first voltage signal maintaining a fixed potential, the first holding sub-circuit 50 is controlled to disconnect the electrical connection between the first node PU and the third node N3, and the second holding sub-circuit 60 is controlled to disconnect the electrical connection between the second node PD and the fourth node N4, thereby locking the voltages of the first node PU and the second node PD and ensuring the stability of the signal output by the gate drive signal output terminal. In the shift register provided by the above embodiment, the driving function of the shift register is ensured in refresh phase P1. In hold phase P2, the power consumption of the shift register is effectively reduced by controlling the signal input to the clock signal input terminal to switch from a high-frequency transition state to a fixed voltage hold state. At the same time, during the hold phase P2, the voltages of the first node PU and the second node PD are locked by the first hold sub-circuit 50 and the second hold sub-circuit 60, preventing the voltages of the first node PU and the second node PD from shifting at the hold nodes, thereby ensuring the stability of the signal output by the gate drive signal output terminal. Therefore, the gate drive circuit provided by the embodiments of the present disclosure, when including the above-described shift register, can effectively reduce the power consumption of the gate drive circuit and ensure the stability of the output signal of the gate drive circuit.

[0098] An embodiment of the present disclosure further provides a display device, comprising the gate driving circuit provided by the above embodiment.

[0099] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0100] The gate driving circuit provided in the above embodiment can effectively reduce the power consumption generated by the gate driving circuit and ensure the stability of the output signal of the gate driving circuit. Therefore, the display device provided in the embodiment of the present disclosure also has the above beneficial effects when including the above gate driving circuit, which will not be repeated here.

[0101] The present disclosure also provides a shift register driving method for driving the shift register provided in the above embodiment. The driving method includes multiple driving cycles. In one driving cycle:

[0102] As shown in FIG9 and FIG10 , in the holding phase P2 , the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register inputs a first voltage signal;

[0103] Under the control of the first node PU, the first output sub-circuit 10 controls the electrical connection between the first level signal input terminal VGH and the gate drive signal output terminal; under the control of the second node PD, the second output sub-circuit 20 controls the electrical connection between the first clock signal input terminal and the gate drive signal output terminal. During at least part of the period of the holding phase P2, the first holding sub-circuit 50 is in the first operating mode under the control of the control signal input terminal Vcon, and keeps the voltage of the first node PU basically unchanged; the second holding sub-circuit 60 is in the first operating mode under the control of the control signal input terminal Vcon, and keeps the voltage of the second node PD basically unchanged.

[0104] Illustratively, during at least a portion of the holding phase P2, the first holding sub-circuit 50, under the control of the control signal input terminal Vcon, controls the disconnection of the electrical connection between the first node PU and the third node N3; and during at least a portion of the holding phase P2, the second holding sub-circuit 60, under the control of the control signal input terminal Vcon, controls the disconnection of the electrical connection between the second node PD and the fourth node N4.

[0105] Exemplarily, the first holding sub-circuit 50 includes a tenth transistor T10, the second holding sub-circuit 60 includes a ninth transistor T9, and the ninth transistor T9 and the tenth transistor T10 include oxide transistors; during at least part of the holding phase P2, under the control of the control signal input terminal Vcon, the ninth transistor T9 and the tenth transistor T10 are turned off.

[0106] Exemplarily, a driving cycle includes a refresh phase P1 and a hold phase P2. During the refresh phase P1, a clock signal is input to the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register, where the clock signal is a high-frequency hopping signal; under the control of the control signal input terminal Vcon, the ninth transistor T9 and the tenth transistor T10 are turned on. During the hold phase P2, a first voltage signal is input to the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register; under the control of the control signal input terminal Vcon, the ninth transistor T9 and the tenth transistor T10 are turned off.

[0107] In the shift register provided in the above embodiment, the first holding sub-circuit 50 is set to be able to control the conduction or disconnection of the electrical connection between the first node PU and the third node N3 under the control of the control signal input terminal Vcon; the second holding sub-circuit 60 is able to control the conduction or disconnection of the electrical connection between the second node PD and the fourth node N4 under the control of the control signal input terminal Vcon.

[0108] When the driving method provided by the embodiment of the present disclosure is used to drive the shift register provided by the above embodiment, in the refresh phase P1, the clock signal input terminal coupled to the shift register is controlled to input a jumping clock signal, the first holding sub-circuit 50 is controlled to conduct the electrical connection between the first node PU and the third node N3, and the second holding sub-circuit 60 is controlled to conduct the electrical connection between the second node PD and the fourth node N4, thereby realizing the driving function of the shift register. In the hold phase P2, the clock signal input terminal coupled to the shift register is controlled to input a first voltage signal maintaining a fixed potential, the first holding sub-circuit 50 is controlled to disconnect the electrical connection between the first node PU and the third node N3, and the second holding sub-circuit 60 is controlled to disconnect the electrical connection between the second node PD and the fourth node N4, so as to lock the voltages of the first node PU and the second node PD, thereby ensuring the stability of the signal output by the gate drive signal output terminal.

[0109] Therefore, the driving method provided by the embodiment of the present disclosure is used to drive the shift register provided by the above embodiment, and the driving function of the shift register is guaranteed in the refresh phase P1. In the holding phase P2, the signal inputted by the clock signal input terminal is switched from a high-frequency jump state to a fixed voltage holding state by controlling the clock signal input terminal, thereby effectively reducing the power consumption of the shift register. At the same time, in the holding phase P2, the voltages of the first node PU and the second node PD are locked by the first holding sub-circuit 50 and the second holding sub-circuit 60, thereby preventing the voltages of the first node PU and the second node PD from shifting at the holding nodes, thereby ensuring the stability of the signal outputted by the gate drive signal output terminal. Therefore, when the shift register provided by the embodiment of the present disclosure is applied to the gate drive circuit, the power consumption generated by the gate drive circuit portion is effectively reduced.

[0110] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0111] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0112] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0113] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0114] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0115] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A shift register, comprising: A first node, a second node, a first output subcircuit, and a second output subcircuit; the shift register further includes a first holding subcircuit and / or a second holding subcircuit; The first output subcircuit is coupled to the first level signal input terminal, the gate drive signal output terminal and the first node respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the gate drive signal output terminal under the control of the first node; The second output subcircuit is coupled to the first clock signal input terminal, the gate drive signal output terminal and the second node respectively, and is used to control the conduction or disconnection of the electrical connection between the first clock signal input terminal and the gate drive signal output terminal under the control of the second node; The first holding subcircuit is coupled to the control signal input terminal and the first node respectively, and is used to keep the voltage of the first node substantially unchanged in the first working mode; The second holding subcircuit is coupled to the control signal input terminal and the second node respectively, and is used to keep the voltage of the second node substantially unchanged in the first working mode.

2. The shift register according to claim 1, wherein: The shift register further comprises a third node, a fourth node, a third node control subcircuit and a fourth node control subcircuit, wherein the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node; The first holding subcircuit includes a tenth transistor, a gate of the tenth transistor is coupled to the control signal input terminal, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the third node; The second holding subcircuit includes a ninth transistor, a gate of the ninth transistor is coupled to the control signal input terminal, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the fourth node.

3. The shift register according to claim 2, wherein: The ninth transistor and the tenth transistor include oxide transistors.

4. The shift register according to claim 1, wherein: The shift register further includes a fourth node and a fourth node control subcircuit, wherein the fourth node control subcircuit is used to control the potential of the fourth node; The shift register also includes: a third holding sub-circuit, which is coupled to the second level signal input terminal, the fourth node and the second holding sub-circuit respectively, and is used to control the conduction or disconnection of the electrical connection between the fourth node and the second holding sub-circuit under the control of the second level signal input terminal.

5. The shift register according to claim 4, wherein: The third holding subcircuit includes an eighth transistor, a gate of the eighth transistor is coupled to the second level signal input terminal, a first electrode of the eighth transistor is coupled to the second holding subcircuit, and a second electrode of the eighth transistor is coupled to the fourth node.

6. The shift register according to claim 1, wherein: The shift register further comprises a third node, a fourth node, a third node control subcircuit and a fourth node control subcircuit, wherein the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node; The third node control subcircuit is coupled to the second clock signal input terminal, the second level signal input terminal, the third node and the fourth node respectively, and is used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node under the control of the second clock signal input terminal; It is also used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node under the control of the fourth node.

7. The shift register according to claim 6, wherein: The third node control subcircuit includes a second transistor and a third transistor; The gate of the second transistor is coupled to the fourth node, the first electrode of the second transistor is coupled to the second clock signal input terminal, and the second electrode of the second transistor is coupled to the third node; A gate of the third transistor is coupled to the second clock signal input terminal, a first electrode of the third transistor is coupled to the second level signal input terminal, and a second electrode of the third transistor is coupled to the third node.

8. The shift register according to claim 1, wherein: The shift register further comprises a third node, a fourth node, a third node control subcircuit and a fourth node control subcircuit, wherein the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node; The fourth node control subcircuit is coupled to the input signal terminal, the first clock signal input terminal, the second clock signal input terminal, the first level signal input terminal, the third node and the fourth node respectively; and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the fourth node under the control of the second clock signal input terminal; It is also used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the fourth node under the common control of the third node and the first clock signal input terminal.

9. The shift register according to claim 8, wherein: The fourth node control subcircuit includes a first transistor, a sixth transistor and a seventh transistor; The gate of the first transistor is coupled to the second clock signal input terminal, the first electrode of the first transistor is coupled to the input signal terminal, and the second electrode of the first transistor is coupled to the fourth node; The gate of the sixth transistor is coupled to the third node, the first electrode of the sixth transistor is coupled to the first level signal input terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor; A gate of the seventh transistor is coupled to the first clock signal input terminal, and a second electrode of the seventh transistor is coupled to the fourth node.

10. The shift register according to claim 1, wherein: The first output subcircuit includes a fourth transistor and a first capacitor, the gate of the fourth transistor is coupled to the first node, the first electrode of the fourth transistor is coupled to the first level signal input terminal, and the second electrode of the fourth transistor is coupled to the gate drive signal output terminal; the first terminal of the first capacitor is coupled to the first level signal input terminal, and the second terminal of the first capacitor is coupled to the first node; The second output subcircuit includes a fifth transistor and a second capacitor, the gate of the fifth transistor is coupled to the second node, the first electrode of the fifth transistor is coupled to the first clock signal input terminal, the second electrode of the fifth transistor is coupled to the gate drive signal input terminal, the first terminal of the second capacitor is coupled to the second node, and the second terminal of the second capacitor is coupled to the gate drive signal output terminal.

11. A gate driving circuit, comprising a plurality of cascaded shift registers according to any one of claims 1 to 10.

12. A display device comprising the gate driving circuit according to claim 11.

13. A shift register driving method, for driving the shift register according to any one of claims 1 to 10, the driving method comprising a plurality of driving cycles, in one driving cycle: In the holding phase, the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register inputs a first voltage signal; The first output subcircuit, under the control of the first node, controls the electrical connection between the first level signal input terminal and the gate drive signal output terminal; the second output subcircuit, under the control of the second node, controls the electrical connection between the first clock signal input terminal and the gate drive signal output terminal to be disconnected; during at least part of the holding phase, the first holding subcircuit, under the control of the control signal input terminal, is in the first operating mode, keeping the voltage of the first node basically unchanged; the second holding subcircuit, under the control of the control signal input terminal, is in the first operating mode, keeping the voltage of the second node basically unchanged.

14. The shift register driving method according to claim 13, wherein: The first holding subcircuit includes a tenth transistor, the second holding subcircuit includes a ninth transistor, the ninth transistor and the tenth transistor include oxide transistors; During at least a portion of the holding phase, under the control of the control signal input terminal, the ninth transistor and the tenth transistor are turned off.

15. The driving method of the shift register according to claim 13, wherein: In a drive cycle: In the refresh phase, the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register inputs a clock signal; under the control of the control signal input terminal, the ninth transistor and the tenth transistor are turned on.

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