Shift register and drive method therefor, and gate drive circuit and display apparatus

Abstract

A shift register and a drive method therefor, and a gate drive circuit and a display apparatus. The shift register comprises: an input sub-circuit, an output sub-circuit and a first control sub-circuit, wherein the input sub-circuit is electrically connected to a signal input end and a pull-up node, and is configured to provide a signal to the pull-up node under the control of a signal from the signal input end; the output sub-circuit is electrically connected to a first output end, the pull-up node and a clock signal end, and is configured to provide a signal from the clock signal end to the first output end under the control of a signal from the pull-up node; and the first control sub-circuit is electrically connected to a control signal end and a signal input end, and is configured to provide a signal from the control signal end to the signal input end under the control of the signal from the control signal end.

Description

Shift register and driving method thereof, gate driving circuit, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 20, 2023, with application number 202310904148.7 and invention name “Shift register and its driving method, gate drive circuit, display device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0003] In recent years, flat panel displays, such as Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Active Matrix Organic Light Emitting Diode (AMOLED), have been widely used in electronic products such as televisions and mobile phones due to their advantages such as light weight, thin thickness and low power consumption.

[0004] With the advancement of technology, high-resolution, narrow-border display panels have become a development trend. To this end, the array substrate gate driver (GOA) technology has emerged. GOA technology refers to the technology of placing the GOA circuit used to drive the gate line on both sides of the effective display area of ​​the array substrate in the display panel.

[0005] Summary of the Invention

[0006] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0007] In a first aspect, the present disclosure provides a shift register, comprising: an input subcircuit, an output subcircuit, and a first control subcircuit, wherein the operation process of the shift register comprises: a display phase and a non-display phase, wherein the display phase comprises: an output phase and a non-output phase;

[0008] The input sub-circuit is electrically connected to the signal input terminal and the pull-up node, respectively, and is configured to provide a signal to the pull-up node under the control of the signal of the signal input terminal;

[0009] The output sub-circuit is electrically connected to the first output terminal, the pull-up node and the clock signal terminal respectively, and is configured to provide the signal of the clock signal terminal to the first output terminal under the control of the signal of the pull-up node;

[0010] The first control subcircuit is electrically connected to the control signal terminal and the signal input terminal, and is configured to provide the signal of the control signal terminal to the signal input terminal under the control of the signal of the control signal terminal.

[0011] In an exemplary embodiment, the shift register further includes: a first reset subcircuit;

[0012] The first reset sub-circuit is electrically connected to the general reset signal terminal, the pull-up node and the first power supply terminal respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node under the control of the general reset signal terminal;

[0013] The general reset signal terminal is a valid level signal in a partial time period of the non-display phase, and is an invalid level signal in the display phase.

[0014] In an exemplary embodiment, the control signal terminal includes: at least one of a first control signal terminal and a second control signal terminal;

[0015] The first control signal terminal is electrically connected to the general reset signal terminal, and the second control signal terminal is electrically connected to the first output terminal.

[0016] In an exemplary embodiment, in a state where the control signal terminal includes the first control signal terminal, the first control sub-circuit includes: a nineteenth transistor;

[0017] The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal.

[0018] In an exemplary embodiment, in a state where the control signal terminal includes the second control signal terminal, the first control subcircuit includes: a twentieth transistor;

[0019] The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

[0020] In an exemplary embodiment, in a state where the control signal terminal includes a first control signal terminal and a second control signal terminal, the control subcircuit includes: a nineteenth transistor and a twentieth transistor;

[0021] The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal;

[0022] The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

[0023] In an exemplary embodiment, the input subcircuit includes: a first transistor;

[0024] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the pull-up node.

[0025] In an exemplary embodiment, the input subcircuit includes: a first transistor and a twenty-first transistor;

[0026] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0027] The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

[0028] In an exemplary embodiment, the output subcircuit includes: a second transistor and a capacitor;

[0029] A control electrode of the second transistor is electrically connected to the pull-up node, a first electrode of the second transistor is electrically connected to the clock signal terminal, and a second electrode of the second transistor is electrically connected to the first output terminal;

[0030] A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output end.

[0031] In an exemplary embodiment, the output sub-circuit is further electrically connected to the second output terminal and is configured to provide a signal from the clock signal terminal to the second output terminal under the control of a signal from the pull-up node.

[0032] In an exemplary embodiment, the output sub-circuit includes: a second transistor, a third transistor, and a capacitor;

[0033] A control electrode of the second transistor is electrically connected to the pull-up node, a first electrode of the second transistor is electrically connected to the clock signal terminal, and a second electrode of the second transistor is electrically connected to the first output terminal;

[0034] A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal;

[0035] A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output end.

[0036] In an exemplary embodiment, the first reset sub-circuit includes: a fourth transistor;

[0037] The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal.

[0038] In an exemplary embodiment, the shift register further includes: a second reset subcircuit;

[0039] The second reset sub-circuit is electrically connected to the first reset signal terminal, the second reset signal terminal, the pull-up node, the first output terminal, the first power terminal, and the third power terminal, respectively, and is configured to provide a signal from the first power terminal to the pull-up node and a signal from the third power terminal to the first output terminal under the control of the signals from the first reset signal terminal and the second reset signal terminal;

[0040] The absolute value of the voltage of the signal at the first power supply terminal is greater than the absolute value of the voltage of the signal at the third power supply terminal;

[0041] The first reset signal terminal and the second reset signal terminal are invalid level signals in the non-display stage and the output stage, and are valid level signals in a partial time period of the non-output stage.

[0042] In an exemplary embodiment, the second reset sub-circuit includes: a fifth transistor and a sixth transistor;

[0043] The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal;

[0044] The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the third power supply terminal.

[0045] In an exemplary embodiment, the shift register further includes: a noise reduction subcircuit, wherein the noise reduction subcircuit includes: at least one of a first noise reduction subcircuit and a second noise reduction subcircuit;

[0046] The first noise reduction sub-circuit is electrically connected to the fourth power supply terminal, the signal input terminal, the pull-up node, the first output terminal, the second output terminal, the first power supply terminal, and the third power supply terminal, respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node and the second output terminal, and provide the signal of the third power supply terminal to the pull-down node under the control of the signals of the signal input terminal, the pull-up node, and the fourth power supply terminal;

[0047] The second noise reduction sub-circuit is electrically connected to the fifth power supply terminal, the signal input terminal, the pull-up node, the first output terminal, the second output terminal, the first power supply terminal and the third power supply terminal, respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node and the second output terminal, and provide the signal of the third power supply terminal to the pull-down node under the control of the signals of the signal input terminal, the pull-up node and the fifth power supply terminal.

[0048] In an exemplary embodiment, the first noise reduction sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor, and the second noise reduction sub-circuit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor;

[0049] The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal;

[0050] a control electrode of the eighth transistor electrically connected to the pull-up node, a first electrode of the eighth transistor electrically connected to the first pull-down node, and a second electrode of the eighth transistor electrically connected to the first power supply terminal;

[0051] The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node;

[0052] The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal;

[0053] The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal;

[0054] The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node;

[0055] A control electrode of the thirteenth transistor is electrically connected to the first pull-down node, a first electrode of the thirteenth transistor is electrically connected to the pull-up node, and a second electrode of the thirteenth transistor is electrically connected to the first power supply terminal;

[0056] a control electrode of the fourteenth transistor electrically connected to the first pull-down node, a first electrode of the fourteenth transistor electrically connected to the first output terminal, and a second electrode of the fourteenth transistor electrically connected to the third power supply terminal;

[0057] A control electrode of the fifteenth transistor is electrically connected to the first pull-down node, a first electrode of the fifteenth transistor is electrically connected to the second output terminal, and a second electrode of the fifteenth transistor is electrically connected to the first power supply terminal;

[0058] A control electrode of the sixteenth transistor is electrically connected to the second pull-down node, a first electrode of the sixteenth transistor is electrically connected to the pull-up node, and a second electrode of the sixteenth transistor is electrically connected to the first power supply terminal;

[0059] The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal;

[0060] The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal.

[0061] In an exemplary embodiment, the invention further includes: a first reset sub-circuit, a second reset sub-circuit, and a noise reduction sub-circuit; the input sub-circuit includes: a first transistor; the output sub-circuit includes: a second transistor, a third transistor, and a capacitor; the first control sub-circuit includes: at least one of a nineteenth transistor and a twentieth transistor; the first reset sub-circuit includes: a fourth transistor; the second reset sub-circuit includes: a fifth transistor and a sixth transistor; the noise reduction sub-circuit includes: seventh to eighteenth transistors;

[0062] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the pull-up node;

[0063] A control electrode of the second transistor is electrically connected to the pull-up node, a first electrode of the second transistor is electrically connected to the clock signal terminal, and a second electrode of the second transistor is electrically connected to the first output terminal;

[0064] A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal;

[0065] A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal;

[0066] The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal;

[0067] The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal;

[0068] The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the first power supply terminal;

[0069] The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal;

[0070] a control electrode of the eighth transistor electrically connected to the pull-up node, a first electrode of the eighth transistor electrically connected to the first pull-down node, and a second electrode of the eighth transistor electrically connected to the first power supply terminal;

[0071] The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node;

[0072] The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal;

[0073] The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal;

[0074] The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node;

[0075] A control electrode of the thirteenth transistor is electrically connected to the first pull-down node, a first electrode of the thirteenth transistor is electrically connected to the pull-up node, and a second electrode of the thirteenth transistor is electrically connected to the first power supply terminal;

[0076] a control electrode of the fourteenth transistor electrically connected to the first pull-down node, a first electrode of the fourteenth transistor electrically connected to the first output terminal, and a second electrode of the fourteenth transistor electrically connected to the third power supply terminal;

[0077] A control electrode of the fifteenth transistor is electrically connected to the first pull-down node, a first electrode of the fifteenth transistor is electrically connected to the second output terminal, and a second electrode of the fifteenth transistor is electrically connected to the first power supply terminal;

[0078] A control electrode of the sixteenth transistor is electrically connected to the second pull-down node, a first electrode of the sixteenth transistor is electrically connected to the pull-up node, and a second electrode of the sixteenth transistor is electrically connected to the first power supply terminal;

[0079] The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal;

[0080] The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal;

[0081] The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal;

[0082] The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

[0083] In an exemplary embodiment, the invention further includes: a first reset sub-circuit, a second reset sub-circuit, and a noise reduction sub-circuit; the input sub-circuit includes: a first transistor and a twenty-first transistor; the output sub-circuit includes: a second transistor, a third transistor, and a capacitor; the first control sub-circuit includes: at least one of a nineteenth transistor and a twenty-first transistor; the first reset sub-circuit includes: a fourth transistor; the second reset sub-circuit includes: a fifth transistor and a sixth transistor; the noise reduction sub-circuit includes: a seventh transistor to an eighteenth transistor;

[0084] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0085] A control electrode of the second transistor is electrically connected to the pull-up node, a first electrode of the second transistor is electrically connected to the clock signal terminal, and a second electrode of the second transistor is electrically connected to the first output terminal;

[0086] A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal;

[0087] A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal;

[0088] The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal;

[0089] The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal;

[0090] The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the first power supply terminal;

[0091] The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal;

[0092] a control electrode of the eighth transistor electrically connected to the pull-up node, a first electrode of the eighth transistor electrically connected to the first pull-down node, and a second electrode of the eighth transistor electrically connected to the first power supply terminal;

[0093] The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node;

[0094] The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal;

[0095] The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal;

[0096] The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node;

[0097] A control electrode of the thirteenth transistor is electrically connected to the first pull-down node, a first electrode of the thirteenth transistor is electrically connected to the pull-up node, and a second electrode of the thirteenth transistor is electrically connected to the first power supply terminal;

[0098] a control electrode of the fourteenth transistor electrically connected to the first pull-down node, a first electrode of the fourteenth transistor electrically connected to the first output terminal, and a second electrode of the fourteenth transistor electrically connected to the third power supply terminal;

[0099] A control electrode of the fifteenth transistor is electrically connected to the first pull-down node, a first electrode of the fifteenth transistor is electrically connected to the second output terminal, and a second electrode of the fifteenth transistor is electrically connected to the first power supply terminal;

[0100] A control electrode of the sixteenth transistor is electrically connected to the second pull-down node, a first electrode of the sixteenth transistor is electrically connected to the pull-up node, and a second electrode of the sixteenth transistor is electrically connected to the first power supply terminal;

[0101] The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal;

[0102] The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal;

[0103] The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal;

[0104] The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal;

[0105] The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

[0106] In a second aspect, the present disclosure further provides a shift register, comprising: an input subcircuit, an output subcircuit, and a second control subcircuit;

[0107] The input subcircuit is electrically connected to the signal input terminal and the control node respectively, and is configured to provide a signal to the control node under the control of the signal input terminal;

[0108] The second control sub-circuit is electrically connected to the control node and the pull-up node, respectively, and is configured to provide the signal of the control node to the pull-up node under the control of the signal of the control node;

[0109] The output sub-circuit is electrically connected to the first output terminal, the pull-up node and the clock signal terminal respectively, and is configured to provide the signal of the clock signal terminal to the first output terminal under the control of the signal of the pull-up node.

[0110] In an exemplary embodiment, the invention further includes: a first reset sub-circuit, a second reset sub-circuit, and a noise reduction sub-circuit; the input sub-circuit includes: a first transistor; the output sub-circuit includes: a second transistor, a third transistor, and a capacitor; the second control sub-circuit includes: a twenty-first transistor; the first reset sub-circuit includes: a fourth transistor; the second reset sub-circuit includes: a fifth transistor and a sixth transistor; the noise reduction sub-circuit includes: seventh to eighteenth transistors;

[0111] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0112] A control electrode of the second transistor is electrically connected to the pull-up node, a first electrode of the second transistor is electrically connected to the clock signal terminal, and a second electrode of the second transistor is electrically connected to the first output terminal;

[0113] A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal;

[0114] A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal;

[0115] The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal;

[0116] The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal;

[0117] The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the first power supply terminal;

[0118] The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal;

[0119] a control electrode of the eighth transistor electrically connected to the pull-up node, a first electrode of the eighth transistor electrically connected to the first pull-down node, and a second electrode of the eighth transistor electrically connected to the first power supply terminal;

[0120] The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node;

[0121] The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal;

[0122] The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal;

[0123] The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node;

[0124] A control electrode of the thirteenth transistor is electrically connected to the first pull-down node, a first electrode of the thirteenth transistor is electrically connected to the pull-up node, and a second electrode of the thirteenth transistor is electrically connected to the first power supply terminal;

[0125] a control electrode of the fourteenth transistor electrically connected to the first pull-down node, a first electrode of the fourteenth transistor electrically connected to the first output terminal, and a second electrode of the fourteenth transistor electrically connected to the third power supply terminal;

[0126] A control electrode of the fifteenth transistor is electrically connected to the first pull-down node, a first electrode of the fifteenth transistor is electrically connected to the second output terminal, and a second electrode of the fifteenth transistor is electrically connected to the first power supply terminal;

[0127] A control electrode of the sixteenth transistor is electrically connected to the second pull-down node, a first electrode of the sixteenth transistor is electrically connected to the pull-up node, and a second electrode of the sixteenth transistor is electrically connected to the first power supply terminal;

[0128] The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal;

[0129] The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal;

[0130] The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

[0131] In a third aspect, the present disclosure further provides a gate drive circuit, comprising: a plurality of cascaded shift registers as described above.

[0132] In an exemplary embodiment, the gate driving circuit is provided in a display device, the display device is further provided with a gate line, and the shift register includes an output subcircuit;

[0133] When the output sub-circuit includes the first output terminal, the first output terminal of any level shift register is electrically connected to the gate line, the first output terminal of the current level shift register is electrically connected to the signal input terminal of the next level shift register, and the first output terminal of the current level shift register is electrically connected to the first reset signal terminal or the second reset signal terminal of the previous level shift register.

[0134] In an exemplary embodiment, the gate driving circuit is provided in a display device, the display device is further provided with a gate line, and the shift register includes an output subcircuit;

[0135] When the output sub-circuit includes a first output terminal and a second output terminal, the first output terminal of any level shift register is electrically connected to the gate line, the second output terminal of the current level shift register is electrically connected to the signal input terminal of the next level shift register, and the second output terminal of the current level shift register is electrically connected to the first reset signal terminal or the second reset signal terminal of the previous level shift register.

[0136] In a fourth aspect, the present disclosure further provides a display device comprising the above-mentioned gate driving circuit.

[0137] In a fifth aspect, the present disclosure further provides a shift register driving method, which is configured to drive the above-mentioned shift register, the method comprising:

[0138] The input subcircuit provides a signal to the pull-up node under the control of the signal at the signal input terminal;

[0139] The output sub-circuit provides a signal from the clock signal terminal to the first output terminal under the control of the signal from the pull-up node;

[0140] The control subcircuit provides the signal of the control signal terminal to the signal input terminal under the control of the signal of the control signal terminal.

[0141] In a sixth aspect, the present disclosure further provides a shift register driving method, which is configured to drive the above-mentioned shift register, the method comprising:

[0142] The input subcircuit provides a signal to the control node under the control of the signal input terminal;

[0143] The second control subcircuit provides the signal of the control node to the pull-up node under the control of the signal of the control node;

[0144] The output sub-circuit is configured to provide a signal of the clock signal terminal to the first output terminal under the control of a signal of the pull-up node.

[0145] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0146] Summary of the Figures

[0147] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0148] FIG1 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure;

[0149] FIG2 is a first structural diagram of a shift register provided in an exemplary embodiment;

[0150] FIG3 is a first connection diagram of a first control subcircuit provided in an exemplary embodiment;

[0151] FIG4 is a second connection diagram of a first control subcircuit provided in an exemplary embodiment;

[0152] FIG5 is a third connection diagram of a first control subcircuit provided in an exemplary embodiment;

[0153] FIG6 is an equivalent circuit diagram 1 of a first control subcircuit provided in an exemplary embodiment;

[0154] FIG7 is a second equivalent circuit diagram of a first control subcircuit provided in an exemplary embodiment;

[0155] FIG8 is a third equivalent circuit diagram of a first control subcircuit provided in an exemplary embodiment;

[0156] FIG9 is an equivalent circuit diagram 1 of an input sub-circuit provided in an exemplary embodiment;

[0157] FIG10 is a second equivalent circuit diagram of an input sub-circuit provided in an exemplary embodiment;

[0158] FIG11 is an equivalent circuit diagram 1 of an output sub-circuit provided in an exemplary embodiment;

[0159] FIG12 is a second equivalent circuit diagram of an output sub-circuit provided in an exemplary embodiment;

[0160] FIG13 is an equivalent circuit diagram of a first reset sub-circuit provided in an exemplary embodiment;

[0161] FIG14 is a second structural diagram of a shift register provided in an exemplary embodiment;

[0162] FIG15 is an equivalent circuit diagram of a second reset sub-circuit provided in an exemplary embodiment;

[0163] FIG16 is an equivalent circuit diagram of a noise reduction sub-circuit provided in an exemplary embodiment;

[0164] FIG17 is an equivalent circuit diagram 1 of a shift register provided in an exemplary embodiment;

[0165] FIG18 is a second equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0166] FIG19 is a third equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0167] FIG20 is a fourth equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0168] FIG21 is a fifth equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0169] FIG22 is a sixth equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0170] FIG23 is an operation timing diagram of the shift register provided in FIG17 and FIG20;

[0171] FIG24 is an operation timing diagram of the shift register provided in FIG18 and FIG21;

[0172] FIG25 is an operation timing diagram of the shift register provided in FIG19 and FIG22;

[0173] FIG26 is a schematic structural diagram of another shift register provided by an embodiment of the present disclosure;

[0174] FIG27 is an equivalent circuit diagram of a shift register provided by another exemplary embodiment;

[0175] FIG28 is an operation timing diagram of the shift register provided in FIG27 ;

[0176] FIG29 is a cascade diagram of a gate drive circuit;

[0177] FIG30 is a second cascade diagram of a gate drive circuit.

[0178] Details

[0179] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0180] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0181] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0182] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of components with reference to the accompanying drawings. This is merely to facilitate the description of this specification and simplify the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of the components may be appropriately changed depending on the direction in which each component is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced as appropriate.

[0183] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0184] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0185] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0186] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0187] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0188] GOA technology is widely used in flat panel displays due to its advantages such as reducing the frame and simplifying the binding process. As the market's requirements for display reliability are getting higher and higher. The GOA circuit includes multiple shift registers. Some transistors in the shift register will be in a negative bias state during the operation of the shift register, that is, the voltage value of the signal at the gate electrode of the transistor is less than the voltage value of the signal at the first or second pole of the transistor. In a high temperature and high humidity environment, the characteristics of the transistors under negative bias in the shift register will deteriorate, causing the turn-on voltage of the transistors in the negative bias state to become smaller, which increases the leakage current in the shift register, and the shift register cannot output normally, thereby reducing the display effect of the display product.

[0189] Figure 1 is a schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure. As shown in Figure 1, the shift register provided by an embodiment of the present disclosure may include: an input sub-circuit, an output sub-circuit, and a first control sub-circuit.

[0190] As shown in Figure 1, the input sub-circuit is electrically connected to the signal input terminal IN and the pull-up node PU, respectively, and is configured to provide a signal to the pull-up node PU under the control of the signal from the signal input terminal IN. The output sub-circuit is electrically connected to the first output terminal OUT1, the pull-up node PU, and the clock signal terminal CLK, respectively, and is configured to provide the clock signal terminal CLK signal to the first output terminal OUT1 under the control of the signal from the pull-up node PU. The first control sub-circuit is electrically connected to the control signal terminal CON and the signal input terminal IN, respectively, and is configured to provide the control signal terminal CON signal to the signal input terminal IN under the control of the signal from the control signal terminal CON.

[0191] In an exemplary embodiment, the operation process of the shift register includes a display phase and a non-display phase. The display phase includes an output phase and a non-output phase. The non-output phase may include an input phase, and the input phase occurs before the output phase.

[0192] In an exemplary embodiment, the non-display phase may include a power-on phase, a power-off phase, and a blank phase between the display phases.

[0193] In the input phase, the signal at the signal input terminal IN is an effective level signal, wherein the effective level signal at the signal terminal refers to a signal that turns on the transistor connected to the signal terminal.

[0194] In an exemplary embodiment, the signal of the first output terminal OUT1 is a single pulse signal. The first output terminal OUT1 can output the current stage driving signal, or can output the current stage driving signal and the cascade signal.

[0195] In an exemplary embodiment, the signal at the clock signal terminal CLK is a clock signal with an adjustable pulse width during the display phase, and is a DC signal during the non-display phase.

[0196] In an exemplary embodiment, the signal at the control signal terminal CON may be a single pulse signal in the display phase or the non-display phase.

[0197] In an exemplary embodiment, the first control sub-circuit can control the signal of the signal input terminal IN so that the voltage value of the signal at the signal input terminal IN is greater than the voltage value of the signal of the pull-up node PU in a non-output stage or a partial time period of the non-display stage, or, in the output stage, the voltage value of the signal at the signal input terminal IN is less than the voltage value of the signal of the pull-up node PU, thereby improving the characteristics of some transistors in the output sub-circuit, reducing the leakage current of the shift register, ensuring the normal output of the shift register, improving the reliability of the shift register, and enhancing the display effect of the display product.

[0198] In an exemplary embodiment, FIG2 is a first schematic diagram of the structure of a shift register provided in an exemplary embodiment. As shown in FIG2 , the shift register may further include a first reset subcircuit. The first reset subcircuit is electrically connected to the master reset signal terminal TRST, the pull-up node PU, and the first power supply terminal V1, respectively, and is configured to provide a signal from the first power supply terminal V1 to the pull-up node PU under the control of the master reset signal terminal TRST.

[0199] In an exemplary embodiment, the total reset signal terminal TRST is a valid level signal during a portion of the non-display phase and an invalid level signal during the display phase, wherein the invalid level signal of the signal terminal is a signal that turns off the transistor connected to the signal terminal.

[0200] In an exemplary embodiment, the first power terminal V1 continuously provides a low-level signal in the display stage and the non-display stage.

[0201] In an exemplary embodiment, FIG3 is a first connection diagram of a first control subcircuit provided in an exemplary embodiment, FIG4 is a second connection diagram of a first control subcircuit provided in an exemplary embodiment, and FIG5 is a third connection diagram of a first control subcircuit provided in an exemplary embodiment. As shown in FIG3 to FIG5 , the control signal terminal CON includes at least one of a first control signal terminal CON1 and a second control signal terminal CON2. FIG3 illustrates an example in which the control signal terminal CON includes the first control signal terminal CON1, FIG4 illustrates an example in which the control signal terminal CON includes the second control signal terminal CON2, and FIG5 illustrates an example in which the control signal terminal CON includes the first control signal terminal CON1 and the second control signal terminal CON2.

[0202] In an exemplary embodiment, as shown in Figures 3 and 5, the first control signal terminal CON1 is electrically connected to the total reset signal terminal TRST, that is, the first control signal terminal CON1 can be the same signal terminal as the total reset signal terminal TRST. Exemplarily, the first control signal terminal CON1 and the total reset signal terminal TRST can be connected to the same signal line, or can be connected to different signal lines with the same signal.

[0203] In an exemplary embodiment, the signal at the first control signal terminal CON1 is a valid level signal during a partial period of the non-display phase.

[0204] In an exemplary embodiment, as shown in Figures 4 and 5, the second control signal terminal CON2 is electrically connected to the first output terminal OUT1, that is, the second control signal terminal CON2 and the first output terminal OUT1 are the same signal terminal. Exemplarily, the second control signal terminal CON2 and the first output terminal OUT1 can be connected to the same signal line, or can be connected to different signal lines with the same signal.

[0205] In an exemplary embodiment, the signal of the second control signal terminal CON2 is a valid level signal in the output stage.

[0206] In an exemplary embodiment, FIG6 is an equivalent circuit diagram 1 of a first control subcircuit provided in an exemplary embodiment. As shown in FIG6 , when the control signal terminal CON includes the first control signal terminal CON1, the first control subcircuit may include a nineteenth transistor T19. The control electrode and first electrode of the nineteenth transistor T19 are respectively electrically connected to the first control signal terminal CON1, and the second electrode of the nineteenth transistor T19 is electrically connected to the signal input terminal IN.

[0207] In an exemplary embodiment, FIG7 is a second equivalent circuit diagram of a first control subcircuit provided in an exemplary embodiment. As shown in FIG7 , when the control signal terminal CON includes the second control signal terminal CON2, the first control subcircuit includes a twentieth transistor T20. The control electrode and first electrode of the twentieth transistor T20 are electrically connected to the second control signal terminal CON2, respectively, and the second electrode of the twentieth transistor T20 is electrically connected to the signal input terminal IN.

[0208] In an exemplary embodiment, FIG8 is a third equivalent circuit diagram of a first control subcircuit provided in an exemplary embodiment. As shown in FIG8 , when the control signal terminal CON includes a first control signal terminal CON1 and a second control signal terminal CON2, the control subcircuit may include: a nineteenth transistor T19; a twentieth transistor T20. The control electrode and first electrode of the nineteenth transistor T19 are electrically connected to the first control signal terminal CON1, respectively; and the second electrode of the nineteenth transistor T19 is electrically connected to the signal input terminal IN. The control electrode and first electrode of the twentieth transistor T20 are electrically connected to the second control signal terminal CON2, respectively; and the second electrode of the twentieth transistor T20 is electrically connected to the signal input terminal IN.

[0209] 6 to 8 show exemplary structures of the first control sub-circuit. The implementation of the detection node control sub-circuit is not limited thereto, as long as it can achieve its functions.

[0210] In an exemplary embodiment, FIG9 is an equivalent circuit diagram of an input subcircuit provided in an exemplary embodiment. As shown in FIG9 , the input subcircuit may include a first transistor T1. A control electrode of the first transistor T1 is electrically connected to the signal input terminal IN, a first electrode of the first transistor T1 is electrically connected to the signal input terminal IN or the second power supply terminal V2, and a second electrode of the first transistor T1 is electrically connected to the pull-up node PU.

[0211] In an exemplary embodiment, Figure 10 is a second equivalent circuit diagram of an input subcircuit provided in an exemplary embodiment. As shown in Figure 10 , the input subcircuit may include: a first transistor T1 and a twenty-first transistor T21. The control electrode of the first transistor T1 is electrically connected to the signal input terminal IN, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN or the second power supply terminal V2, and the second electrode of the first transistor T1 is electrically connected to the control node N; the control electrode and first electrode of the twenty-first transistor T21 are respectively electrically connected to the control node N, and the second electrode of the twenty-first transistor T21 is electrically connected to the pull-up node PU.

[0212] In an exemplary embodiment, the second power terminal V2 continuously provides a high level signal.

[0213] In the exemplary embodiment, the twenty-first transistor corresponds to a unidirectionally conducting diode.

[0214] In an exemplary embodiment, since the voltage value of the signal at the pull-up node PU is greater than the voltage value of the signal input terminal IN during the output stage, the first transistor T1 is in a negative bias state during the output stage. Since the voltage value of the signal at the signal input terminal IN is greater than the voltage value of the signal at the pull-up node PU during a portion of the non-output stage and the non-display stage, the first transistor T1 is in a forward bias state during a portion of the non-output stage and the non-display stage, thereby improving the characteristics of the first transistor.

[0215] Figures 9 and 10 show exemplary structures of the input sub-circuit. The implementation of the input sub-circuit is not limited thereto, as long as its functions can be achieved.

[0216] In an exemplary embodiment, Figure 11 is an equivalent circuit diagram of an output sub-circuit provided in an exemplary embodiment. As shown in Figure 11, when the output sub-circuit is electrically connected to the first output terminal OUT1, the output sub-circuit may include: a second transistor T2 and a capacitor C. The control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the first output terminal OUT1. The first end of the capacitor C is electrically connected to the pull-up node PU, and the second end of the capacitor C is electrically connected to the first output terminal OUT1.

[0217] As shown in Figures 1 to 10, the output sub-circuit can also be electrically connected to the second output terminal OUT2 and is configured to provide the signal of the clock signal terminal CLK to the second output terminal OUT2 under the control of the signal of the pull-up node PU. When the output sub-circuit is electrically connected to the first output terminal OUT1 and the second output terminal OUT2, the first output terminal OUT1 outputs the drive signal, and the second output terminal OUT2 outputs the cascade signal.

[0218] In an exemplary embodiment, the signal at the second output terminal OUT2 is the same as the signal at the first output terminal OUT1 .

[0219] In an exemplary embodiment, FIG12 is a second equivalent circuit diagram of an output subcircuit provided in an exemplary embodiment. As shown in FIG12 , when the output subcircuit is electrically connected to the first output terminal OUT1 and the second output terminal OUT2, the output subcircuit may include: a second transistor T2, a third transistor T3, and a capacitor C. The control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the first output terminal OUT1; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the second output terminal OUT2; the first end of the capacitor C is electrically connected to the pull-up node PU, and the second end of the capacitor C is electrically connected to the first output terminal OUT1.

[0220] In an exemplary embodiment, the capacitor C can ensure the stability of the signal at the pull-up node PU and the stability of the signal at the first output terminal OUT1 , thereby improving the reliability of the shift register.

[0221] 11 and 12 show exemplary structures of the output sub-circuit. The implementation of the output sub-circuit is not limited thereto, as long as its functions can be achieved.

[0222] In an exemplary embodiment, Figure 13 is an equivalent circuit diagram of a first reset sub-circuit provided in an exemplary embodiment. As shown in Figure 13 , the first reset sub-circuit may include a fourth transistor T4. The control electrode of the fourth transistor T4 is electrically connected to the master reset signal terminal TRST, the first electrode of the fourth transistor T4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1.

[0223] 13 shows an exemplary structure of the first reset sub-circuit. The implementation of the first reset sub-circuit is not limited thereto, as long as its function can be achieved.

[0224] In an exemplary embodiment, FIG14 is a second schematic diagram of the structure of a shift register provided in an exemplary embodiment. As shown in FIG14 , the shift register may further include a second reset subcircuit. The second reset subcircuit is electrically connected to the first reset signal terminal RST1, the second reset signal terminal RST2, the pull-up node PU, the first output terminal OUT1, the first power supply terminal V1, and the third power supply terminal V3, respectively. The second reset subcircuit is configured to provide a signal from the first power supply terminal V1 to the pull-up node PU and a signal from the third power supply terminal V3 to the first output terminal OUT1, under the control of the signals from the first reset signal terminal RST1 and the second reset signal terminal RST2.

[0225] In an exemplary embodiment, the first reset signal terminal RST1 and the second reset signal terminal RST2 are inactive level signals in the non-display phase and the output phase, and are active level signals in a partial period of the non-output phase.

[0226] In an exemplary embodiment, the non-output phase further includes a reset phase, which occurs after the output phase. The first reset signal terminal RST1 and the second reset signal terminal RST2 are active level signals in the reset phase and inactive level signals in the remaining phases except the reset phase.

[0227] In an exemplary embodiment, the third power terminal V3 continuously provides a low-level signal.

[0228] In an exemplary embodiment, the absolute value of the voltage of the signal at the first power terminal V1 is greater than the absolute value of the voltage of the signal at the third power terminal V3 .

[0229] In an exemplary embodiment, Figure 15 is an equivalent circuit diagram of a second reset sub-circuit provided in an exemplary embodiment. As shown in Figure 15, the second reset sub-circuit may include a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the first reset signal terminal RST1, the first electrode of the fifth transistor T5 is electrically connected to the pull-up node PU, and the second electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1. The control electrode of the sixth transistor T6 is electrically connected to the second reset signal terminal RST2, the first electrode of the sixth transistor T6 is electrically connected to the first output terminal OUT1, and the second electrode of the sixth transistor T6 is electrically connected to the third power supply terminal V3.

[0230] 15 shows an exemplary structure of the second reset sub-circuit. The implementation of the second reset sub-circuit is not limited thereto, as long as its function can be achieved.

[0231] In an exemplary embodiment, as shown in FIG14 , the shift register may further include a noise reduction sub-circuit, which may include at least one of a first noise reduction sub-circuit and a second noise reduction sub-circuit. The first noise reduction sub-circuit is electrically connected to the fourth power terminal V4, the signal input terminal IN, the pull-up node PU, the first output terminal OUT1, the second output terminal OUT2, the first power terminal V1, and the third power terminal V3, respectively. The first noise reduction sub-circuit is configured to provide a signal from the first power terminal V1 to the pull-up node PU and the second output terminal OUT2, and a signal from the third power terminal V3 to the pull-down node, under control of signals from the signal input terminal IN, the pull-up node PU, and the fourth power terminal V4. The second noise reduction sub-circuit is electrically connected to the fifth power terminal V5, the signal input terminal IN, the pull-up node PU, the first output terminal OUT1, the second output terminal OUT2, the first power terminal V1, and the third power terminal V3, respectively. The first noise reduction sub-circuit is configured to provide a signal from the first power terminal V1 to the pull-up node PU and the second output terminal OUT2, and a signal from the third power terminal V3 to the pull-down node, under control of signals from the signal input terminal IN, the pull-up node PU, and the fifth power terminal V5. FIG14 illustrates an example in which the noise reduction sub-circuit includes a first noise reduction sub-circuit and a second noise reduction sub-circuit.

[0232] In an exemplary embodiment, the signal of the third power supply terminal V3 is a low level signal in the display stage and the non-display stage. The absolute value of the voltage of the signal of the first power supply terminal V1 is greater than the absolute value of the voltage of the signal of the third power supply terminal V3.

[0233] In an exemplary embodiment, when the noise reduction sub-circuit includes the first noise reduction sub-circuit, the fourth power supply terminal V4 continuously provides a high-level signal. When the noise reduction sub-circuit includes the second noise reduction sub-circuit, the fifth power supply terminal V5 continuously provides a high-level signal.

[0234] In an exemplary embodiment, when the noise reduction sub-circuit includes: a first noise reduction sub-circuit and a second noise reduction sub-circuit, the fourth power supply terminal V4 and the fifth power supply terminal V5 are mutually inverted signals, and the fourth power supply terminal V4 and the fifth power supply terminal V5 are not high-level signals at the same time. Exemplarily, when the fourth power supply terminal V4 is a high-level signal, the fifth power supply terminal V5 is a low-level signal, or, when the fourth power supply terminal V4 is a low-level signal, the fifth power supply terminal V5 is a high-level signal.

[0235] In an exemplary embodiment, a display frame may include a first display frame and a second display frame, and the first display frame and the second display frame may be alternately arranged. In the first display frame, the signal of the fourth power supply terminal V4 is a high-level signal, and the signal of the fifth power supply terminal V5 is a low-level signal. In the second display frame, the signal of the fourth power supply terminal V4 is a low-level signal, and the signal of the fifth power supply terminal V5 is a high-level signal.

[0236] In an exemplary embodiment, the first noise reduction sub-circuit and the second noise reduction sub-circuit do not perform noise reduction at the same time, which can increase the lifespan of transistors in the first noise reduction sub-circuit and the second noise reduction sub-circuit and improve the reliability of the shift register.

[0237] In an exemplary embodiment, Figure 16 is an equivalent circuit diagram of a noise reduction sub-circuit provided in an exemplary embodiment. Figure 16 illustrates an example of a noise reduction sub-circuit comprising a first noise reduction sub-circuit and a second noise reduction sub-circuit. As shown in Figure 16, the first noise reduction sub-circuit comprises a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15. The second noise reduction sub-circuit comprises a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18.Among them, the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the first pull-down node PD1, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor T8 is electrically connected to the first pull-down node PD1, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the ninth transistor T9 are respectively electrically connected to the fourth power supply terminal V4, and the second electrode of the ninth transistor T9 is electrically connected to the first pull-down node PD1; the control electrode of the tenth transistor T10 is electrically connected to the signal input terminal IN The first electrode of the tenth transistor T10 is electrically connected to the second pull-down node PD2, and the second electrode of the tenth transistor T10 is electrically connected to the first power supply terminal V1; the control electrode of the eleventh transistor T11 is electrically connected to the pull-up node PU, the first electrode of the eleventh transistor T11 is electrically connected to the second pull-down node PD2, and the second electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the twelfth transistor T12 are electrically connected to the fifth power supply terminal V5 respectively, and the second electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2; the control electrode of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1, and the thirteenth transistor T13 is electrically connected to the first pull-down node PD1. A first electrode of the transistor T13 is electrically connected to the pull-up node PU, a second electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1; a control electrode of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1, a first electrode of the fourteenth transistor T14 is electrically connected to the first output terminal OUT1, and a second electrode of the fourteenth transistor T14 is electrically connected to the third power supply terminal V3; a control electrode of the fifteenth transistor T15 is electrically connected to the first pull-down node PD1, a first electrode of the fifteenth transistor T15 is electrically connected to the second output terminal OUT2, and a second electrode of the fifteenth transistor T15 is electrically connected to the first power supply terminal V1; a control electrode of the sixteenth transistor T16 is electrically connected to the first pull-down node PD1, a first electrode of the fifteenth transistor T16 is electrically connected to the second output terminal OUT2, and a second electrode of the fifteenth transistor T16 is electrically connected to the first power supply terminal V1; The first electrode of the sixteenth transistor T16 is electrically connected to the pull-up node PU, and the second electrode of the sixteenth transistor T16 is electrically connected to the first power supply terminal V1; the control electrode of the seventeenth transistor T17 is electrically connected to the second pull-down node PD2, the first electrode of the seventeenth transistor T17 is electrically connected to the first output terminal OUT1, and the second electrode of the seventeenth transistor T17 is electrically connected to the third power supply terminal V3; the control electrode of the eighteenth transistor T18 is electrically connected to the second pull-down node PD2, the first electrode of the eighteenth transistor T18 is electrically connected to the second output terminal OUT2, and the second electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1.

[0238] Figure 17 is an equivalent circuit diagram 1 of a shift register provided in an exemplary embodiment, Figure 18 is an equivalent circuit diagram 2 of a shift register provided in an exemplary embodiment, and Figure 19 is an equivalent circuit diagram 3 of a shift register provided in an exemplary embodiment. As shown in Figures 17 to 19, the input subcircuit in the shift register includes a first transistor T1, an output subcircuit includes a second transistor T2, a third transistor T3, and a capacitor C, a first control subcircuit includes at least one of a nineteenth transistor T19 and a twentieth transistor T20, a first reset subcircuit includes a fourth transistor T4, a second reset subcircuit includes a fifth transistor T5 and a sixth transistor T6, and a noise reduction subcircuit includes seventh transistors T7 to eighteenth transistors T18. Figures 17 to 19 illustrate the example of a noise reduction subcircuit including a first noise reduction subcircuit and a second noise reduction subcircuit. FIG17 illustrates the case where the first control sub-circuit includes the nineteenth transistor T19, FIG18 illustrates the case where the first control sub-circuit includes the twentieth transistor T20, and FIG19 illustrates the case where the first control sub-circuit includes the nineteenth transistor T19 and the twentieth transistor T20.

[0239] As shown in Figures 17 to 19, the control electrode of the first transistor T1 is electrically connected to the signal input terminal IN, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN or the second power supply terminal V2, and the second electrode of the first transistor T1 is electrically connected to the pull-up node PU; the control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the first output terminal OUT1; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the third transistor T3 is electrically connected to the pull-up node PU. The second electrode of T3 is electrically connected to the second output terminal OUT2; the first end of the capacitor C is electrically connected to the pull-up node PU, and the second end of the capacitor C is electrically connected to the first output terminal OUT1; the control electrode of the fourth transistor T4 is electrically connected to the total reset signal terminal TRST, the first electrode of the fourth transistor T4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1; the control electrode of the fifth transistor T5 is electrically connected to the first reset signal terminal RST1, the first electrode of the fifth transistor T5 is electrically connected to the pull-up node PU, and the second electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1; the sixth transistor T6 The control electrode of the sixth transistor T6 is electrically connected to the second reset signal terminal RST2, the first electrode of the sixth transistor T6 is electrically connected to the first output terminal OUT1, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the first pull-down node PD1, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor T8 is electrically connected to the first pull-down node PD1, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1; The control electrode and first electrode of the transistor T9 are respectively electrically connected to the fourth power supply terminal V4, and the second electrode of the ninth transistor T9 is electrically connected to the first pull-down node PD1; the control electrode of the tenth transistor T10 is electrically connected to the signal input terminal IN, the first electrode of the tenth transistor T10 is electrically connected to the second pull-down node PD2, and the second electrode of the tenth transistor T10 is electrically connected to the first power supply terminal V1; the control electrode of the eleventh transistor T11 is electrically connected to the pull-up node PU, the first electrode of the eleventh transistor T11 is electrically connected to the second pull-down node PD2, and the second electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal V1; the control electrode and first electrode of the twelfth transistor T12 are respectively electrically connected to the fifth power supply terminal V5, and the second electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2; the control electrode of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1, the first electrode of the thirteenth transistor T13 is electrically connected to the pull-up node PU, and the second electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1;The control electrode of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1, the first electrode of the fourteenth transistor T14 is electrically connected to the first output terminal OUT1, and the second electrode of the fourteenth transistor T14 is electrically connected to the third power supply terminal V3; the control electrode of the fifteenth transistor T15 is electrically connected to the first pull-down node PD1, the first electrode of the fifteenth transistor T15 is electrically connected to the second output terminal OUT2, and the second electrode of the fifteenth transistor T15 is electrically connected to the first power supply terminal V1; the control electrode of the sixteenth transistor T16 is electrically connected to the second pull-down node PD2, the first electrode of the sixteenth transistor T16 is electrically connected to the pull-up node PU, and the second electrode of the sixteenth transistor T16 is electrically connected to the first power supply terminal V1; the control electrode of the seventeenth transistor T17 is electrically connected to the second pull-down node PD 2, a first electrode of a seventeenth transistor T17 is electrically connected to the first output terminal OUT1, and a second electrode of the seventeenth transistor T17 is electrically connected to the third power supply terminal V3; a control electrode of an eighteenth transistor T18 is electrically connected to the second pull-down node PD2, a first electrode of the eighteenth transistor T18 is electrically connected to the second output terminal OUT2, and a second electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1; a control electrode and a first electrode of a nineteenth transistor T19 are respectively electrically connected to the first control signal terminal CON1, and a second electrode of the nineteenth transistor T19 is electrically connected to the signal input terminal IN; a control electrode and a first electrode of a twentieth transistor T20 are respectively electrically connected to the second control signal terminal CON2, and a second electrode of the twentieth transistor T20 is electrically connected to the signal input terminal IN.

[0240] Figure 20 is a fourth equivalent circuit diagram of a shift register provided in an exemplary embodiment, Figure 21 is a fifth equivalent circuit diagram of a shift register provided in an exemplary embodiment, and Figure 22 is a sixth equivalent circuit diagram of a shift register provided in an exemplary embodiment. As shown in Figures 20 to 22, the shift register further includes: a first reset sub-circuit, a second reset sub-circuit, and a noise reduction sub-circuit; the input sub-circuit includes: a first transistor T1 and a twenty-first transistor T21; the output sub-circuit includes: a second transistor T2, a third transistor T3, and a capacitor C; the first control sub-circuit includes: at least one of: a nineteenth transistor T19 and a twenty-first transistor T20; the first reset sub-circuit includes: a fourth transistor T4; the second reset sub-circuit includes: a fifth transistor T5 and a sixth transistor T6; and the noise reduction sub-circuit includes: seventh transistor T7 to eighteenth transistor T18. Figures 20 to 22 illustrate the example of a noise reduction sub-circuit including: a first noise reduction sub-circuit and a second noise reduction sub-circuit. FIG20 illustrates the case where the first control sub-circuit includes the nineteenth transistor T19, FIG21 illustrates the case where the first control sub-circuit includes the twentieth transistor T20, and FIG22 illustrates the case where the first control sub-circuit includes the nineteenth transistor T19 and the twentieth transistor T20.

[0241] As shown in Figures 20 to 22, the control electrode of the first transistor T1 is electrically connected to the signal input terminal IN, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN or the second power supply terminal V2, and the second electrode of the first transistor T1 is electrically connected to the control node; the control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the first output terminal OUT1; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the second output terminal OUT2; the first end of the capacitor C is electrically connected to the pull-up node P U is electrically connected, the second end of the capacitor C is electrically connected to the first output terminal OUT1; the control electrode of the fourth transistor T4 is electrically connected to the total reset signal terminal TRST, the first electrode of the fourth transistor T4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1; the control electrode of the fifth transistor T5 is electrically connected to the first reset signal terminal RST1, the first electrode of the fifth transistor T5 is electrically connected to the pull-up node PU, and the second electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1; the control electrode of the sixth transistor T6 is electrically connected to the second reset signal terminal RST2, the first electrode of the sixth transistor T6 is electrically connected to the first output terminal OUT1, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1 The control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the first pull-down node PD1, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor T8 is electrically connected to the first pull-down node PD1, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the ninth transistor T9 are electrically connected to the fourth power supply terminal V4 respectively, and the second electrode of the ninth transistor T9 is electrically connected to the first pull-down node PD1; the control electrode of the tenth transistor T10 is electrically connected to the signal input terminal IN, and the first electrode of the tenth transistor T10 is electrically connected to the second pull-down node PD2 is electrically connected, a second electrode of the tenth transistor T10 is electrically connected to the first power supply terminal V1; a control electrode of the eleventh transistor T11 is electrically connected to the pull-up node PU, a first electrode of the eleventh transistor T11 is electrically connected to the second pull-down node PD2, and a second electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal V1; a control electrode and a first electrode of the twelfth transistor T12 are respectively electrically connected to the fifth power supply terminal V5, and a second electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2; a control electrode of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1, a first electrode of the thirteenth transistor T13 is electrically connected to the pull-up node PU, and a second electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1;The control electrode of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1, the first electrode of the fourteenth transistor T14 is electrically connected to the first output terminal OUT1, and the second electrode of the fourteenth transistor T14 is electrically connected to the third power supply terminal V3; the control electrode of the fifteenth transistor T15 is electrically connected to the first pull-down node PD1, the first electrode of the fifteenth transistor T15 is electrically connected to the second output terminal OUT2, and the second electrode of the fifteenth transistor T15 is electrically connected to the first power supply terminal V1; the control electrode of the sixteenth transistor T16 is electrically connected to the second pull-down node PD2, the first electrode of the sixteenth transistor T16 is electrically connected to the pull-up node PU, and the second electrode of the sixteenth transistor T16 is electrically connected to the first power supply terminal V1; the control electrode of the seventeenth transistor T17 is electrically connected to the second pull-down node PD2, the first electrode of the seventeenth transistor T17 is electrically connected to the first output terminal OUT 1, the second electrode of the seventeenth transistor T17 is electrically connected to the third power supply terminal V3; the control electrode of the eighteenth transistor T18 is electrically connected to the second pull-down node PD2, the first electrode of the eighteenth transistor T18 is electrically connected to the second output terminal OUT2, and the second electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the nineteenth transistor T19 are respectively electrically connected to the first control signal terminal CON1, and the second electrode of the nineteenth transistor T19 is electrically connected to the signal input terminal IN; the control electrode and the first electrode of the twentieth transistor T20 are respectively electrically connected to the second control signal terminal CON2, and the second electrode of the twentieth transistor T20 is electrically connected to the signal input terminal IN; the control electrode and the first electrode of the twenty-first transistor T21 are respectively electrically connected to the control node, and the second electrode of the twenty-first transistor T21 is electrically connected to the pull-up node PU.

[0242] In an exemplary embodiment, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0243] In an exemplary embodiment, all transistors in the shift register are N-type transistors. For example, all transistors in the shift register may be metal oxide transistors. Because metal oxide transistors have higher mobility and lower leakage current, using all transistors in the shift register as metal oxide transistors can increase the refresh rate of display products, enabling high-frequency display, and can also enable low-frequency display, thereby reducing power consumption.

[0244] For any of the shift registers provided in Figures 17 to 22, during the display phase and the non-display phase, the signals at the first power supply terminal V1 and the third power supply terminal V3 are low-level signals. The signal at the clock signal terminal CLK is a clock signal during the display phase, and a low-level signal during the non-display phase. The fourth power supply terminal V4 and the fifth power supply terminal V5 are constant voltage signals during any display frame. In the first display frame, the fourth power supply terminal V4 is a high-level signal, the ninth transistor T9 is continuously turned on, the fifth power supply terminal V5 is a low-level signal, and the twelfth transistor T12 is continuously turned off. In the second display frame, the fourth power supply terminal V4 is a low-level signal, the ninth transistor T9 is continuously turned off, the fifth power supply terminal V5 is a high-level signal, and the twelfth transistor T12 is continuously turned on. The fourth power supply terminal V4 switches from a first-level signal to a second-level signal during a time period when the signal at the total reset signal terminal TRST is a valid-level signal. The fifth power supply terminal V5 switches from a second-level signal to a first-level signal during a time period when the signal at the total reset signal terminal TRST is a valid-level signal. Exemplarily, when the first-level signal is a high-level signal, the second-level signal is a low-level signal; and when the first-level signal is a low-level signal, the second-level signal is a high-level signal.

[0245] Figure 23 is an operation timing diagram of the shift register provided in Figures 17 and 20. Figure 23 is illustrated by taking an example where all transistors in the shift register unit are N-type transistors.

[0246] In an exemplary embodiment, as shown in FIG23 , when the signal at the total reset signal terminal TRST is a valid level signal, the signal at the second power supply terminal V2 is a low level signal, and when the signal at the total reset signal terminal TRST is an invalid level signal, the signal at the second power supply terminal V2 is a high level signal.

[0247] As shown in FIG17 and FIG23 , the operation process of the shift register provided in FIG17 in the display phase may include the following stages:

[0248] In the first phase P11, i.e., the input phase, the signal at the signal input terminal IN is a high-level signal, and the signals at the clock signal terminal CLK, the first reset signal terminal RST1, the second reset signal terminal RST2, the first control signal terminal CON1, and the total reset signal terminal TRST are low-level signals. The first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is disconnected, the signal of the signal input terminal IN is not pulled low, the signal of the signal input terminal IN is a high-level signal, the first transistor T1 is turned on, the high-level signal of the second power supply terminal V2 or the signal input terminal IN is written into the pull-up node PU, the pull-up node PU is pulled high, the seventh transistor T7 and the tenth transistor T10 are turned on, the low-level signal of the first power supply terminal V1 is written into the first pull-down node PD1 and the second pull-down node PD2, the signal of the pull-up node PU is a high-level signal, the second transistor T2 and the third transistor T3 are turned on, the low-level signal of the clock signal terminal CLK is written into the first output terminal OUT1 and the second output terminal OUT2, the eighth transistor T8 and the eleventh transistor T11 are turned on, and the low-level signal of the first power supply terminal V1 is continuously written into the first pull-down node PD1 and the second pull-down node PD2. The first pull-down node PD1 and the second pull-down node PD2 are continuously low-level signals, and the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are turned off. In this stage, the signal on the pull-up node PU is a high-level signal, and the signals on the first pull-down node PD1, the second pull-down node PD2, the first output terminal OUT1, and the second output terminal OUT2 are low-level signals.

[0249] In the first phase, when the shift register is in the first display frame, the ninth transistor T9 is turned on and the twelfth transistor T12 is turned off. Although the ninth transistor T9 is turned on, the high-level signal at the fourth power supply terminal V4 will pull the signal of the first pull-down node PD1 high. However, because the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11 are continuously turned on, the signal of the first pull-down node PD1 will still be pulled down to a low-level signal. Similarly, when the shift register is in the second display frame, the ninth transistor T9 is turned off and the twelfth transistor T12 is turned on. Although the high-level signal at the fifth power supply terminal V5 will pull the signal of the second pull-down node PD2 high, because the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11 are continuously turned on, the signal of the second pull-down node PD2 will still be pulled down to a low-level signal. Regardless of whether the shift register is in the first or second display frame, the first and second pull-down nodes PD1 and PD2 remain low-level signals in the first phase.

[0250] In the second phase P12, ie, the output phase, the clock signal terminal CLK is a high-level signal, and the signals of the first control signal terminal CON1, the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2 and the total reset signal terminal TRST are low-level signals. The signal at the first control signal terminal CON1 is low, the nineteenth transistor T19 is off, the signal at the signal input terminal IN is low, the first transistor T1, the seventh transistor T7, and the tenth transistor T10 are off, and under the bootstrap effect of the capacitor C, the pull-up node PU is pulled high. The second transistor T2 and the third transistor T3 are turned on, the high-level signal at the clock signal terminal CLK is written to the first output terminal OUT1 and the second output terminal OUT2, the eighth transistor T8 and the eleventh transistor T11 are turned on, the low-level signal at the first power supply terminal V1 is continuously written to the first pull-down node PD1 and the second pull-down node PD2, and the first pull-down node PD1 and the second pull-down node PD2 remain low. The thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are off. In this stage, the signals at the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 are high, and the signals at the first pull-down node PD1 and the second pull-down node PD2 are low.

[0251] In the second phase, when the shift register is in the first display frame, the ninth transistor T9 is turned on and the twelfth transistor T12 is turned off. Although the ninth transistor T9 is turned on, the high-level signal at the fourth power supply terminal V4 will pull the signal at the first pull-down node PD1 high. However, because the eighth transistor T8 and the eleventh transistor T11 are continuously turned on, the signal at the first pull-down node PD1 is still pulled down to a low-level signal. Similarly, when the shift register is in the second display frame, the ninth transistor T9 is turned off and the twelfth transistor T12 is turned on. Although the high-level signal at the fifth power supply terminal V5 will pull the signal at the second pull-down node PD2 high, because the eighth transistor T8 and the eleventh transistor T11 are continuously turned on, the signal at the second pull-down node PD2 is still pulled down to a low-level signal. Regardless of whether the shift register is in the first or second display frame, the first and second pull-down nodes PD1 and PD2 remain low-level signals in the second phase.

[0252] In the second stage, the voltage value of the signal at the signal input terminal IN is lower than the voltage value of the signal at the pull-up node PU, so that the first transistor T1 is in a negative bias state and the turn-on voltage of the first transistor T1 becomes smaller.

[0253] In the third phase P13, i.e., the reset phase, the first reset signal terminal RST1 and the second reset signal terminal RST2 are high level signals, and the signals of the signal input terminal IN, the first control signal terminal CON1, the total reset signal terminal TRST and the clock signal terminal CLK are low level signals. The signals at the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, the low-level signal at the first power supply terminal V1 is written into the signal of the pull-up node PU, and the signal of the pull-up node PU is pulled low. The low-level signal at the third power supply terminal V3 is written into the first output terminal OUT1, and the signal of the first output terminal OUT1 is pulled low. The signal at the first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is turned off, the signal at the signal input terminal IN is a low-level signal, the first transistor T1, the seventh transistor T7, and the tenth transistor T10 are turned off, the pull-up node PU is a low-level signal, the eighth transistor T8 and the eleventh transistor T11 are turned off, the first pull-down node PD1 and the second pull-down node PD2 are not pulled low by the low-level signal at the first power supply terminal V1. When the shift register is in the first display frame, the ninth transistor T9 is turned on, the high-level signal at the fourth power supply terminal V4 is written into the first pull-down node PD1, and the thirteenth transistor T13 and the fourteenth transistor T14 are turned off. The first and fifth transistors T14 and T15 are turned on, the low-level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low-level signal of the third power supply terminal V3 is written into the first output terminal OUT1, the twelfth transistor T12 is turned off, the second pull-down node PD2 maintains the low-level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high-level signal of the fifth power supply terminal V5 is written into the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low-level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low-level signal of the third power supply terminal V3 is written into the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low-level signal of the previous stage, the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0254] In the fourth phase P14, i.e., the first noise reduction phase, the signal at the clock signal terminal CLK is a high-level signal, and the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, the first control signal terminal CON1, and the total reset signal terminal TRST are low-level signals. The signal at the signal input terminal IN is a low-level signal, the first transistor T1, the seventh transistor T7, and the tenth transistor T10 are disconnected, the signal at the first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is disconnected, the signal at the second power supply terminal V2 or the signal input terminal IN cannot be written to the pull-up node PU, and the signal at the pull-up node PU remains the low-level signal of the previous phase. The second transistor T2, the third transistor T3, the eighth transistor T8, and the eleventh transistor T11 are disconnected, and the first pull-down node PD1 and the second pull-down node PD2 are not pulled down by the low-level signal at the first power supply terminal V1. When the shift register is in the first display frame, the ninth transistor T9 is turned on, the high-level signal at the fourth power supply terminal V4 is written to the first pull-down node PD1, and the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are disconnected. 15 is turned on, the low-level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low-level signal of the third power supply terminal V3 is written into the first output terminal OUT1, the twelfth transistor T12 is turned off, the second pull-down node PD2 maintains the low-level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high-level signal of the fifth power supply terminal V5 is written into the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low-level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low-level signal of the third power supply terminal V3 is written into the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low-level signal of the previous stage, and the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0255] In the fifth stage P15, ie, the second noise reduction stage, the clock signal terminal CLK, the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, the first control signal terminal CON1 and the total reset signal terminal TRST are low level signals. The signal of the signal input terminal IN is a low-level signal, the first transistor T1, the seventh transistor T7 and the tenth transistor T10 are disconnected, the signal of the first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is disconnected, the signal of the second power supply terminal V2 or the signal input terminal IN cannot be written to the pull-up node PU, the signal of the pull-up node PU maintains the low-level signal of the previous stage, the second transistor T2, the third transistor T3, the eighth transistor T8 and the eleventh transistor T11 are disconnected, the first pull-down node PD1 and the second pull-down node PD2 will not be pulled down by the low-level signal of the first power supply terminal V1, when the shift register is in the first display frame, the ninth transistor T9 is turned on, the high-level signal of the fourth power supply terminal V4 is written into the first pull-down node PD1, the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned on, and the low-level signal of the first power supply terminal V1 is written into the pull-up node PU and At the second output terminal OUT2, the low-level signal of the third power terminal V3 is written into the first output terminal OUT1, the twelfth transistor T12 is turned off, the second pull-down node PD2 maintains the low-level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high-level signal of the fifth power terminal V5 is written into the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low-level signal of the first power terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low-level signal of the third power terminal V3 is written into the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low-level signal of the previous stage, and the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0256] The working process of the shift register unit further includes: a plurality of fourth phases P14 and fifth phases P15, and the fourth phases P14 and the fifth phases P15 work alternately.

[0257] The fourth stage P14 and the fifth stage P15 can ensure that the signals of the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 of the shift register are continuously low-level signals, which can reduce the noise of the shift register and improve the reliability of the shift register.

[0258] As shown in FIG23 , the operation process of the shift register provided in FIG17 in the non-display phase may include the following phases:

[0259] In the sixth phase P16, the signals at the master reset signal terminal TRST and the first control signal terminal CON1 are high-level signals, the fourth transistor T4 and the nineteenth transistor T19 are turned on, the high-level signal at the first control signal terminal CON1 is written to the signal input terminal IN, and the signal at the signal input terminal IN is also high-level. A path is formed between the signal input terminal IN or the second power supply terminal V2 and the first power supply terminal V1, causing the voltage value of the signal at the pull-up node PU to be lower than the voltage value of the signal at the signal input terminal IN. Furthermore, because the master reset signal terminal TRST connected to all shift registers is high-level at the same time, the signals at the signal input terminal IN connected to all shift registers are also high-level signals. Due to the cascade relationship of the shift registers, the second output terminal OUT2 of the shift register at this level will be electrically connected to the signal input terminal IN of the shift register at other levels, and the first reset signal terminal RST1 and the second reset signal terminal RST2 of the shift register at this level will be electrically connected to the second output terminal OUT2 of the shift register at other levels. Therefore, the signals of the second output terminal OUT2, the first reset signal terminal RST1 and the second reset signal terminal RST2 of all shift registers are high-level signals in the sixth stage P16, the signals of the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, the signal of the first power supply terminal V1 is written to the pull-up node PU, and the signal of the third power supply terminal V3 is written to the first output terminal OUT1, which can avoid the shift register from outputting in the non-display stage, thereby ensuring the reliability of the shift register.

[0260] Since the voltage value of the signal at the signal input terminal IN in the sixth stage is greater than the voltage value of the signal at the pull-up node PU, the first transistor T1 is in a forward bias state, and the turn-on voltage of the first transistor T1 becomes larger, which can improve the transistor characteristic drift of the first transistor T1 caused by being in a negative bias state in the second stage, and can restore the transistor characteristics of the first transistor T1.

[0261] In an exemplary embodiment, since the second power supply terminal V2 is a low-level signal in the sixth stage P16 and the signal at the signal input terminal IN is a high-level signal, the voltage value of the signal at the pull-up node PU of the shift register provided with the first transistor T1 connected to the second power supply terminal V2 in the sixth stage P16 is lower than the voltage value of the signal at the pull-up node PU of the shift register provided with the first transistor T1 connected to the signal input terminal in the sixth stage P16, that is, the degree of improvement of the transistor characteristic drift caused by the first transistor T1 being in a negative bias state in the second stage by the shift register provided with the first transistor T1 connected to the second power supply terminal V2 is stronger than the degree of improvement of the transistor characteristic drift caused by the first transistor T1 being in a negative bias state in the second stage by the shift register provided with the first transistor T1 connected to the signal input terminal.

[0262] The shift register provided in FIG20 has a twenty-first transistor T21 compared to the shift register provided in FIG17 . As shown in FIG20 and FIG23 , the operation process of the shift register provided in FIG20 in the display phase may include the following phases:

[0263] Compared with the shift register provided in Figure 17 in the first stage P11, the working processes of the first transistor T1 to the nineteenth transistor T19 in the first stage P11 provided in Figure 20 are the same, except that the first transistor T1 is turned on, the high-level signal of the second power supply terminal V2 or the signal input terminal IN is written into the control node N, the twenty-first transistor T21 is turned on, the high-level signal of the control node N is written into the pull-up node PU, and the pull-up node PU is pulled high by the signal of the control node N.

[0264] Compared with the shift register provided in FIG17 in the second stage P12, the operation processes of the first transistor T1 to the nineteenth transistor T19 in the second stage P12 provided in FIG20 are the same, except that the signal of the control node N maintains the high-level signal of the previous stage, and the twenty-first transistor T21 is continuously turned on.

[0265] In the second stage, the voltage value of the signal at the signal input terminal IN is less than the voltage value of the signal at the control node N, causing the first transistor T1 to be in a negative bias state and the turn-on voltage of the first transistor T1 to be reduced. Compared with the shift register provided in FIG17 , the shift register provided in FIG20 has the following characteristics: due to the presence of the twenty-first transistor T21, the voltage value of the signal at the control node N in the second stage is less than the voltage value of the signal at the pull-up node PU. That is, the absolute value of the difference between the voltage value of the signal at the signal input terminal in the shift register provided in FIG20 and the voltage value of the signal at the control node N is less than the absolute value of the difference between the voltage value of the signal at the signal input terminal in the shift register provided in FIG17 and the voltage value of the signal at the pull-up node. That is, the negative bias degree of the first transistor in the shift register provided in FIG20 is less than the negative bias degree of the first transistor in the shift register provided in FIG17 . The shift register region provided in FIG20 can prevent the characteristic drift of the first transistor to a certain extent.

[0266] Compared with the shift register provided in Figure 17 in the third stage P13, the working processes of the first transistor T1 to the nineteenth transistor T19 in the third stage P13 provided in Figure 20 are the same, except that the control node N maintains the high-level signal of the previous stage, the twenty-first transistor T21 is turned on, and since the low-level signal of the pull-up node PU is also written into the control node N, the twenty-first transistor T21 is disconnected.

[0267] The control node N is pulled down to a low-level signal in the third stage, the twenty-first transistor T21 is disconnected, and the working process of the shift register provided in Figure 20 in the fourth stage P14 is the same as the working process of the shift register provided in Figure 17 in the fourth stage P14. The working process of the shift register provided in Figure 20 in the fifth stage P15 is the same as the working process of the shift register provided in Figure 17 in the fifth stage P15, which will not be repeated here.

[0268] The operation process of the shift register provided in FIG20 in the non-display phase may include the following stages:

[0269] In the sixth phase P16, when the first transistor T1 is electrically connected to the signal input terminal IN, the shift register provided in FIG20 operates in the same manner as the first transistor T1 to the nineteenth transistor T19 in the shift register provided in FIG17 , except that the first transistor T1 is turned on, a high-level signal from the signal input terminal IN is written to the control node N, the twenty-first transistor T21 is turned on, a path is formed between the signal input terminal IN and the first power supply terminal V1, such that the voltage of the signal at the control node N is less than the voltage of the signal at the signal input terminal IN. When the first transistor T1 is electrically connected to the second power supply terminal V2, the shift register provided in FIG20 operates in the same manner as the first transistor T1 to the nineteenth transistor T19 in the shift register provided in FIG17 , except that the first transistor T1 is turned on, a low-level signal from the second power supply terminal V2 is written to the control node N, the twenty-first transistor T21 is turned off, and the voltage of the signal at the control node N is less than the voltage of the signal at the signal input terminal IN.

[0270] Since the voltage value of the signal at the signal input terminal IN in the sixth stage is greater than the voltage value of the signal at the pull-up node PU, the first transistor T1 is in a forward bias state, and the turn-on voltage of the first transistor T1 becomes larger, which can improve the transistor characteristic drift of the first transistor T1 caused by being in a negative bias state in the second stage, and can restore the transistor characteristics of the first transistor T1.

[0271] When the shift register provided in Figure 17 is compared with the shift register provided in Figure 20, when the first transistor T1 of both is electrically connected to the signal input terminal IN, the resistance of the path between the signal input terminal IN and the first power supply terminal V1 in the sixth stage of the shift register provided in Figure 20 is greater than the resistance of the path between the signal input terminal IN and the first power supply terminal V1 in the sixth stage of the shift register provided in Figure 17. Therefore, the voltage value of the signal at the control node N of the shift register provided in Figure 20 is less than the voltage value of the signal at the pull-up node PU of the shift register provided in Figure 17, that is, the forward bias degree of the first transistor T1 in the shift register provided in Figure 20 is greater than the forward bias degree of the first transistor T1 in the shift register provided in Figure 17.

[0272] Figure 24 is an operating timing diagram of the shift register provided in Figures 18 and 21. Figure 24 is illustrated by taking an example where all transistors in the shift register unit are N-type transistors.

[0273] In an exemplary embodiment, the second power supply terminal V2 is a DC signal, and is a high-level signal.

[0274] As shown in FIG18 and FIG24 , the operation process of the shift register provided in FIG18 in the display phase may include the following phases:

[0275] During the first phase P21, i.e., the input phase, the signal at signal input terminal IN is a high-level signal, while the signals at clock signal terminal CLK, first reset signal terminal RST1, second reset signal terminal RST2, second control signal terminal CON2, and master reset signal terminal TRST are low-level signals. The second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is disconnected, and the signal at signal input terminal IN is not pulled low. The operation of the first through eighteenth transistors T1 through T18 is identical to the operation of the first through eighteenth transistors T1 through T18 in the first phase P11 of the shift register shown in FIG. 17 , and will not be further described herein.

[0276] In the second phase P22, i.e., the output phase, the second control signal terminal CON2 and the clock signal terminal CLK are high-level signals, and the signals at the first reset signal terminal RST1, the second reset signal terminal RST2, and the master reset signal terminal TRST are low-level signals. The signal at the second control signal terminal CON2 is high-level, the twentieth transistor T20 is turned on, the signal at the signal input terminal IN is pulled high, the first transistor T1 is turned on, and the high-level signal at the second power supply terminal V2 or the signal input terminal IN is continuously written to the pull-up node PU. The operation process of the second transistor T2 to the eighteenth transistor T18 is the same as the operation process of the second transistor T2 to the eighteenth transistor T18 in the second phase P12 of the shift register shown in FIG. 17 , and will not be further described here.

[0277] In the second phase, since the signal at the signal input terminal IN is a high-level signal, the first transistor T1 will not be in a negative bias state in the second phase P22 , and the characteristics of the first transistor T1 will not drift.

[0278] In the third phase P23, i.e., the reset phase, the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, and the signals at the signal input terminal IN, the second control signal terminal CON2, the master reset signal terminal TRST, and the clock signal terminal CLK are low-level signals. The signal at the second control signal terminal CON2 is low-level, and the twentieth transistor T20 is disconnected. The signal at the second control signal terminal CON2 is not written to the signal input terminal IN. Since the signal input terminal IN of the current-stage shift register is electrically connected to the second output terminal OUT2 of the previous-stage shift register, in this phase, the signal at the second output terminal OUT2 of the previous-stage shift register is low-level. Therefore, the signal at the signal input terminal IN of the current-stage shift register is pulled low and remains low-level. The operation of the first transistor T1 through the eighteenth transistor T18 is the same as the operation of the first transistor T1 through the eighteenth transistor T18 in the third phase P13 of the shift register shown in FIG. 17 .

[0279] In the third stage P23, since the second output terminal OUT2 of the shift register at this stage is electrically connected to the signal input terminal IN of the shift register at the next stage, and since the signal input terminal IN of the shift register at the next stage is a high-level signal at this stage, the second output terminal OUT2 of the shift register at this stage is a high-level signal at this stage.

[0280] In the fourth phase P24, i.e., the first noise reduction phase, the signals at the first reset signal terminal RST1, the second reset signal terminal RST2, and the clock signal terminal CLK are high-level signals, while the signal input terminal IN, the second control signal terminal CON2, and the total reset signal terminal TRST are low-level signals. The signal at the second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is disconnected, the signal at the second power supply terminal V2 or the signal input terminal IN cannot be written to the pull-up node PU, and the signal at the pull-up node PU remains the low-level signal of the previous phase. The signals at the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the operating processes of the first transistor T1 to the fourth transistor T4 and the seventh transistor T7 to the eighteenth transistor T18 are the same as the operating processes of the first transistor T1 to the fourth transistor T4 and the seventh transistor T7 to the eighteenth transistor T18 in the fourth phase P14 of the shift register provided in FIG. 17 , and are not further described herein.

[0281] In the fifth phase P25, i.e., the second noise reduction phase, the clock signal terminal CLK, the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, the second control signal terminal CON2, and the master reset signal terminal TRST are low-level signals. The signal at the second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is disconnected, and the signal at the second power supply terminal V2 or the signal input terminal IN cannot be written to the pull-up node PU. The signal at the pull-up node PU remains the low-level signal of the previous phase. The operation process of the first transistor T1 to the eighteenth transistor T18 is the same as the operation process of the first transistor T1 to the eighteenth transistor T18 in the fifth phase P25 of the shift register shown in FIG. 17 , and will not be further described here.

[0282] The working process of the shift register unit further includes: a plurality of fourth phases P14 and fifth phases P15, and the fourth phases P14 and the fifth phases P15 work alternately.

[0283] The fourth stage P14 and the fifth stage P15 can ensure that the signals of the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 of the shift register are continuously low-level signals, which can reduce the noise of the shift register and improve the reliability of the shift register.

[0284] The operation process of the shift register provided in FIG18 in the non-display phase may include the following stages:

[0285] In the sixth phase P26, the signal at the master reset signal terminal TRST is high, while the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, and the second control signal terminal CON2 are low. With the signal at the master reset signal terminal TRST high, the fourth transistor T4 is turned on, and the low-level signal at the first power supply terminal V1 is written to the pull-up node PU, pulling the signal at the pull-up node PU low.

[0286] The shift register provided in FIG21 has a twenty-first transistor T21 compared to the shift register provided in FIG18 . As shown in FIG21 and FIG24 , the operation process of the shift register provided in FIG21 in the display phase may include the following phases:

[0287] Compared with the shift register provided in FIG18 in the first stage P21, the working processes of the first transistor T1 to the eighteenth transistor T18 and the twentieth transistor T20 in the first stage P21 provided in FIG21 are the same, except that the first transistor T1 is turned on, the high-level signal of the second power supply terminal V2 or the signal input terminal IN is written into the control node N, the twenty-first transistor T21 is turned on, the high-level signal of the control node N is written into the pull-up node PU, and the pull-up node PU is pulled high by the signal of the control node N.

[0288] Compared with the shift register provided in FIG18 in the second stage P22, the operation processes of the first transistor T1 to the eighteenth transistor T18 and the twentieth transistor T20 in the second stage P22 provided in FIG21 are the same, except that the signal of the control node N maintains the high-level signal of the previous stage, and the twenty-first transistor T21 is continuously turned on.

[0289] Compared with the shift register provided in Figure 18, the shift register provided in Figure 21 has the presence of the twenty-first transistor T21, so that the voltage value of the signal of the control node N in the second stage is smaller than the voltage value of the signal of the pull-up node PU, that is, the absolute value of the difference between the voltage value of the signal at the signal input end of the shift register provided in Figure 21 and the voltage value of the signal at the control node N is smaller than the absolute value of the difference between the voltage value of the signal at the signal input end of the shift register provided in Figure 18 and the voltage value of the signal at the pull-up node, that is, the negative bias degree of the first transistor in the shift register provided in Figure 21 is smaller than the negative bias degree of the first transistor in the shift register provided in Figure 18. The shift register area provided in Figure 21 can prevent the characteristic drift of the first transistor to a certain extent.

[0290] The working process of the shift register provided in FIG. 21 in the third stage P23 is the same as that of the shift register provided in FIG. 18 in the third stage P23 , and will not be described again here.

[0291] The working process of the shift register provided in FIG. 21 in the fourth stage P24 is the same as the working process of the shift register provided in FIG. 18 in the fourth stage P24, and will not be repeated here.

[0292] The working process of the shift register provided in FIG21 in the fifth stage P25 is the same as the working process of the shift register provided in FIG18 in the fifth stage P25, and will not be repeated here.

[0293] The operation process of the sixth stage P26 of the shift register in the non-display stage provided in FIG21 is the same as the operation process of the sixth stage P26 of the shift register in the non-display stage provided in FIG18 , and will not be repeated here.

[0294] Figure 25 is an operation timing diagram of the shift register provided in Figures 19 and 22. Figure 25 is illustrated by taking an example where all transistors in the shift register unit are N-type transistors.

[0295] In an exemplary embodiment, as shown in FIG23 , when the signal at the total reset signal terminal TRST is a valid level signal, the signal at the second power supply terminal V2 is a low level signal, and when the signal at the total reset signal terminal TRST is an invalid level signal, the signal at the second power supply terminal V2 is a high level signal.

[0296] As shown in FIG19 and FIG25 , the operation process of the shift register provided in FIG19 in the display phase may include the following stages:

[0297] During the first phase P31, i.e., the input phase, the signal at signal input terminal IN is a high-level signal, while the signals at clock signal terminal CLK, first reset signal terminal RST1, second reset signal terminal RST2, first control signal terminal CON1, second control signal terminal CON2, and master reset signal terminal TRST are low-level signals. The first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is off, the second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is off, and the signal at signal input terminal IN is not pulled low. The operation of the first through eighteenth transistors T1 to T18 is identical to the operation of the first through eighteenth transistors T1 to T18 in the first phase P21 of the shift register shown in FIG. 18 , and will not be further described herein.

[0298] During the second phase P32, i.e., the output phase, the signals at the second control signal terminal CON2 and the clock signal terminal CLK are high-level signals, while the signals at the first control signal terminal CON1, the first reset signal terminal RST1, the second reset signal terminal RST2, and the master reset signal terminal TRST are low-level signals. The signal at the first control signal terminal CON1 is low-level, the nineteenth transistor T19 is off, the signal at the second control signal terminal CON2 is high-level, the twentieth transistor T20 is on, and the signal at the signal input terminal IN is pulled high. The operation of the first through eighteenth transistors T1 through T18 is identical to the operation of the first through eighteenth transistors T1 through T18 in the second phase P22 of the shift register shown in FIG. 18 , and will not be further described here.

[0299] In the second phase, since the signal at the signal input terminal IN is a high-level signal, the first transistor T1 will not be in a negative bias state in the second phase P22 , and the characteristics of the first transistor T1 will not drift.

[0300] In the third phase P33, i.e., the reset phase, the signals at the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, while the signals at the first control signal terminal CON1, the second control signal terminal CON2, the master reset signal terminal TRST, and the clock signal terminal CLK are low-level signals. The signal at the first control signal terminal CON1 is low-level, the nineteenth transistor T19 is off, the signal at the second control signal terminal CON2 is low-level, the twentieth transistor T20 is off, and the signal at the signal input terminal IN is pulled low by the signal at the second output terminal of the previous shift register. The operation of the first to eighteenth transistors T1 to T18 is the same as the operation of the first to eighteenth transistors T1 to T18 in the third phase P23 of the shift register shown in FIG. 18 , and will not be further described here.

[0301] In the fourth phase P34, i.e., the first noise reduction phase, the signals at the clock signal terminal CLK, the first reset signal terminal RST1, and the second reset signal terminal RST2 are high-level signals, and the signals at the signal input terminal IN, the first control signal terminal CON1, the second control signal terminal CON2, and the total reset signal terminal TRST are low-level signals. The signal at the first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is disconnected, the signal at the second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is disconnected, and the signal at the second power supply terminal V2 or the signal input terminal IN cannot be written to the pull-up node PU. The signal at the pull-up node PU maintains the low-level signal of the previous phase. The operation process of the first transistor T1 to the eighteenth transistor T18 is the same as the operation process of the first transistor T1 to the eighteenth transistor T18 in the fourth phase P24 of the shift register provided in FIG. 18 , and will not be repeated here.

[0302] In the fifth stage P35, i.e., the second noise reduction stage, the signals at the clock signal terminal CLK, the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, the first control signal terminal CON1, the second control signal terminal CON2, and the total reset signal terminal TRST are low-level signals. The signal at the first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is disconnected, the signal at the second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is disconnected, the signal at the second power supply terminal V2 or the signal input terminal IN cannot be written to the pull-up node PU, and the signal at the pull-up node PU remains the low-level signal of the previous stage. The operation process of the first transistor T1 to the eighteenth transistor T18 is the same as the operation process of the first transistor T1 to the eighteenth transistor T18 in the fifth stage P25 of the shift register provided in FIG. 18 , and will not be repeated here.

[0303] The working process of the shift register unit further includes: a plurality of fourth phases P14 and fifth phases P15, and the fourth phases P14 and the fifth phases P15 work alternately.

[0304] The fourth stage P14 and the fifth stage P15 can ensure that the signals of the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 of the shift register are continuously low-level signals, which can reduce the noise of the shift register and improve the reliability of the shift register.

[0305] The operation process of the shift register provided in FIG19 in the non-display phase may include the following stages:

[0306] In the sixth phase P36, the signals at the master reset signal terminal TRST and the first control signal terminal CON1 are high-level signals, while the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, and the second control signal terminal CON2 are low-level signals. The signal at the second control signal terminal CON2 is low-level, the twentieth transistor T20 is turned off, and the operation process of the first transistor T1 and the nineteenth transistor T19 is the same as the operation process of the shift register shown in FIG. 17 in the sixth phase P16, and will not be repeated here.

[0307] The shift register provided in FIG22 has a twenty-first transistor T21 compared to the shift register provided in FIG19 . As shown in FIG22 and FIG25 , the operation process of the shift register provided in FIG22 in the display phase may include the following phases:

[0308] Compared with the shift register provided in Figure 19 in the first stage P31, the working processes of the first transistor T1 to the twentieth transistor T20 in the first stage P31 provided in Figure 22 are the same, except that the first transistor T1 is turned on, the high-level signal of the second power supply terminal V2 or the signal input terminal IN is written into the control node N, the twenty-first transistor T21 is turned on, the high-level signal of the control node N is written into the pull-up node PU, and the pull-up node PU is pulled high by the signal of the control node N.

[0309] Compared with the shift register provided in FIG19 in the second stage P32, the working processes of the first transistor T1 to the twentieth transistor T20 in the second stage P32 provided in FIG22 are the same, except that the signal of the control node N maintains the high-level signal of the previous stage, and the twenty-first transistor T21 is continuously turned on.

[0310] Compared with the shift register provided in Figure 19, the shift register provided in Figure 22 has the presence of the twenty-first transistor T21, so that the voltage value of the signal of the control node N in the second stage is smaller than the voltage value of the signal of the pull-up node PU, that is, the absolute value of the difference between the voltage value of the signal at the signal input end in the shift register provided in Figure 22 and the voltage value of the signal at the control node N is smaller than the absolute value of the difference between the voltage value of the signal at the signal input end in the shift register provided in Figure 19 and the voltage value of the signal at the pull-up node, that is, the negative bias degree of the first transistor in the shift register provided in Figure 22 is smaller than the negative bias degree of the first transistor in the shift register provided in Figure 19, and the shift register area provided in Figure 22 can prevent the characteristic drift of the first transistor to a certain extent.

[0311] The working process of the shift register provided in FIG. 22 in the third stage P33 is the same as that of the shift register provided in FIG. 19 in the third stage P33 , and will not be described again here.

[0312] Compared with the shift register provided in Figure 19, the shift register provided in Figure 22 has the presence of the twenty-first transistor T21, so that the voltage value of the signal of the control node N in the second stage is smaller than the voltage value of the signal of the pull-up node PU, that is, the absolute value of the difference between the voltage value of the signal at the signal input end and the voltage value of the signal at the control node N in the shift register provided in Figure 22 is smaller than the absolute value of the difference between the voltage value of the signal at the signal input end and the voltage value of the signal at the pull-up node in the shift register provided in Figure 18, that is, the negative bias degree of the first transistor in the shift register provided in Figure 22 is smaller than the negative bias degree of the first transistor in the shift register provided in Figure 19, and the shift register area provided in Figure 22 can prevent the characteristic drift of the first transistor to a certain extent.

[0313] The working process of the shift register provided in FIG22 in the fourth stage P34 is the same as the working process of the shift register provided in FIG19 in the fourth stage P34, and will not be repeated here.

[0314] The working process of the shift register provided in FIG22 in the fifth stage P35 is the same as the working process of the shift register provided in FIG19 in the fifth stage P35, and will not be repeated here.

[0315] The operation process of the shift register provided in FIG22 in the non-display phase may include the following stages:

[0316] In the sixth stage P36, the signals of the total reset signal terminal TRST and the first control signal terminal CON1 are high-level signals, the signal of the second control signal terminal CON2 is a low-level signal, the signal of the second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is disconnected, and the working process of the first transistor T1 to the nineteenth transistor T19 is the same as the working process of the first transistor T1 to the nineteenth transistor T19 in the shift register provided in Figure 19, and will not be repeated here.

[0317] The present disclosure also provides a shift register. FIG26 is a schematic diagram of the structure of another shift register provided by the present disclosure. As shown in FIG26, the shift register provided by the present disclosure may include: an input subcircuit, an output subcircuit, and a second control subcircuit. The input subcircuit is electrically connected to the signal input terminal IN and the control node N, respectively, and is configured to provide a signal to the control node N under the control of the signal input terminal IN; the second control subcircuit is electrically connected to the control node N and the pull-up node PU, respectively, and is configured to provide a signal of the control node N to the pull-up node PU under the control of the signal of the control node N; the output subcircuit is electrically connected to the first output terminal OUT1, the pull-up node PU, and the clock signal terminal CLK, respectively, and is configured to provide a signal of the clock signal terminal CLK to the first output terminal OUT1 under the control of the signal of the pull-up node PU.

[0318] The setting of the second control subcircuit in the present disclosure can play a role in voltage division, so that the signal of the control node N can be smaller than the signal of the pull-up node PU in the output stage, thereby reducing the negative bias degree of some transistors in the input subcircuit and improving the reliability of the shift register.

[0319] Figure 27 is an equivalent circuit diagram of a shift register provided by another exemplary embodiment. As shown in Figure 27, the shift register may further include: a first reset sub-circuit, a second reset sub-circuit, and a noise reduction sub-circuit; the input sub-circuit includes: a first transistor T1; the output sub-circuit includes: a second transistor T2, a third transistor T3, and a capacitor; the second control sub-circuit includes: a twenty-first transistor T21; the first reset sub-circuit includes: a fourth transistor T4; the second reset sub-circuit includes: a fifth transistor T5 and a sixth transistor T6; and the noise reduction sub-circuit includes: seventh transistor T7 through eighteenth transistors T18. wherein, the control electrode of the first transistor T1 is electrically connected to the signal input terminal IN, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN or the second power supply terminal V2, and the second electrode of the first transistor T1 is electrically connected to the control node; the control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the first output terminal OUT1; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the second output terminal OUT2; the first end of the capacitor C is electrically connected to the pull-up node PU, and the second end of the capacitor C is electrically connected to the first output terminal OUT1; the control electrode of the fourth transistor T4 is electrically connected to the total reset signal terminal TRST, the first electrode of the fourth transistor T4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1; the control electrode of the fifth transistor T5 is electrically connected to the first reset signal terminal RST1, the first electrode of the fifth transistor T5 is electrically connected to the pull-up node a control electrode of the seventh transistor T7 electrically connected to the signal input terminal IN, a first electrode of the seventh transistor T7 electrically connected to the first pull-down node PD1, and a second electrode of the seventh transistor T7 electrically connected to the first power supply terminal V1; a control electrode of the eighth transistor T8 electrically connected to the pull-up node PU, a first electrode of the eighth transistor T8 electrically connected to the first pull-down node PD1, and a second electrode of the eighth transistor T8 electrically connected to the first power supply terminal V1; a control electrode and a first electrode of the ninth transistor T9 electrically connected to the fourth power supply terminal V4, respectively, and a second electrode of the ninth transistor T9 electrically connected to the first pull-down node PD1; a control electrode of the tenth transistor T10 electrically connected to the signal input terminal IN, a first electrode of the tenth transistor T10 electrically connected to the second pull-down node PD2, and a second electrode of the tenth transistor T10 electrically connected to the first power supply terminal V1;The control electrode of the eleventh transistor T11 is electrically connected to the pull-up node PU, the first electrode of the eleventh transistor T11 is electrically connected to the second pull-down node PD2, and the second electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the twelfth transistor T12 are electrically connected to the fifth power supply terminal V5, respectively, and the second electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2; the control electrode of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1, the first electrode of the thirteenth transistor T13 is electrically connected to the pull-up node PU, and the second electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1; the control electrode of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1, the first electrode of the fourteenth transistor T14 is electrically connected to the first output terminal OUT1, and the second electrode of the fourteenth transistor T14 is electrically connected to the third power supply terminal V3; the control electrode of the fifteenth transistor T15 is electrically connected to the first pull-down node PD1, and the first electrode of the fifteenth transistor T15 is electrically connected to the third power supply terminal V3. The control electrode of the 16th transistor T16 is electrically connected to the second pull-down node PD2, the first electrode of the 16th transistor T16 is electrically connected to the pull-up node PU, and the second electrode of the 16th transistor T16 is electrically connected to the first power supply terminal V1. The control electrode of the 17th transistor T17 is electrically connected to the second pull-down node PD2, the first electrode of the 17th transistor T17 is electrically connected to the first output terminal OUT1, and the second electrode of the 17th transistor T17 is electrically connected to the third power supply terminal V3. The control electrode of the 18th transistor T18 is electrically connected to the second pull-down node PD2, the first electrode of the 18th transistor T18 is electrically connected to the second output terminal OUT2, and the second electrode of the 18th transistor T18 is electrically connected to the first power supply terminal V1. The control electrode and the first electrode of the 21st transistor T21 are respectively electrically connected to the control node, and the second electrode of the 21st transistor T21 is electrically connected to the pull-up node PU.

[0320] In an exemplary embodiment, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0321] In an exemplary embodiment, all transistors in the shift register are N-type transistors. For example, all transistors in the shift register may be metal oxide transistors. Because metal oxide transistors have higher mobility and lower leakage current, using all transistors in the shift register as metal oxide transistors can increase the refresh rate of display products, enabling high-frequency display, and can also enable low-frequency display, thereby reducing power consumption.

[0322] Fig. 28 is an operation timing diagram of the shift register provided in Fig. 27. Fig. 28 is illustrated by taking an example where all transistors in the shift register unit are N-type transistors.

[0323] As shown in FIG27 and FIG28 , the operation process of the shift register provided in FIG27 in the display phase may include the following stages:

[0324] During the first phase P1, i.e., the input phase, the signal at the signal input terminal IN is a high-level signal, while the signals at the clock signal terminal CLK, the first reset signal terminal RST1, the second reset signal terminal RST2, and the master reset signal terminal TRST are low-level signals. The signal at the signal input terminal IN is a high-level signal, the first transistor T1 is turned on, and the high-level signal at the second power supply terminal V2 or the signal input terminal IN is written to the control node N. The twenty-first transistor T21 is turned on, and the high-level signal at the control node N is written to the pull-up node PU, which is pulled high. The seventh transistor T7 and the tenth transistor T10 are turned on, and the low-level signal at the first power supply terminal V1 is written to the first pull-down node PD1 and the second pull-down node PD2. The signal at the pull-up node PU is a high-level signal, the second transistor T2 and the third transistor T3 are turned on, and the low-level signal at the clock signal terminal CLK is written to the first output terminal OUT1 and the second output terminal OUT2. The eighth transistor T8 and the eleventh transistor T11 are turned on, and the low-level signal at the first power supply terminal V1 is continuously written to the first pull-down node PD1 and the second pull-down node PD2. The first pull-down node PD1 and the second pull-down node PD2 are continuously low-level signals, and the thirteenth transistor T13 to the eighteenth transistor T18 are turned off. In this stage, the signal on the pull-up node PU is high-level, and the signals on the first pull-down node PD1, the second pull-down node PD2, the first output terminal OUT1, and the second output terminal OUT2 are low-level signals.

[0325] In the first phase, when the shift register is in the first display frame, the ninth transistor T9 is turned on and the twelfth transistor T12 is turned off. Although the ninth transistor T9 is turned on, the high-level signal at the fourth power supply terminal V4 will pull the signal of the first pull-down node PD1 high. However, because the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11 are continuously turned on, the signal of the first pull-down node PD1 is still pulled down to a low-level signal. Similarly, when the shift register is in the second display frame, the ninth transistor T9 is turned off and the twelfth transistor T12 is turned on. Although the high-level signal at the fifth power supply terminal V5 will pull the signal of the second pull-down node PD2 high, because the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11 are continuously turned on, the signal of the second pull-down node PD2 is still pulled down to a low-level signal. Regardless of whether the shift register is in the first or second display frame, the first and second pull-down nodes PD1 and PD2 remain low-level signals in the first phase.

[0326] In the second phase P2, ie, the output phase, the signals at the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, and the total reset signal terminal TRST are low level signals, and the clock signal terminal CLK is a high level signal. The signal at the signal input terminal IN is a low-level signal. The first transistor T1, the seventh transistor T7, and the tenth transistor T10 are turned off. The signal at the control node N remains high at the previous stage. The twenty-first transistor T21 is continuously turned on. Under the bootstrap effect of the capacitor C, the signal at the pull-up node PU is pulled high. The second transistor T2 and the third transistor T3 are turned on. The high-level signal at the clock signal terminal CLK is written to the first output terminal OUT1 and the second output terminal OUT2. The eighth transistor T8 and the eleventh transistor T11 are turned on. The low-level signal at the first power supply terminal V1 is continuously written to the first pull-down node PD1 and the second pull-down node PD2. The first pull-down node PD1 and the second pull-down node PD2 remain low-level signals. The thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are turned off. In this stage, the signals at the pull-up node PU, the first output terminal OUT1, and the second output terminal OUT2 are high-level signals, and the signals at the first pull-down node PD1 and the second pull-down node PD2 are low-level signals.

[0327] In the second phase, when the shift register is in the first display frame, the ninth transistor T9 is turned on and the twelfth transistor T12 is turned off. Although the ninth transistor T9 is turned on, the high-level signal at the fourth power supply terminal V4 will pull the signal of the first pull-down node PD1 high. However, because the eighth transistor T8 and the eleventh transistor T11 are continuously turned on, the signal of the first pull-down node PD1 is still pulled down to a low-level signal. Similarly, when the shift register is in the second display frame, the ninth transistor T9 is turned off and the twelfth transistor T12 is turned on. Although the twelfth transistor T12 is turned on, the high-level signal at the fifth power supply terminal V5 will pull the signal of the second pull-down node PD2 high. However, because the eighth transistor T8 and the eleventh transistor T11 are continuously turned on, the signal of the second pull-down node PD2 is still pulled down to a low-level signal. Regardless of whether the shift register is in the first display frame or the second display frame, the first pull-down node PD1 and the second pull-down node PD2 continue to be low-level signals in the second phase.

[0328] In the second stage, the voltage value of the signal at the signal input terminal IN is less than the voltage value of the signal at the control node N, causing the first transistor T1 to be in a negative bias state and reducing the turn-on voltage of the first transistor T1. In the present disclosure, due to the presence of the twenty-first transistor T21, the voltage value of the signal at the control node N in the second stage is less than the voltage value of the signal at the pull-up node PU. That is, the absolute value of the difference between the voltage value of the signal at the signal input terminal in the shift register provided in FIG20 and the voltage value of the signal at the control node N is less than the absolute value of the difference between the voltage value of the signal at the signal input terminal in the shift register without the second control sub-circuit and the voltage value of the signal at the pull-up node. That is, the negative bias degree of the first transistor in the shift register provided in FIG27 is less than the negative bias degree of the first transistor in the shift register without the second control sub-circuit. The shift register provided in FIG27 can prevent the characteristic drift of the first transistor to a certain extent.

[0329] In the third phase P3, ie, the reset phase, the first reset signal terminal RST1 and the second reset signal terminal RST2 are high level signals, and the signals of the signal input terminal IN, the total reset signal terminal TRST and the clock signal terminal CLK are low level signals. The signals at the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, the low-level signal at the first power supply terminal V1 is written into the signal of the pull-up node PU, the signal of the pull-up node PU is pulled low, the signal of the control node N is pulled low by the pull-up node PU, the low-level signal at the third power supply terminal V3 is written into the signal of the first output terminal OUT1, the signal of the first output terminal OUT1 is pulled low, the signal at the signal input terminal IN is a low-level signal, the first transistor T1, the seventh transistor T7 and the tenth transistor T10 are turned off, the pull-up node PU is a low-level signal, the eighth transistor T8 and the eleventh transistor T11 are turned off, the first pull-down node PD1 and the second pull-down node PD2 are not pulled low by the low-level signal of the first power supply terminal V1, when the shift register is in the first display frame, the ninth transistor T9 is turned on, the high-level signal of the fourth power supply terminal V4 is written into the first pull-down node PD1, the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off, The transistor T15 is turned on, the low-level signal of the first power terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low-level signal of the third power terminal V3 is written into the first output terminal OUT1, the twelfth transistor T12 is turned off, the second pull-down node PD2 maintains the low-level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high-level signal of the fifth power terminal V5 is written into the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low-level signal of the first power terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low-level signal of the third power terminal V3 is written into the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low-level signal of the previous stage, and the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0330] In the fourth phase P4, i.e., the first noise reduction phase, the signal at the clock signal terminal CLK is a high-level signal, and the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, and the total reset signal terminal TRST are low-level signals. The signal at the signal input terminal IN is a low-level signal, the first transistor T1, the seventh transistor T7, and the tenth transistor T10 are disconnected, the signals at the control node N and the pull-up node PU maintain the low-level signals of the previous phase, the twenty-first transistor T21, the second transistor T2, the third transistor T3, the eighth transistor T8, and the eleventh transistor T11 are disconnected, the first pull-down node PD1 and the second pull-down node PD2 are not pulled down by the low-level signal at the first power supply terminal V1, when the shift register is in the first display frame, the ninth transistor T9 is turned on, the high-level signal at the fourth power supply terminal V4 is written to the first pull-down node PD1, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are turned on, the low-level signal at the first power supply terminal V1 is written to the pull-up node PU and the second output terminal OUT2, and the low-level signal at the third power supply terminal V3 is turned on. The first output terminal OUT1 is written, the twelfth transistor T12 is turned off, the second pull-down node PD2 maintains the low-level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high-level signal of the fifth power supply terminal V5 is written to the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low-level signal of the first power supply terminal V1 is written to the pull-up node PU and the second output terminal OUT2, the low-level signal of the third power supply terminal V3 is written to the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low-level signal of the previous stage, and the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0331] In the fifth stage P5, i.e., the second noise reduction stage, the clock signal terminal CLK, the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, and the total reset signal terminal TRST are low-level signals. The signal at the signal input terminal IN is a low-level signal, the first transistor T1, the seventh transistor T7, and the tenth transistor T10 are disconnected, the signals at the control node N and the pull-up node PU maintain the low-level signals of the previous stage, the twenty-first transistor T21, the second transistor T2, the third transistor T3, the eighth transistor T8, and the eleventh transistor T11 are disconnected, the first pull-down node PD1 and the second pull-down node PD2 are not pulled down by the low-level signal of the first power supply terminal V1, when the shift register is in the first display frame, the ninth transistor T9 is turned on, the high-level signal of the fourth power supply terminal V4 is written into the first pull-down node PD1, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are turned on, the low-level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, and the low-level signal of the third power supply terminal V3 is turned on. The first output terminal OUT1 is written, the twelfth transistor T12 is turned off, the second pull-down node PD2 maintains the low-level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high-level signal of the fifth power supply terminal V5 is written to the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low-level signal of the first power supply terminal V1 is written to the pull-up node PU and the second output terminal OUT2, the low-level signal of the third power supply terminal V3 is written to the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low-level signal of the previous stage, and the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0332] The working process of the shift register unit further includes: a plurality of fourth phases P4 and fifth phases P5, and the fourth phases P4 and the fifth phases P5 work alternately.

[0333] The fourth stage P4 and the fifth stage P5 can ensure that the signals of the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 of the shift register are continuously low-level signals, which can reduce the noise of the shift register and improve the reliability of the shift register.

[0334] As shown in FIG28 , the operation process of the shift register provided in FIG27 in the non-display phase may include the following stages:

[0335] In the sixth phase P6 , the signal of the master reset signal terminal TRST is a high-level signal, the fourth transistor T4 is turned on, and the low-level signal of the first power supply terminal V1 is written into the pull-up node PU.

[0336] The present disclosure also provides a shift register driving method, which is configured to drive the shift registers shown in FIG17 to FIG22 . The shift register driving method may include the following steps:

[0337] Step 110, the input sub-circuit provides a signal to the pull-up node under the control of the signal at the signal input terminal.

[0338] Step 120 : The output sub-circuit provides the signal of the clock signal terminal to the first output terminal under the control of the signal of the pull-up node.

[0339] Step 130 : The control sub-circuit provides the signal of the control signal terminal to the signal input terminal under the control of the signal of the control signal terminal.

[0340] The shift register is the shift register provided by any of the aforementioned embodiments, and its implementation principle and effect are similar, which will not be described in detail here.

[0341] The embodiment of the present disclosure further provides a shift register driving method, which is configured to drive the shift register shown in FIG23 . The shift register driving method may include the following steps:

[0342] Step 210: The input sub-circuit provides a signal to the control node under the control of the signal input terminal.

[0343] Step 220 : Under the control of the signal of the control node, the second control sub-circuit provides the signal of the control node to the pull-up node.

[0344] Step 230 : The output sub-circuit is configured to provide the signal of the clock signal terminal to the first output terminal under the control of the signal of the pull-up node.

[0345] An embodiment of the present disclosure further provides a gate driving circuit, which includes: a plurality of cascaded shift registers.

[0346] The shift register is the shift register provided by any of the aforementioned embodiments, and its implementation principle and effect are similar, which will not be described in detail here.

[0347] In an exemplary embodiment, the gate driving circuit is provided in a display device, the display device is further provided with gate lines, and the shift register includes an output sub-circuit.

[0348] In an exemplary embodiment, the general reset signal terminals in all shift registers are connected to the same signal line, the first power supply terminals in all shift registers are connected to the same signal line, the second power supply terminals in all shift registers are connected to the same signal line, the third power supply terminals in all shift registers are connected to the same signal line, the fourth power supply terminals in all shift registers are connected to the same signal line, and the fifth power supply terminals in all shift registers are connected to the same signal line.

[0349] Figure 29 is a first schematic diagram of a cascaded gate drive circuit. As shown in Figure 29, when the output sub-circuit includes the first output terminal OUT1, the first output terminal OUT1 of any shift register stage is electrically connected to the gate line, the first output terminal OUT1 of the current shift register is electrically connected to the signal input terminal IN of the next shift register stage, and the first output terminal OUT1 of the current shift register is electrically connected to the first reset signal terminal RST1 or the second reset signal terminal RST2 of the previous shift register stage.

[0350] Figure 30 is a second schematic diagram of the cascade connection of the gate drive circuit. As shown in Figure 30, when the output sub-circuit includes a first output terminal OUT1 and a second output terminal OUT2, the first output terminal OUT1 of any shift register is electrically connected to the gate line, the second output terminal OUT2 of the shift register at the current stage is electrically connected to the signal input terminal IN of the shift register at the next stage, and the second output terminal OUT2 of the shift register at the current stage is electrically connected to the first reset signal terminal RST1 or the second reset signal terminal RST2 of the shift register at the previous stage.

[0351] GOA(i) in FIG. 29 and FIG. 30 refers to the i-th stage shift register.

[0352] An embodiment of the present disclosure further provides a display device including a gate driving circuit.

[0353] The gate driving circuit is the gate driving circuit provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be repeated here.

[0354] In an exemplary embodiment, the display device may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. The display device may be any product or component with a display function, such as an LCD panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0355] A display device may include: a display substrate. The display substrate may include a plurality of pixel units arranged in a matrix, the plurality of pixel units including a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and at least one third sub-pixel emitting a third color light. The first sub-pixel, the second sub-pixel, and the third sub-pixel each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the pixel driving circuit of the sub-pixel. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0356] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel may be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the sub-pixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure.

[0357] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0358] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be a first sub-pixel, a second sub-pixel, and two third sub-pixels. The four sub-pixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in the present disclosure.

[0359] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0360] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0361] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0362] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A shift register, characterized in that: include: an input subcircuit, an output subcircuit and a first control subcircuit; The input subcircuit is electrically connected to the signal input terminal and the pull-up node, respectively, and is configured to provide a signal to the pull-up node under the control of the signal of the signal input terminal; The output subcircuit is electrically connected to the first output terminal, the pull-up node and the clock signal terminal respectively, and is configured to provide a signal of the clock signal terminal to the first output terminal under the control of a signal of the pull-up node; The first control subcircuit is electrically connected to the control signal terminal and the signal input terminal respectively, and is configured to provide the signal of the control signal terminal to the signal input terminal under the control of the signal of the control signal terminal.

2. The shift register according to claim 1, characterized in that: The shift register further includes: a first reset subcircuit; The first reset subcircuit is electrically connected to the general reset signal terminal, the pull-up node and the first power supply terminal respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node under the control of the general reset signal terminal; The total reset signal terminal is a valid level signal in a partial period of time in the non-display stage, and is an invalid level signal in the display stage.

3. The shift register according to claim 1, characterized in that: The control signal terminal includes: at least one of a first control signal terminal and a second control signal terminal; The first control signal terminal is electrically connected to the general reset signal terminal, and the second control signal terminal is electrically connected to the first output terminal.

4. The shift register according to claim 3, characterized in that: In a state where the control signal terminal includes the first control signal terminal, the first control subcircuit includes: a nineteenth transistor; The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal.

5. The shift register according to claim 3, characterized in that: In a state where the control signal terminal includes the second control signal terminal, the first control subcircuit includes: a twentieth transistor; The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

6. The shift register according to claim 3, characterized in that: In a state where the control signal terminal includes a first control signal terminal and a second control signal terminal, the control subcircuit includes: a nineteenth transistor and a twentieth transistor; The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal; The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

7. The shift register according to claim 1, characterized in that: The input subcircuit comprises: a first transistor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the pull-up node.

8. The shift register according to claim 1, characterized in that: The input subcircuit comprises: a first transistor and a twenty-first transistor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node; The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

9. The shift register according to claim 1, characterized in that: The output subcircuit includes: a second transistor and a capacitor; The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal; A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output end.

10. The shift register according to claim 1, characterized in that: The output subcircuit is also electrically connected to the second output terminal, and is configured to provide the signal of the clock signal terminal to the second output terminal under the control of the signal of the pull-up node.

11. The shift register according to claim 10, characterized in that: The output subcircuit includes: a second transistor, a third transistor and a capacitor; The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal; A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal; A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output end.

12. The shift register according to claim 2, characterized in that: The first reset subcircuit comprises: a fourth transistor; The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal.

13. The shift register according to claim 1, characterized in that: The shift register further includes: a second reset subcircuit; The second reset subcircuit is electrically connected to the first reset signal terminal, the second reset signal terminal, the pull-up node, the first output terminal, the first power supply terminal and the third power supply terminal, respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node and provide the signal of the third power supply terminal to the first output terminal under the control of the signals of the first reset signal terminal and the second reset signal terminal; The absolute value of the voltage of the signal at the first power supply terminal is greater than the absolute value of the voltage of the signal at the third power supply terminal; The first reset signal terminal and the second reset signal terminal are invalid level signals in the non-display stage and the output stage, and are valid level signals in a partial time period of the non-output stage.

14. The shift register according to claim 13, characterized in that: The second reset subcircuit comprises: a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal; The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the third power supply terminal.

15. The shift register according to claim 10, characterized in that: The shift register further includes: a noise reduction subcircuit, wherein the noise reduction subcircuit includes: at least one of a first noise reduction subcircuit and a second noise reduction subcircuit; The first noise reduction sub-circuit is electrically connected to the fourth power supply terminal, the signal input terminal, the pull-up node, the first output terminal, the second output terminal, the first power supply terminal and the third power supply terminal, respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node and the second output terminal, and provide the signal of the third power supply terminal to the pull-down node under the control of the signal of the signal input terminal, the pull-up node and the fourth power supply terminal; The second noise reduction sub-circuit is electrically connected to the fifth power supply terminal, the signal input terminal, the pull-up node, the first output terminal, the second output terminal, the first power supply terminal and the third power supply terminal, respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node and the second output terminal, and provide the signal of the third power supply terminal to the pull-down node under the control of the signals of the signal input terminal, the pull-up node and the fifth power supply terminal.

16. The shift register according to claim 15, characterized in that: The first noise reduction sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, and the second noise reduction sub-circuit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor; The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal; The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node; The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal; The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node; The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal; The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal; The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal; The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal; The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal; The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal.

17. The shift register according to claim 1, characterized in that: Also includes: a first reset subcircuit, a second reset subcircuit and a noise reduction subcircuit; The input subcircuit includes: a first transistor, the output subcircuit includes: a second transistor, a third transistor and a capacitor, the first control subcircuit includes: at least one of a nineteenth transistor and a twentieth transistor; the first reset subcircuit includes: a fourth transistor, the second reset subcircuit includes: a fifth transistor and a sixth transistor, and the noise reduction subcircuit includes: a seventh transistor to an eighteenth transistor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the pull-up node; The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal; A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal; A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal; The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal; The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal; The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the first power supply terminal; The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal; The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node; The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal; The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node; The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal; The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal; The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal; The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal; The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal; The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal; The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

18. The shift register according to claim 1, characterized in that: Also includes: a first reset subcircuit, a second reset subcircuit and a noise reduction subcircuit; The input subcircuit includes: a first transistor and a twenty-first transistor, the output subcircuit includes: a second transistor, a third transistor and a capacitor, the first control subcircuit includes: at least one of a nineteenth transistor and a twenty-first transistor; the first reset subcircuit includes: a fourth transistor, the second reset subcircuit includes: a fifth transistor and a sixth transistor, and the noise reduction subcircuit includes: a seventh transistor to an eighteenth transistor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node; The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal; A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal; A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal; The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal; The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal; The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the first power supply terminal; The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal; The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node; The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal; The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node; The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal; The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal; The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal; The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal; The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal; The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal; The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal; The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

19. A shift register, characterized in that: include: An input subcircuit, an output subcircuit, and a second control subcircuit; The input subcircuit is electrically connected to the signal input terminal and the control node respectively, and is configured to provide a signal to the control node under the control of the signal input terminal; The second control subcircuit is electrically connected to the control node and the pull-up node, respectively, and is configured to provide the signal of the control node to the pull-up node under the control of the signal of the control node; The output subcircuit is electrically connected to the first output terminal, the pull-up node and the clock signal terminal respectively, and is configured to provide a signal from the clock signal terminal to the first output terminal under the control of a signal from the pull-up node.

20. The shift register according to claim 19, characterized in that: Also includes: a first reset subcircuit, a second reset subcircuit and a noise reduction subcircuit; The input subcircuit includes: a first transistor, the output subcircuit includes: a second transistor, a third transistor and a capacitor, the second control subcircuit includes: a twenty-first transistor; the first reset subcircuit includes: a fourth transistor, the second reset subcircuit includes: a fifth transistor and a sixth transistor, the noise reduction subcircuit includes: a seventh transistor to an eighteenth transistor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node; The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal; A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal; A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal; The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal; The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal; The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, and the first electrode of the sixth transistor is electrically connected to the first output terminal. The second electrode of the sixth transistor is electrically connected to the first power supply terminal; The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal; The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node; The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal; The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node; The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal; The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal; The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal; The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal; The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal; The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

21. A gate drive circuit, characterized in that: include: A plurality of cascaded shift registers as claimed in any one of claims 1 to 20.

22. The gate driving circuit according to claim 21, characterized in that: The gate drive circuit is arranged in a display device, the display device is further provided with a gate line, and the shift register includes an output subcircuit; When the output sub-circuit includes the first output terminal, the first output terminal of any level of shift register is electrically connected to the gate line, the first output terminal of the shift register at this level is electrically connected to the signal input terminal of the shift register at the next level, and the first output terminal of the shift register at this level is electrically connected to the first reset signal terminal or the second reset signal terminal of the shift register at the previous level.

23. The gate driving circuit according to claim 21, characterized in that: The gate drive circuit is arranged in a display device, the display device is further provided with a gate line, and the shift register includes an output subcircuit; In the state where the output subcircuit includes the first output terminal and the second output terminal, the first output terminal of any stage of the shift register is electrically connected to the gate line, the second output terminal of the current stage of the shift register is electrically connected to the signal input terminal of the next stage of the shift register, and the second output terminal of the current stage of the shift register is electrically connected to the first reset signal terminal or the second reset signal terminal of the previous stage of the shift register. Terminal electrical connection.

24. A display device, characterized in that: Comprising the gate drive circuit as described in any one of claims 21 to 23.

25. A shift register driving method, characterized in that: is configured to drive the shift register according to any one of claims 1 to 18, the method comprising: The input subcircuit provides a signal to the pull-up node under the control of the signal at the signal input terminal; The output subcircuit provides the signal of the clock signal terminal to the first output terminal under the control of the signal of the pull-up node; The control subcircuit provides the signal of the control signal terminal to the signal input terminal under the control of the signal of the control signal terminal.

26. A shift register driving method, characterized in that: is configured to drive a shift register as claimed in claim 19 or 20, the method comprising: The input subcircuit provides a signal to the control node under the control of the signal input terminal; The second control subcircuit provides the signal of the control node to the pull-up node under the control of the signal of the control node; The output sub-circuit is configured to provide a signal of the clock signal terminal to the first output terminal under the control of a signal of the pull-up node.

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