Semiconductor structure and manufacturing method therefor

Abstract

Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a dielectric layer, which comprises a deep trench capacitor array and an isolation structure, wherein the deep trench capacitor array comprises a plurality of deep trench capacitors, and the isolation structure at least partially surrounds the deep trench capacitor on the outermost edge of the deep trench capacitor array.

Description

Semiconductor structure and manufacturing method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 14, 2023, with application number 202310868012.5 and application name “A semiconductor structure and its manufacturing method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0003] With the development of semiconductor technology, packaging different types of chips together through an interposer has gradually become a trend in packaging technology. In related technologies, deep trench capacitors (DTCs) are usually installed in the interposer as decoupling capacitors to reduce signal noise and leakage between adjacent semiconductor devices coupled to the interposer. However, there is a large parasitic capacitance between the deep trench capacitors and other devices on the interposer, which can easily cause interference to other devices.

[0004] Summary of the Invention

[0005] According to a first aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: an interposer, the interposer comprising a deep trench capacitor array and an isolation structure; wherein the deep trench capacitor array comprises a plurality of deep trench capacitors, and the isolation structure at least partially surrounds the deep trench capacitors at the outermost side of the deep trench capacitor array.

[0006] In some embodiments, the deep trench capacitor includes: a first electrode layer, a capacitor dielectric layer, a second electrode layer and a conductive layer; wherein, the first electrode layer covers the inner wall of the deep trench in the intermediary layer and extends to the upper surface of the intermediary layer; the capacitor dielectric layer covers the first electrode layer; the second electrode layer covers the capacitor dielectric layer; and the conductive layer covers the second electrode layer.

[0007] In some embodiments, the isolation structure includes a first isolation structure, an isolation trench is provided in the intermediary layer, and the first isolation structure is located in the isolation trench; for a deep trench capacitor array, on the side away from the first isolation structure, the ends of the first electrode layer, the capacitor dielectric layer, the second electrode layer and the conductive layer of the deep trench capacitor on the outermost side located on the upper surface of the intermediary layer completely overlap; on the side close to the first isolation structure, the deep trench capacitor on the outermost side exposes part of the first electrode layer, and the ends of the capacitor dielectric layer, the second electrode layer and the conductive layer of the deep trench capacitor on the outermost side located on the upper surface of the intermediary layer completely overlap, and the remaining part of the first electrode layer located on the upper surface of the intermediary layer is covered by the capacitor dielectric layer.

[0008] In some embodiments, the semiconductor structure further includes a dielectric material layer, wherein the dielectric material layer covers the conductive layer in the deep trench and completely fills the deep trench.

[0009] In some embodiments, the semiconductor structure further includes an insulating layer, which is located between the deep trench capacitor array and the interposer and is exposed on the interposer on a side of the deep trench capacitors on the outermost side away from the first isolation structure.

[0010] In some embodiments, the isolation structure further includes a second isolation structure, wherein the second isolation structure covers the deep trench capacitor array, the first isolation structure, and the exposed insulating layer.

[0011] In some embodiments, in a cross section perpendicular to a first direction, the cross section of the first isolation structure is rectangular, trapezoidal, inverted trapezoidal, or elliptical; the first direction is perpendicular to the vertical direction.

[0012] In some embodiments, the isolation trench has an aspect ratio of 2-10.

[0013] In some embodiments, projections of the plurality of deep trench capacitors on the upper surface of the interposer along the vertical direction are arranged in a regular hexagonal shape.

[0014] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing an intermediary layer; forming an initial deep trench capacitor array structure in the intermediary layer, the initial deep trench capacitor array structure comprising a plurality of initial deep trench capacitor structures; performing a first etching on the initial deep trench capacitor array structure to expose a first electrode layer at the periphery of the initial deep trench capacitor structure at the outermost edge of the initial deep trench capacitor array structure to form an intermediate deep trench capacitor array structure; performing a second etching on the intermediate deep trench capacitor array structure to etch the exposed first electrode layer away from the side of the initial deep trench capacitor structure at the outermost edge to form an isolation trench, and cutting off adjacent capacitor units in the intermediate deep trench capacitor array structure to form a deep trench capacitor array; filling the isolation trench with isolation material to form an isolation structure; the isolation structure at least partially surrounds the deep trench capacitor at the outermost edge of the deep trench capacitor array.

[0015] In some embodiments, an initial deep trench capacitor array structure is formed in the interposer, comprising: forming a deep trench array in the interposer, the deep trench array comprising a plurality of deep trenches; depositing insulating material on the upper surface of the interposer and in the deep trenches to form an insulating layer, the insulating layer covering the inner walls of the deep trenches and extending to the upper surface of the interposer; depositing the first electrode layer, the capacitor dielectric layer, the second electrode layer and the conductive layer in sequence on the insulating layer to form the initial deep trench capacitor array structure; wherein the first electrode layer covers the insulating layer; the capacitor dielectric layer covers the first electrode layer; the second electrode layer covers the capacitor dielectric layer; and the conductive layer covers the second electrode layer.

[0016] In some embodiments, after forming an initial deep trench capacitor array structure in the interposer, the method further includes depositing a dielectric material on the conductive layer, the dielectric material covering the conductive layer in the deep trench and completely filling the deep trench to form a dielectric material layer.

[0017] In some embodiments, the initial deep trench capacitor array structure is etched for the first time, including: forming a patterned first mask layer on the initial deep trench capacitor array structure; etching the initial deep trench capacitor array structure for the first time according to the patterned first mask layer, forming a first trench around the initial deep trench capacitor structure at the outermost side of the initial deep trench capacitor array structure, the first trench exposing the first electrode layer; and the remaining initial deep trench capacitor array structure serves as the intermediate deep trench capacitor array structure.

[0018] In some embodiments, the intermediate deep trench capacitor array structure is etched a second time, including: forming a patterned second mask layer on the intermediate deep trench capacitor array structure; etching the intermediate deep trench capacitor array structure a second time according to the patterned second mask layer to form the isolation trench on the side of the first trench away from the initial deep trench capacitor structure on the outermost side; and cutting off adjacent capacitor units in the intermediate deep trench capacitor array structure to expose part of the insulating layer; the isolation trench extends into the intermediate layer; and the remaining intermediate deep trench capacitor array structure serves as the deep trench capacitor array.

[0019] In some embodiments, an isolation material is filled in the isolation trench to form an isolation structure, including: depositing an isolation material on the interposer formed with the deep trench capacitor array, wherein a portion of the isolation material fills the isolation trench to form a first isolation structure; a portion of the isolation material covers the deep trench capacitor array, the first isolation structure and the exposed insulating layer to form a second isolation structure, and the first isolation structure and the second isolation structure constitute the isolation structure.

[0020] Thus, the present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes an interposer, the interposer including a deep trench capacitor array and an isolation structure. The deep trench capacitor array includes a plurality of deep trench capacitors, and the isolation structure at least partially surrounds the deep trench capacitors at the outermost edges of the deep trench capacitor array.

[0021] In the embodiment of the present disclosure, an isolation structure is provided in the interposer, and the isolation structure at least partially surrounds the deep trench capacitor at the outermost side of the deep trench capacitor array. In this way, the deep trench capacitor array can be isolated from other semiconductor devices located on the interposer, which is beneficial to reducing the parasitic capacitance between the deep trench capacitor array and other semiconductor devices on the interposer, thereby reducing the interference caused by the deep trench capacitor array to other semiconductor devices and improving the electrical performance of the semiconductor structure.

[0022] The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] FIG1 is a vertical cross-sectional schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0025] FIG2 is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0026] FIG3 is an enlarged schematic diagram of the dotted line frame area in FIG2 ;

[0027] FIG4 is a microscopic image of a semiconductor structure provided by an embodiment of the present disclosure;

[0028] FIG5 is a second vertical cross-sectional diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0029] FIG6 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

[0030] FIG7 is a first structural diagram of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0031] FIG8 is a second structural schematic diagram of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0032] FIG9 is a third structural diagram of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0033] FIG10 is a fourth structural diagram of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0034] FIG11 is a fifth structural diagram of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0035] FIG12 is a sixth structural diagram of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0036] FIG13 is a seventh structural diagram of a semiconductor structure during the manufacturing process according to an embodiment of the present disclosure;

[0037] FIG14 is a structural schematic diagram eight of a semiconductor structure during the manufacturing process according to an embodiment of the present disclosure;

[0038] FIG15 is a ninth structural diagram of a semiconductor structure during the manufacturing process according to an embodiment of the present disclosure;

[0039] FIG16 is a first structural diagram of a semiconductor structure during the manufacturing process provided by the related art;

[0040] FIG17 is a second structural schematic diagram of a semiconductor structure during the manufacturing process provided by the related art;

[0041] FIG18 is a third structural diagram of a semiconductor structure during the manufacturing process provided by the related art;

[0042] FIG19 is a fourth structural diagram of a semiconductor structure during the manufacturing process provided by the related art;

[0043] FIG20 is a fifth structural diagram of a semiconductor structure during the manufacturing process provided by the related art;

[0044] FIG21 is a sixth structural diagram of a semiconductor structure during the manufacturing process provided by the related art;

[0045] FIG22 is a seventh structural diagram of a semiconductor structure during the manufacturing process provided by the related art;

[0046] FIG23 is a structural schematic diagram 8 of a semiconductor structure during the manufacturing process provided by the related art;

[0047] FIG24 is a ninth structural diagram of a semiconductor structure during the manufacturing process provided by the related art. DETAILED DESCRIPTION

[0048] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0049] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0050] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0051] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0052] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0053] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0054] With the advancement of semiconductor technology, traditional two-dimensional packaging can no longer meet industry needs. Therefore, vertical interconnect stacking packaging based on through-silicon via (TSV) technology, which packages different types of chips together through a silicon interposer, has gradually led the development of packaging technology, offering key advantages such as short-distance interconnection and high-density integration.

[0055] In related art, deep trench capacitors (DTCs) are typically provided in the interposer as decoupling capacitors to reduce signal noise and leakage between adjacent semiconductor devices coupled to the interposer. However, because the DTC array on the interposer lacks an isolation structure, the DTC array has a large keep-out zone (KOZ). The keep-out zone refers to the area around the DTC array where no circuit components, such as transistors, are located. Consequently, large parasitic capacitance exists between the DTC array and other devices on the interposer (including between DTC arrays), which can easily interfere with other devices.

[0056] Based on this, the present disclosure proposes the following technical solutions:

[0057] An embodiment of the present disclosure provides a semiconductor structure, and FIG1 is a vertical cross-sectional schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; FIG2 is a top view schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; and FIG3 is an enlarged schematic diagram of the dotted box area in FIG2.

[0058] 1 , the semiconductor structure includes an interposer 10 , which includes a deep trench capacitor array 11 (as shown in FIG. 2 ) and an isolation structure 12 .

[0059] The deep trench capacitor array 11 includes a plurality of deep trench capacitors 110 , and the isolation structure 12 at least partially surrounds the deep trench capacitors 110 at the outermost side of the deep trench capacitor array 11 (ie, the periphery of the deep trench capacitor array).

[0060] It should be noted that the first direction x shown in FIG1 and the vertical direction z shown in FIG2 are directions perpendicular to the paper. Furthermore, to clearly illustrate the contents of this embodiment, FIG1 only shows the positional relationship between the deep trench capacitors 110 at the outermost edge of the deep trench capacitor array 11 and the isolation structure 12. This will not be further described.

[0061] In the embodiment of the present disclosure, referring to FIG1 , the interposer 10 is a conduit for transmitting electrical signals between multiple chips in a package. The interposer 10 can realize interconnection between chips, and can also realize interconnection with the package substrate, acting as a bridge between multiple bare chips and circuit boards. For example, the interposer 10 can connect memory chips (e.g., dynamic random access memory (DRAM)) and logic chips (e.g., central processing unit (CPU), graphics processing unit (GPU)). The material of the interposer 10 can be materials such as silicon, polysilicon, germanium, silicon germanium, and silicon carbide.

[0062] In some embodiments of the present disclosure, referring to FIG2 , the projections of multiple deep trench capacitors 110 onto the upper surface of the interposer 10 along the vertical direction z are arranged in a regular hexagon. Specifically, the projections of six adjacent deep trench capacitors 110 onto the plane of the interposer 10 are arranged in a regular hexagon, with a deep trench capacitor 110 located at each vertex of the regular hexagon and a deep trench capacitor 110 located at the center of the regular hexagon. In other words, the deep trench capacitors 110 are arranged in a hexagonal closet packed (HCP) structure.

[0063] It is understandable that the arrangement of the multiple deep trench capacitors 110 is a hexagonal closest packing structure, which can obtain a densely arranged deep trench capacitor array 11 and further improve the capacitance value of the deep trench capacitor array 11.

[0064] In some embodiments of the present disclosure, referring to FIG1 , the deep trench capacitor 110 includes: a first electrode layer 111, a capacitor dielectric layer 112, a second electrode layer 113, and a conductive layer 114; wherein the first electrode layer 111 covers the inner wall of the deep trench T0 in the interposer 10 and extends to the upper surface of the interposer 10; the capacitor dielectric layer 112 covers the first electrode layer 111; the second electrode layer 113 covers the capacitor dielectric layer 112; and the conductive layer 114 covers the second electrode layer 113.

[0065] In some other embodiments, the deep trench capacitor may include multiple electrode layers and multiple capacitor dielectric layers stacked alternately. For example, the deep trench capacitor may be a double-sided deep trench capacitor, thereby increasing the capacitance of the deep trench capacitor.

[0066] It should be noted that the deep trench T0 refers to the trench where the deep trench capacitor 110 is located in the interposer 10 , and the deep trench T0 has a relatively high aspect ratio. For example, the aspect ratio of the deep trench T0 may be 10, 15, or 20.

[0067] In the embodiment of the present disclosure, referring to FIG1 , the materials of the first electrode layer 111, the second electrode layer 113, and the conductive layer 114 can be at least one of conductive materials such as doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, etc. Specifically, the materials of the first electrode layer 111 and the second electrode layer 113 are titanium nitride, and the material of the conductive layer 114 is polysilicon. The material of the capacitor dielectric layer 112 can be at least one of insulating materials such as aluminum oxide (Al2O3) and zirconium oxide (ZrO). The capacitor dielectric layer 112 can also include other insulating materials with a higher dielectric constant (high-k), such as a material with a dielectric constant greater than 3.9.

[0068] In the embodiment of the present disclosure, referring to FIG1 , the isolation structure 12 at least partially surrounds the deep trench capacitors 110 at the outermost edge of the deep trench capacitor array 11. In other words, the isolation structure 12 may partially surround the deep trench capacitors 110 at the outermost edge of the deep trench capacitor array 11, or may completely surround the deep trench capacitors 110 at the outermost edge of the deep trench capacitor array 11. The following description will take the case where the isolation structure 12 completely surrounds the deep trench capacitors 110 at the outermost edge of the deep trench capacitor array 11 as an example.

[0069] In some embodiments of the present disclosure, referring to FIG. 1 , the isolation structure 12 includes a first isolation structure 13 . An isolation trench T1 is provided in the interposer 10 , and the first isolation structure 13 is located in the isolation trench T1 .

[0070] In some embodiments of the present disclosure, referring to FIG1 , the aspect ratio of the isolation trench T1 is 2-10, inclusive. For example, the aspect ratio of the isolation trench T1 can be 2, 5, 7, or 10.

[0071] It should be noted that the size of the isolation trench T1 can be determined based on actual needs, taking into account factors such as the number, size, and layout of the deep trench capacitors, the capacitance value, the operating voltage, the tolerance of the peripheral circuits, and the distance between the device to be isolated and the deep trench capacitor array. For example, the closer the distance between the device to be isolated and the deep trench capacitor array 11 is, the deeper and wider the isolation trench T1 can be.

[0072] In some embodiments of the present disclosure, referring to FIG1 , the cross-sectional shape of the first isolation structure 13 in a cross section perpendicular to a first direction x can be rectangular, trapezoidal, inverted trapezoidal, or elliptical. The first direction x is perpendicular to the vertical direction z. The cross-sectional shape of the first isolation structure 13 is not specifically limited herein. The following description uses a rectangular cross-sectional shape of the first isolation structure 13 as an example.

[0073] In the embodiment of the present disclosure, referring to FIG1 , the material of the first isolation structure 13 may include insulating materials such as oxide, nitride, or oxynitride. The first isolation structure 13 may also adopt an oxide-nitride-oxide (ONO) stacked structure. Specifically, the material of the first isolation structure 13 is silicon oxide.

[0074] In one embodiment of the present disclosure, a semiconductor device is provided in the interposer, and the isolation structure may be located between the deep trench capacitor array 11 and the semiconductor device, or between the deep trench capacitor arrays 11 and the deep trench capacitor arrays 11 .

[0075] It can be understood that the isolation structure 12 at least partially surrounds the deep trench capacitor 110 at the outermost side of the deep trench capacitor array 11. In this way, the deep trench capacitor array 11 can be isolated from other semiconductor devices located on the interposer 10, which is beneficial to reducing the parasitic capacitance between the deep trench capacitor array 11 and other semiconductor devices on the interposer 10, thereby reducing the interference caused by the deep trench capacitor array 11 to other semiconductor devices and improving the electrical performance of the semiconductor structure.

[0076] FIG4 is a microscopic image of a semiconductor structure provided by an embodiment of the present disclosure.

[0077] In the disclosed embodiment, referring to FIG4 , the isolation trench T1 is located in the etch overlap region 120. Here, the etch overlap region 120 is the region where the first etch region 121 and the second etch region 122 partially overlap. The first etch region 121 and the second etch region 122 are formed by the first and second etching steps, respectively, to form the deep trench capacitor array 11.

[0078] In the disclosed embodiment, referring to Figures 2 and 3 , in a cross section perpendicular to the vertical direction z, the first etched region 121, the second etched region 122, and the etched overlap region 120 form a rectangular ring structure. In other words, in a cross section perpendicular to the vertical direction z, the first isolation structure 13 forms a rectangular ring structure. This allows the first isolation structure 13 to completely surround the deep trench capacitors 110 at the outermost edges of the deep trench capacitor array 11.

[0079] It should be noted that the first etched area 121, the second etched area 122, and the etched overlap area 120 herein refer to a region demarcated on the plane of the interposer 10, rather than the actual region formed when etching is performed on the interposer 10. In other words, the first etched area 121, the second etched area 122, and the etched overlap area 120 are regions that occupy a portion of the interposer 10. These will not be further described.

[0080] It can be understood that the etching overlap region 120 is the partial overlap between the first etched region 121 and the second etched region 122 obtained by the first and second etches, respectively, during the formation of the deep trench capacitor array 11. In other words, the first isolation structure 13 can be fabricated using the same two photomasks required for the deep trench capacitor array 11. This process of fabricating the first isolation structure 13 does not require the use of new photomasks or the addition of new process steps, resulting in a simple fabrication process and low production costs.

[0081] In some embodiments of the present disclosure, referring to FIG. 1 , for a deep trench capacitor array 11 , on a side away from the first isolation structure 13 , the ends of the first electrode layer 111 , the capacitor dielectric layer 112 , the second electrode layer 113 , and the conductive layer 114 of the outermost deep trench capacitor 110 located on the upper surface of the interposer 10 completely overlap;

[0082] On the side close to the first isolation structure 13, the deep trench capacitor 110 at the outermost side exposes a portion of the first electrode layer 111, and the ends of the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 of the deep trench capacitor 110 at the outermost side located on the upper surface of the intermediary layer 10 completely overlap, and the remaining portion of the first electrode layer 111 located on the upper surface of the intermediary layer 10 is covered by the capacitor dielectric layer 112.

[0083] It is understood that, on the one hand, by completely or partially overlapping the ends of the first electrode layer 111, capacitor dielectric layer 112, conductive layer 114, and second electrode layer 113 in the deep trench capacitor 110, which are located on the interposer 10, the uniformity of the electrode lead-out in the deep trench capacitor 110 can be improved, thereby reducing parasitic resistance and improving the performance of the deep trench capacitor 110. On the other hand, on the side close to the first isolation structure 13, the deep trench capacitor 110 at the outermost side exposes a portion of the first electrode layer 111, which can facilitate subsequent electrical connection with the conductive plug.

[0084] In some embodiments of the present disclosure, referring to FIG1 , the semiconductor structure further includes a dielectric material layer 16 . The dielectric material layer 16 covers the conductive layer 114 located in the deep trench T0 and completely fills the deep trench T0 . Here, the dielectric material layer 16 can completely fill the deep trench T0 , thereby improving the problem of using polysilicon to fill the deep trench in related technologies, which can easily lead to incomplete filling of the deep trench and the formation of gaps.

[0085] In the embodiment of the present disclosure, the material of the dielectric material layer 16 can be at least one of silicon oxide, silicon nitride, and silicon oxynitride. Specifically, the material of the dielectric material layer 16 is silicon oxide.

[0086] In some embodiments of the present disclosure, referring to FIG. 1 , the semiconductor structure further includes an insulating layer 15 , which is located between the deep trench capacitor array 11 and the interposer 10 and is exposed on the interposer 10 on a side of the outermost deep trench capacitors 110 away from the first isolation structure 13 . Here, the insulating layer 15 is located between the deep trench capacitor array 11 and the interposer 10 to provide electrical isolation between the deep trench capacitors 110 and the interposer 10.

[0087] In the embodiment of the present disclosure, the insulating layer 15 may be made of at least one insulating material selected from silicon oxide, silicon nitride, silicon oxynitride, etc. Specifically, the insulating layer 15 may be made of silicon oxide.

[0088] FIG5 is a schematic vertical cross-sectional view of another semiconductor structure provided by an embodiment of the present disclosure;

[0089] In some embodiments of the present disclosure, referring to FIG5 , the isolation structure 12 further includes a second isolation structure 14, which covers the deep trench capacitor array 11, the first isolation structure 13, and the exposed insulating layer 15. Thus, the second isolation structure 14 can isolate the deep trench capacitor array 11 from the outside world, thereby protecting the deep trench capacitor array 11.

[0090] In the disclosed embodiment, referring to FIG. 5 , the material of the second isolation structure 14 may include oxide, nitride, or oxynitride. The second isolation structure 14 may also employ an oxide-nitride-oxide (ONO) stacked structure. The materials of the second isolation structure 14 and the first isolation structure 13 may be the same or different. Specifically, the material of the second isolation structure 14 is silicon oxide.

[0091] The present disclosure also provides a method for manufacturing a semiconductor structure. FIG6 is a flow chart of a method for manufacturing a semiconductor structure provided by the present disclosure. As shown in FIG6 to FIG24 , the method includes the following steps:

[0092] Step S101: providing an interposer 10;

[0093] Step S102 : forming an initial deep trench capacitor array structure 23 in the interposer 10 , wherein the initial deep trench capacitor array structure 23 includes a plurality of initial deep trench capacitor structures 230 ;

[0094] Step S103: performing a first etching on the initial deep trench capacitor array structure 23 to expose the first electrode layer 111 at the periphery of the initial deep trench capacitor structure 230 at the outermost side of the initial deep trench capacitor array structure 23 to form an intermediate deep trench capacitor array structure 24;

[0095] Step S104: performing a second etching on the middle deep trench capacitor array structure 24 to form an isolation trench T1 on the side of the exposed first electrode layer 111 away from the initial deep trench capacitor structure 230 at the outermost side, and cutting off adjacent capacitor units in the middle deep trench capacitor array structure 24 to form a deep trench capacitor array 11;

[0096] Step S105 : filling the isolation trench T1 with an isolation material to form an isolation structure 12 ; the isolation structure 12 at least partially surrounds the deep trench capacitor 110 at the outermost edge of the deep trench capacitor array 11 .

[0097] 7 to 15 are schematic diagrams of the structure of the semiconductor structure during the manufacturing process according to the embodiment of the present disclosure. The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be further described below with reference to FIG7 to 15.

[0098] First, referring to FIG. 7 to FIG. 10 , step S101 is performed: providing an interposer 10 ; step S102 is performed: forming an initial deep trench capacitor array structure 23 in the interposer 10 , the initial deep trench capacitor array structure 23 including a plurality of initial deep trench capacitor structures 230 .

[0099] In the embodiment of the present disclosure, referring to FIG7 , the interposer 10 is a conduit for transmitting electrical signals between multiple chips in a package. The interposer 10 can realize interconnection between chips, and can also realize interconnection with the package substrate, acting as a bridge between multiple bare chips and circuit boards. For example, the interposer 10 can connect memory chips (e.g., dynamic random access memory (DRAM)) and logic chips (e.g., central processing unit (CPU), graphics processing unit (GPU)). The material of the interposer 10 can be materials such as silicon, polysilicon, germanium, silicon germanium, and silicon carbide.

[0100] In some embodiments of the present disclosure, referring to FIG. 7 to FIG. 10 , an initial deep trench capacitor array structure 23 is formed in an interposer 10 , including:

[0101] A deep trench array is formed in the interposer 10 , wherein the deep trench array includes a plurality of deep trenches T0 ;

[0102] Depositing an insulating material on the upper surface of the interposer 10 and in the deep trench T0 to form an insulating layer 15 , wherein the insulating layer 15 covers the inner wall of the deep trench T0 and extends to the upper surface of the interposer 10 ;

[0103] A first electrode layer 111, a capacitor dielectric layer 112, a second electrode layer 113 and a conductive layer 114 are sequentially deposited on the insulating layer 15 to form an initial deep trench capacitor array structure 23; wherein the first electrode layer 111 covers the insulating layer 15; the capacitor dielectric layer 112 covers the first electrode layer 111; the second electrode layer 113 covers the capacitor dielectric layer 112; and the conductive layer 114 covers the second electrode layer 113.

[0104] In the disclosed embodiment, the specific steps for forming a deep trench array in the interposer 10 include forming a patterned deep trench mask layer 20 on the interposer 10 (as shown in FIG. 7 ), etching the interposer 10 based on the patterned deep trench mask layer 20 to form a plurality of deep trenches T0 (as shown in FIG. 8 ), thereby forming a deep trench array. Here, the deep trenches T0 have a relatively high aspect ratio. For example, the aspect ratio of the deep trenches T0 can be 10, 15, or 20.

[0105] In the disclosed embodiment, referring to FIG9 , the insulating layer 15 can be made of at least one of silicon oxide, silicon nitride, and silicon oxynitride. Specifically, the insulating layer 15 is made of silicon oxide. Here, the insulating layer 15 formed by depositing the insulating material can provide electrical isolation between the interposer 10 and the subsequently formed deep trench capacitor.

[0106] In the embodiment of the present disclosure, referring to FIG10 , the materials of the first electrode layer 111, the second electrode layer 113, and the conductive layer 114 can be at least one of conductive materials such as doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, etc. Specifically, the materials of the first electrode layer 111 and the second electrode layer 113 are titanium nitride, and the material of the conductive layer 114 is polysilicon. The material of the capacitor dielectric layer 112 can be at least one of insulating materials such as aluminum oxide (Al2O3) and zirconium oxide (ZrO). The capacitor dielectric layer 112 can also include other insulating materials with a higher dielectric constant (high-k), such as a material with a dielectric constant greater than 3.9.

[0107] In the embodiment of the present disclosure, the insulating layer 15, the first electrode layer 111, the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 can be deposited by one or more processes including chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0108] In some embodiments of the present disclosure, referring to FIG10 , after forming an initial deep trench capacitor array structure 23 in the interposer 10 , the method further includes: depositing a dielectric material on the conductive layer 114 , the dielectric material covering the conductive layer 114 in the deep trench T0 and completely filling the deep trench T0 to form a dielectric material layer 16 .

[0109] Here, the dielectric material layer 16 can completely fill the deep trench T0 , which can improve the situation in the related art where polysilicon is used to fill the deep trench, which easily leads to incomplete filling of the deep trench and the presence of gaps.

[0110] In the embodiment of the present disclosure, the material of the dielectric material layer 16 can be at least one of silicon oxide, silicon nitride, and silicon oxynitride. Specifically, the material of the dielectric material layer 16 is silicon oxide.

[0111] Next, step S103 is performed: performing a first etching on the initial deep trench capacitor array structure 23 to expose the first electrode layer 111 at the periphery of the initial deep trench capacitor structure 230 at the outermost side of the initial deep trench capacitor array structure 23 to form an intermediate deep trench capacitor array structure 24 .

[0112] In some embodiments of the present disclosure, referring to FIG11 and FIG12 , a first etching is performed on the initial deep trench capacitor array structure 23, including:

[0113] forming a patterned first mask layer 21 on the initial deep trench capacitor array structure 23;

[0114] The initial deep trench capacitor array structure 23 is first etched using the patterned first mask layer 21. A first trench T2 is formed around the initial deep trench capacitor structure 230 at the outermost edge of the initial deep trench capacitor array structure 23. The first trench T2 exposes the first electrode layer 111. The remaining initial deep trench capacitor array structure 23 serves as the intermediate deep trench capacitor array structure 24. Exposing a portion of the first electrode layer 111 through the first trench T2 facilitates electrical connection with the subsequently formed conductive plug.

[0115] It should be noted that the periphery of the initial deep trench capacitor structure 230 on the outermost side of the initial deep trench capacitor array structure 23 refers to the side of the initial deep trench capacitor structure 230 away from the initial deep trench capacitor array structure 23 and the area where the initial deep trench capacitor structure 230 is located on the upper part of the intermediate layer 10.

[0116] In the disclosed embodiment, the initial deep trench capacitor array structure 23 may be etched by plasma etching, or other dry etching processes such as reactive ion etching, sputtering etching, magnetic field enhanced reactive ion etching, reactive ion beam etching, or high density plasma etching.

[0117] In the embodiment of the present disclosure, referring to FIG. 12 , the initial deep trench capacitor array structure 23 is first etched through the patterned first mask layer 21 to obtain a first etched region 121 . The first trench T2 is located in the first etched region 121 .

[0118] Next, step S104 is executed: the middle deep trench capacitor array structure 24 is etched for the second time, and the side of the exposed first electrode layer 111 away from the initial deep trench capacitor structure 230 on the outermost side is etched to form an isolation trench T1, and the adjacent capacitor units in the middle deep trench capacitor array structure 24 are cut off to form a deep trench capacitor array 11, and the isolation trench T1 is located in the intermediate layer 10 between the deep trench capacitor arrays 11.

[0119] In some embodiments of the present disclosure, referring to FIG13 and FIG14 , a second etching is performed on the middle deep trench capacitor array structure 24 , including:

[0120] forming a patterned second mask layer 22 on the middle deep trench capacitor array structure 24;

[0121] According to the patterned second mask layer 22, the middle deep trench capacitor array structure 24 is etched for the second time to form an isolation trench T1 on the side of the first trench T2 away from the initial deep trench capacitor structure 230 on the outermost side; and adjacent capacitor units in the middle deep trench capacitor array structure 24 are cut off to expose part of the insulating layer 15; the isolation trench T1 extends into the interposer 10; and the remaining middle deep trench capacitor array structure 24 serves as the deep trench capacitor array 11.

[0122] It should be noted that the second etching is performed on the middle deep trench capacitor array structure 24 to cut off adjacent capacitor units in the middle deep trench capacitor array structure 24, thereby forming a deep trench capacitor array 11 including multiple deep trench capacitors 110. In some other embodiments, the second etching can also be used to cut off the connection between the deep trench capacitor array 11 and other devices, which is not specifically limited here.

[0123] In the disclosed embodiment, referring to FIG13 , the patterned second mask layer 22 partially covers the first trench T2. That is, the opening of the first photomask used to form the patterned first mask layer 21 partially overlaps with the opening of the second photomask used to form the patterned second mask layer 22. Consequently, the second etched region 122 obtained by the second etching partially overlaps with the first etched region 121, forming an etched overlap region 120. Referring to FIG14 , the isolation trench T1 is located in the etched overlap region 120.

[0124] In the embodiment of the present disclosure, the aspect ratio of the isolation trench T1 is 2-10, inclusive. For example, the aspect ratio of the isolation trench T1 can be 2, 5, 7, or 10.

[0125] Figures 16 to 24 are schematic diagrams of the semiconductor structure during the manufacturing process provided by the related art. As can be seen from the figures, in the related art, the preparation steps of the deep trench capacitor array 11 are as follows:

[0126] First, an initial capacitor structure 27 is formed on the interposer 10 (as shown in Figures 16 to 19); then, a second mask is used to form a patterned third mask layer 25 on the initial capacitor structure 27, and the initial capacitor structure 27 is etched to form an intermediate capacitor structure 28 (as shown in Figures 20 and 21); then, a first mask is used to form a patterned fourth mask layer 26 on the intermediate capacitor structure 28, and the intermediate capacitor structure 28 is etched to expose a portion of the first electrode layer 111 located on the upper surface of the interposer 10 to form a deep trench capacitor array (as shown in Figures 22 and 23); finally, a protective layer 29 is formed on the deep trench capacitor array 11 (as shown in Figure 24).

[0127] Here, the two photomasks used in the preparation of the deep trench capacitor array 11 in the present disclosure are the same as the two photomasks used in the preparation of the deep trench capacitor 110 in the related art. However, by adjusting the opening positions of the first photomask and the second photomask so that the openings of the first photomask and the second photomask partially overlap, the present disclosure can use the original two photomasks required for preparing the deep trench capacitor array 11 to etch the isolation trench T1 while preparing the deep trench capacitor array 11, which is used to subsequently form the first isolation structure 13. In this way, trench isolation (trench isolation) of the deep trench capacitor array 11 can be established without adding additional processes.

[0128] It can be understood that by partially overlapping the first and second photomasks required for fabricating the deep trench capacitor array 11 in the related art, the deep trench capacitor array 11 and the subsequent first isolation structure 13 can be fabricated using the same two photomasks. This process of fabricating the first isolation structure 13 does not require the use of new photomasks or the addition of new process steps, thus simplifying the process steps, saving production costs, and improving production efficiency.

[0129] Furthermore, in the related art, when the initial capacitor structure 27 is etched twice, the electrodes in the capacitor structure are first cut off, and then the first electrode layer 111 required for connection to the conductive plug is exposed. The openings of the photomasks used in the two etching processes do not overlap, that is, the two etching processes do not overlap, and the electrode cutting process is completed in a single etching process.

[0130] In the double etching process of the present disclosure, a portion of the first electrode layer 111 is exposed by the first etching (as shown in FIG12 ); then, during the second etching, the exposed portion of the first electrode layer 111 is cut off (as shown in FIG14 ). In this way, the first electrode layer 111 can be cut off using a two-step etching process, which can reduce the difficulty of the electrode cutting process.

[0131] In the disclosed embodiment, referring to FIG2 , the projections of the multiple deep trench capacitors 110 along the vertical direction z onto the upper surface of the interposer 10 are arranged in a regular hexagonal pattern. In other words, the deep trench capacitors 110 are arranged in a hexagonal closest-packed structure. This results in a densely packed deep trench capacitor array 11 , which in turn increases the capacitance of the deep trench capacitor array 11 .

[0132] In the embodiment of the present disclosure, referring to FIG14 , for a deep trench capacitor array 11, on the side away from the isolation trench T1, the ends of the first electrode layer 111, the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 of the deep trench capacitor 110 on the outermost side located on the upper surface of the intermediary layer 10 completely overlap; on the side close to the isolation trench T1, the deep trench capacitor 110 on the outermost side exposes a portion of the first electrode layer 111, and the ends of the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 of the deep trench capacitor 110 on the outermost side located on the upper surface of the intermediary layer 10 completely overlap, and the remaining portion of the first electrode layer 111 located on the upper surface of the intermediary layer 10 is covered by the capacitor dielectric layer 112.

[0133] It can be understood that by setting the ends of the first electrode layer 111, the capacitor dielectric layer 112, the conductive layer 114 and the second electrode layer 113 located on the interposer 10 in the deep trench capacitor 110 to completely overlap or partially overlap, the uniformity of the electrode lead-out in the deep trench capacitor 110 can be improved, thereby reducing the parasitic resistance and improving the performance of the deep trench capacitor 110.

[0134] Finally, step S105 is performed: filling the isolation trench T1 with an isolation material to form an isolation structure 12 ; the isolation structure 12 at least partially surrounds the deep trench capacitor 110 at the outermost side of the deep trench capacitor array 11 .

[0135] In some embodiments of the present disclosure, referring to FIG. 15 , an isolation material is filled in the isolation trench T1 to form an isolation structure 12 , including:

[0136] An isolation material is deposited on the interposer 10 on which the deep trench capacitor array 11 is formed, wherein part of the isolation material fills the isolation trench T1 to form a first isolation structure 13; part of the isolation material covers the deep trench capacitor array 11, the first isolation structure 13 and the exposed insulating layer 15 to form a second isolation structure 14. The first isolation structure 13 and the second isolation structure 14 constitute an isolation structure 12.

[0137] It can be understood that by depositing the isolation material on the interposer 10 and forming the first isolation structure 13 and the second isolation structure 14 at the same time, it is beneficial to simplify the process and reduce the difficulty of preparation and production cost.

[0138] In the disclosed embodiment, the isolation structure 12 may partially surround the deep trench capacitors 110 at the outermost side of the deep trench capacitor array 11 , or may completely surround the deep trench capacitors 110 at the outermost side of the deep trench capacitor array 11 .

[0139] In the embodiment of the present disclosure, referring to FIG. 15 , in a cross section perpendicular to the first direction x, the cross-sectional shape of the first isolation structure 13 can be rectangular, trapezoidal, inverted trapezoidal, or elliptical, without specific limitation herein.

[0140] In the embodiment of the present disclosure, referring to FIG15 , the materials of the first isolation structure 13 and the second isolation structure 14 may include oxide, nitride, or oxynitride, etc. Specifically, the material of the first isolation structure 13 and the second isolation structure 14 is silicon oxide.

[0141] It should be noted that, in some other embodiments, the first isolation structure 13 and the second isolation structure 14 may also be formed through two deposition processes, and the materials of the first isolation structure 13 and the second isolation structure 14 may be prepared by selecting different materials according to actual needs.

[0142] It should be noted that the semiconductor structure and its manufacturing method provided in the embodiments of the present disclosure can be applied to DRAM structures or other semiconductor devices, and are not further limited herein. The embodiments of the semiconductor structure and the embodiments of the semiconductor structure manufacturing method provided in the present disclosure are based on the same concept; the technical features of the technical solutions described in the various embodiments can be arbitrarily combined unless they conflict.

[0143] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure comprising: An intermediary layer (10), the intermediary layer (10) comprising a deep trench capacitor array (11) and an isolation structure (12); wherein: The deep trench capacitor array (11) comprises a plurality of deep trench capacitors (110), and the isolation structure (12) at least partially surrounds the deep trench capacitors (110) at the outermost side of the deep trench capacitor array (11).

2. The semiconductor structure according to claim 1, wherein: The deep trench capacitor (110) comprises: a first electrode layer (111), a capacitor dielectric layer (112), a second electrode layer (113) and a conductive layer (114); wherein: The first electrode layer (111) covers the inner wall of the deep groove (T0) in the intermediate layer (10) and extends to the upper surface of the intermediate layer (10); the capacitor dielectric layer (112) covers the first electrode layer (111); the second electrode layer (113) covers the capacitor dielectric layer (112); and the conductive layer (114) covers the second electrode layer (113).

3. The semiconductor structure according to claim 2, wherein: The isolation structure (12) comprises a first isolation structure (13), an isolation trench (T1) is provided in the intermediary layer (10), and the first isolation structure (13) is located in the isolation trench (T1); for a deep trench capacitor array (11), On the side away from the first isolation (13), the ends of the first electrode layer (111), the capacitor dielectric layer (112), the second electrode layer (113) and the conductive layer (114) of the deep trench capacitor (110) at the outermost edge, which are located on the upper surface of the intermediate layer (10), completely overlap; On a side close to the first isolation structure (13), the deep trench capacitor (110) at the outermost edge exposes a portion of the first electrode layer (111), and ends of the capacitor dielectric layer (112), the second electrode layer (113) and the conductive layer (114) of the deep trench capacitor (110) at the outermost edge located on the upper surface of the intermediate layer (10) completely overlap, and the remaining portion of the first electrode layer (111) located on the upper surface of the intermediate layer (10) is covered by the capacitor dielectric layer (112).

4. The semiconductor structure according to claim 3, wherein: The semiconductor structure also includes a dielectric material layer (16), wherein the dielectric material layer (16) covers the conductive layer (114) located in the deep trench (T0) and completely fills the deep trench (T0).

5. The semiconductor structure according to claim 3 or 4, wherein: The semiconductor structure further comprises an insulating layer (15), wherein the insulating layer (15) is located between the deep trench capacitor array (11) and the intermediate layer (10), and is exposed on the intermediate layer (10) on a side of the deep trench capacitor (110) at the outermost side away from the first isolation structure (13).

6. The semiconductor structure according to claim 5, wherein: The isolation structure (12) further comprises a second isolation structure (14), wherein the second isolation structure (14) covers the deep trench capacitor array (11), the first isolation structure (13) and the exposed insulating layer (15).

7. The semiconductor structure according to any one of claims 3 to 6, wherein: In a cross section perpendicular to a first direction, the cross section of the first isolation structure (13) is in the shape of a rectangle, a trapezoid, an inverted trapezoid or an ellipse; the first direction is perpendicular to the vertical direction.

8. The semiconductor structure according to any one of claims 3 to 7, wherein: The depth-to-width ratio of the isolation trench (T1) is 2-10.

9. The semiconductor structure according to any one of claims 1 to 8, wherein: The projections of the plurality of deep trench capacitors (110) on the upper surface of the intermediate layer (10) in the vertical direction are arranged in a regular hexagonal shape.

10. A method for manufacturing a semiconductor structure, comprising: Providing an intermediary layer (10); forming an initial deep trench capacitor array structure (23) in the interposer (10), wherein the initial deep trench capacitor array structure (23) comprises a plurality of initial deep trench capacitor structures (230); Performing a first etching on the initial deep trench capacitor array structure (23), exposing a first electrode layer (111) at the periphery of the initial deep trench capacitor structure (230) at the outermost side of the initial deep trench capacitor array structure (23), and forming an intermediate deep trench capacitor array structure (24); The middle deep trench capacitor array structure (24) is etched for a second time, a side of the exposed first electrode layer (111) away from the initial deep trench capacitor structure (230) at the outermost side is etched to form an isolation trench (T1), and adjacent capacitor units in the middle deep trench capacitor array structure (24) are cut off to form a deep trench capacitor array (11); An isolation material is filled in the isolation trench (T1) to form an isolation structure (12); the isolation structure (12) at least partially surrounds the deep trench capacitor (110) at the outermost side of the deep trench capacitor array (11).

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: An initial deep trench capacitor array structure (23) is formed in the interposer (10), comprising: forming a deep trench array in the interposer (10), the deep trench array comprising a plurality of deep trenches (T0); Depositing insulating material on the upper surface of the intermediary layer (10) and in the deep trench (T0) to form an insulating layer (15), wherein the insulating layer (15) covers the inner wall of the deep trench (T0) and extends to the upper surface of the intermediary layer (10); The first electrode layer (111), the capacitor dielectric layer (112), the second electrode layer (113) and the conductive layer (114) are sequentially deposited on the insulating layer (15) to form the initial deep trench capacitor array structure (23); wherein the first electrode layer (111) covers the insulating layer (15); the capacitor dielectric layer (112) covers the first electrode layer (111); the second electrode layer (113) covers the capacitor dielectric layer (112); and the conductive layer (114) covers the second electrode layer (113).

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: After forming an initial deep trench capacitor array structure (23) in the interposer (10), the method comprises: A dielectric material is deposited on the conductive layer (114), the dielectric material covers the conductive layer (114) in the deep trench (T0) and completely fills the deep trench (T0), thereby forming a dielectric material layer (16).

13. The method for manufacturing a semiconductor structure according to claim 11 or 12, wherein: The initial deep trench capacitor array structure (23) is subjected to a first etching, comprising: forming a patterned first mask layer (21) on the initial deep trench capacitor array structure (23); According to the patterned first mask layer (21), the initial deep trench capacitor array structure (23) is etched for the first time, and a first trench (T2) is formed on the periphery of the initial deep trench capacitor structure (230) at the outermost side of the initial deep trench capacitor array structure (23), wherein the first trench (T2) exposes the first electrode layer (111); and the remaining initial deep trench capacitor array structure (23) serves as the intermediate deep trench capacitor array structure (24).

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: Performing a second etching on the middle deep trench capacitor array structure (24), comprising: forming a patterned second mask layer (22) on the middle deep trench capacitor array structure (24); According to the patterned second mask layer (22), the intermediate deep trench capacitor array structure (24) is etched for a second time to form the isolation trench (T1) on a side of the first trench (T2) away from the initial deep trench capacitor structure (230) at the outermost side; and adjacent capacitor units in the intermediate deep trench capacitor array structure (24) are cut off to expose a portion of the insulating layer (15); the isolation trench (T1) extends into the intermediate layer (10); and the remaining intermediate deep trench capacitor array structure (24) serves as the deep trench capacitor array (11).

15. The method for manufacturing a semiconductor structure according to claim 14, wherein: Filling the isolation trench (T1) with an isolation material to form an isolation structure (12), comprising: An isolation material is deposited on an intermediate layer (10) formed with the deep trench capacitor array (11), wherein part of the isolation material fills the isolation trench (T1) to form a first isolation structure (13); part of the isolation material covers the deep trench capacitor array (11), the first isolation structure (13) and the exposed insulating layer (15) to form a second isolation structure (14), and the first isolation structure (13) and the second isolation structure (14) constitute the isolation structure (12).

Images