Data processing method and apparatus, and electronic device and storage medium

Abstract

Provided in the present disclosure are a data processing method and apparatus, and an electronic device and a storage medium. The data processing method provided in the present disclosure comprises: receiving a first request message from a first device, wherein the first request message comprises a first address which is aligned according to a first data length, and a first size in units of the first data length; converting the first address into a second address which is aligned according to a second data length, wherein the second data length is greater than the first data length; converting the first size into a second size in units of the second data length; and sending a second request message to a second device, wherein the second request message comprises the second address and the second size. In the data processing method, format conversion is performed on a processing request, such that the processing request can be easily switched between different types of hardware, thereby improving the overall processing efficiency.

Description

Data processing method and device, electronic device, and storage medium

[0001] This application claims priority to Chinese Patent Application No. 202310898226.7 filed on July 20, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a data processing method, a data processing device, an electronic device, and a storage medium. Background Art

[0003] For different operators such as convolutional neural networks (CNNs) and matrix multiplication (Matrix Multiplication), various computing devices, coprocessors, accelerators, etc. have different implementation methods. Different hardware has different granularity for reading and writing data, which may cause gaps within or between data. For example, some computing devices can read and write data byte by byte, and the data can be arranged tightly. However, for some external accelerators (such as open source neural network accelerators), the starting address of each row of data must be aligned according to a specific data length (for example, 32 bytes), which may cause gaps between each row of data. These different data format requirements make it difficult to switch computing tasks between different hardware.

[0004] Summary of the Invention

[0005] This summary is provided to briefly introduce concepts that will be described in detail in the detailed description below. This summary is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0006] At least one embodiment of the present disclosure provides a data processing method, including: receiving a first request message from a first device, wherein the first request message includes a first address aligned according to a first data length and a first size in units of the first data length; converting the first address into a second address aligned according to a second data length, wherein the second data length is greater than the first data length; converting the first size into a second size in units of the second data length; and sending a second request message to a second device, wherein the second request message includes the second address and the second size.

[0007] At least one embodiment of the present disclosure provides a data processing device, including: a first interface for receiving a first request message from a first device, wherein the first request message includes a first address aligned according to a first data length and a first size in units of the first data length; a first conversion module for converting the first address into a second address aligned according to a second data length, wherein the second data length is greater than the first data length; a second conversion module for converting the first size into a second size in units of the second data length; and a second interface for sending a second request message to a second device, wherein the second request message includes the second address and the second size.

[0008] At least one embodiment of the present disclosure provides a data processing device, comprising: at least one processor; and a storage device on which at least one program is stored, and when the at least one program is executed by the at least one processor, the at least one processor implements any data processing method according to the embodiments of the present disclosure.

[0009] At least one embodiment of the present disclosure provides an electronic device, including any data processing device according to the embodiments of the present disclosure.

[0010] At least one embodiment of the present disclosure provides a non-transitory storage medium containing computer-executable instructions, wherein the computer-executable instructions, when executed by a computer processor, are used to perform any data processing method according to the embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the originals and elements are not necessarily drawn to scale.

[0012] FIG1 shows a schematic diagram of the architecture of a non-aligned direct memory access translator (UDMAC) according to at least one embodiment of the present disclosure;

[0013] FIG2 shows a flowchart of an example data processing method according to at least one embodiment of the present disclosure;

[0014] FIG3 shows a schematic diagram of an exemplary processing flow of an exemplary data processing method according to at least one embodiment of the present disclosure;

[0015] FIG4 shows another exemplary processing flow diagram of an exemplary data processing method according to at least one embodiment of the present disclosure;

[0016] FIG5 shows a schematic diagram of a data processing device according to at least one embodiment of the present disclosure;

[0017] FIG6 shows a schematic diagram of another data processing device according to at least one embodiment of the present disclosure; and

[0018] FIG. 7 shows a schematic diagram of an example structure of an electronic device suitable for implementing at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0020] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0021] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0022] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0023] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0024] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0025] As mentioned above, the interfaces of some neural network accelerators (e.g., Deep Learning Accelerator (DLA)) require that the processed address (addr) and size (size) must be an integer multiple of a specific data length (e.g., 32 bytes), and that the starting address of each row of data must be aligned according to the specific data length. Therefore, it is impossible to directly read tightly arranged data (e.g., aligned per byte) processed by some specific computing devices.

[0026] Embodiments of the present disclosure provide an Unaligned Direct Memory Access (DLA) translator (UDMAC) to support the conversion of aligned and unaligned data. The UDMAC can convert unaligned read and write requests into an aligned format, enabling support for operations, commands, or requests (e.g., read and write requests) in an unaligned format, allowing the DLA to directly read tightly packed data in memory.

[0027] In this document, "aligned data" may also refer to data whose address and size are aligned according to a second data length. In some embodiments, the second data length may be 2N bytes greater than the first data length, where N is an integer greater than or equal to 1. For example, the second data length may be 32 bytes, 64 bytes, etc. Correspondingly, data whose address and size are not aligned according to the second data length is "unaligned data." For example, data whose address and size are aligned according to a first data length less than the second data length may be referred to as "unaligned data." In some embodiments, the first data length may be 2X bytes, where X is an integer greater than or equal to 0. For example, the first data length may be 1 byte, 2 bytes, etc. In the following, an example description is given using the first data length of 1 byte and the second data length of 32 bytes. In addition, "byte" is used as the basic unit of data for example description herein. However, in some embodiments, other data units such as "bit" or "nibble" may also be used for description, without limitation herein.

[0028] Next, FIG1 shows a schematic diagram of the architecture of a unaligned direct memory access translator (UDMAC) according to at least one embodiment of the present disclosure.

[0029] As shown in Figure 1, according to at least one embodiment of the present disclosure, UDMAC 102 can be located between the first device 101 and the second device 103, and can be communicatively connected to the first device 101 and the second device 103 respectively. For example, the communication connection can be based on a certain bus protocol and the bus width (for example, 16 bytes, 32 bytes, etc.) can be selected as needed. The bus can be an intra-chip bus (for example, AXI) or an inter-chip bus (for example, PCIE), and the embodiments of the present disclosure are not limited to this.

[0030] The first device 101 may be a computing device that arranges and processes data according to a first data length (e.g., 1 byte). The embodiments of the present disclosure are not limited to this. For example, the computing device may be a processor based on any instruction set (e.g., X86, RISC-V, or ARM instruction set), and may be a single-core or multi-core processor. For example, in some embodiments, the first device 101 may further refer to an interface device of the computing device that arranges and processes data according to the first data length, such as a DMA interface device of the computing device. The UDMAC 102 may receive a first request message 104 aligned according to the first data length from the first device 101.

[0031] The first request message 104 may be or include one or more of a first write request message (or write command), a first read request message (or read command), etc. It should be understood that in other implementations, the first request message may also be any other request such as a data transmission request.

[0032] The second device 103 may be a device that arranges and processes data according to the second data length (e.g., 32 bytes). The embodiments of the present disclosure are not limited to this. For example, the second device is provided in the form of a coprocessor. For example, in some embodiments, the second device 103 may further refer to an interface device of a device that arranges and processes data according to the second data length, such as a data bus interface device of the device, such as an AXI interface or ACE interface of a DLA.

[0033] UDMAC 102 can convert the first request message 104 corresponding to the first data length received from the first device 101 to generate a second request message 105 corresponding to the second data length, thereby sending the second request message 105 corresponding to the second data length to the second device 103 for subsequent processing by the second device 103.

[0034] The data processing method of the UDMAC 102 according to at least one embodiment of the present disclosure will be described in detail below with reference to FIG. 2 to FIG. 4 .

[0035] Figure 2 shows a flow chart of an exemplary data processing method according to at least one embodiment of the present disclosure. Figure 3 shows a schematic diagram of an exemplary processing flow of an exemplary data processing method according to at least one embodiment of the present disclosure. Figure 4 shows another schematic diagram of an exemplary processing flow of an exemplary data processing method according to at least one embodiment of the present disclosure.

[0036] As shown in FIG2 , an exemplary data processing method 200 according to an embodiment of the present disclosure may include the following steps:

[0037] Step S201: receiving a first request message from a first device, wherein the first request message may include a first address aligned according to a first data length and a first size in units of the first data length;

[0038] Step S202: converting the first address into a second address aligned according to a second data length, wherein the second data length may be greater than the first data length;

[0039] Step S203: converting the first size into a second size in units of a second data length; and

[0040] Step S204: Send a second request message to the second device, where the second request message includes a second address and a second size.

[0041] For example, in one example, in step S201 , the data processing method 200 may include receiving a first request message 104 from a first device.

[0042] In some embodiments, the first request message 104 may be a first write request message or a first read request message. As described above, in some embodiments, the first device may be a computing device or an interface device thereof that arranges and processes data according to a first data length. Therefore, the first request message 104 may include a first address addr_u_start aligned according to the first data length and a first size size_u in units of the first data length. If the first request message 104 is a first write request message, the first request message 104 may also include first write data data_u in units of the first data length. The processing of the first address addr_u_start, the first size size_u, and / or the first write data data_u by the UDMAC 102 will be described in detail below in conjunction with specific embodiments.

[0043] FIG3 provides an exemplary description by taking the first request message 104 as a first write request message as an example.

[0044] As shown in 310 in Figure 3, the first address addr_u_start aligned according to the first data length (i.e., 1 byte) can be any address within the memory range, and the first size size_u in units of the first data length can be any size in units of bytes. In Figure 3, it is assumed that the first address addr_u_start included in the first request message 104 is 0x10052 and the first size size_u is 0x0005f (i.e., 95 bytes).

[0045] Continuing as shown in 310, the first write data data_u may be the shaded portion from the first address addr_u_start (0x10052) to the first end address addr_u_end (0x100b0). Here, the first end address addr_u_end may be determined by the first address addr_u_start and the first size size_u. For example, the first end address addr_u_end may be determined according to the following equation (1): addr_u_end=addr_u_start+size_u-1 (1)

[0046] For example, in this example, in step S202 , the data processing method 200 may include converting the first address addr_u_start into a second address addr_a_start aligned according to the second data length.

[0047] As described above, the second data length may be 2N bytes greater than the first data length, where N is an integer greater than or equal to 1. In FIG3 , it is assumed that the first data length is 1 byte and the second data length is 32 bytes.

[0048] In some embodiments, converting the first address addr_u_start to the second address addr_a_start aligned with the second data length may include setting the low bits of the first address addr_u_start corresponding to the low bits of the value 0 in the binary representation of the second data length to 0, thereby obtaining the second address addr_a_start. For example, taking the second data length as 32 bytes, its corresponding binary representation is 0010 0000, where the low bits of the value 0 are the lowest 5 bits. Therefore, the lowest 5 bits of the first address 0x10052 (i.e., 0001 0000 0000 0101 0010) may be set to 0, thereby obtaining the second address addr_a_start = 0x10040 (i.e., 0001 0000 0000 0100 0000). It can be seen that the second address 0x10040 after conversion is an integer multiple of 32 bytes, that is, it is aligned with the second data length 32 bytes.

[0049] 320 in FIG3 shows four consecutive "32-byte" data units starting from the second address 0x10040. By setting the low bit of the first address addr_u_start corresponding to the low bit of the value 0 in the binary representation of the second data length to 0, the second address addr_a_start aligned with the second data length can be easily and efficiently determined.

[0050] For example, in one example, in step S203 , the data processing method 200 may include converting the first size size_u into a second size size_a in units of the second data length.

[0051] In some embodiments, the quotient of the first size size_u=0x0005f (ie, 95 bytes) and the second data length 32 bytes may be rounded up to obtain an intermediate size size_m in units of 32 bytes. For example, in the above example, in is a round-up function. In some embodiments, the first boundary address addr_bound1 may be determined based on the second address addr_a_start=0x10040 and the intermediate size size_m=3 obtained in step S202. For example, the first boundary address addr_bound1 may be determined by the following equation (2): addr_bound1=addr_a_start+0x00020*size_m-1 (2)

[0052] Here, "0x00020" is the hexadecimal representation of the second data length 32. In the above example, the first boundary address addr_bound1=0x1009f, ie, the end address of the third "32-byte" data unit in 320, can be calculated by equation (2).

[0053] In some embodiments, as described above, the first end address addr_u_end can be determined based on the first address addr_u_start and the first size size_u by using equation (1). In the above example, the first end address addr_u_end=0x100b0 can be calculated by equation (1).

[0054] In some embodiments, the required second size size_a can be determined based on a comparison of the first end address addr_u_end=0x100b0 and the first boundary address addr_bound1=0x1009f, and the intermediate size size_m=3. In some embodiments, when the first end address addr_u_end is greater than the first boundary address addr_bound1, the value of the intermediate size size_m+1 can be determined as the second size size_a. 320 in FIG. 3 illustrates this situation. In the example shown in 320 in FIG. 3 , since the data start address in the request message is converted from the first address 0x10052 to the second address 0x10040 aligned according to the second data length, it is essentially equivalent to shifting the valid data corresponding to the first write data data_u backward from the second address 0x10040. Therefore, if the end address 0x100b0 of the valid data corresponding to the first write data data_u after shifting exceeds the first boundary address addr_bound1=0x1009f calculated based on the second address 0x10040 and the intermediate size size_m=3, that is, the valid data after shifting exceeds the third "32-byte" data unit and falls into the fourth "32-byte" data unit, the value of the intermediate size size_m+1 should be determined as the second size size_a, that is, size_a=4 (that is, 0x00004).

[0055] However, in some other embodiments, for example, when the first end address addr_u_end is less than or equal to the first boundary address addr_bound1, the value of the intermediate size size_m can be directly determined as the second size size_a. For example, in another example, assuming that the first address addr_u_start' is still 0x10052, but the first size size_u'=0x0004a (i.e., 74 bytes). In this case, the second address addr_a_start'=0x10040 and the intermediate size can be calculated according to the method described above. The first boundary address addr_bound1'=0x1009f, and the first end address addr_u_end'=0x1009b. In this case, since the data start address in the request message is converted from the first address 0x10052 to the second address 0x10040 aligned according to the second data length, it is actually equivalent to shifting the valid data corresponding to the first write data data_u' backward from the second address 0x10040. However, since the end address 0x1009b of the valid data corresponding to the first write data data_u' after the shift does not exceed the first boundary address addr_bound1'=0x1009f calculated based on the second address 0x10040 and the intermediate size size_m'=3, that is, the end address of the valid data after the shift still falls within the third "32-byte" data unit. Therefore, the value of the intermediate size size_m' can be directly determined as the second size size_a', that is, size_a'=3 (i.e., 0x00003). In this way, the second size after conversion can be optimally determined so that the second size after conversion can be the minimum size that can contain the first size before conversion.

[0056] In the example shown in Figure 3, according to the method described above, the first address addr_u_start=0x10052 aligned with 1 byte is converted to the second address addr_a_start=0x10040 aligned with 32 bytes, and the first size size_u=0x0005f (i.e., 95 bytes) in units of 1 byte is converted to the second size size_a=4 (i.e., 0x00004) in units of 32 bytes, which corresponds to an integer multiple of 32 bytes, i.e., 128 bytes.

[0057] For example, in one example, in step S204, the data processing method 200 may further include sending a second request message 105 including a second address addr_a_start and a second size size_a to the second device 103, so that the second device 103 performs subsequent operations or processing. As described above, the second device 105 may be a device that arranges and processes data according to the second data length (e.g., 32 bytes) or an interface device thereof.

[0058] In some embodiments, as described above, when the first request message 104 is or includes a first write request message, the first request message 104 may further include first write data data_u in units of a first data length. In this case, the example data processing method 200 according to an embodiment of the present disclosure may further include converting the first write data data_u into second write data data_a in units of a second data length.

[0059] Still taking the example shown in FIG3 as an example, first, a first offset value offset1 = addr_u_start - addr_a_start = 0x00012 (i.e., 18) bytes between the first address addr_u_start = 0x10052 included in the first request message 104 and the converted second address addr_a_start = 0x10040 aligned to 32 bytes can be determined. After determining the value J of the first offset value offset1 (J is an integer, for example, 18 in this example), J bytes of "0" can be added before the first write data data_u. These J bytes of "0" can be considered invalid data.

[0060] Next, as described above, according to equation (1), the first end address addr_u_end=0x100b0 of the first write data data_u is calculated based on the first address addr_u_start=0x10052 and the first size size_u=0x0005f included in the first request message 104, and the second end address addr_a_end is determined based on the converted second address addr_a_start=0x10040 and the second size size_a=4 (i.e., 0x00004). For example, the second end address addr_a_end can be determined by the following equation (3): addr_a_end=addr_a_start+0x00020*size_a-1 (3)

[0061] Here, "0x00020" is the hexadecimal representation of the second data length 32. In the above example, the second end address addr_a_end=0x100bf, ie, the end address of the fourth "32-byte" data unit in 320, can be calculated by equation (3).

[0062] After determining the second end address addr_a_end, the second offset value offset2 = addr_a_end - addr_u_end = 0x0000f (i.e., 15) bytes between the first end address addr_u_end = 0x100b0 and the second end address addr_a_end = 0x100bf can be further determined. After determining the value M of the second offset value offset2 (M is an integer, for example, 15 in this example), M bytes of "0" can be added after the first write data data_u. The M bytes of "0" can be considered as invalid data. In other embodiments, "1" can also be added as invalid data, which is not limited herein.

[0063] Thus, by padding the first and last zeros of the first write data data_u having a first size of 0x0005f (i.e., 95 bytes) according to the above method, the second write data data_a having a second size of 0x00004 (i.e., 128 bytes) in units of 32 bytes can be obtained, which meets the processing format requirements of the second device 103, for example, as shown by the data corresponding to addresses 0x10040 to 0x100bf in 320 of FIG. 3. The second write data data_a can be further included in the second request message 105 to be sent to the second device 103 for subsequent operation or processing, such as a write operation.

[0064] As described above, since the second write data data_a is generated by padding the first and last portions of the first write data data_u with zeros, the first and last portions of the second write data data_a may contain a certain length of invalid data (such as the "invalid data" shown in 320). In some embodiments, an indication signal may be generated to indicate which data in the second write data data_a is valid data corresponding to the first write data data_u, and the indication signal may be included in the second request message 105 and sent to the second device 103. By sending this indication signal, the second device 103 can easily know which data in the received second write data data_a is valid data, thereby improving operational efficiency.

[0065] In some embodiments, the indication signal may include a first indication signal and a second indication signal. The first indication signal may be used to indicate which data in the first 32-byte data unit of the second write data data_a is valid data corresponding to the first write data data_u, and the second indication signal may be used to indicate which data in the last 32-byte data unit of the second write data data_a is valid data corresponding to the first write data data_u.

[0066] For example, still using the example shown in FIG3 , since the method described above has determined that 18 bytes of "0" are added before the first write data data_u to generate the second write data data_a, it can be determined that the first 18 bytes in the first 32-byte data unit are invalid data. Therefore, for example, a 32-bit first indication signal "0000 0000 0000 0000 0011 1111 1111 1111" can be generated to indicate which data in the first 32-byte data unit is valid data corresponding to the first write data data_u, wherein the upper 18 bits of the 32 bits are 0 to indicate "invalid", and the lower 14 bits are 1 to indicate "valid". In other embodiments, "1" can be used to indicate "invalid", and "0" can be used to indicate "valid". Similarly, since the method described above has determined that 15 bytes of "0" are added after the first write data data_u to generate the second write data data_a, it can be determined that in the last 32-byte data unit, the last 15 bytes are invalid data. Therefore, for example, a 32-bit second indication signal "1111 1111 1111 1111 1000 0000 0000 0000" can also be generated to indicate which data in the last 32-byte data unit is valid data corresponding to the first write data data_u, wherein the upper 17 bits of the 32 bits are 1 to indicate "valid", and the lower 15 bits are 0 to indicate "invalid".

[0067] Furthermore, since the intermediate data units between the first 32 bytes and the last 32 bytes of the second write data data_a are all valid data corresponding to the first write data data_u, there is no need to generate additional indication signals to indicate the validity of these data. In this way, by only generating and sending indication signals indicating the validity of the data in the first 32 bytes and the last 32 bytes of the second write data data_a, not only can the second device 103 be informed of which data in the second write data is valid data, but signaling overhead can also be saved, thereby improving processing efficiency.

[0068] As described above, Figure 3 shows an example case where the first request message 104 is a first write request message (or a first write command). Next, Figure 4 shows an example case where the first request message 104 is a first read request message (or a first read command).

[0069] The various methods described above for the write command scenario in conjunction with FIG3 can also be applied to the read command scenario. For example, as shown in FIG4 , in the case where the first request message 104 is a first read command, it is still assumed that the first address addr_u_start included in the first request message 104 is 0x10052 and the first size size_u is 0x0005f (i.e., 95 bytes). The converted second address addr_a_start = 0x10040 aligned with the second data length and the second size size_a = 4 (i.e., 0x00004) in units of the second data length can be determined according to the method described above. Therefore, based on the second address and second size, the UDMAC 102 can read data (which can be referred to as second read data) in units of 32 bytes from 0x10040 to 0x100bf (a size of four 32-byte data units, i.e., 128 bytes) from the second device 103. At the same time, for the read command, the UDMAC 102 may also store the first address addr_u_start and the first size size_u in the read command in a memory or cache (e.g., a command FIFO) for use in subsequent operations (e.g., when converting the read data). Since, according to the read command, only the first read data starting from the first address addr_u_start = 0x10052 and having the first size size_u = 0x0005f is to be read, the second read data read from the second device 103 may be converted based on the first address addr_u_start and the first size size_u to obtain the first read data.

[0070] In some embodiments, similar to the method described in conjunction with FIG3 , a third offset value offset3 = addr_u_start - addr_a_start = 0x00012 (i.e., 18) bytes between the first address addr_u_start = 0x10052 and the second address addr_a_start = 0x10040 can be determined. After determining the value K (K is an integer, e.g., 18 in this example) of the third offset value offset3, the first K bytes of data in the second read data can be removed or discarded.

[0071] Next, as described above, according to equation (1), the third end address addr_u_end=0x100b0 of the first read data can be calculated based on the first address addr_u_start=0x10052 and the first size size_u=0x0005f included in the first request message 104, and the fourth end address addr_a_end=0x100bf, that is, the end address of the 4th "32-byte" data unit in 420, can be determined based on the converted second address addr_a_start=0x10040 and the second size size_a=4 (i.e., 0x00004).

[0072] After determining the fourth end address addr_a_end, a fourth offset value offset4 = addr_a_end - addr_u_end = 0x0000f (i.e., 15) bytes between the third end address addr_u_end = 0x100b0 and the fourth end address addr_a_end = 0x100bf can be further determined. After determining the value L (L is an integer, e.g., 15 in this example) of the fourth offset value offset4, the last L bytes of data in the second read data can be removed or discarded, thereby obtaining the first read data from the second read data (as shown in 410). UDMAC 102 can send the converted first read data to first device 101, which arranges and processes the data according to the first data length (e.g., 1 byte), to complete the read operation.

[0073] Next, FIG5 shows a schematic diagram of a data processing device according to at least one embodiment of the present disclosure.

[0074] As shown in FIG5 , a data processing device 500 according to at least one embodiment of the present disclosure may include a first interface 501, a first conversion module 502, a second conversion module 503, and a second interface 504. In one embodiment, the data processing device 500 may be the UDMAC 102 described above in conjunction with FIG1 . In other embodiments, the data processing device 500 may be any other data processing device including the UDMAC 102 described above in conjunction with FIG1 .

[0075] The first interface 501 may be configured to receive a first request message from the first device 101. In some embodiments, the first request message may include a first address aligned according to a first data length and a first size in units of the first data length.

[0076] The first conversion module 502 may be configured to convert the first address into a second address aligned according to a second data length. In some embodiments, the second data length may be 2N bytes longer than the first data length, where N is an integer greater than or equal to 1.

[0077] The second conversion module 503 may be configured to convert the first size into a second size in units of a second data length.

[0078] The second interface 504 may be configured to send a second request message to the second device 103 , where the second request message may include a second address and a second size.

[0079] For example, the first conversion module 502 and the second conversion module 503 may be implemented by software, hardware, firmware, or any combination thereof; for example, the first conversion module 502 and the second conversion module 503 may be implemented by converters or conversion circuits, respectively.

[0080] For example, the first interface 501 may be a bus interface (e.g., an AXI interface, an ACE interface, etc.) that interfaces or communicates with a computing device that arranges and processes data according to a first data length (e.g., 1 byte) or an interface device of the computing device (e.g., a DMA interface device); the second interface 504 may be a bus interface (e.g., an AXI interface, an ACE interface, etc.) that arranges and processes data according to a second data length (e.g., 32 bytes) or an interface device thereof. For example, the first interface 501 and the second interface 504 may be implemented by software, hardware, firmware, or any combination thereof; for example, the first interface 501 and the second interface 504 may be implemented by bus interface circuits, respectively.

[0081] In some embodiments, converting the first address to a second address aligned according to the second data length may include setting a low bit in the first address corresponding to a low bit of value 0 in a binary representation of the second data length to 0 to obtain the second address.

[0082] In some embodiments, converting the first size to a second size in units of a second data length may include: rounding up the quotient of the first size and the second data length to obtain an intermediate size in units of the second data length; determining a first boundary address based on the second address and the intermediate size; determining a first end address based on the first address and the first size; and determining the second size based on a comparison of the first end address and the first boundary address and the intermediate size.

[0083] In some embodiments, determining the second size based on a comparison of the first end address and the first boundary address and the intermediate size may include: determining the intermediate size as the second size when the first end address is less than or equal to the first boundary address; and determining the second size by adding 1 to the intermediate size when the first end address is greater than the first boundary address.

[0084] In some embodiments, the first request message may include a first write request message, the first write request message may also include first write data in units of a first data length, and the data processing device 500 may also include: a third conversion module for converting the first write data into second write data in units of a second data length; and a first processing module for including the second write data in the second request message.

[0085] In some embodiments, converting the first write data into second write data in units of the second data length may also include: determining a first offset value between the first address and the second address; adding J zeros corresponding to the first data length before the first write data, where J is an integer the same as the first offset value; determining a first end address based on the first address and the first size; determining a second end address based on the second address and the second size; determining a second offset value between the first end address and the second end address; and adding M zeros corresponding to the first data length after the first write data to generate the second write data, where M is an integer the same as the second offset value.

[0086] In some embodiments, the data processing device 500 may further include: a first generating module for generating an indication signal for indicating which data in the second write data is valid data corresponding to the first write data; and a second processing module for including the indication signal in the second request message.

[0087] In some embodiments, the indication signal may include a first indication signal and a second indication signal, wherein the first indication signal may be used to indicate which data of the first second data length in the second write data is valid data corresponding to the first write data; and wherein the second indication signal is used to indicate which data of the last second data length in the second write data is valid data corresponding to the first write data.

[0088] In some embodiments, the first request message may include a first read request message, and the data processing device 500 may also include: a first receiving module, used to receive second read data in units of a second data length from the second device based on the second address and the second size; a fourth conversion module, used to convert the second read data into first read data based on the first address and the first size; and a first sending module, used to send the first read data to the first device.

[0089] In some embodiments, converting the second read data into the first read data based on the first address and the first size may include: determining a third offset value between the first address and the second address; removing data corresponding to the first K first data lengths in the second read data, where K is an integer the same as the third offset value; determining a third end address based on the first address and the first size; determining a fourth end address based on the second address and the second size; determining a fourth offset value between the third end address and the fourth end address; and removing data corresponding to the last L first data lengths in the second read data to generate the first read data, where L is an integer the same as the fourth offset value.

[0090] In some implementations, the first device may be a direct memory access interface device, and the second device may be a data bus interface device.

[0091] In some implementations, the first data length may be 1 byte, and the second data length may be 2N bytes, where N is an integer greater than or equal to 1.

[0092] It should be understood that the data processing device 500 according to an embodiment of the present disclosure may also include modules for executing any data processing method described according to an embodiment of the present disclosure (e.g., the data processing method 200 described above and any other data processing method described in conjunction with Figures 1-4). Similarly, these modules can be implemented by software, hardware, firmware, or any combination thereof; for example, these modules can be implemented by functional circuits that implement corresponding functions. In addition, these modules and the various modules described above can be implemented in an integrated manner in any combination, or can also be implemented separately.

[0093] FIG6 shows a schematic diagram of another data processing device according to at least one embodiment of the present disclosure.

[0094] As shown in FIG6 , a data processing device 600 according to an embodiment of the present disclosure may include at least one processor 601 and a storage device 602. The storage device 602 may store at least one program, which, when executed by the at least one processor 601, may enable the at least one processor 601 to implement any method according to an embodiment of the present disclosure, such as the data processing method 200 described above and any other data processing method described in conjunction with FIG1 to FIG4 .

[0095] In addition, an embodiment of the present disclosure also provides an electronic device, which may include a data processing device 500 or 600 according to an embodiment of the present disclosure, and may execute or implement any method according to an embodiment of the present disclosure, such as the data processing method 200 above and any other data processing method described in combination with Figures 1-4.

[0096] For example, the electronic device may further include other devices that cooperate with the data processing device 500 or 600, for example, including the first device and the second device mentioned in the aforementioned embodiment, wherein the data processing device 500 or 600 is respectively connected to the first device and the second device in a communication manner. For example, the communication connection may be based on a certain bus protocol and the bus width (e.g., 16 bytes, 32 bytes, etc.) may be selected as needed, and the embodiments of the present disclosure are not limited thereto. For example, the electronic device may include, but is not limited to, a personal computer (PC), a server, a mobile phone, a laptop computer, a digital broadcast receiver, a PDA (personal digital assistant), a PAD (tablet computer), a PMP (portable multimedia player), an in-vehicle terminal (e.g., an in-vehicle navigation terminal), a digital TV, a desktop computer, etc.

[0097] FIG7 shows an example schematic diagram of an electronic device 700 suitable for implementing at least one embodiment of the present disclosure. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. The electronic device shown in FIG7 is merely an example and should not limit the functionality or scope of use of the embodiments of the present disclosure.

[0098] As shown in Figure 7, the electronic device 700 may include a processing device 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage device 706 into a random access memory (RAM) 703. For example, the processing device 701 may include a data processing device 500 or 600 according to an embodiment of the present disclosure, and may execute or implement any method according to an embodiment of the present disclosure, such as the data processing method 200 above and any other data processing method described in conjunction with Figures 1 to 4. As described above, the processing device 701 may also include other devices that work in conjunction with the data processing device 500 or 600, for example, including the first device and the second device mentioned in the aforementioned embodiment, such as a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a tensor processing unit (TPU), a data processing unit (DPU), an artificial intelligence (AI) accelerator, a deep learning accelerator (DLA), etc. In some embodiments, in the RAM 703, various programs and data required for the operation of the electronic device 700 are also stored. The processing device 701, the ROM 702, and the RAM 703 are connected to one another via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0099] Typically, the following devices may be connected to the I / O interface 705: an input device 706 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 706 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 709. The communication device 709 may allow the electronic device 700 to communicate with other devices wirelessly or by wire to exchange data. Although FIG. 7 shows the electronic device 700 with various devices, it should be understood that not all of the devices shown are required to be implemented or present. More or fewer devices may be implemented or present instead.

[0100] In addition, an embodiment of the present disclosure also provides a non-transitory storage medium containing computer-executable instructions, wherein the computer-executable instructions, when executed by a computer processor, are used to execute any method according to an embodiment of the present disclosure, such as the data processing method 200 above and any other data processing method described in combination with Figures 1-4.

[0101] The data processing method provided by the embodiments of the present disclosure converts the format of processing requests (eg, read / write requests) so that the processing requests can be easily switched between different hardware, thereby improving overall processing efficiency.

[0102] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processing device, the above-mentioned functions defined in the method of the embodiment of the present disclosure are performed.

[0103] It should be noted that the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or component. In the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0104] In some embodiments, the client and server can communicate using any currently known or later developed network protocol, such as HTTP (HyperText Transfer Protocol), and can be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or later developed network.

[0105] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0106] The above-mentioned computer-readable medium carries one or more programs. When the above-mentioned one or more programs are executed by the electronic device, the electronic device: receives a first request message from a first device, wherein the first request message includes a first address aligned according to a first data length and a first size in units of the first data length; converts the first address into a second address aligned according to a second data length, wherein the second data length is greater than the first data length; converts the first size into a second size in units of the second data length; and sends a second request message to a second device, wherein the second request message includes the second address and the second size.

[0107] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages, or a combination thereof, including, but not limited to, object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0108] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0109] The units involved in the embodiments described in this disclosure may be implemented in software or hardware. In some cases, the name of a unit does not limit the unit itself. For example, the first acquisition unit may also be described as a "unit for acquiring at least two Internet Protocol addresses."

[0110] The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, and without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0111] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0112] According to one or more embodiments of the present disclosure, a data processing method is provided, including:

[0113] receiving a first request message from a first device, wherein the first request message includes a first address aligned according to a first data length and a first size in units of the first data length;

[0114] Converting the first address into a second address aligned according to a second data length, wherein the second data length is greater than the first data length;

[0115] converting the first size into a second size in units of the second data length; and

[0116] A second request message is sent to the second device, wherein the second request message includes the second address and the second size.

[0117] According to one or more embodiments of the present disclosure, converting the first address into a second address aligned according to a second data length includes:

[0118] The lower bit of the first address corresponding to the lower bit of the value 0 in the binary representation of the second data length is set to 0 to obtain the second address.

[0119] According to one or more embodiments of the present disclosure, converting the first size into a second size in units of the second data length includes:

[0120] rounding up a quotient of the first size and the second data length to obtain an intermediate size using the second data length as a unit;

[0121] determining a first boundary address based on the second address and the intermediate size;

[0122] determining a first end address based on the first address and the first size; and

[0123] The second size is determined based on a comparison of the first end address and the first boundary address and the intermediate size.

[0124] According to one or more embodiments of the present disclosure, determining the second size based on a comparison between the first end address and the first boundary address and the intermediate size includes:

[0125] If the first end address is less than or equal to the first boundary address, determining the intermediate size as the second size; and

[0126] When the first end address is greater than the first boundary address, the intermediate size is increased by 1 to determine the second size.

[0127] According to one or more embodiments of the present disclosure, the first request message includes a first write request message, the first write request message also includes first write data in units of the first data length, and the method further includes:

[0128] converting the first write data into second write data in units of the second data length; and

[0129] The second write data is included in the second request message.

[0130] According to one or more embodiments of the present disclosure, converting the first write data into second write data in units of the second data length includes:

[0131] determining a first offset value between the first address and the second address;

[0132] Adding J zeros corresponding to the first data length before the first written data, where J is an integer equal to the first offset value;

[0133] determining a first end address based on the first address and the first size;

[0134] determining a second end address based on the second address and the second size;

[0135] determining a second offset value between the first end address and the second end address; and

[0136] M zeros corresponding to the first data length are added after the first write data to generate the second write data, where M is an integer the same as the second offset value.

[0137] According to one or more embodiments of the present disclosure, the method further includes:

[0138] generating an indication signal for indicating which data in the second write data is valid data corresponding to the first write data; and

[0139] The indication signal is included in the second request message.

[0140] According to one or more embodiments of the present disclosure, the indication signal includes a first indication signal and a second indication signal, wherein:

[0141] The first indication signal is used to indicate which data of the first second data length in the second write data is valid data corresponding to the first write data; and wherein,

[0142] The second indication signal is used to indicate which data in the last data of the second data length in the second write data is valid data corresponding to the first write data.

[0143] According to one or more embodiments of the present disclosure, the first request message includes a first read request message,

[0144] The method further comprises:

[0145] receiving second read data in units of the second data length from the second device based on the second address and the second size;

[0146] converting the second read data into first read data based on the first address and the first size; and

[0147] The first read data is sent to the first device.

[0148] According to one or more embodiments of the present disclosure, converting the second read data into the first read data based on the first address and the first size includes:

[0149] determining a third offset value between the first address and the second address;

[0150] Remove the first K data corresponding to the first data length in the second read data, where K is an integer equal to the third offset value;

[0151] determining a third end address based on the first address and the first size;

[0152] determining a fourth end address based on the second address and the second size;

[0153] determining a fourth offset value between the third end address and the fourth end address; and

[0154] The data corresponding to the last L first data lengths in the second read data are removed to generate the first read data, where L is an integer equal to the fourth offset value.

[0155] According to one or more embodiments of the present disclosure, the first device is a direct memory access interface device, and the second device is a data bus interface device.

[0156] According to one or more embodiments of the present disclosure, the first data length is 1 byte, and the second data length is 2N bytes, where N is an integer greater than or equal to 1.

[0157] According to one or more embodiments of the present disclosure, there is provided a data processing apparatus, including:

[0158] a first interface configured to receive a first request message from a first device, wherein the first request message includes a first address aligned according to a first data length and a first size in units of the first data length;

[0159] a first conversion module, configured to convert the first address into a second address aligned according to a second data length, wherein the second data length is greater than the first data length;

[0160] a second conversion module, configured to convert the first size into a second size in units of the second data length; and

[0161] The second interface is used to send a second request message to the second device, wherein the second request message includes the second address and the second size.

[0162] According to one or more embodiments of the present disclosure, converting the first address into a second address aligned according to a second data length includes:

[0163] The lower bit of the first address corresponding to the lower bit of the value 0 in the binary representation of the second data length is set to 0 to obtain the second address.

[0164] According to one or more embodiments of the present disclosure, converting the first size into a second size in units of the second data length includes:

[0165] rounding up a quotient of the first size and the second data length to obtain an intermediate size using the second data length as a unit;

[0166] determining a first boundary address based on the second address and the intermediate size;

[0167] determining a first end address based on the first address and the first size; and

[0168] The second size is determined based on a comparison of the first end address and the first boundary address and the intermediate size.

[0169] According to one or more embodiments of the present disclosure, determining the second size based on a comparison between the first end address and the first boundary address and the intermediate size includes:

[0170] If the first end address is less than or equal to the first boundary address, determining the intermediate size as the second size; and

[0171] When the first end address is greater than the first boundary address, the intermediate size is increased by 1 to determine the second size.

[0172] According to one or more embodiments of the present disclosure, the first request message includes a first write request message, the first write request message also includes first write data in units of the first data length,

[0173] The data processing device further includes:

[0174] a third conversion module, configured to convert the first write data into second write data in units of the second data length; and

[0175] The first processing module is configured to include the second write data in the second request message.

[0176] According to one or more embodiments of the present disclosure, converting the first write data into second write data in units of the second data length includes:

[0177] determining a first offset value between the first address and the second address;

[0178] Adding J zeros corresponding to the first data length before the first written data, where J is an integer equal to the first offset value;

[0179] determining a first end address based on the first address and the first size;

[0180] determining a second end address based on the second address and the second size;

[0181] determining a second offset value between the first end address and the second end address; and

[0182] M zeros corresponding to the first data length are added after the first write data to generate the second write data, where M is an integer the same as the second offset value.

[0183] According to one or more embodiments of the present disclosure, the data processing device further includes:

[0184] a first generating module, configured to generate an indication signal for indicating which data in the second write data is valid data corresponding to the first write data; and

[0185] The second processing module is configured to include the indication signal in the second request message.

[0186] According to one or more embodiments of the present disclosure, the indication signal includes a first indication signal and a second indication signal, wherein:

[0187] The first indication signal is used to indicate which data of the first second data length in the second write data is valid data corresponding to the first write data; and wherein,

[0188] The second indication signal is used to indicate which data in the last data of the second data length in the second write data is valid data corresponding to the first write data.

[0189] According to one or more embodiments of the present disclosure, the first request message includes a first read request message,

[0190] The data processing device further includes:

[0191] a first receiving module, configured to receive second read data in units of the second data length from the second device based on the second address and the second size;

[0192] a fourth conversion module, configured to convert the second read data into first read data based on the first address and the first size; and

[0193] A first sending module is configured to send the first read data to the first device.

[0194] According to one or more embodiments of the present disclosure, converting the second read data into the first read data based on the first address and the first size includes:

[0195] determining a third offset value between the first address and the second address;

[0196] Remove the first K data corresponding to the first data length in the second read data, where K is an integer equal to the third offset value;

[0197] determining a third end address based on the first address and the first size;

[0198] determining a fourth end address based on the second address and the second size;

[0199] determining a fourth offset value between the third end address and the fourth end address; and

[0200] The data corresponding to the last L first data lengths in the second read data are removed to generate the first read data, where L is an integer equal to the fourth offset value.

[0201] According to one or more embodiments of the present disclosure, the first device is a direct memory access interface device, and the second device is a data bus interface device.

[0202] According to one or more embodiments of the present disclosure, the first data length is 1 byte, and the second data length is 2N bytes, where N is an integer greater than or equal to 1.

[0203] According to one or more embodiments of the present disclosure, a data processing device is provided, including:

[0204] at least one processor; and

[0205] A storage device stores at least one program thereon, which, when executed by the at least one processor, enables the at least one processor to implement any data processing method according to the embodiments of the present disclosure.

[0206] According to one or more embodiments of the present disclosure, an electronic device is provided, including any data processing device according to the embodiments of the present disclosure.

[0207] According to one or more embodiments of the present disclosure, a non-transitory storage medium containing computer-executable instructions is provided, wherein the computer-executable instructions, when executed by a computer processor, are used to perform any data processing method according to the embodiments of the present disclosure.

[0208] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also includes other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the above-mentioned disclosed concepts. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this disclosure.

[0209] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details have been included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0210] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A data processing method, comprising: receiving a first request message from a first device, wherein the first request message includes a first address aligned according to a first data length and a first size in units of the first data length; Converting the first address into a second address aligned according to a second data length, wherein the second data length is greater than the first data length; converting the first size into a second size in units of the second data length; and A second request message is sent to a second device, wherein the second request message includes the second address and the second size.

2. The method according to claim 1, wherein: Converting the first address into a second address aligned according to a second data length comprises: The lower bits in the first address corresponding to the lower bits of the value 0 in the binary representation of the second data length are set to 0 to obtain the second address.

3. The method according to claim 1 or 2, wherein: Converting the first size into a second size in units of the second data length includes: Rounding up a quotient of the first size and the second data length to obtain an intermediate size in units of the second data length; determining a first boundary address based on the second address and the intermediate size; determining a first end address based on the first address and the first size; and The second size is determined based on a comparison of the first end address and the first boundary address and the intermediate size.

4. The method according to claim 3, wherein: Determining the second size based on a comparison between the first end address and the first boundary address and the intermediate size includes: In a case where the first end address is less than or equal to the first boundary address, determining the intermediate size as the second size; and When the first end address is greater than the first boundary address, the intermediate size is increased by 1 to determine the second size.

5. The method according to any one of claims 1 to 4, wherein: The first request message includes a first write request message, and the first write request message also includes first write data in units of the first data length. The method further comprises: converting the first write data into second write data in units of the second data length; and The second write data is included in the second request message.

6. The method according to claim 5, wherein: Converting the first write data into second write data in units of the second data length includes: determining a first offset value between the first address and the second address; Adding J zeros corresponding to the first data length before the first written data, where J is an integer equal to the first offset value; determining a first end address based on the first address and the first size; determining a second end address based on the second address and the second size; determining a second offset value between the first end address and the second end address; and M zeros corresponding to the first data length are added after the first write data to generate the second write data, where M is an integer the same as the second offset value.

7. The method according to claim 5 or 6, further comprising: generating an indication signal for indicating which data in the second write data is valid data corresponding to the first write data; as well as The indication signal is included in the second request message.

8. The method according to claim 7, wherein: The indication signal includes a first indication signal and a second indication signal, wherein: The first indication signal is used to indicate which data of the first second data length in the second write data is valid data corresponding to the first write data; and wherein, The second indication signal is used to indicate which data of the last data of the second data length in the second write data is valid data corresponding to the first write data.

9. The method according to any one of claims 1 to 8, wherein: The first request message includes a first read request message, The method further comprises: receiving second read data in units of the second data length from the second device based on the second address and the second size; converting the second read data into first read data based on the first address and the first size; and The first read data is sent to the first device.

10. The method according to claim 9, wherein: Based on the first address and the first size, converting the second read data into first read data includes: determining a third offset value between the first address and the second address; Remove the first K data corresponding to the first data length in the second read data, where K is an integer equal to the third offset value; determining a third end address based on the first address and the first size; determining a fourth end address based on the second address and the second size; determining a fourth offset value between the third end address and the fourth end address; and The data corresponding to the last L first data lengths in the second read data are removed to generate the first read data, wherein L is an integer the same as the fourth offset value.

11. The method according to any one of claims 1 to 10, wherein: The first device is a direct memory access interface device, and the second device is a data bus interface device.

12. The method according to any one of claims 1 to 11, wherein: The first data length is 1 byte, and the second data length is 2N bytes, where N is an integer greater than or equal to 1.

13. A data processing device, comprising: A first interface is configured to receive a first request message from a first device, wherein the first request message includes a first address aligned according to a first data length and a first size in units of the first data length; A first conversion module is configured to convert the first address into a second address aligned according to a second data length, wherein the second data length is greater than the first data length; A second conversion module configured to convert the first size into a second size in units of the second data length; and The second interface is configured to send a second request message to the second device, wherein the second request message includes the second address and the second size.

14. A data processing device, comprising: at least one processor; and A storage device having at least one program stored thereon, when the at least one program is When executed by a processor, the at least one processor implements the method according to any one of claims 1 to 12.

15. An electronic device comprising the data processing device according to claim 13 or 14.

16. A non-transitory storage medium containing computer executable instructions, wherein: The computer executable instructions are used to perform the method of any one of claims 1-12 when executed by a computer processor.

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