Multilayer ceramic capacitor

Abstract

In this multilayer ceramic capacitor, the occurrence of "squeaking" is suppressed by the capacitor itself.　A multilayer ceramic capacitor 10 according to the present invention comprises: a multilayer body having a first surface and a second surface facing each other in the height direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the height direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the height direction and the first direction; first external electrodes arranged on the third surface, the first surface, the second surface, the fifth surface, and the sixth surface of the multilayer body; and second external electrodes arranged on the fourth surface, the first surface, the second surface, the fifth surface, and the sixth surface of the multilayer body. The first external electrodes each have a first base electrode layer and a first plating layer arranged on the first base electrode layer. The second external electrodes each have a second base electrode layer and a second plating layer arranged on the second base electrode layer. The first base electrode layers each have a first connection portion arranged on a first end surface, a first band portion arranged on a first main surface, and a third band portion arranged on a second main surface. The second base electrode layers each have a second connection portion arranged on a second end surface, a second band portion arranged on the first main surface, and a fourth band portion arranged on the second main surface. In each of the first base electrode layers, the height dimension of the first band portion is greater than the height dimension of the third band portion, and in each of the second base electrode layers, the height dimension of the second band portion is greater than the height dimension of the fourth band portion.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors have a capacitor body formed by a laminate in which dielectric layers and internal electrodes are alternately stacked, and external electrodes provided on the surface of the laminate. In the capacitor body, the internal electrodes face each other with the dielectric layers interposed between them to generate capacitance, but this causes a piezoelectric phenomenon that generates vibrations in the capacitor body, which in turn vibrates the substrate, resulting in a phenomenon known as "noise."

[0003] To suppress the occurrence of "squeak noise," a multilayer ceramic capacitor is known in which bumps are provided on the side of the capacitor body that is mounted on the substrate, so as to cover part of the external electrodes, thereby reducing the impact of vibrations of the capacitor body on the substrate.

[0004] For example, Patent Document 1 discloses a technology that reduces the effects of vibration by increasing the distance between the capacitor body and the substrate using bumps (connection terminals), and also uses a substrate material such as alumina, which has high rigidity and Young's modulus, to suppress the vibration itself.

[0005] For example, Patent Document 2 discloses a technology in which bumps (spacers) are applied to the component body with a bump-forming paste and then heat-treated to form bumps in order to increase the distance between the capacitor body and the substrate and reduce the effects of vibration.

[0006] U.S. Patent No. 10,542,626 U.S. Patent No. 10,971,301

[0007] In the technique disclosed in Patent Document 1, when the bumps are attached to the capacitor body later, they may be displaced to an undesired position or rotated in an undesired direction when being aligned with the capacitor body.

[0008] In the technology disclosed in Patent Document 2, bumps are formed using a paste, which allows for relatively desirable alignment accuracy. However, depending on the paste material, the heat generated when the paste is heat-treated and hardened can burn the metal components contained in the external electrodes of the capacitor body, resulting in the formation of voids and a decrease in moisture resistance.

[0009] Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of "squeak" in the capacitor itself.

[0010] A multilayer ceramic capacitor according to the present invention includes a laminate having a first surface and a second surface opposed to each other in a height direction, a third surface and a fourth surface opposed to each other in a first direction perpendicular to the height direction, and a fifth surface and a sixth surface opposed to each other in a second direction perpendicular to the height direction and the first direction; first external electrodes arranged on the third surface, the first surface, the second surface, the fifth surface, and the sixth surface of the laminate; and second external electrodes arranged on the fourth surface, the first surface, the second surface, the fifth surface, and the sixth surface of the laminate, the first external electrodes having a first base electrode layer and a first plating layer arranged on the first base electrode layer, and the second external electrodes having a second base electrode layer and a second plating layer arranged on the second base electrode layer. and a second plating layer disposed on the electrode layer, wherein the first base electrode layer includes a first connection portion disposed on the first end face, a first band portion disposed on the first main surface, and a third band portion disposed on the second main surface, and the second base electrode layer includes a second connection portion disposed on the second end face, a second band portion disposed on the first main surface, and a fourth band portion disposed on the second main surface, wherein in the first base electrode layer, the height dimension of the first band portion is greater than the height dimension of the third band portion, and in the second base electrode layer, the height dimension of the second band portion is greater than the height dimension of the fourth band portion.

[0011] According to the multilayer ceramic capacitor of the present invention, the first external electrode has a first base electrode layer and a first plating layer disposed on the first base electrode layer, the second external electrode has a second base electrode layer and a second plating layer disposed on the second base electrode layer, the first base electrode layer includes a first connecting portion disposed on the first end face, a first band portion disposed on the first main surface, and a third band portion disposed on the second main surface, and the second base electrode layer includes a second connecting portion disposed on the second end face, and a first plating layer disposed on the first main surface. and a fourth band portion arranged on the second main surface, wherein in the first base electrode layer, the height dimension of the first band portion is greater than the height dimension of the third band portion, and in the second base electrode layer, the height dimension of the second band portion is greater than the height dimension of the fourth band portion. Therefore, when mounting the multilayer ceramic capacitor, the inner layer portion of the laminate is kept away from the mounting substrate, thereby reducing the effect of vibration of the laminate on the substrate and suppressing "noise."

[0012] According to the present invention, in a multilayer ceramic capacitor, the occurrence of "squeak" can be suppressed in the capacitor itself.

[0013] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0014] 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention; FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention; FIG. 3 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1; FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1; FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1; FIG. 7 is a diagram for explaining the effects of an example of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 8 is an external perspective view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to another embodiment of the present invention; FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 8; and FIG. 10 is a cross-sectional view taken along line X-X in FIG.

[0015] As an example of the present invention, a multilayer ceramic capacitor will be described below in this embodiment.

[0016] A. First Embodiment 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor 10 according to a first embodiment of the present invention will be described. FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1.

[0017] The multilayer ceramic capacitor 10 has a laminate 12 and external electrodes 24. The configuration of each will be described below in the order of the laminate 12 and the external electrodes 24.

[0018] (Laminate) The laminate 12 has a first surface 12a and a second surface 12b facing in a height direction x, a third surface 12c and a fourth surface 12d facing in a first direction y perpendicular to the height direction x, and a fifth surface 12e and a sixth surface 12f facing in a second direction z perpendicular to the height direction x and the first direction y. The direction connecting the first surface 12a and the second surface 12b of the laminate 12 is the height direction x. In this embodiment, the first main surface 12a of the laminate 12 is the mounting surface side.

[0019] The laminate 12 has a rectangular parallelepiped shape. Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. The ridges refer to the intersections of two of the first surface 12a, the second surface 12b, the third surface 12c, the fourth surface 12d, the fifth surface 12e, and the sixth surface 12f. The corners refer to the intersections of three adjacent surfaces of the laminate 12. The ridges and corners are preferably rounded, which can prevent chipping and cracking. When the ridges and corners are rounded, the surfaces other than the ridges and corners may be flat. Furthermore, unevenness may be formed on some or all of the first surface 12a, the second surface 12b, the third surface 12c, the fourth surface 12d, and the fifth surface 12e and the sixth surface 12f. The first surface 12a is the mounting surface.

[0020] The laminate 12 has a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 have a first internal electrode 16a and a second internal electrode 16b.

[0021] The laminate 12 also has an inner layer portion 15a, a first outer layer portion 15b1 located on the first surface 12a side, and a second outer layer portion 15b2 located on the second surface 12b side.

[0022] The first outer layer portion 15b1 is located on the first surface 12a side of the laminate 12 and is an aggregate of multiple outer layer dielectric layers 14b located between the first surface 12a and the internal electrode 16 closest to the first surface 12a.

[0023] The second outer layer portion 15b2 is located on the second surface 12b side of the laminate 12 and is an aggregate of multiple outer layer dielectric layers 14b located between the second surface 12b and the internal electrode 16 closest to the second surface 12b.

[0024] The region sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the inner layer portion 15a.

[0025] The inner layer portion 15a has a first inner electrode 16a having one end exposed on the third surface 12c, a second inner electrode 16b having one end exposed on the fourth surface 12d, and an inner dielectric layer 14a.

[0026] The inner dielectric layer 14a has a first region 22a covering one end of the first internal electrode 16a and the second internal electrode 16b in the first direction y that is not exposed on the third surface 12c or the fourth surface 12d, and a second region 22b covering at least a portion of one surface of the first internal electrode 16a and the second internal electrode 16b in the stacking direction.

[0027] That is, the first region 22a refers to the region between the first internal electrode 16a and the fourth surface 12d and the region between the second internal electrode 16b and the third surface 12c. The second region 22b covers at least a part of the surfaces of the first internal electrode 16a and the second internal electrode 16b on the first surface 12a side.

[0028] The dielectric component most abundant in the first region 22 a and the dielectric component most abundant in the second region 22 b are preferably the same type, such as, but not limited to, Ba, Ti, Ca, Zr, and Sr.

[0029] For example, if the dielectric component contains a large amount of CaTiO3 or CaZrO3, it is possible to make it difficult for dielectric breakdown to occur between the end of the first internal electrode 16a in the first direction y and the second external electrode 24b, and between the first internal electrode 16a and the second internal electrode 16b. Furthermore, without being limited to this, SrTiO3 or the like can also be used as the main component.

[0030] In order to increase the capacitance of the multilayer ceramic capacitor 10, the second region 22b is preferably made of a material with a high dielectric constant, such as BaTiO3.

[0031] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 5 to 1000, including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the dielectric layer 14 is preferably, for example, 0.3 μm to 6.0 μm.

[0032] The first outer layer portion 15b1 and the second outer layer portion 15b2 are each formed of an insulating material.

[0033] When the first outer layer portion 15b1 and the second outer layer portion 15b2 are formed from the same type of dielectric material as the first region 22a and the second region 22b of the inner dielectric layer 14a, each outer layer portion 15b1, 15b2 may be formed from multiple outer dielectric layers 14b or from a single outer dielectric layer 14b.

[0034] The inner dielectric layer 14a and the outer dielectric layer 14b may be formed of different components. For example, the inner dielectric layer 14a may have a higher dielectric constant than the outer dielectric layer 14b, and the outer dielectric layer 14b may be made of a material that has improved moisture resistance, weather resistance, and strength resistance.

[0035] Furthermore, without being limited to this, the first outer layer portion 15b1 and the second outer layer portion 15b2 may be formed of a DLC film or may be formed of a different type of insulating material such as an insulating resin.

[0036] 4 and 5, the internal electrode 16 includes a first internal electrode 16a and a second internal electrode 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the dielectric layer 14 interposed therebetween.

[0037] The first internal electrode 16a is disposed on the surface of the dielectric layer 14. The first internal electrode 16a has a first opposing electrode portion 18a that faces the second internal electrode 16b, and a first lead electrode portion 20a that is located on one end side of the first internal electrode 16a and extends from the first opposing electrode portion 18a to the third surface 12c of the laminate 12. An end of the first lead electrode portion 20a is led out to and exposed on the third surface 12c.

[0038] The shape of the first opposing electrode portion 18a of the first internal electrode 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed at an angle in plan view (tapered). Alternatively, the first opposing electrode portion 18a may be tapered in plan view, with a slope increasing in either direction.

[0039] The shape of the first lead electrode portion 20a of the first internal electrode 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 20a may be tapered in plan view, with a slope increasing in either direction.

[0040] The width of the first opposing electrode portion 18a of the first internal electrode 16a and the width of the first extraction electrode portion 20a of the first internal electrode 16a may be formed to be the same width, or one of them may be formed to be narrower in width.

[0041] The second internal electrode 16b is arranged on a surface of a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode 16a is arranged. The second internal electrode 16b has a second opposing electrode portion 18b facing the first internal electrode 16a, and a second extraction electrode portion 20b located on one end side of the second internal electrode 16b and extending from the second opposing electrode portion 18b to the fourth surface 12d of the laminate 12. The end of the second extraction electrode portion 20b is drawn out and exposed on the fourth surface 12d.

[0042] The shape of the second opposing electrode portion 18b of the second internal electrode 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed at an angle in plan view (tapered). Alternatively, the second opposing electrode portion 18b may be tapered in plan view, with a slope increasing in either direction.

[0043] The shape of the second extraction electrode portion 20b of the second internal electrode 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second extraction electrode portion 20b may be tapered in plan view, with a slope increasing in either direction.

[0044] The width of the second opposing electrode portion 18b of the second internal electrode 16b and the width of the second extraction electrode portion 20b of the second internal electrode 16b may be formed to be the same width, or one of them may be formed to be narrower in width.

[0045] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, such as, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys, but are not limited to these.

[0046] The first internal electrode 16a and the second internal electrode 16b may contain Sn. When the first internal electrode 16a and the second internal electrode 16b contain Sn, electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14 can be alleviated, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is contained in only one of the internal electrodes 16, either the first internal electrode 16a or the second internal electrode 16b.

[0047] When the regions between the first internal electrode 16 a and the fifth surface 12 e and between the second internal electrode 16 b and the fifth surface 12 e are defined as third regions 22 c, and the regions between the first internal electrode 16 a and the sixth surface 12 f and between the second internal electrode 16 b and the sixth surface 12 f are defined as fourth regions 22 d, there may be segregation of Si between the internal electrode 16 and the third region 22 c and between the internal electrode 16 a and the fourth region 22 d, thereby improving the flexural strength of the multilayer ceramic capacitor 10.

[0048] In this embodiment, the first opposing electrode portion 18a of the first internal electrode 16a and the second opposing electrode portion 18b of the second internal electrode 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0049] The number of stacked internal electrodes 16 is not particularly limited, but is preferably 5 to 1000. The thickness of the internal electrodes 16 is preferably 0.2 μm to 2.0 μm.

[0050] (External Electrodes) As shown in FIGS. 1 to 6, external electrodes 24 are disposed on the third surface 12c side and the fourth surface 12d side of the laminate 12.

[0051] The external electrode 24 includes a base electrode layer 26 formed to cover each of the third surface 12c side and the fourth surface 12d side of the laminate 12, and a plating layer 28 formed to cover the base electrode layer 26.

[0052] The external electrode 24 includes a first external electrode 24a and a second external electrode 24b.

[0053] The first external electrode 24a includes a first base electrode layer 26a covering the third surface 12c side, and a first plating layer 28a covering the first base electrode layer 26a.

[0054] The second external electrode 24b includes a second base electrode layer 26b covering the fourth surface 12d side, and a second plating layer 28b covering the second base electrode layer 26b.

[0055] The first external electrode 24a is disposed on the third surface 12c, a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f of the laminate 12. In this case, the first external electrode 24a is electrically connected to the first extraction electrode portion 20a of the first internal electrode 16a.

[0056] The first external electrode 24a is formed so that the thickness on the first surface 12a side, which is the dimension along the height direction x, is greater than the thickness on the second surface 12b side, in accordance with the shape of the underlying electrode layer 26 described later.

[0057] The second external electrode 24b is disposed on the fourth surface 12d, part of the first surface 12a, part of the second surface 12b, part of the fifth surface 12e, and part of the sixth surface 12f of the laminate 12. In this case, the second external electrode 24b is electrically connected to the second extraction electrode portion 20b of the second internal electrode 16b.

[0058] The second external electrode 24b is formed so that the thickness on the first surface 12a side, which is the dimension along the height direction x, is greater than the thickness on the second surface 12b side, in accordance with the shape of the underlying electrode layer 26 described later.

[0059] (Underlying Electrode Layer) The underlying electrode layer 26 includes a first underlying electrode layer 26a and a second underlying electrode layer 26b.

[0060] The first underlying electrode layer 26a is arranged to integrally cover each of the third surface 12c of the laminate 12, a portion of the first surface 12a and a portion of the second surface 12b, and a portion of the fifth surface 12e and a portion of the sixth surface 12f.

[0061] The second base electrode layer 26b is arranged to integrally cover each of the fourth surface 12d of the laminate 12, part of the first surface 12a and part of the second surface 12b, and part of the fifth surface 12e and part of the sixth surface 12f.

[0062] As shown in FIG. 4, the first underlying electrode layer 26a has a first connection portion 40a disposed on the third surface 12c, a first band portion 42a disposed on the first surface 12a, and a third band portion 44a disposed on the second surface 12b.

[0063] As shown particularly in FIG. 4, the second underlying electrode layer 26b has a second connection portion 40b disposed on the fourth surface 12d, a second band portion 42b disposed on the first surface 12a, and a fourth band portion 44b disposed on the second surface 12b.

[0064] In the first base electrode layer 26a, the dimension BH1 in the height direction x of the first band portion 42a is larger than the dimension BH3 in the height direction x of the third band portion 44a (BH1>BH3).

[0065] In the second base electrode layer 26b, the dimension BH2 in the height direction x of the second band portion 42b is larger than the dimension BH4 in the height direction x of the fourth band portion 44b (BH2>BH4).

[0066] In the base electrode layer 26, the larger the dimension BH1 of the first band portion 42a and the dimension BH2 of the second band portion 42b are compared with the dimension BH3 of the third band portion 44a and the dimension BH4 of the fourth band portion 44b, the greater the effect of suppressing "squeak." However, making the dimensions BH1 of the first band portion 42a and the dimension BH2 of the second band portion 42b too large increases the overall dimension of the multilayer ceramic capacitor 10 in the height direction x, thereby reducing the degree of freedom in mounting. Therefore, it is preferable that the dimension BH1 of the first band portion 42a and the dimension BH2 of the second band portion 42b be 70 μm or more and 270 μm or less than the dimension BH3 of the third band portion 44a and the dimension BH4 of the fourth band portion 44b.

[0067] Furthermore, the dimension BH1 of the first band portion 42a is greater than the thickness in the first direction y of the center of the first connection portion 40a in the height direction x, and the dimension BH2 of the second band portion 42b is greater than the thickness in the first direction y of the center of the first connection portion 40a in the height direction x.

[0068] Furthermore, the length BL1 in the first direction y of the first band portion 42a is preferably equal to or greater than the length BL3 in the first direction y of the third band portion 44a, and the length BL2 in the first direction y of the second band portion 42b is preferably equal to or greater than the length BL4 in the first direction y of the fourth band portion 44b. This further increases the bonding area between the first band portion 42a and the second band portion 42b and the solder during mounting, thereby improving stability.

[0069] 7, in the multilayer ceramic capacitor 10, the distance D in the first direction y between an edge e1 of the first band portion 42a of the first base electrode layer 26a that is closer to the center of the laminate 12 and an edge e2 of the second band portion 42b of the second base electrode layer that is closer to the center of the laminate 12 is preferably 300 μm or more. If the distance D is too small, there is a risk that the first external electrode 24a and the second external electrode 24b will become conductive to each other due to migration or the like. Therefore, by setting the distance D to 300 μm or more, it is possible to reduce this risk.

[0070] Note that the positions of the edge e1 of the first band portion 42a closest to the center of the laminate 12 and the edge e2 of the second band portion 42b closest to the center of the laminate 12 may be closer to the center of the laminate 12 in the region closer to the first main surface 12a of the laminate 12. In this case, the distance D in the first direction y between the first band portion 42a and the second band portion 42b is defined as the distance between their respective innermost points. In other words, the length BL1 of the first band portion 42a closer to the first main surface 12a of the laminate 12 and the length BL2 of the second band portion 42b are longer than those on the mounting surface side. This increases the bonding area between the first band portion 42a and the second band portion 42b and the laminate 12 on the mounting surface side.

[0071] Furthermore, in the multilayer ceramic capacitor 10, as shown in FIG. 7 , when viewed in the second direction z, the area SB1 of the first band portion 42a, i.e., the product (BL1 × BH1) of the dimension BL1 of the first band portion 42a in the first direction y and the dimension BH1 of the first band portion 42a in the height direction x, is preferably larger than the area SB3 of the third band portion 44a, i.e., the product (BL3 × BH3) of the dimension BL3 of the third band portion 44a in the first direction y and the dimension BH3 of the third band portion 44a in the height direction x (SB1 > SB3).

[0072] Similarly, as shown in FIG. 7, when viewed in the second direction z, it is preferable that the area SB2 of the second band portion 42b, i.e., the product (BL2 × BH2) of the dimension BH2 of the second band portion 42b in the first direction y and the dimension BH2 in the height direction x of the second band portion 42b, is greater than the area SB4 of the fourth band portion 44b, i.e., the product (BL4 × BH4) of the dimension BL4 of the fourth band portion 44b in the first direction y and the dimension BH4 in the height direction x of the fourth band portion 44b (SB2 > SB4).

[0073] This allows the area of ​​the first band portion 42a and the second band portion 42b to be relatively large, and therefore, when mounted, the bonding area between the first band portion 42a and the second band portion 42b and the solder increases, thereby further improving the stability of the multilayer ceramic capacitor 10 when mounted.

[0074] In the multilayer ceramic capacitor 10, the dimensions of the first band portion 42a, the second band portion 42b, the third band portion 44a, and the fourth band portion 44b in the height direction x and the first direction y can be measured as follows.

[0075] The height direction x dimension of each band portion is measured as follows. In the direction connecting the third surface 12c and the fourth surface 12d of the laminate 12 (first direction y), the multilayer ceramic capacitor 10 is cross-section polished in the second direction z up to the ½W plane to expose the polished surface (LT cross section). Then, using a microscope (Olympus, model number: BX-51) connected to a microscope digital camera (Olympus, model number: DP22), the height direction x dimension of each of the first band portion 42a, the second band portion 42b, the third band portion 44a, and the fourth band portion 44b at their central portions along the first direction y is measured at a total magnification of 100x to 500x. Furthermore, measurements are performed on multiple mutually orthogonal polished surfaces, and the height direction x dimension of each band portion on each polished surface is determined. The average of these measurements is used to define the height direction x dimension of each band portion.

[0076] The dimension in the first direction y is measured based on observation of the polished surface, using the boundary between the first connecting portion 40a and the first band portion 42a or the third band portion 44a, or the boundary between the second connecting portion 40b and the second band portion 42b or the fourth band portion 44b as a reference.

[0077] In addition, when the contour of the laminate 12 is rounded and the boundary between the first connecting portion 40a and the first band portion 42a or the third band portion 44a, or the boundary between the second connecting portion 40b and the second band portion 42b or the fourth band portion 44b, is observed to be unclear, the measurement is carried out as follows.

[0078] That is, the first internal electrode 16a or the second internal electrode 16b closest to the first surface 12a is selected in the laminate 12, and the end portion of the first extraction electrode portion 20a or the second extraction electrode portion 20b included in either of the selected internal electrodes that is exposed on the third surface 12c or the fourth surface 12d is identified. The end portion is defined as the boundary between the first connecting portion 40a and the first band portion 42a or the boundary between the second connecting portion 40b and the second band portion 42b, and the dimensions in the first direction y of the first band portion 42a and the second band portion 42b are measured.

[0079] Similarly, the first internal electrode 16 a or the second internal electrode 16 b that is closest to the second surface 12 b is selected in the laminate 12, and the end portion of the first extraction electrode portion 20 a or the second extraction electrode portion 20 b included in either of the selected internal electrodes that is exposed on the third surface 12 c or the fourth surface 12 d is identified. The end portion is defined as the boundary between the first connecting portion 40 a and the third band portion 44 a or the boundary between the second connecting portion 40 b and the fourth band portion 44 b, and the dimensions in the first direction y of the third band portion 44 a and the fourth band portion 44 b are measured.

[0080] The base electrode layer 26 preferably contains Cu as its main component. However, it may contain other metal components and glass components in addition to Cu. Examples of the other metal components that can be used include Mg, Cr, Sr, Al, Na, and Fe. Examples of the glass components that can be used include oxides of Ba, Sr, Si, Ca, Zn, Al, and B.

[0081] The base electrode layer 26 can be formed as a baked layer. The baked layer is formed by applying a conductive paste containing glass and metal to the laminate and baking it, and may be baked simultaneously with the internal electrodes 16 or may be baked after baking the internal electrodes 16. The baked layer may be a multi-layered layer.

[0082] The dimension BH3 of the third band portion 44a and the dimension BH4 of the fourth band portion 44b are preferably in the range of 10 μm to 40 μm, for example. The length in the first direction y of the third band portion 44a and the fourth band portion 44b is preferably 200 μm or more. The distance in the first direction y between the third band portion 44a and the fourth band portion 44b is defined as the distance between their innermost points.

[0083] (Plating Layer) The plating layer 28 includes a first plating layer 28a and a second plating layer 28b.

[0084] The first plating layer 28a is disposed so as to cover the first base electrode layer 26a.

[0085] The second plating layer 28b is disposed so as to cover the second base electrode layer 26b.

[0086] The plating layer 28 may be formed as a single layer, but is particularly preferably formed as a plurality of layers, i.e., at least two layers. For example, it may be a laminate of Ni plating and Sn plating, in that order, from the laminate 12 side. Furthermore, in the case of a three-layer structure, it may be a laminate of Sn plating, Ni plating, and Sn plating, in that order, from the laminate 12 side. Ni plating can prevent the internal electrodes 16 from being eroded by solder. Sn plating can improve mountability.

[0087] Furthermore, without being limited thereto, it is preferable that the plating layer 28 contains at least one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. It is preferable that the plating layer 28 does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99% by volume or more.

[0088] The thickness of each plating layer of the plating layer 28 is preferably 1.0 μm or more and 15.0 μm or less.

[0089] The dimension of the multilayer ceramic capacitor 10 in the first direction y is defined as dimension L, the dimension in the height direction x is defined as dimension T, and the dimension in the second direction z is defined as dimension W.

[0090] The dimensions of the multilayer ceramic capacitor 10 are preferably such that the L dimension in the first direction y is 1.0 mm or more and 3.2 mm or less, the T dimension in the height direction x is 0.55 mm or more and 2.1 mm or less, and the W dimension in the second direction z is 0.5 mm or more and 1.6 mm or less.

[0091] 1 , in the first base electrode layer 26a of the base electrode layer 26, the dimension BH1 of the first band portion 42a is larger than the dimension BH3 of the third band portion 44a, and in the second base electrode layer 26b, the dimension BH2 of the second band portion 42b is larger than the dimension BH4 of the fourth band portion 44b. Thus, when mounting the multilayer ceramic capacitor 10, the external electrode 24 is arranged so that the side including the first band portion 42a of the first base electrode layer 26a and the second band portion 42b of the second base electrode layer 26b, which are located on the first surface 12a, faces the mounting surface. This positions the inner layer portion 15a of the laminate 12 farther from the mounting substrate than when the second surface 12b is the mounting surface. This reduces the effect of vibration of the laminate 12 on the substrate, thereby suppressing acoustic noise.

[0092] Furthermore, the multilayer ceramic capacitor 10 does not use components separate from the multilayer ceramic capacitor 10, such as bumps, for the external electrodes 24. This makes it possible to suppress problems such as misalignment or rotation of the multilayer ceramic capacitor 10 during alignment, or defects in the multilayer ceramic capacitor 10 due to the effects of heat treatment, which would otherwise result from using such separate components. This makes it possible to suppress the occurrence of "noise" in the multilayer ceramic capacitor alone.

[0093] 2. Method for Manufacturing the Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor, which is an example of the multilayer ceramic capacitor according to the above embodiment, will now be described.

[0094] (1) Prepare a dielectric sheet and a conductive paste for the internal electrodes. The dielectric sheet and the conductive paste for the internal electrodes contain a binder (for example, a known organic binder) and an organic solvent (for example, a known organic binder).

[0095] (2) Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing to form an internal electrode pattern. Regarding the dielectric sheet, an outer layer dielectric sheet on which no internal electrode pattern is printed is also produced.

[0096] (3) A predetermined number of dielectric sheets for outer layers on which no internal electrode pattern is formed are stacked, and dielectric sheets on which an internal electrode pattern corresponding to the first internal electrode 16 a and an internal electrode pattern corresponding to the second internal electrode 16 b are alternately stacked thereon, and a predetermined number of dielectric sheets for outer layers on which no internal electrode pattern is formed are stacked thereon to produce a laminated sheet. The laminated sheets are then pressed in the stacking direction by means of a hydrostatic press or the like to produce a laminated block.

[0097] (4) The laminated block is then cut to a predetermined size to cut out laminated chips, which may then be wet-barreled to round the corners and ridges of the laminated chips.

[0098] (5) Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and the materials of the internal electrodes 16, but is preferably 900° C. or higher and 1400° C. or lower.

[0099] Next, a base electrode layer 26 is formed as a baked layer. A conductive paste containing a glass component and a metal component is applied to the third surface 12c and the fourth surface 12d of the laminate 12 by, for example, a dipping method to form the connection portion and the band portion. Thereafter, the laminate 12 to which the conductive paste has been applied is dried at 100°C or higher and 300°C or lower.

[0100] (7) After drying, conductive paste is applied to the first surface 12a and the second surface 12b of the laminate 12 to form the first band portion 42a, the second band portion 42b, the third band portion 44a, and the fourth band portion 44b, and the thicknesses of the band portions are adjusted. Specifically, the conductive paste is applied by extruding it through a slit plate. The dimensions of each band portion can be controlled by the amount of conductive paste and the strength with which it is extruded through the slit plate.

[0101] Furthermore, the method is not limited to the above, and each band portion may be formed by aligning laminates 12 coated with conductive paste, and then applying the conductive paste thereon by, for example, screen printing. In this case, by controlling the size of the through holes in the masking jig or the amount of conductive paste, each band portion having the desired dimensions can be formed.

[0102] (8) The base electrode layer 26 according to the present embodiment can be formed by firing the laminate 12 obtained in the above step (7) in an environment of, for example, 700° C. to 900° C. In this step, the step of firing the base electrode layer 26 can be performed all at once, so that no regions are partially over-fired, and structural defects can be suppressed.

[0103] (9) A plating layer 28 is formed so as to be electrically connected to the base electrode layer 26. Electrolytic plating is preferably used as the plating process. For example, barrel plating is preferably used as the plating method.

[0104] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in FIG. 1 can be manufactured.

[0105] According to the method for manufacturing a multilayer ceramic capacitor according to this embodiment, it is possible to obtain a multilayer ceramic capacitor that can suppress the occurrence of "squeak" in the capacitor itself.

[0106] The multilayer ceramic capacitor according to the embodiment of the present invention is exemplified as the multilayer ceramic capacitor 10 in which the lamination direction of the dielectric layers 14 and the internal electrodes 16 in the laminate 12 coincides with the height direction x and is perpendicular to the mounting surface. However, the multilayer ceramic capacitor may be, for example, a vertically stacked multilayer ceramic capacitor in which the lamination direction of the dielectric layers and the internal electrodes is parallel to the mounting surface.

[0107] B. Second Embodiment 1. Multilayer Ceramic Capacitor Next, an example of a multilayer ceramic capacitor 110 according to a second embodiment of the present invention will be described.

[0108] Fig. 8 is an external perspective view showing a multilayer ceramic capacitor as an example of a multilayer ceramic capacitor according to another embodiment of the present invention. Fig. 9 is a schematic cross-sectional view taken along line IX-IX in Fig. 8. Fig. 10 is a schematic cross-sectional view taken along line X-X in Fig. 8. The multilayer ceramic capacitor 110 according to the second embodiment differs from the multilayer ceramic capacitor 10 according to the first embodiment in that the lamination direction of the internal electrodes is the width direction (second direction z).

[0109] As shown in each figure, the multilayer ceramic capacitor 110 includes a laminate 112 and external electrodes 124 .

[0110] The laminate 112 includes a plurality of dielectric layers 114 and a plurality of internal electrodes 116 stacked along a second direction z. The laminate 112 has a first surface 112a and a second surface 112b facing each other in a height direction x, a third surface 112c and a fourth surface 112d facing in a first direction y perpendicular to the height direction x, and a fifth surface 112e and a sixth surface 112f facing in a second direction z perpendicular to the height direction x and the first direction y. The direction connecting the first surface 112a and the second surface 112b of the laminate 112 is the height direction x.

[0111] The laminate 112 has a plurality of dielectric layers 114 and a plurality of internal electrodes 116. The dielectric layers 114 include an inner dielectric layer 114a and an outer dielectric layer 114b. The internal electrodes 116 have a first internal electrode 116a and a second internal electrode 116b.

[0112] The laminate 112 also has an inner layer portion 115a, a first outer layer portion 115b1 located on the fifth surface 112e side, and a second outer layer portion 115b2 located on the sixth surface 112f side.

[0113] The first outer layer portion 115b1 is located on the fifth surface 112e side of the laminate 112 and is an aggregate of multiple outer layer dielectric layers 114b located between the fifth surface 112e and the internal electrode 116 closest to the fifth surface 112e.

[0114] The second outer layer portion 115b2 is located on the sixth surface 112f side of the laminate 112 and is an aggregate of multiple outer layer dielectric layers 114b located between the sixth surface 112f and the internal electrode 116 closest to the sixth surface 112f.

[0115] The region sandwiched between the first outer layer portion 115b1 and the second outer layer portion 115b2 is the inner layer portion 115a.

[0116] The inner layer portion 115a has a first inner electrode 116a having one end exposed on the third surface 112c, a second inner electrode 116b having one end exposed on the fourth surface 112d, and an inner dielectric layer 114a.

[0117] The inner dielectric layer 114a has a first region 122a covering one end of the first internal electrode 116a and the second internal electrode 116b in the first direction y that is not exposed on the third surface 112c or the fourth surface 112d, and a second region 122b covering at least a portion of one surface in the stacking direction of the first internal electrode 116a and the second internal electrode 116b.

[0118] 9 and 10, the internal electrode 116 includes a first internal electrode 116a and a second internal electrode 116b. The first internal electrodes 116a and the second internal electrodes 116b are alternately stacked with the dielectric layer 114 interposed therebetween.

[0119] The first internal electrode 116a is disposed on the surface of the dielectric layer 114. The first internal electrode 116a has a first opposing electrode portion 118a that faces the second internal electrode 116b, and a first extraction electrode portion 120a that is located on one end side of the first internal electrode 116a and extends from the first opposing electrode portion 118a to the third surface 112c of the laminate 12. An end of the first extraction electrode portion 120a is extracted to and exposed on the third surface 112c.

[0120] The second internal electrode 116b is disposed on a surface of a dielectric layer 114 different from the dielectric layer 114 on which the first internal electrode 116a is disposed. The second internal electrode 116b has a second opposing electrode portion 118b that faces the first internal electrode 116a, and a second extraction electrode portion 120b that is located on one end side of the second internal electrode 116b and extends from the second opposing electrode portion 118b to the fourth surface 112d of the laminate. The end of the second extraction electrode portion 120b is extended to and exposed on the fourth surface 112d.

[0121] When the regions between the first internal electrode 116a and the first surface 112a and between the second internal electrode 116b and the first surface 112a are defined as third regions 122c, and the regions between the first internal electrode 116a and the second surface 112b and between the second internal electrode 116b and the second surface 112b are defined as fourth regions 122d, there may be segregation of Si between the internal electrode 116a and the third region 122c and between the internal electrode 116a and the fourth region 122d, thereby improving the flexural strength of the multilayer ceramic capacitor 10.

[0122] In this embodiment, the first opposing electrode portion 118a of the first internal electrode 116a and the second opposing electrode portion 118b of the second internal electrode 116b face each other via the inner dielectric layer 114a, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0123] As shown in FIGS. 8 to 10, external electrodes 124 are disposed on the third surface 112c and the fourth surface 112d of the laminate 112.

[0124] The external electrode 124 includes a base electrode layer 126 formed to cover each of the third surface 112 c side and the fourth surface 112 d side of the laminate 112 , and a plating layer 128 formed to cover the base electrode layer 126 .

[0125] The external electrode 124 includes a first external electrode 124a and a second external electrode 124b.

[0126] The first external electrode 124a includes a first base electrode layer 126a covering the third surface 112c side, and a first plating layer 128a covering the first base electrode layer 126a.

[0127] The second external electrode 124b includes a second base electrode layer 126b covering the fourth surface 112d side, and a second plating layer 128b covering the second base electrode layer 126b.

[0128] The first external electrode 124a is disposed on the third surface 112c, a portion of the first surface 112a, a portion of the second surface 112b, a portion of the fifth surface 112e, and a portion of the sixth surface 112f of the laminate 112. In this case, the first external electrode 124a is electrically connected to the first internal electrode 116a.

[0129] The second external electrode 124b is arranged on the fourth surface 112d of the laminate 112, a portion on the first surface 112a, a portion on the second surface 112b, and a portion on the fifth surface 112e and a portion on the sixth surface 112f. In this case, the second external electrode 124b is electrically connected to the second internal electrode 116b.

[0130] (Base Electrode Layer) The base electrode layer 126 has a first base electrode layer 126a and a second base electrode layer 126b.

[0131] The first underlying electrode layer 126a is arranged to integrally cover the third surface 112c of the laminate 112, part of the first surface 112a and part of the second surface 112b, and part of the fifth surface 112e and sixth surface 112f.

[0132] The second base electrode layer 126b is arranged to integrally cover each of the fourth surface 112d of the laminate 112, part of the first surface 112a and part of the second surface 112b, and part of the fifth surface 112e and sixth surface 112f.

[0133] As shown in FIG. 9, the first underlying electrode layer 126a has a first connection portion 140a arranged on the third surface 112c, a first band portion 142a arranged on the first surface 112a, and a third band portion 144a arranged on the second surface 112b.

[0134] As shown in FIG. 9, the second base electrode layer 126b has a second connection portion 140b arranged on the fourth surface 112d, a second band portion 142b arranged on the first surface 112a, and a fourth band portion 144b arranged on the second surface 112b.

[0135] In the first base electrode layer 126a, the dimension BH1 in the height direction x of the first band portion 142a is larger than the dimension BH3 in the height direction x of the third band portion 144a (BH1>BH3).

[0136] In the second base electrode layer 126b, the dimension BH2 in the height direction x of the second band portion 142b is larger than the dimension BH4 in the height direction x of the fourth band portion 144b (BH2>BH4).

[0137] The multilayer ceramic capacitor 110 according to the second embodiment shown in Fig. 8 achieves the same effects as the multilayer ceramic capacitor 10 shown in Fig. 1. That is, when mounting the multilayer ceramic capacitor 110, by arranging the external electrodes 124 so that the side including the first base electrode layer 126a and the second base electrode layer 126b located on the first surface 12a faces the mounting surface, the inner layer portion 115a of the laminate 112 is located farther away from the mounting substrate than when the second surface 12b is the mounting surface. This reduces the effect of vibration of the laminate 112 on the substrate, thereby suppressing "noise."

[0138] The shapes, materials, and other configurations of the laminate 112, the internal electrodes 116, and the external electrodes 124 may be modified in various ways similar to those described for the multilayer ceramic capacitor 10 above.

[0139] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0140] In other words, various modifications can be made to the above-described embodiments and variants in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0141] <1> A laminate having a first surface and a second surface opposing each other in a height direction, a third surface and a fourth surface opposing each other in a first direction orthogonal to the height direction, and a fifth surface and a sixth surface opposing each other in a second direction orthogonal to the height direction and the first direction; a first external electrode disposed on the third surface, the first surface, the second surface, the fifth surface, and the sixth surface of the laminate; a second external electrode disposed on the fourth surface, the first surface, the second surface, the fifth surface, and the sixth surface of the laminate; the first external electrode having: a first base electrode layer; and a first plating layer disposed on the first base electrode layer; the second external electrode having: a second base electrode layer; and a second plating layer disposed on the second base electrode layer; the first base electrode layer having: a first connection portion disposed on the first end face; a first band portion disposed on the first principal surface and a third band portion disposed on the second principal surface; the second base electrode layer includes a second connection portion disposed on the second end face, a second band portion disposed on the first principal surface, and a fourth band portion disposed on the second principal surface; in the first base electrode layer, the height dimension of the first band portion is greater than the height dimension of the third band portion; and in the second base electrode layer, the height dimension of the second band portion is greater than the height dimension of the fourth band portion.

[0142] <2> The multilayer ceramic capacitor according to <1>, wherein, when viewed in a second direction, an area of ​​the first band portion of the first base electrode layer is larger than an area of ​​the third band portion of the first base electrode layer, and an area of ​​the second band portion of the second base electrode layer is larger than an area of ​​the fourth band portion of the second base electrode layer.

[0143] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein, in the first direction, a dimension of the first band portion of the first base electrode layer is larger than a dimension of the third band portion of the first base electrode layer, and a dimension of the second band portion of the second base electrode layer is smaller than a dimension of the fourth band portion of the second base electrode layer.

[0144] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein a distance in the first direction between an edge portion of the first band portion of the first base electrode layer that is closer to the center of the laminate and an edge portion of the second band portion of the second base electrode layer that is closer to the center of the laminate is 300 μm or more.

[0145] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the first base electrode layer and the second base electrode layer are made of a material mainly composed of Cu.

[0146] 10, 110 Multilayer ceramic capacitor 12, 112 Laminate 12a, 112a First surface 12b, 112b Second surface 12c, 112c Third surface 12d, 112d Fourth surface 12e, 112e Fifth surface 12f, 112f Sixth surface 14, 114 Dielectric layer 14a, 114a Inner dielectric layer 14b, 114b Outer dielectric layer 15a, 115a Inner layer portion 15b1, 115b1 First outer layer portion 15b2, 115b2 Second outer layer portion 16, 116 Internal electrode 16a, 116a First internal electrode 16b, 116b Second internal electrode 18a, 118a First opposing electrode portion 18b, 118b Second opposing electrode portion 20a, 120a First lead electrode portion 20b, 120b Second lead electrode portion 22a, 122a First region 22b, 122b Second region 22c, 122c Third region 22d, 122d Fourth region 24, 124 External electrode 24a, 124a First external electrode 24b, 124b Second external electrode 26, 126 Base electrode layer 26a, 126a First base electrode layer 26b, 126b Second base electrode layer 40a, 140a First connecting portion 42a, 142a First band portion 44a, 144a Third band portion 40b, 140b Second connecting portion 42b, 142b Second band portion 44b, 144b Fourth band portion 28, 128 Plated layer 28a, 128a First plated layer 28b, 128b Second plated layer x Height direction y First direction z Second direction

Claims

1. A laminate having a first surface and a second surface opposed to each other in a height direction, a third surface and a fourth surface opposed to each other in a first direction perpendicular to the height direction, and a fifth surface and a sixth surface opposed to each other in a second direction perpendicular to the height direction and the first direction, a first external electrode disposed on the third surface, the first surface, the second surface, the fifth surface and the sixth surface of the laminate, a second external electrode disposed on the fourth surface, the first surface, the second surface, the fifth surface and the sixth surface of the laminate, the first external electrode having a first base electrode layer and a first plating layer disposed on the first base electrode layer, the second external electrode having a second base electrode layer and a second plating layer disposed on the second base electrode layer, the first base electrode layer having a first connection portion disposed on the first end face, a first band portion arranged on the first main surface and a third band portion arranged on the second main surface; the second base electrode layer includes a second connection portion arranged on the second end face, a second band portion arranged on the first main surface, and a fourth band portion arranged on the second main surface; in the first base electrode layer, a height dimension of the first band portion is greater than a height dimension of the third band portion; and in the second base electrode layer, a height dimension of the second band portion is greater than a height dimension of the fourth band portion.

2. The multilayer ceramic capacitor as described in claim 1, wherein, when viewed in a second direction, an area of ​​the first band portion of the first base electrode layer is larger than an area of ​​the third band portion of the first base electrode layer, and an area of ​​the second band portion of the second base electrode layer is larger than an area of ​​the fourth band portion of the second base electrode layer.

3. A multilayer ceramic capacitor as described in claim 1 or claim 2, wherein, in the first direction, a dimension of the first band portion of the first base electrode layer is larger than a dimension of the third band portion of the first base electrode layer, and a dimension of the second band portion of the second base electrode layer is smaller than a dimension of the fourth band portion of the second base electrode layer.

4. A multilayer ceramic capacitor as described in any one of claims 1 to 3, wherein the distance in the first direction between an edge portion of the first band portion of the first base electrode layer that is closer to the center of the laminate and an edge portion of the second band portion of the second base electrode layer that is closer to the center of the laminate is 300 μm or more.

5. The multilayer ceramic capacitor according to claim 1, wherein the main component of the material of said first and second underlying electrode layers is Cu.

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