Semiconductor package

Abstract

A circuit board according to an embodiment comprises: an insulating layer; an upper bonding part disposed on the insulating layer; and an upper protective layer disposed on the insulating layer and having a first through-hole overlapping the upper bonding part in the vertical direction, wherein the width of the upper bonding part in the horizontal direction satisfies a range of 0.55 to 0.95 times the width of the first through-hole in the horizontal direction.

Description

semiconductor package

[0001] The embodiment relates to a semiconductor package.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on a limited-size semiconductor package substrate. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. Accordingly, these semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are increasing the number of semiconductor elements and / or the size of each semiconductor element in line with the trend toward high integration, but the concept is expanding to semiconductor element lets (Chiplets) in which the functional parts of semiconductor elements are divided due to limitations of the reticle, etc.

[0005] Accordingly, intercommunication between semiconductor devices and / or semiconductor chiplets is becoming more important, and accordingly, there is a trend toward placing an interposer between the substrate of a semiconductor package and the semiconductor devices.

[0006] An interposer can function as a redistribution layer that gradually increases the width or depth of a circuit pattern from a semiconductor device toward a semiconductor package to facilitate communication between semiconductor devices and / or semiconductor chiplets, or to interconnect a semiconductor device and a semiconductor package substrate, thereby facilitating electrical signals between a semiconductor device and a semiconductor package substrate having a circuit pattern that is relatively large compared to the terminals of the semiconductor device.

[0007] Meanwhile, as the number of input and output terminals of semiconductor devices increases, the miniaturization of wiring and / or pads provided on interposers is becoming increasingly important. Accordingly, the width and / or spacing of pads provided on interposers is trending toward narrowing. At this time, the terminals of the semiconductor devices and the pads of the interposer, and / or the pads of the interposer and the pads of the semiconductor package substrate can be electrically connected using a conductive adhesive such as solder. In addition, as the width and spacing of the pads are miniaturized as described above, the volume of the conductive adhesive needs to be precisely controlled.

[0008] At this time, if the volume of the conductive adhesive is reduced, the bonding strength between the interposer and the semiconductor element and / or the semiconductor package substrate may be reduced, which may result in electrical and / or mechanical reliability issues. Furthermore, if the volume of the conductive adhesive is increased, horizontal diffusion of the conductive adhesive may occur, which may result in electrical short-circuit issues due to the interconnection of multiple adjacent conductive adhesives.

[0009] The embodiment provides a semiconductor package of a novel structure.

[0010] Additionally, the embodiment provides a semiconductor package in which the volume of a conductive adhesive such as solder can be easily controlled.

[0011] Additionally, the embodiment provides a semiconductor package capable of improving electrical coupling reliability between a first circuit board and a semiconductor element and / or a second circuit board.

[0012] In addition, the embodiment provides a semiconductor package capable of preventing diffusion of a conductive adhesive without affecting the circuit integration density by controlling the width of a through hole of a protective layer provided on the first and second circuit boards.

[0013] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0014] A circuit board according to an embodiment includes an insulating layer; an upper bonding portion disposed on the insulating layer; and an upper protective layer disposed on the insulating layer and having a first through hole vertically overlapping the upper bonding portion, wherein a horizontal width of the upper bonding portion satisfies a range between 0.55 and 0.95 times the horizontal width of the first through hole.

[0015] In addition, the circuit board further includes a lower bonding portion arranged on the lower surface of the insulating layer, and a horizontal width of the lower bonding portion satisfies a range of 1.3 to 3 times the horizontal width of the upper bonding portion.

[0016] Additionally, the circuit board further includes a lower protective layer disposed on the lower surface of the insulating layer and having a second through hole vertically overlapping with the lower bonding portion.

[0017] Additionally, the horizontal width of the second through hole is greater than the horizontal width of the first through hole.

[0018] Additionally, the horizontal width of the second through hole satisfies a range of 1.5 to 4 times the horizontal width of the first through hole.

[0019] Additionally, the horizontal width of the lower bonding portion satisfies a range of 0.55 to 0.95 times the horizontal width of the second through hole.

[0020] In addition, the circuit board further includes a connecting member embedded in the insulating layer, and the first through hole includes a 1-1 through hole that does not vertically overlap with the connecting member, and a 1-2 through hole that vertically overlaps with the connecting member, and a horizontal width of the 1-1 through hole is larger than a horizontal width of the 1-2 through hole.

[0021] In addition, the upper bonding portion includes a first upper bonding portion disposed within the 1-1 through hole and not vertically overlapping with the connecting member, and a second upper bonding portion disposed within the 1-2 through hole and vertically overlapping with the connecting member, and a horizontal width of the first upper bonding portion is greater than a horizontal width of the second upper bonding portion.

[0022] Meanwhile, a semiconductor package according to an embodiment further includes a circuit board; and a semiconductor element disposed on the circuit board and having a terminal facing the upper bonding portion, wherein a horizontal width of the upper bonding portion satisfies a range between 1.25 and 2.5 times that of the terminal.

[0023] Additionally, the horizontal width of the upper bonding portion satisfies a range of 1.05 to 2 times the horizontal width of the terminal.

[0024] Additionally, the horizontal width of the lower bonding portion satisfies a range of 1.8 to 4 times the horizontal width of the terminal.

[0025] Additionally, the horizontal width of the penetration hole of the lower protective layer satisfies a range of 2.2 to 6 times the horizontal width of the terminal.

[0026] In addition, the semiconductor package further includes a semiconductor package substrate disposed below the circuit board, the semiconductor package substrate including a first bonding portion facing the lower bonding portion; and a first protective layer having a third through hole vertically overlapping the first bonding portion and the lower bonding portion.

[0027] Additionally, the horizontal width of the lower bonding portion satisfies a range of 0.5 to 0.9 times the horizontal width of the first bonding portion.

[0028] In addition, the horizontal width of the second through hole of the lower protective layer satisfies a range of 1.1 to 2 times the horizontal width of the first bonding portion or a range of 2.2 to 6 times the horizontal width of the terminal.

[0029] In addition, the horizontal width of the third through hole of the first protective layer satisfies a range between 1.25 and 2.5 times the horizontal width of the lower bonding portion, or a range between 2.5 and 6.5 times the horizontal width of the terminal of the semiconductor element.

[0030] Meanwhile, a semiconductor package according to an embodiment includes a circuit board including a substrate, a connecting member embedded in the substrate, an upper bonding portion disposed on the substrate, and a through hole disposed on the substrate and vertically overlapping the upper bonding portion; a semiconductor element disposed on the circuit board and having a terminal facing the upper bonding portion; and a connecting portion disposed in the through hole and electrically connecting the upper bonding portion and the terminal, wherein the through hole of the upper protective layer includes a first through hole vertically overlapping the connecting member; and a second through hole horizontally overlapping the first through hole without vertically overlapping the connecting member, wherein a horizontal width of the first through hole is greater than a horizontal width of the second through hole, and the horizontal width of the first through hole satisfies a range between 1.25 and 2.5 times a horizontal width of the terminal.

[0031] Additionally, the horizontal width of the second through hole satisfies a range of 0.7 to 1.25 times the horizontal width of the terminal.

[0032] In addition, the upper bonding portion includes a first upper bonding portion arranged in the first through hole and a second upper bonding portion arranged in the second through hole, and a horizontal width of the first upper bonding portion is larger than a horizontal width of the second upper bonding portion, and the horizontal width of the upper bonding portion satisfies a range of 1.05 to 2 times the horizontal width of the terminal.

[0033] Additionally, the horizontal width of the second upper bonding portion satisfies a range of 0.5 to 1.2 times the horizontal width of the terminal.

[0034] A semiconductor package of the embodiment includes a first circuit board, a second circuit board, and a semiconductor element. The first circuit board is disposed between the second circuit board and the semiconductor element, the semiconductor element is disposed on the first circuit board, and the second circuit board is disposed between the first circuit board and a main board of an electronic device.

[0035] At this time, the embodiment controls the horizontal width of a terminal provided in a semiconductor element, the horizontal width of a through hole of an upper protective layer of a first circuit board, the horizontal width of an upper bonding portion of the first circuit board, the horizontal width of a through hole of a lower protective layer of the first circuit board, the horizontal width of a lower protective layer of the first circuit board, the horizontal width of a bonding portion of a second circuit board, and the horizontal width of a through hole of a protective layer of a second circuit board.

[0036] Through this, the embodiment can secure a sufficient volume of a connection portion that electrically couples between the first circuit board and the semiconductor element and / or the first circuit board and the second circuit board, thereby improving the electrical coupling force between the first circuit board and the semiconductor element and / or the first circuit board and the second circuit board. Accordingly, the embodiment can enable the semiconductor element to operate stably. Accordingly, the embodiment can enable the electronic product, such as a server to which the semiconductor package is applied, to operate stably. In addition, the embodiment can improve the signal communication characteristics between the first circuit board and the semiconductor element and / or the first circuit board and the second circuit board, thereby improving the operational reliability of the semiconductor package.

[0037] In addition, the embodiment can secure sufficient volume of a connection portion that electrically connects between the first circuit board and the semiconductor element and / or the first circuit board and the second circuit board without affecting the circuit integration of the first circuit board and / or the second circuit board by controlling the width in the horizontal direction of each component as described above, and further prevents the connection portion from overflowing outside of each through hole, thereby preventing reliability problems such as electrical short circuits in advance.

[0038] In addition, the embodiment can control the horizontal width of each component by considering the direction in which the first circuit board is bent, thereby preventing the semiconductor package from being bent significantly in a specific direction. Accordingly, the embodiment can provide ease in the electrical bonding process between the first circuit board and the semiconductor element and / or the electrical bonding process between the first circuit board and the second circuit board, and further can enable the semiconductor element and / or the second circuit board to be bonded to the first circuit board more stably.

[0039] Figure 1 is a schematic diagram showing a semiconductor package according to the first embodiment.

[0040] FIG. 2 is a drawing showing a detailed configuration of the first circuit board illustrated in FIG. 1.

[0041] FIG. 3 is a cross-sectional view showing the horizontal width of each configuration of the first circuit board, the second circuit board, and the semiconductor element illustrated in FIG. 1.

[0042] Figure 4a is a plan view showing the horizontal width of each component of the first circuit board and semiconductor elements.

[0043] Figure 4b is a plan view showing the horizontal width of each configuration of the first circuit board and the second circuit board.

[0044] FIG. 5 is a drawing showing a detailed configuration of the first circuit board illustrated in FIG. 1 according to the second embodiment.

[0045] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0046] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0047] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0048] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0049] These terms are intended only to distinguish a component from other components, and are not intended to limit the nature, order, or sequence of the component. Furthermore, when a component is referred to as being "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there are no other intervening components.

[0050] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0051] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0052] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components will be given the same reference numbers, and redundant descriptions thereof will be omitted.

[0053] Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. In addition, the semiconductor package includes a first circuit board, a semiconductor element, and a second circuit board. Here, various semiconductor elements may be mounted on the semiconductor package.

[0054] The semiconductor device may include active components and / or passive components. The active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of the above.

[0055] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0056] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0057] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0058]

[0059] Figure 1 is a schematic diagram showing a semiconductor package according to the first embodiment.

[0060] Referring to FIG. 1, a semiconductor package of a first embodiment includes a first circuit board (100), a semiconductor element (200) attached on the first circuit board (100), a second circuit board (300) attached under the first circuit board (100), a first connection portion (400) disposed between the first circuit board (100) and the semiconductor element (200), and a second connection portion (500) disposed between the first circuit board (100) and the second circuit board (300).

[0061] The first circuit board (100) is placed between the second circuit board (300) and the semiconductor element (200), and can electrically connect them.

[0062] The second circuit board (300) may refer to a semiconductor package board. The second circuit board (300) may provide a space to which at least one external board is coupled. The external board may refer to a first circuit board (100) coupled on the second circuit board (300). In addition, the external board may refer to a main board of an electronic device coupled to a lower portion of the second circuit board (300). That is, the second circuit board (300) may electrically connect the main board of the electronic device and the first circuit board (100). In addition, although not shown in the drawing, at least one semiconductor element may be mounted on the second circuit board (300). The second circuit board (300) may include at least one insulating layer and an electrode portion disposed on the at least one insulating layer.

[0063] A first circuit board (100) is placed on a second circuit board (300).

[0064] The first circuit board (100) may be an interposer. The first circuit board (100) provides a space in which at least one semiconductor element (200) is mounted. For example, the first circuit board (100) may provide a space in which a first semiconductor element (200a) and a second semiconductor element (200b) are mounted. The first circuit board (100) may electrically connect the first semiconductor element (200a) and the second semiconductor element (200b), and electrically connect the first and second semiconductor elements (200a, 200b) and the second circuit board (300). That is, the first circuit board (100) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor elements and the package substrate.

[0065] At this time, in Fig. 1, two semiconductor elements (200a, 200b) are illustrated as being arranged on the first circuit board (100), but this is not limited thereto. For example, one semiconductor element may be arranged on the first circuit board (100), or alternatively, three or more semiconductor elements may be arranged horizontally and / or vertically.

[0066] For example, the first circuit board (100) can function as a signal relay between the semiconductor element (200) and the second circuit board (300), and can have passive element functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor element (200) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased picture quality, and increased communication speed. That is, the number of terminals provided in the semiconductor element (200) is increasing, and accordingly, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the second circuit board (300) can be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided in the second circuit board (300) to have the width and spacing for being connected to the semiconductor element (200) and the main board, respectively, there is a problem that the thickness of the second circuit board (300) increases or the layer structure of the second circuit board (300) becomes complicated. Accordingly, the first embodiment may place the first circuit board (100) on the second circuit board (300) and the semiconductor element (200). And the electrodes of the first circuit board (100) may have a micro width and spacing corresponding to the terminals of the semiconductor element (200), and the width and / or spacing of the electrodes may increase as they get farther from the semiconductor element (200) or closer to the second circuit board (300).

[0067] The first connecting portion (400) is positioned between the first circuit board (100) and the semiconductor element (200). The first connecting portion (400) can electrically connect between the first bonding portion (to be described later) provided on the first circuit board (100) and the terminal of the semiconductor element (200). That is, the first connecting portion (400) can couple the semiconductor element (200) to the first circuit board (100).

[0068] The second connecting portion (500) is positioned between the first circuit board (100) and the second circuit board (300). The second connecting portion (500) can electrically connect between the second bonding portion (to be described later) provided on the first circuit board (100) and the third bonding portion (to be described later) of the second circuit board (300). That is, the second connecting portion (500) can couple the second circuit board (300) to the first circuit board (100).

[0069] The first connecting portion (400) and the second connecting portion (500) can electrically connect a plurality of components using a solder bonding method. Preferably, the first connecting portion (400) and the second connecting portion (500) can connect a plurality of components to each other using a thermal compression bonding method. That is, as the pitch of the terminals of the semiconductor element (200) becomes finer, an electrical short may occur between the plurality of first connecting portions (400) connected to the first circuit board (100) and the semiconductor element (200) by a conductive adhesive such as solder, and / or an electrical short may occur between the plurality of second connecting portions (500) connecting the first circuit board (100) and the second circuit board (300). Accordingly, the embodiment can perform thermal compression bonding that can easily control the volume of the first connecting portion (400) and / or the second connecting portion (500) while reducing the volume of the first connecting portion (400) and / or the second connecting portion (500).

[0070] Furthermore, the embodiment adjusts the width of the through hole of the upper protective layer of the first circuit board (100) on which the first connection portion (400) is arranged, and / or the width of the through hole of the lower protective layer of the first circuit board (100) on which the second connection portion (500) is arranged, and / or the width of the through hole of the upper protective layer of the second circuit board (300). Through this, the embodiment maximizes the volume of the first connection portion (400) and / or the second connection portion (500), thereby improving the bonding force between the first circuit board (100) and the semiconductor element (200), and / or the bonding force between the first circuit board (100) and the second circuit board (300), while preventing the horizontal diffusion of the first connection portion (400) and / or the second connection portion (500).

[0071]

[0072] FIG. 2 is a drawing showing a detailed configuration of the first circuit board illustrated in FIG. 1.

[0073] Referring to FIG. 2, the first circuit board (100) includes an insulating layer (110), an upper protective layer (120) disposed on the upper surface of the insulating layer (110), a lower protective layer (130) disposed on the lower surface of the insulating layer (110), and an electrode portion embedded in the insulating layer (110) or disposed on the upper or lower surface of the insulating layer (110). Hereinafter, for easy explanation of the embodiment, terms referring to components included in the first circuit board (100) are described, and a description of each of the referred components will be provided later.

[0074] The electrode part includes an internal electrode part provided within the insulating layer (110) and an external electrode part provided on the uppermost and / or lowermost side of the insulating layer (110). At this time, the external electrode part provided on the uppermost side of the insulating layer (110) can function as an upper bonding part connected to the terminal of the semiconductor element (200). In addition, the external electrode part provided on the lowermost side of the insulating layer (110) can function as a lower bonding part of the first circuit board (100) connected to the bonding part of the second circuit board (300).

[0075] The insulating layer (110) is provided with a structure in which a plurality of layers are sequentially laminated. The insulating layer (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). At this time, the upper surface of the insulating layer (110) may mean the upper surface of the upper build-up layer (112), and the lower surface of the insulating layer (110) may mean the lower surface of the lower build-up layer (113). At this time, the drawing illustrates that the upper build-up layer (112) and the lower build-up layer (112) are provided as two layers each, but the present invention is not limited thereto. For example, the upper build-up layer (112) and / or the lower build-up layer (113) may be provided as a single layer, or may be provided as three or more layers.

[0076] The electrode portion includes a wiring electrode and a via electrode. The wiring electrode includes a first wiring electrode (141) disposed on an upper surface of the core layer (111), a second wiring electrode (142) disposed on a lower surface of the core layer (111), a third wiring electrode (143) disposed on an upper surface of the first layer of the upper build-up layer (112), a fourth wiring electrode (144) disposed on an upper surface of the second layer of the upper build-up layer (112), a fifth wiring electrode (145) disposed on a lower surface of the first layer of the lower build-up layer (113), and a sixth wiring electrode (146) disposed on a lower surface of the second layer of the lower build-up layer (113). At this time, the fourth wiring electrode (144) is an electrode portion disposed on the uppermost layer of the insulating layer (110) and may include an upper bonding portion. For example, the fourth wiring electrode (144) may include an upper bonding portion that vertically overlaps a through hole (121) of the upper protective layer (120). Accordingly, the fourth wiring electrode (144) will be described below as an upper bonding portion. In addition, the sixth wiring electrode (146) may include a lower bonding portion that vertically overlaps the through hole (131) of the lower protective layer (130). Accordingly, the sixth wiring electrode (146) will be described below as a lower bonding portion.

[0077] The via electrode includes a first via electrode (151) penetrating the core layer (111), a second via electrode (152) penetrating the first layer of the upper build-up layer (112), a third via electrode (153) penetrating the second layer of the upper build-up layer (112), a fourth via electrode (154) penetrating the first layer of the lower build-up layer (113), and a fifth via electrode (155) penetrating the second layer of the lower build-up layer (113).

[0078] The laminated upper build-up layer (112) and lower build-up layer (113) may be formed of an insulating material having ease of process, excellent insulating properties, the ability to reduce loss of signals transmitted through the electrode portion, or the ability to create a fine gap between the electrode portions. In addition, both the upper build-up layer (112) and the lower build-up layer (113) may be formed of the same insulating material, but this is not limited to the above, and at least one layer may be formed of an insulating material different from the other insulating layers. For example, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and FR-4, BT (Bismaleimide Triazine), and PID (Photo Image-able Dielectric resin) can also be used.

[0079] The core layer (111) may include a reinforcing member including at least one of glass fiber and GCP (Glass Core Primer), and accordingly, the first circuit board (100) may be classified as a core board. The reinforcing member may improve the rigidity of the first circuit board (100), thereby preventing the first circuit board (100) and / or the semiconductor package from being bent in a specific direction. However, the first circuit board (100) of the embodiment is not limited to a core board, and may be provided as a coreless board without a core layer or manufactured by an ETS (Embedded Trace Substrate) method depending on the product. Hereinafter, for the convenience of explanation, it is assumed that the first circuit board (100) of the embodiment is classified as a core board.

[0080] In addition, an insulating member (111a) is provided in the core layer (111) including the reinforcing member. The insulating member (111a) penetrates the core layer (111) including the reinforcing member. The insulating member (111a) may be provided with hole plugging ink, but is not limited thereto. The insulating member (111a) is provided surrounded by a first via electrode (151) penetrating the core layer (111). That is, when the core layer (111) is thick, a problem may occur in which the first via electrode (151) penetrating the core layer (111) does not densely fill the penetration hole of the core layer (111). This problem may cause the first wiring electrode (141) or the second wiring electrode (142) not to be plated flatly, or a problem in which a void is generated inside the first via electrode (151). Therefore, the arrangement of the insulating member (111a) can solve electrical reliability problems and / or mechanical reliability problems that may occur due to the through holes of the core layer (111) not being entirely filled with a conductive material.

[0081] In addition, an upper protective layer (120) is disposed on the upper surface of the upper build-up layer (112), and a lower protective layer (130) is disposed on the lower surface of the lower build-up layer (113). The upper protective layer (120) and the lower protective layer (130) can have the function of protecting the electrode portion of the first circuit board (100) from external moisture or contaminants, and can be provided with a photosensitive material and / or solder resist to prevent an electrical short circuit problem when bonding between the semiconductor element (200) and the first circuit board (100) and / or the second circuit board (300) and the first circuit board (100). In addition, a photosensitive solder resist can be applied as an example.

[0082] In addition, the upper protective layer (120) has a plurality of through holes (121). For example, the upper protective layer (120) has a plurality of through holes (121) that overlap vertically with each of the plurality of upper bonding portions (144). For example, the fourth wiring electrode (144) may have a plurality of electrode patterns such as pads and / or traces, and among these, the electrode patterns that overlap vertically with the plurality of through holes (121) of the upper protective layer (120) may function as upper bonding portions that are connected to terminals of the semiconductor element (200).

[0083] The width of the through hole (121) of the upper protective layer (120) in the horizontal direction may be different from the width of the upper bonding portion (144) in the horizontal direction. Preferably, the width of the through hole (121) of the upper protective layer (120) in the horizontal direction may be larger than the width of the upper bonding portion (144) in the horizontal direction. For example, the through hole (121) of the upper protective layer (120) may be provided as a NSMD (Non-solder Mask Defined) type. In this case, the plurality of through holes (121) of the upper protective layer (120) may be spaced apart from each other without being connected to each other. Through this, each of the plurality of through holes (121) of the upper protective layer (120) may function as a dam to prevent the horizontal diffusion of the first connection portion (400) provided for electrical coupling between the upper bonding portion (144) and the terminal of the semiconductor element (200).

[0084] At this time, the width of the through hole (121) of the upper protective layer (120) in the horizontal direction can be determined based on the width of the terminal provided in the semiconductor element (200) in the horizontal direction. For example, the embodiment determines the width of the through hole (121) of the upper protective layer (120) in the horizontal direction based on the width of the terminal provided in the semiconductor element (200) in the horizontal direction, and uses this to maximize the volume of the first connection portion (400) arranged in the through hole (121), thereby maximizing the bonding force between the upper bonding portion (144) and the terminal of the semiconductor element (200) while preventing the horizontal diffusion of the first connection portion (400). Through this, the embodiment can ensure that the semiconductor element (200) is stably attached on the first circuit board (100) and that the semiconductor element (200) operates stably. Therefore, the embodiment can ensure that electronic products such as servers to which a semiconductor package is applied operate stably.

[0085] Furthermore, the width of the through hole (121) of the upper protective layer (120) of the embodiment may be determined based on the width of the through hole (122) of the lower protective layer (130). For example, the first circuit board (100) may be greatly warped in a specific direction due to differences in the wiring density of the wiring electrodes (141, 142, 143, 144, 145, 146) provided in each layer, differences in the thickness and / or thermal expansion coefficient of each layer (111, 112, 123) of the insulating layer, etc.

[0086] Therefore, the embodiment controls the width of the through hole (121) of the upper protective layer (120) and the width of the through hole (131) of the lower protective layer (130) in consideration of the direction in which the first circuit board (100) is bent, thereby adjusting the planar area of ​​the upper protective layer (120) and the planar area of ​​the lower protective layer (130). Through this, the embodiment can prevent the first circuit board (100) from being bent significantly in a specific direction. Therefore, the embodiment can provide ease in the electrical bonding process between the first circuit board (100) and the semiconductor element (200) and / or the electrical bonding process between the first circuit board (100) and the second circuit board (300), and further, can enable the semiconductor element (200) and / or the second circuit board (300) to be bonded to the first circuit board (100) more stably.

[0087] In addition, the lower protective layer (130) has a plurality of through holes (131). For example, the lower protective layer (130) has a plurality of through holes (131) that overlap vertically with each of the plurality of lower bonding portions (146). For example, the sixth wiring electrode (146) may have a plurality of electrode patterns such as pads and / or traces, and among these, the electrode patterns that overlap vertically with the plurality of through holes (131) of the lower protective layer (130) may function as lower bonding portions that are connected to the bonding portions of the second circuit board (300).

[0088] The width of the through hole (131) of the lower protective layer (130) in the horizontal direction may be different from the width of the lower bonding portion (146) in the horizontal direction. Preferably, the width of the through hole (131) of the lower protective layer (130) in the horizontal direction may be larger than the width of the lower bonding portion (146) in the horizontal direction. For example, the through hole (131) of the lower protective layer (130) may be provided as a NSMD (Non-solder Mask Defined) type. In this case, the plurality of through holes (131) of the lower protective layer (130) may be spaced apart from each other without being connected to each other. Through this, each of the plurality of through holes (131) of the lower protective layer (130) may function as a dam to prevent the horizontal diffusion of the second connection portion (500) provided for electrical coupling between the lower bonding portion (146) and the bonding portion of the second circuit board (300).

[0089] At this time, the width of the through hole (131) of the lower protective layer (130) in the horizontal direction can be determined based on the width of the bonding portion provided in the second circuit board (300). For example, the embodiment determines the width of the through hole (131) of the lower protective layer (130) in the horizontal direction based on the width of the bonding portion provided in the second circuit board (300), and uses this to maximize the volume of the second connecting portion (500) arranged in the through hole (131), thereby maximizing the bonding force between the lower bonding portion (146) and the bonding portion of the second circuit board (300) while preventing the horizontal diffusion of the second connecting portion (500). Through this, the embodiment can ensure that the second circuit board (300) is stably attached to the first circuit board (100), thereby ensuring smooth communication between them.

[0090]

[0091] Hereinafter, the relationship among the horizontal width of the terminal (210) provided in the semiconductor element (200), the horizontal width of the through hole (121) of the upper protective layer (120) of the first circuit board (100), the horizontal width of the upper bonding portion (144) of the first circuit board (100), the horizontal width of the through hole (131) of the lower protective layer (130) of the first circuit board (100), the horizontal width of the lower protective layer (130) of the first circuit board (100), the horizontal width of the bonding portion (320) of the second circuit board (300), and the horizontal width of the through hole (331) of the protective layer (330) of the second circuit board (300) will be described.

[0092] FIG. 3 is a cross-sectional view showing the horizontal width of each component of the first circuit board, the second circuit board, and the semiconductor element shown in FIG. 1, FIG. 4a is a plan view showing the horizontal width of each component of the first circuit board and the semiconductor element, and FIG. 4b is a plan view showing the horizontal width of each component of the first circuit board and the second circuit board.

[0093] Referring to FIGS. 3, 4a and 4b, the first circuit board (100) includes an insulating layer (110), an upper bonding portion (144), an upper protective layer (120), a lower protective layer (130) and a lower bonding portion (146). In addition, the semiconductor element (200) includes a terminal (210) facing the upper bonding portion (144) of the first circuit board (100). The upper bonding portion (144) of the first circuit board (100) and the terminal (210) of the semiconductor element (200) are arranged to face each other. In addition, a first connection portion (400) is arranged within a through hole (121) of an upper protective layer (120) of a first circuit board (100), and the first connection portion (400) can electrically connect an upper bonding portion (144) of the first circuit board (100) and a terminal (210) of a semiconductor element (200). In addition, the second circuit board (300) includes an insulating layer (310), a bonding portion (320) arranged on the insulating layer (310), and a protective layer (330) arranged on the insulating layer (310). A plurality of electrode patterns may be provided on the upper surface of the insulating layer (310) of the second circuit board (300), and among these, an electrode pattern that vertically overlaps with the through hole (331) of the protective layer (330) may function as a bonding portion (320) that is electrically coupled to the lower bonding portion (146) of the first circuit board (100).

[0094] At this time, a plurality of terminals (210) are arranged on the lower surface of the semiconductor element (200). At this time, the terminals (210) of the semiconductor element (200) may have a first width (W1) in the horizontal direction. The first width (W1) in the horizontal direction of the terminals (210) of the semiconductor element (200) may vary depending on the type and specifications of the semiconductor element (200), and thus, a detailed numerical description thereof will be omitted.

[0095] At this time, the through hole (121) of the upper protective layer (120) of the first circuit board (100) is provided to vertically overlap with the terminal (210) of the semiconductor element (200). In addition, the width of the through hole (121) of the upper protective layer (120) of the first circuit board (100) in the horizontal direction may have a second width (W2) that is larger than the first width (W1) of the terminal (210) of the semiconductor element (200). At this time, if the second width (W2) of the through hole (121) of the upper protective layer (120) is smaller than the first width (W1) of the terminal (210) of the semiconductor element (200), it may be difficult to place the first connection portion (400) of sufficient volume to electrically couple the upper bonding portion (144) and the terminal (210) within the through hole (121), and thus, the bonding strength between the upper bonding portion (144) and the terminal (210) may be reduced, resulting in an electrical open problem. In addition, at this time, if the second width (W2) of the through hole (121) of the upper protective layer (120) is smaller than the first width (W1) of the terminal (210) of the semiconductor element (200), the first connection portion (400) may overflow to the outside of the through hole (121), and thus, an electrical short problem may occur due to horizontal diffusion of the first connection portion (400).

[0096] Preferably, the second width (W2) of the through hole (121) of the upper protective layer (120) can satisfy a range of 1.25 to 2.5 times the first width (W1) of the terminal (210) of the semiconductor element (200). At this time, if the second width (W2) of the through hole (121) of the upper protective layer (120) is less than 1.25 times the first width (W1) of the terminal (210) of the semiconductor element (200), it may be difficult to place the first connection portion (400) of sufficient volume to electrically couple between the upper bonding portion (144) and the terminal (210) within the through hole (121), and accordingly, the bonding strength between the upper bonding portion (144) and the terminal (210) may be reduced, resulting in an electrical open problem. In addition, if the second width (W2) of the through hole (121) of the upper protective layer (120) is less than 1.25 times the first width (W1) of the terminal (210) of the semiconductor element (200), the first connection portion (400) may overflow to the outside of the through hole (121), and thus, an electrical short circuit problem may occur due to horizontal diffusion of the first connection portion (400). In addition, if the second width (W2) of the through hole (121) of the upper protective layer (120) exceeds 2.5 times the first width (W1) of the terminal (210) of the semiconductor element (200), the volume of the first connection portion (400) arranged within the through hole (121) may increase excessively, and thus, the product manufacturing cost may increase. In addition, when the second width (W2) of the through hole (121) of the upper protective layer (120) exceeds 2.5 times the first width (W1) of the terminal (210) of the semiconductor element (200), the spacing between the plurality of adjacent through holes (121) and / or the spacing between the plurality of upper bonding portions (144) may increase, and thus the circuit integration of the first circuit board (100) may decrease. As a result, the planar area of ​​the first circuit board (100) required to place all the upper bonding portions (144) connected to the terminals (210) of the semiconductor element (200) on the first circuit board (100) may increase, and thus, it may be difficult to miniaturize the semiconductor package.

[0097] In addition, the horizontal width of the upper bonding portion (144) may have a third width (W3) smaller than the second width (W2) of the through hole (121) of the upper protective layer (120). At this time, the third width (W3) may be larger than the first width (W1) of the terminal (210) of the semiconductor element (200) and smaller than the seventh width (W7) of the lower bonding portion (146) of the first circuit board (100). Preferably, the third width (W3) of the upper bonding portion (144) may have a value between the first width (W1) and the seventh width (W7). Preferably, the third width (W3) of the upper bonding portion (144) may satisfy a range of 1.05 to 2 times the first width (W1) of the terminal (210) of the semiconductor element (200). More preferably, the third width (W3) of the upper bonding portion (144) can satisfy a range of between 1.05 and 2 times the first width (W1) of the terminal (210) of the semiconductor element (200) while being smaller than the second width (W2) of the through hole (121) of the upper protective layer (120). In addition, the third width (W3) of the upper bonding portion (144) can satisfy a range of between 0.55 and 0.95 times the second width (W2) of the through hole (121) of the upper protective layer (120). If the third width (W3) of the upper bonding portion (144) is less than 1.05 times the first width (W1) of the terminal (210) of the semiconductor element (200), among the wiring electrodes provided on the first circuit board (100) between the upper bonding portion (144) connected to the semiconductor element (200) and the lower bonding portion (146) connected to the second circuit board (300), a wiring electrode whose width in the horizontal direction rapidly increases may be required, and accordingly, as the width of the wiring electrode in the horizontal direction rapidly increases, signal transmission loss may increase. Accordingly, signal communication characteristics between the semiconductor element (200), the first circuit board (100), and the second circuit board (300) may deteriorate.In addition, if the third width (W3) of the upper bonding portion (144) exceeds twice the first width (W1) of the terminal (210) of the semiconductor element (200), the signal transmission loss due to the width difference between the terminal (210) and the upper bonding portion (144) may increase, and thus the signal communication characteristics may deteriorate. In addition, if the third width (W3) of the upper bonding portion (144) is less than 0.55 times the second width (W2) of the through hole (121) of the upper protective layer (120), the width of the upper bonding portion (144) may become too small, and thus the width difference with the terminal (210) of the semiconductor element (200) may increase, and thus the signal transmission loss may increase, and thus the communication characteristics may deteriorate. If the third width (W3) of the upper bonding portion (144) is less than 0.55 times the second width (W2) of the through hole (121) of the upper protective layer (120), the electrical characteristics may deteriorate, and communication may not be smooth between the first circuit board (100) and the semiconductor element (200). In addition, if the third width (W3) of the upper bonding portion (144) exceeds 0.95 times the second width (W2) of the through hole (121) of the upper protective layer (120), the third width (W3) may become larger than the second width (W2) due to process deviation, and thus the gap between the plurality of neighboring upper bonding portions may become narrower. In addition, in some cases, an electrical short circuit problem may occur in which the plurality of neighboring upper bonding portions are electrically connected to each other.

[0098] Additionally, the lower bonding portion (146) of the first circuit board (100) may have a fourth width (W4) that is larger than the first width (W1) of the terminal (210) and the third width (W3) of the upper bonding portion (144). Additionally, the fourth width (W4) of the lower bonding portion (146) may be smaller than the seventh width (W7) of the bonding portion (320) of the second circuit board (300).

[0099] Preferably, the fourth width (W4) of the lower bonding portion (146) of the first circuit board (100) may have a range of between 1.8 and 4 times the first width (W1) of the terminal (210). Alternatively, the fourth width (W4) of the lower bonding portion (146) of the first circuit board (100) may have a range of between 1.3 and 3 times the second width (W2) of the upper bonding portion (144). Alternatively, the fourth width (W4) of the lower bonding portion (146) of the first circuit board (100) may have a range of between 0.5 and 0.9 times the seventh width (W7) of the bonding portion (320) of the second circuit board (300). When the fourth width (W4) of the lower bonding portion (146) is less than 1.8 times the first width (W1) of the terminal (210), or less than 1.3 times the second width (W2) of the upper bonding portion (144), or less than 0.5 times the seventh width (W7) of the bonding portion (320) of the second circuit board (300), the difference in width between the lower bonding portion (146) of the first circuit board (100) and the bonding portion (320) of the second circuit board (300) may increase, and thus, signal communication characteristics between the first circuit board (100) and the second circuit board (300) may deteriorate. In addition, when the fourth width (W4) of the lower bonding portion (146) is more than four times the first width (W1) of the terminal (210), or more than three times the second width (W2) of the upper bonding portion (144), or more than 0.9 times the seventh width (W7) of the bonding portion (320) of the second circuit board (300), among the wiring electrodes (141, 142, 143, 145) provided between the upper bonding portion (144) and the lower bonding portion (146), a wiring electrode having a rapidly increasing width may be required, and accordingly, signal transmission characteristics may be deteriorated due to an increase in signal transmission loss in the wiring electrode having a rapidly increasing width.

[0100] In addition, the fourth width (W4) of the lower bonding portion (146) can satisfy a range of 0.55 to 0.95 times the sixth width (W6) of the through hole (131) of the lower protective layer (130). If the fourth width (W4) of the lower bonding portion (146) is less than 0.55 times the sixth width (W6) of the through hole (131) of the lower protective layer (130), the width of the lower bonding portion (146) may become too small, and the width difference with the terminal (210) of the semiconductor element (200) may become large, or the width difference with the bonding portion (320) provided on the second circuit board (310) may become large, and thus, signal transmission loss may increase, which may deteriorate communication characteristics. If the fourth width (W4) of the lower bonding portion (146) is less than 0.55 times the sixth width (W6) of the through hole (131) of the lower protective layer (130), the electrical characteristics may deteriorate, and communication may not be smooth between the first circuit board (100) and the semiconductor element (200) and / or the first circuit board (100) and the second circuit board (300). In addition, if the fourth width (W4) of the lower bonding portion (146) exceeds 0.95 times the sixth width (W6) of the through hole (131) of the lower protective layer (130), the fourth width (W4) may become larger than the sixth width (W6) due to process deviation, and thus the gap between the plurality of neighboring lower bonding portions may become narrower. In addition, in some cases, an electrical short circuit problem may occur in which the plurality of neighboring lower bonding portions are electrically connected to each other.

[0101] In addition, the horizontal width of the through hole (331) of the protective layer (330) of the second circuit board (300) may have a fifth width (W5) that is larger than the first width (W1), the second width (W2), the third width (W3), the fourth width (W4), and the seventh width (W7). At this time, the fifth width (W5) of the through hole (331) of the protective layer (330) of the second circuit board (300) may have a range of 1.25 to 2.5 times the fourth width (W4) of the lower bonding portion (146). Alternatively, the fifth width (W5) of the through hole (331) of the protective layer (330) of the second circuit board (300) may have a range of 2.5 to 6.5 times the first width (W1) of the terminal (210) of the semiconductor element (200). If the fifth width (W5) of the through hole (331) of the protective layer (330) of the second circuit board (300) is less than 1.25 times the fourth width (W4) of the lower bonding portion (146) or less than 2.5 times the first width (W1) of the terminal (210), it may be difficult to place a second connecting portion (500) of sufficient volume to electrically couple the lower bonding portion (146) of the first circuit board (100) and the bonding portion (320) of the second circuit board (300) within the through hole (331), and accordingly, the bonding strength between the lower bonding portion (146) of the first circuit board (100) and the bonding portion (320) of the second circuit board (300) may be reduced, resulting in an electrical open problem. If the fifth width (W5) of the through hole (331) of the protective layer (330) of the second circuit board (300) is less than 1.25 times the fourth width (W4) of the lower bonding portion (146), or less than 2.5 times the first width (W1) of the terminal (210), the second connection portion (500) disposed within the through hole (331) may overflow to the outside of the through hole (331), thereby causing an electrical short-circuit problem due to horizontal diffusion of the second connection portion (500). In addition, if the fifth width (W5) of the through hole (331) of the protective layer (330) of the second circuit board (300) is more than 2.5 times the fourth width (W4) of the lower bonding portion (146), or less than 6 times the first width (W1) of the terminal (210),If it exceeds 5 times, the volume of the second connecting portion (500) placed within the through hole (331) of the protective layer (330) of the second circuit board (300) may increase excessively, and the product manufacturing cost may increase accordingly.

[0102] In addition, the horizontal width of the through hole (131) of the lower protective layer (130) of the first circuit board (100) may have a sixth width (W6) that is larger than the seventh width (W7) of the bonding portion (320) of the second circuit board (300). Preferably, the sixth width (W6) of the through hole (131) of the lower protective layer (130) of the first circuit board (100) may satisfy a range of 1.1 to 2 times the seventh width (W7) of the bonding portion (320) of the second circuit board (300). Alternatively, the sixth width (W6) of the through hole (131) of the lower protective layer (130) of the first circuit board (100) may satisfy a range of 2.2 to 6 times the first width (W1) of the terminal (210) of the semiconductor element (200). Alternatively, the sixth width (W6) of the through hole (131) of the lower protective layer (130) of the first circuit board (100) may satisfy a range of 1.5 to 4 times the second width (W2) of the through hole (121) of the upper protective layer (120). If the sixth width (W6) of the through hole (131) of the lower protective layer (130) of the first circuit board (100) is less than 1.1 times the seventh width (W7) of the bonding portion (320) of the second circuit board (300) or less than 2.2 times the first width (W1) of the terminal (210) of the semiconductor element (200), it may be difficult to arrange a second connecting portion (500) of sufficient volume within the through hole (131), or it may be difficult for the through hole (131) to function as a dam to prevent the horizontal diffusion of the second connecting portion (500). If the sixth width (W6) of the through hole (131) of the lower protective layer (130) of the first circuit board (100) exceeds twice the seventh width (W7) of the bonding portion (320) of the second circuit board (300) or six times the first width (W1) of the terminal (210) of the semiconductor element (200), the volume of the second connection portion (500) may increase excessively, causing an increase in the unit price of the product or making it difficult to miniaturize the semiconductor package. In addition, if the sixth width (W6) of the through hole (131) of the lower protective layer (130) of the first circuit board (100) exceeds 1.0 times the second width (W2) of the through hole (121) of the upper protective layer (120),If the range is exceeded by 5 to 4 times, the effect of preventing the first circuit board (100) from being bent in a specific direction, which can be achieved through the difference in the planar area of ​​the upper protective layer (120) and the lower protective layer (130), may be insufficient, and thus the electrical reliability and / or mechanical reliability of the semiconductor package may be reduced.

[0103] As described above, the embodiment can control the relationship between the horizontal width of the terminal (210) provided in the semiconductor element (200), the horizontal width of the through hole (121) of the upper protective layer (120) of the first circuit board (100), the horizontal width of the upper bonding portion (144) of the first circuit board (100), the horizontal width of the through hole (131) of the lower protective layer (130) of the first circuit board (100), the horizontal width of the lower protective layer (130) of the first circuit board (100), the horizontal width of the bonding portion (320) of the second circuit board (300), and the horizontal width of the through hole (331) of the protective layer (330) of the second circuit board (300). Through this, the embodiment can secure sufficient volume of the first connection portion (400) and / or the second connection portion (500) within a range that does not affect the circuit integration, thereby improving the electrical coupling strength between them, and thus improving the signal communication characteristics between them. Furthermore, the embodiment can prevent the semiconductor package from being significantly bent in a specific direction.

[0104]

[0105] FIG. 5 is a drawing showing a detailed configuration of the first circuit board illustrated in FIG. 1 according to the second embodiment.

[0106] Referring to FIG. 5, the first circuit board includes an insulating layer (1110) including a core layer (1111), an upper build-up layer (1112), and a lower build-up layer (1113). In addition, the first circuit board includes wiring electrodes (1141, 1142, 1143, 1144, 1145, 1146) and via electrodes (1151, 1152, 1153, 1154, 1155). In addition, the first circuit board includes an insulating member (1111-1) penetrating the core layer (1111). In addition, the first circuit board includes an upper protective layer (1120) and a lower protective layer (1130).

[0107] At this time, the basic structural features of each component of the first circuit board are the same as the structural features of each corresponding component of the first circuit board of the first embodiment described with reference to FIG. 2, and thus, redundant descriptions thereof are omitted.

[0108] The first circuit board further includes a connecting member (2000). The connecting member (2000) may be embedded in the first circuit board. Preferably, the connecting member (2000) may be embedded in the insulating layer (1110) of the first circuit board. For example, the core layer (1111) of the insulating layer (1110) may have a cavity in which the connecting member (2000) is disposed, and the connecting member (2000) may be disposed in the cavity of the core layer (1111). At this time, the location of the cavity of the connecting member (2000) is not limited to the core layer (1111), and the cavity may be disposed in the upper build-up layer (1112), or may be partially disposed in each of the core layer (1111) and the upper build-up layer (1112).

[0109] The connecting member (2000) can be embedded in the first circuit board and made of at least one material selected from the group consisting of silicon, organic materials, and glass, thereby electrically connecting a plurality of semiconductor elements attached to the first circuit board.

[0110] The connecting member (2000) may be a die. At this time, although FIG. 5 illustrates one connecting member (2000) being arranged within the first circuit board, this is not limited thereto, and two or more connecting members may be arranged within the first circuit board, spaced apart horizontally and / or vertically.

[0111] In one embodiment, the connecting member (2000) may be a bridge die. For example, the connecting member (2000) partially overlaps vertically with the semiconductor elements (200a, 200b) arranged on the first circuit board.

[0112] Additionally, the connecting member (2000) electrically connects a portion of the terminal of the first semiconductor element (200a) and a portion of the terminal of the second semiconductor element (200b).

[0113] A plurality of semiconductor devices having different functions, such as a CPU and a GPU, a GPU and an HBM, or a plurality of chiplet units separated according to functionality and / or pitch, may be mounted on a first circuit board, and a connecting member (2000) may function to horizontally electrically connect them. The connecting member (2000) includes a pad portion (2100) connected to an electrode portion of the first circuit board.

[0114] In addition, the upper bonding portion of the first circuit board can be divided into a first upper bonding portion (1144a) and a second upper bonding portion (1144b) depending on the position. The first upper bonding portion (1144a) can be electrically connected to the terminal of the semiconductor element (200) without vertically overlapping with the connecting member (2000). Accordingly, the first upper bonding portion (1144a) can have a width (W3) in the horizontal direction corresponding to the upper bonding portion (144) described in the first embodiment.

[0115] In contrast, the second upper bonding portion (1144b) may overlap the connecting member (2000) in the vertical direction. For example, the second upper bonding portion (1144b) may be electrically connected to the pad portion (2100) of the connecting member (2000). At this time, the second upper bonding portion (1144b) may have a function of connecting the pad portion (2100) of the connecting member (2000) and the terminal (210) of the semiconductor element (200), unlike the first upper bonding portion (1144a), and thus may have a different width from the first upper bonding portion (1144a). For example, the second upper bonding portion (1144b) may have a ninth width (W9) smaller than the first upper bonding portion (1144a). The ninth width (W9) of the second upper bonding portion (1144b) can satisfy a range of 0.5 to 1.2 times the first width (W1) of the terminal (210) of the semiconductor element (200). If the ninth width (W9) of the second upper bonding portion (1144b) is less than 0.5 times the first width (W1) of the terminal (210) of the semiconductor element (200), the electrical bonding force between the terminal (210) of the semiconductor element (200) and the second upper bonding portion (1144b) may be reduced, and thus the electrical reliability may be reduced. In addition, if the ninth width (W9) of the second upper bonding portion (1144b) exceeds 1.2 times the first width (W1) of the terminal (210) of the semiconductor element (200), it may be difficult to place all of the second upper bonding portions (1144b) within a limited space, and thus the circuit integration may be reduced.

[0116] Additionally, the through hole of the upper protective layer (1120) includes a first through hole (1121) that vertically overlaps with the first upper bonding portion (1144a). At this time, the first through hole (1121) may have a second width (W2) corresponding to the width of the through hole (121) of the upper protective layer (120) described in the first embodiment.

[0117] In addition, the through hole of the upper protective layer (1120) may further include a second through hole (1122) that vertically overlaps with the second upper bonding portion (1144b). At this time, the second through hole (1122) may have an eighth width (W8) that is smaller than the second width (W2) of the first through hole (1121). Preferably, the eighth width (W8) of the second through hole (1122) may have a range between 0.7 and 1.25 times the first width (W1) of the terminal (210) of the semiconductor element (200). If the eighth width (W8) of the second through hole (1122) is less than 0.7 times the first width (W1) of the terminal (210) of the semiconductor element (200), it is difficult to secure a sufficient volume of the first connection portion (400) arranged within the second through hole (1122), which may result in a decrease in electrical bonding strength, or the first connection portion (400) may overflow to the outside of the second through hole (1122), which may result in an electrical short circuit problem. If the eighth width (W8) of the second through hole (1122) exceeds 1.25 times the first width (W1) of the terminal (210) of the semiconductor element (200), it may be difficult to arrange all of the second upper bonding portions (1144b) within a limited space, which may result in a decrease in circuit integration.

[0118] In this way, the second embodiment includes a connecting member (2000), and accordingly, the first upper bonding portion (1144a) and the second upper bonding portion (1144b) provided on the first circuit board can have different widths in the horizontal direction, and further, the first through hole (1121) and the second through hole (1122) of the upper protective layer (1120) can have different widths. Through this, it is possible to secure a sufficient volume of the first connecting portion corresponding to each function and / or position of the upper bonding portion, while preventing the first connecting portion from overflowing.

[0119]

[0120] Meanwhile, when a semiconductor package having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, a semiconductor package having the characteristics of the invention can safely protect a semiconductor chip from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying the semiconductor chip. Furthermore, when it is responsible for the function of signal transmission, it can solve noise problems. Through this, a semiconductor package having the characteristics of the invention described above can maintain the stable function of an IT device or home appliance, thereby achieving functional integration or technical interoperability between the entire product and the semiconductor package to which the invention is applied.

[0121] When a semiconductor package having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuits between terminals, or electrical open circuits of terminals supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the semiconductor package to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0122] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0123] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Insulating layer; An upper bonding portion disposed on the insulating layer; and An upper protective layer is disposed on the insulating layer and includes a first through hole vertically overlapping the upper bonding portion, The horizontal width of the upper bonding portion satisfies a range between 0.55 and 0.95 times the horizontal width of the first through hole. Circuit board.

2. In paragraph 1, Further comprising a lower bonding portion arranged on the lower surface of the insulating layer, The horizontal width of the lower bonding portion satisfies a range of 1.3 to 3 times the horizontal width of the upper bonding portion. Circuit board.

3. In paragraph 2, Further comprising a lower protective layer having a second through hole disposed on the lower surface of the insulating layer and vertically overlapping the lower bonding portion. Circuit board.

4. In paragraph 3, The horizontal width of the second through hole is greater than the horizontal width of the first through hole. Circuit board.

5. In paragraph 4, The horizontal width of the second through hole satisfies a range of 1.5 to 4 times the horizontal width of the first through hole. Circuit board.

6. In paragraph 3, The horizontal width of the lower bonding portion satisfies a range between 0.55 and 0.95 times the horizontal width of the second through hole. Circuit board.

7. In paragraph 3, Further comprising a connecting member embedded within the insulating layer, The first through hole includes a first through hole that does not vertically overlap with the connecting member, and a first through hole that vertically overlaps with the connecting member. The horizontal width of the above 1-1 through hole is greater than the horizontal width of the above 1-2 through hole. Circuit board.

8. In paragraph 7, The upper bonding portion includes a first upper bonding portion disposed within the first through hole and not vertically overlapping with the connecting member, and a second upper bonding portion disposed within the first through hole and vertically overlapping with the connecting member. The horizontal width of the first upper bonding portion is greater than the horizontal width of the second upper bonding portion. Circuit board.

9. A circuit board included in any one of clauses 3 to 8; and Further comprising a semiconductor element disposed on the circuit board and having a terminal facing the upper bonding portion, The horizontal width of the upper bonding portion satisfies a range between 1.25 and 2.5 times that of the terminal. Semiconductor package.

10. In paragraph 9, The horizontal width of the upper bonding portion satisfies a range between 1.05 and 2 times the horizontal width of the terminal. Semiconductor package.

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