Apparatus and method for sleep clock calibration and timing-error compensation for discontinuous reception

Abstract

According to another aspect of the present disclosure, a method of wireless communication of a user equipment is provided. The method may include obtaining, by at least one processor, at least one temperature reading associated with a first crystal clock source at a wakeup time from a DRX off-duration. The method may include accessing a frequency stability versus temperature curve at the wakeup time from the DRX off-duration. The method may include estimating a timing offset associated with the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve.

Description

APPARATUS AND METHOD FOR SLEEP CLOCK CALIBRATION AND TIMING-ERROR COMPENSATION FOR DISCONTINUOUS RECEPTIONBACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In cellular communication, such as the 4th-gen eration (4G) Long Term Evolution (LTE) and the 5th- generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various procedures for discontinuous reception (DRX).SUMMARY

[0003] According to one aspect of the present disclosure, an apparatus for wireless communication of a user equipment is provided. The apparatus may include at least one processor. The apparatus may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to obtain at least one temperature reading associated with a first crystal clock source at a wakeup time from a DRX off-duration. The apparatus may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to access a frequency stability versus temperature curve at the wakeup time from the DRX off-duration. The apparatus may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to estimate a timing offset associated with the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve.

[0004] According to another aspect of the present disclosure, a method of wireless communication of a user equipment is provided. The method may include obtaining, by at least one processor, at least one temperature reading associated with a first crystal clock source at a wakeup time from a DRX off-duration. The method may include accessing a frequency stability versus temperature curve at the wakeup time from the DRX off-duration. The method may include estimating a timing offset associated with the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versustemperature curve.

[0005] According to a further aspect of the present disclosure, a non-transitory computer- readable medium for a user equipment is provided. The non-transitory computer-readable medium may store instructions, which when executed by at least one processor of the user equipment, cause the at least one processor to obtain at least one temperature reading associated with a first crystal clock source at a wakeup time from a DRX off-duration. The non-transitory computer-readable medium may store instructions, which when executed by at least one processor of the user equipment, cause the at least one processor to access a frequency stability versus temperature curve at the wakeup time from the DRX off-duration. The non-transitory computer-readable medium may store instructions, which when executed by at least one processor of the user equipment, cause the at least one processor to estimate a timing offset associated with the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve.

[0006] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0009] FIG. 2 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0010] FIG. 3 illustrates a block diagram of an exemplary apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0011] FIG. 4 illustrates an exemplary timing relationship between a system common timer and crystal counters, according to some embodiments of the present disclosure.

[0012] FIG. 5 illustrates a first timing diagram of an exemplary sleep clock calibrationtechnique, according to some embodiments of the present disclosure.

[0013] FIG. 6 illustrates a second timing diagram of the exemplary sleep clock calibration technique, according to some embodiments of the present disclosure.

[0014] FIG. 7 illustrates a flowchart of a method of wireless communication, according to some embodiments of the present disclosure.

[0015] Embodiments of the present disclosure will be described with reference to the accompanying drawings.DETAILED DESCRIPTION

[0016] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0017] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0018] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0019] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0020] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 1000, etc. A TDMA network may implement a RAT, such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as LTE or NR. A WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0021] In a 5G NR network, DRX may be implemented to conserve user equipment (UE) battery power in the radio resource control (RRC) connected mode or idle mode. DRX mode may be configured when the network determines there are no scheduled downlink (DL) or uplink (UL) packets for communication with the UE. In normal operation (e.g., non-DRX operation), the UE remains awake all the time to monitor the physical downlink control channel (PDCCH). On the other hand, if DRX is configured by the network, the UE may enter a sleep state during which the UE does not need to monitor the PDCCH during predetermined sleep periods of a DRX cycle. These sleep periods are referred to as an “off-duration.” While in DRX mode, the UE periodically wakes up during an “on-duration” to monitor the PDCCH for incoming downlink transmission(s) during the on-duration of the DRX cycle.

[0022] Moreover, the UE’s modem (also referred to as a “baseband chip”) may be designed with two crystals. One crystal is a high-speed crystal (e.g., XO crystal) that generates the clocktiming / frequency used by the entire modem when the UE operates in non-DRX mode or during the on-duration of a DRX cycle. The other crystal is an “always-on,” low-speed crystal (e.g., a 32kHz crystal, sleep crystal, etc.) that provides a reference clock for tracking the off-duration and timing recovery upon wakeup. The XO crystal may set the frequency and timing for the system time counter (STC) counter of the modem’s STC, while the low-speed crystal may set the frequency and timing for the sleep counter of the modem’s sleep clock.

[0023] Conventional sleep clock calibration may be achieved via a hardware component in which two hardware counters are driven by the fast and low-speed crystals separately. The hardware component may follow the counter values of the sleep clock and the STC at the low- speed crystal’s rising edge. Using the two counter values, the UE can calculate the normalized clock frequency ratio between two crystals. At the start of the off-duration of each DRX cycle, the XO crystal may be powered down to reduce power consumption, and the low-speed crystal’s sleep counter is used to track the timing of the off-duration and the timing recovery at the start of the on- duration. The output frequency of the crystals can drift due to changes in temperature. Frequency drift increases as the temperature rises. This can lead to a large timing / frequency error, which degrades the UE’s PDCCH decoding performance during the on-duration.

[0024] However, existing sleep clock calibration techniques fail to consider the temperature change during the off duration. Therefore, UE may need extra wakeup time prior to the start of the on-duration to estimate and correct this type of timing error. Furthermore, hardwarebased calibration accuracy depends on the calibration time and speed of the low-speed crystal. Even without temperature change, the sleep clock timing accuracy is proportional to calibration time. In high signal-to-noise ratio (SNR) environments, the UE wakes up for a short time to decode the PDCCH. For hardware-based calibration to finish within a short wakeup time (e.g., to avoid using extra wakeup time), a higher speed sleep crystal frequency is required. However, it can significantly increase modem power consumption due to a larger leakage current.

[0025] To overcome these and other challenges, the present disclosure provides an exemplary software-based sleep clock calibration technique that enables a baseband chip to select timing-offset associated with a sleep-state of the sleep crystal based on a frequency stability versus temperature (AF / T) curve. For example, the baseband chip may obtain temperature readings of the sleep crystal obtained during the off-duration, which are compared to the AF / T curve at a wakeup time to select the timing-offset. To that end, the present baseband may be designed with a temperature sensor, which continuously and / or periodically monitors the temperature of the sleepcrystal during the off duration. At wakeup time, the baseband chip may access the AF / T curve and obtain the temperature readings. Based on a comparison of the temperature readings to the AF / T curve, the baseband chip may estimate the timing-offset of the sleep crystal. This information may be used to implement baseband chip clock timing recovery upon wakeup with limited or no timing error before PDCCH decoding. Using the present techniques, an extended sleep state may be provided because the extra warmup / clock pre-synchronization needed to correct timing errors may be eliminated, thereby providing further power savings and a reduction of computational complexity. Furthermore, using the absolute crystal error identified at the start and the end of each off-duration, the AF / T curve may be updated or generated to further enhance the accuracy of the timing-error estimation. Additional details of the exemplary software-based sleep clock calibration technique are provided below in connection with FIGs. 1-7.

[0026] FIG. 1 illustrates an exemplary wireless network 100, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 1, wireless network 100 may include a network of nodes, such as user equipment 102, an access node 104, and a core network element 106. User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (loT) node. It is understood that user equipment 102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0027] Access node 104 may be a device that communicates with user equipment 102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to user equipment 102, a wireless connection to user equipment 102, or any combination thereof. Access node 104 may be connected to user equipment 102 by multiple connections, and user equipment 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to other user equipments. When configured as a gNB, access node 104 may operate in millimeter wave (mmW) frequencies and / or near mmW frequencies in communication with the user equipment 102. When access node 104 operates in mmW or near mmW frequencies, the access node 104 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the radio frequency (RF) in the electromagneticspectrum. EHF has a range of 30 GHz to 200 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 100 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 102 to compensate for the extremely high path loss and short range. It is understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0028] Access nodes 104, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 104 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 104 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0029] Core network element 106 may serve access node 104 and user equipment 102 to provide core network services. Examples of core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 106 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 102 and the 5GC. Generally, the AMF provides QoS flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides user equipment (UE) IP address allocation as wellas other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and / or other IP services. It is understood that core network element 106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0030] Core network element 106 may connect with a large network, such as the Internet 108, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 102 may be communicated to other user equipments connected to other access points, including, for example, a computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114. Thus, computer 110 and tablet 112 provide additional examples of possible user equipments, and router 114 provides an example of another possible access node.

[0031] A generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as a database 116, and security and authentication servers, such as an authentication server 118. Database 116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack.

[0032] Each element in FIG. 1 may be considered a node of wireless network 100. More detail regarding the possible implementation of a node is provided by way of an example in the description of a node 200 in FIG. 2. Node 200 may be configured as user equipment 102, access node 104, or core network element 106 in FIG. 1. Similarly, node 200 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1. As shown in FIG. 2, node 200 may include a processor 202, a memory 204, and a transceiver 206. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 200 is user equipment 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 200 may be implemented as a blade in a server system when node 200 is configured as core network element106. Other implementations are also possible.

[0033] Transceiver 206 may include any suitable device for sending and / or receiving data. Node 200 may include one or more transceivers, although only one transceiver 206 is shown for simplicity of illustration. An antenna 208 is shown as a possible communication mechanism for node 200. Multiple antennas and / or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 200 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 104 may communicate wirelessly to user equipment 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0034] As shown in FIG. 2, node 200 may include processor 202. Although only one processor is shown, it is understood that multiple processors can be included. Processor 202 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 202 may be a hardware device having one or more processing cores. Processor 202 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software.

[0035] As shown in FIG. 2, node 200 may also include memory 204. Although only one memory is shown, it is understood that multiple memories can be included. Memory 204 can broadly include both memory and storage. For example, memory 204 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc readonly memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that canbe accessed and executed by processor 202. Broadly, memory 204 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0036] Processor 202, memory 204, and transceiver 206 may be implemented in various forms in node 200 for performing wireless communication functions. In some embodiments, at least two of processor 202, memory 204, and transceiver 206 are integrated into a single system- on-chip (SoC) or a single system-in-package (SiP). In some embodiments, processor 202, memory 204, and transceiver 206 of node 200 are implemented (e.g., integrated) on one or more SoCs. In one example, processor 202 and memory 204 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 202 and memory 204 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 202 and transceiver 206 (and memory 204 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 208. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0037] Referring back to FIG. 1, in some embodiments, user equipment 102 may implement the exemplary software-based sleep clock calibration technique, which enables its baseband chip to select a sleep crystal timing-offset based on a AF / T curve, e.g., as described below in connection with FIGs. 3-7.

[0038] FIG. 3 illustrates a block diagram of an exemplary apparatus 300 including a baseband chip 302, an RF chip 304, and a host chip 306, according to some embodiments of the present disclosure.

[0039] Referring to FIG. 3, apparatus 300 may be implemented as user equipment 102 of wireless network 100 in FIG. 1. As shown in FIG. 3, apparatus 300 may include baseband chip 302, RF chip 304, host chip 306, and one or more antennas 310. In some embodiments, baseband chip 302 is implemented by a processor and a memory, and RF chip 304 is implemented by a processor, a memory, and a transceiver. Besides the on-chip memory 313 (also known as “internalmemory,” e.g., registers, buffers, or caches) on each chip 302, 304, or 306, apparatus 300 may further include an external memory 308 (e.g., the system memory or main memory) that can be shared by each chip 302, 304, or 306 through the system / main bus. Although baseband chip 302 is illustrated as a standalone SoC in FIG. 3, it is understood that in one example, baseband chip 302 and RF chip 304 may be integrated as one SoC or one SiP; in another example, baseband chip 302 and host chip 306 may be integrated as one SoC or one SiP; in still another example, baseband chip 302, RF chip 304, and host chip 306 may be integrated as one SoC or one SiP, as described above.

[0040] In the uplink, host chip 306 may generate raw data and send it to baseband chip 302 for encoding, modulation, and mapping. Interface 311 of baseband chip 302 may receive the data from host chip 306. Baseband chip 302 may also access the raw data generated by host chip 306 and stored in external memory 308, for example, using the direct memory access (DMA). Baseband chip 302 may first encode (e.g., by source coding and / or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 302 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 302 may send the modulated signal to RF chip 304 via interface 311. RF chip 304, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 310 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 304.

[0041] In the downlink, antenna 310 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 304. RF chip 304 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 302. RF chip 304 may receive a combined channel (e.g., a combined signal) that includes a serving cell channel and an interfering cell channel. Interface 311 (e.g., a communication interface) may receive the combined channel from RF chip 304.

[0042] Still referring to FIG. 3, baseband chip 302 may include a system common timer 320, an STC 322, a sleep clock 324, an always-on (AON) component 326, and an automatic timingcontrol (ATC) component 328. Sleep clock 324 may include the first crystal (e.g., a 32kHz crystal) and a sleep clock counter, while STC 322 includes a second crystal (e.g., an XO crystal) and an STC counter. System common timer 320 and STC 322 may be configured to enter a sleep-state during an off-duration, while sleep clock 324 and AON component 326 may remain in an awake state during the off-duration. System common timer 320 may include, e.g., software and / or firmware configured to implement the exemplary software-based sleep clock calibration technique. For example, system common timer 320 may determine the timing-offset associated with the sleep clock 324 based on temperature readings obtained by the temperature sensor of AON component 326 and a AF / T curve. The AF / T curve may be maintained in on-chip memory 313 and / or external memory 308. Additional details of the exemplary software-based sleep clock calibration technique are provided below in connection with FIGs. 4-7.

[0043] FIG. 4 illustrates an exemplary timing relationship 400 between system common timer 320, STC 322, and sleep clock 324 of FIG. 3, according to some embodiments of the present disclosure. FIG. 5 illustrates a first timing diagram 500 of an exemplary sleep clock calibration technique implemented by baseband chip 302 of FIG. 3, according to some embodiments of the present disclosure. FIG. 6 illustrates a second timing diagram 600 of the exemplary sleep clock calibration technique implemented by baseband chip 302 of FIG. 3, according to some embodiments of the present disclosure. FIGs. 4-6 will be described together.

[0044] Referring to FIG. 4, system common timer 320 may include a frequency-error adjusted system common timer 402, which may be implemented using software or firmware. STC 322 may include an STC counter 404 driven by second crystal 406. Sleep clock 324 may include a sleep counter 408 driven by first crystal 410. In some embodiments, first crystal 410 may be replaced with a microelectromechanical (MEMS) system oscillator. STC counter 404 and system common timer 320 may be derived from each other, as described below.

[0045] For example, the relative frequency error of first crystal 410 with respect to second crystal 406 may be obtained by system common timer 320 according to expression (1).where fedeltaisthe relative frequency error of first crystal 410 with respect to second crystal 406, L is the value of sleep counter 408, F is the value of STC counter 404,are the latched counter values at time instance i and j, respectively, Rxois the ideal frequency of second crystal 406, and R^k is the ideal frequency of first crystal 410.

[0046] Assuming system common timer 320 uses the same frequency as first crystal 410,expression (1) may be converted to expression (2).where fexois the normalized frequency error of second crystal 406, and and Sj are the value of system common timer 320 at time instances i and j, respectively.

[0047] Furthermore, expression (3) shows the relationship between the normalized frequency errors of second crystal 406 and first crystal 410 and the relative frequency error.where / e32kis the normalized frequency error of first crystal 410.

[0048] Accordingly, / e32kmay be derived according to expression (4).

[0049] Expression (4) reveals the relationship between the system common timer and the sleep clock, which may be used for the exemplary software-based sleep clock calibration technique, as illustrated in FIG. 5.

[0050] Referring to FIG. 5, the time instances used for software calibration by system common timer 320 may be chosen as the sleep time (z) and wakeup time ( / ). During the off- duration, frequency-error adjusted system common timer 402 is not running. Therefore, the software / firmware has to recover the value of system common timer 402 Sj before PDCCH decoding begins. For example, the software / firmware of system common timer 320 may use the best estimate of sleep clock error / e32kat time instance j and the expected length of the off-duration (Li — Lj) to compute Sj at DRX wakeup. However, this value may not be accurate due to the sleep clock frequency error estimation. The sleep clock frequency estimation causes a wakeup timing error, which can be captured by ATC component 328 at the time of wakeup. Denoting the timing correction from ATC component 328 as , the f?2kmay be updated according to expression (5).

[0051] Since the software calibration of sleep clock 324 generates the estimation of the sleep clock normalized frequency error / e32 krather than its relative error fedeltawith respect to first crystal 410, the estimate can be used along with temperature readings To, Ti, T2,... Tnto build the AF / T curve of second crystal 406 and improve the accuracy of timing-offset accuracy upon DRX wakeup.

[0052] Referring to FIG. 6, to facilitate the temperature reading based sleep clock errorcompensation, at least one temperature sensor may be included in AON component 326 to monitor the temperature change of second crystal 406. AON component 326 may be programmed to measure a plurality of temperature readings To, Ti, T2, ... Tnduring the off duration. Prior to entering sleep mode at time instance z, the software of system common timer 320 may estimate (at 601) the sleep clock timing / frequency error and update the AF / T curve. Hence, baseband chip 302 may pre-configure the number of n temperature readings before entering sleep mode based on the known length of the off duration. AON component 326 counts the sleep duration using sleep counter 408 and measures (at 603) the temperature of second crystal 406 periodically. AON component 326 may maintain the temperature readings during the off duration. Prior to system common timer Sj recovery, the software of system common timer 320 may read (at 605) the stored temperature readings and use the AF / T curve to compute the amount of timing error that was introduced during the off duration. The ATC correction may be applied (at 607) the frequency error estimation of first crystal 410 computed (at 601) at the start of the DRX off-duration. The AF / T curve may be updated (at 605) based on the updated frequency error estimation of first crystal 410. Then, the value of system common timer Sj at the start of the on-duration may be recovered (at 605) based on a comparison of the temperature readings and the updated AF / T curve.

[0053] FIG. 7 illustrates a flowchart of an exemplary method 700 of wireless communication, according to some embodiments of the present disclosure. Method 700 may be performed by an apparatus, e.g., such as a UE, a node, a baseband chip, a system common timer, an STC, a sleep clock, an AON component, and / or an ATC component, just to name a few. Method 700 may include steps 702-706 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 7.

[0054] Referring to FIG. 7, at 702, the apparatus may obtain at least one temperature reading associated with a first crystal clock source at a wakeup time from a DRX off-duration. For example, referring to FIGs. 3 and 6, to facilitate the temperature reading based sleep clock error compensation, at least one temperature sensor may be included in AON component 326 to monitor the temperature change of second crystal 406. AON component 326 may be programmed to measure a plurality of temperature readings To, Ti, T2,... Tnduring the off-duration. Prior to system common timer Sj recovery, the software of system common timer 320 may read (at 605) the stored temperature readings from AON component 326.

[0055] At 704, the apparatus may access a frequency stability versus temperature curve atthe wakeup time from the DRX off-duration. For example, referring to FIGs. 3 and 6, system common timer 320 may access the AF / T curve from, e.g., on-chip memory 313 and / or external memory 308.

[0056] At 706, the apparatus may estimate a timing offset associated with the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve. For example, referring to FIGs. 3 and 6, Prior to entering sleep mode at time instance z, the software of system common timer 320 may estimate (at 601) the sleep clock timing / frequency error and update the AF / T curve. Hence, baseband chip 302 may pre-configure the number of n temperature readings before entering sleep mode based on the known length of the off duration. AON component 326 counts the sleep duration using sleep counter 408 and measures (at 603) the temperature of second crystal 406 periodically. AON component 326 may maintain the temperature readings during the off duration. Prior to system common timer Sj recovery, the software of system common timer 320 may read (at 605) the stored temperature readings and use the AF / T curve to compute the amount of timing error that was introduced during the off duration. The ATC correction may be applied (at 607) the frequency error estimation of first crystal 410 computed (at 601) at the start of the DRX off- duration. The AF / T curve may be updated (at 605) based on the updated frequency error estimation of first crystal 410. Then, the value of system common timer Sj at the start of the on-duration may be recovered (at 605) based on a comparison of the temperature readings and the updated AF / T curve.

[0057] Using the exemplary software-based sleep clock calibration technique described above in connection with FIGs. 1-7 may result in a significant reduction in calibration time, as compared to conventional hardware-based methods. Therefore, the user equipment of the present disclosure may wake up later than its conventional counterparts to perform sleep clock calibration. The exemplary software-based calibration technique produces the absolute normalized frequency error of the first and / or second crystal rather than the relative error between the two. Thus, the AF / T curve can be built and stored on the on-chip memory of the baseband chip or external memory. The AF / T curve may be used to predict the unknown timing error caused by temperature change during the off duration. The user equipment described above may use temperature readings of the sleep crystal (e.g., 32kHz crystal) along with the AF / T curve to pre-compensate the timing drift caused by temperature change. Therefore, the present user equipment will estimate timing error offset and ATC convergence with a greater degree of accuracy, as compared to conventionaluser equipments. The present techniques may also reduce power consumption since no extra warmup time is required for loop convergence, and signal quality is improved due to smaller timing errors.

[0058] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 200 in FIG. 2. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital video disc (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0059] According to one aspect of the present disclosure, an apparatus for wireless communication of a user equipment is provided. The apparatus may include at least one processor. The apparatus may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to obtain at least one temperature reading associated with a first crystal clock source at a wakeup time from a DRX off-duration. The apparatus may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to access a frequency stability versus temperature curve at the wakeup time from the DRX off-duration. The apparatus may include memory storing instructions, which when executed by the at least one processor, cause the at least one processor to estimate a timing offset associated with the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve.

[0060] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to cause the second crystal clock source to enter a sleep state at a start of a DRX off-duration.

[0061] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to estimate a first frequencyerror of the first crystal clock source at a start of the DRX off-duration. In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to update the frequency stability versus temperature curve based on the first frequency error of the first crystal clock source.

[0062] In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to cause a temperature sensor to measure the at least one temperature reading of the first crystal clock source during the DRX off-duration. In some embodiments, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to maintain the at least one temperature reading during the DRX off-duration.

[0063] In some embodiments, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to obtain a wakeup-time timing error estimation associated with the first crystal clock source.

[0064] In some embodiments, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to estimate a second frequency error of the first crystal clock source at an end of the DRX off-duration based on the wakeup-time timing error estimation. In some embodiments, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to update the frequency stability versus temperature curve based on the second frequency error of the first crystal clock source.

[0065] In some embodiments, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the memory storing instructions, which when executed by the at least one processor, may further cause the at least one processor to compare the at least one temperature reading to the frequency stability versus temperature curve updated with the first frequency error and the second frequency error of the first crystal clock source to estimatethe timing offset of the first crystal clock source that occurs during the DRX off-duration.

[0066] According to another aspect of the present disclosure, a method of wireless communication of a user equipment is provided. The method may include obtaining, by at least one processor, at least one temperature reading associated with a first crystal clock source at a wakeup time from a DRX off-duration. The method may include accessing a frequency stability versus temperature curve at the wakeup time from the DRX off-duration. The method may include estimating a timing offset associated with the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve.

[0067] In some embodiments, the method may include causing, by the at least one processor, the second crystal clock source to enter a sleep state at a start of a DRX off-duration.

[0068] In some embodiments, the method may include estimating, by the at least one processor, a first frequency error of the first crystal clock source at a start of the DRX off-duration. In some embodiments, the method may include updating, by the at least one processor, the frequency stability versus temperature curve based on the first frequency error of the first crystal clock source.

[0069] In some embodiments, the method may include causing, by the at least one processor, a temperature sensor to measure the at least one temperature reading of the first crystal clock source during the DRX off-duration. In some embodiments, the method may include maintaining, by the at least one processor, the at least one temperature reading during the DRX off-duration.

[0070] In some embodiments, the estimating, by the at least one processor, the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve may include obtaining, by the at least one processor, a wakeup-time timing error estimation associated with the first crystal clock source.

[0071] In some embodiments, the estimating, by the at least one processor, the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve may include estimating a second frequency error of the first crystal clock source at an end of the DRX off-duration based on the wakeup-time timing error estimation. In some embodiments, the estimating, by the at least one processor, the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve may include updating the frequency stability versus temperature curve based on the second frequency error of the first crystal clock source.

[0072] In some embodiments, the estimating, by the at least one processor, the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve may include comparing the at least one temperature reading to the frequency stability versus temperature curve updated with the first frequency error and the second frequency error of the first crystal clock source to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration.

[0073] According to a further aspect of the present disclosure, a non-transitory computer- readable medium for a user equipment is provided. The non-transitory computer-readable medium may store instructions, which when executed by at least one processor of the user equipment, cause the at least one processor to obtain at least one temperature reading associated with a first crystal clock source at a wakeup time from a DRX off-duration. The non-transitory computer-readable medium may store instructions, which when executed by at least one processor of the user equipment, cause the at least one processor to access a frequency stability versus temperature curve at the wakeup time from the DRX off-duration. The non-transitory computer-readable medium may store instructions, which when executed by at least one processor of the user equipment, cause the at least one processor to estimate a timing offset associated with the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve.

[0074] In some embodiments, the instructions, which when executed by the at least one processor of the user equipment, may further cause the at least one processor to estimate a first frequency error of the first crystal clock source at a start of the DRX off-duration. In some embodiments, the instructions, which when executed by the at least one processor of the user equipment, may further cause the at least one processor to update the frequency stability versus temperature curve based on the first frequency error of the first crystal clock source.

[0075] In some embodiments, the instructions, which when executed by the at least one processor of the user equipment, may further cause the at least one processor to cause a temperature sensor to measure the at least one temperature reading of the first crystal clock source during the DRX off-duration. In some embodiments, the instructions, which when executed by the at least one processor of the user equipment, may further cause the at least one processor to maintain theat least one temperature reading during the DRX off-duration.

[0076] In some embodiments, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the instructions, which when executed by the at least one processor of the user equipment, may further cause the at least one processor to obtain a wakeup-time timing error estimation associated with the first crystal clock source.

[0077] In some embodiments, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the instructions, which when executed by the at least one processor of the user equipment, may further cause the at least one processor to estimate a second frequency error of the first crystal clock source at an end of the DRX off-duration based on the wakeup-time timing error estimation. In some embodiments, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the instructions, which when executed by the at least one processor of the user equipment, may further cause the at least one processor to update the frequency stability versus temperature curve based on the second frequency error of the first crystal clock source.

[0078] In some embodiments, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the instructions, which when executed by the at least one processor of the user equipment, may further cause the at least one processor to compare the at least one temperature reading to the frequency stability versus temperature curve updated with the first frequency error and the second frequency error of the first crystal clock source to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration.

[0079] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and / or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpretedby the skilled artisan in light of the teachings and guidance.

[0080] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0081] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0082] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. An apparatus for wireless communication of a user equipment, comprising: at least one processor; and memory storing instructions, which when executed by the at least one processor, cause the at least one processor to: obtain at least one temperature reading associated with a first crystal clock source at a wakeup time from a discontinuous reception (DRX) off-duration; access a frequency stability versus temperature curve at the wakeup time from the DRX off-duration; and estimate a timing offset associated with the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve.

2. The apparatus of claim 1, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: cause a second crystal clock source to enter a sleep state at a start of a DRX off-duration.

3. The apparatus of claim 1, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: estimate a first frequency error of the first crystal clock source at a start of the DRX off- duration; and update the frequency stability versus temperature curve based on the first frequency error of the first crystal clock source.

4. The apparatus of claim 3, wherein the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: cause a temperature sensor to measure the at least one temperature reading of the first crystal clock source during the DRX off-duration; and maintain the at least one temperature reading during the DRX off-duration.

5. The apparatus of claim 4, wherein, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading andthe frequency stability versus temperature curve, the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: obtain a wakeup-time timing error estimation associated with the first crystal clock source.

6. The apparatus of claim 5, wherein, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: estimate a second frequency error of the first crystal clock source at an end of the DRX off- duration based on the wakeup-time timing error estimation; and update the frequency stability versus temperature curve based on the second frequency error of the first crystal clock source.

7. The apparatus of claim 6, wherein, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the memory storing instructions, which when executed by the at least one processor, further cause the at least one processor to: compare the at least one temperature reading to the frequency stability versus temperature curve updated with the first frequency error and the second frequency error of the first crystal clock source to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration.

8. A method of wireless communication of a user equipment, comprising: obtaining, by at least one processor, at least one temperature reading associated with a first crystal clock source at a wakeup time from a discontinuous reception (DRX) off-duration; access a frequency stability versus temperature curve at the wakeup time from the DRX off-duration; and estimate a timing offset associated with the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve.

9. The method of claim 8, further comprising:causing, by the at least one processor, a second crystal clock source to enter a sleep state at a start of a DRX off-duration.

10. The method of claim 8, further comprising: estimating, by the at least one processor, a first frequency error of the first crystal clock source at a start of the DRX off-duration; and updating, by the at least one processor, the frequency stability versus temperature curve based on the first frequency error of the first crystal clock source.

11. The method of claim 10, further comprising: causing, by the at least one processor, a temperature sensor to measure the at least one temperature reading of the first crystal clock source during the DRX off-duration; and maintaining, by the at least one processor, the at least one temperature reading during the DRX off-duration.

12. The method of claim 11, wherein the estimating, by the at least one processor, the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve comprises: obtaining, by the at least one processor, a wakeup-time timing error estimation associated with the first crystal clock source.

13. The method of claim 12, wherein the estimating, by the at least one processor, the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve comprises: estimating a second frequency error of the first crystal clock source at an end of the DRX off-duration based on the wakeup-time timing error estimation; and updating the frequency stability versus temperature curve based on the second frequency error of the first crystal clock source.

14. The method of claim 13, wherein the estimating, by the at least one processor, the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve comprises:comparing the at least one temperature reading to the frequency stability versus temperature curve updated with the first frequency error and the second frequency error of the first crystal clock source to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration.

15. A non-transitory computer-readable medium storing instructions, which when executed by at least one processor of a user equipment, cause the at least one processor to: obtain at least one temperature reading associated with a first crystal clock source at a wakeup time from a discontinuous reception (DRX) off-duration; access a frequency stability versus temperature curve at the wakeup time from the DRX off-duration; and estimate a timing offset associated with the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, which when executed by the at least one processor of the user equipment, further cause the at least one processor to: estimate a first frequency error of the first crystal clock source at a start of the DRX off- duration; and update the frequency stability versus temperature curve based on the first frequency error of the first crystal clock source.

17. The non-transitory computer-readable medium of claim 16, wherein the instructions, which when executed by the at least one processor of the user equipment, further cause the at least one processor to: cause a temperature sensor to measure the at least one temperature reading of the first crystal clock source during the DRX off-duration; and maintain the at least one temperature reading during the DRX off-duration.

18. The non-transitory computer-readable medium of claim 17, wherein, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at leastone temperature reading and the frequency stability versus temperature curve, the instructions, which when executed by the at least one processor of the user equipment, further cause the at least one processor to: obtain a wakeup-time timing error estimation associated with the first crystal clock source.

19. The non-transitory computer-readable medium of claim 18, wherein, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the instructions, which when executed by the at least one processor of the user equipment, further cause the at least one processor to: estimate a second frequency error of the first crystal clock source at an end of the DRX off- duration based on the wakeup-time timing error estimation; and update the frequency stability versus temperature curve based on the second frequency error of the first crystal clock source.

20. The non-transitory computer-readable medium of claim 19, wherein, to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration based on the at least one temperature reading and the frequency stability versus temperature curve, the instructions, which when executed by the at least one processor of the user equipment, further cause the at least one processor to: compare the at least one temperature reading to the frequency stability versus temperature curve updated with the first frequency error and the second frequency error of the first crystal clock source to estimate the timing offset of the first crystal clock source that occurs during the DRX off-duration.

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