Clock signal control module and radio frequency front end module

Abstract

The present invention relates to the technical field of radio frequency, and disclosed are a clock signal control module and a radio frequency front end module. The clock signal control module comprises an RC oscillating circuit, a random sequence generating circuit, and a control circuit; the RC oscillating circuit comprises capacitors and resistors; an input end of the random sequence generating circuit is connected to an input end of the RC oscillating circuit, and an input end of the control circuit is connected to an output end of the random sequence generating circuit; the random sequence generating circuit is used for generating a random control signal, and the control circuit is used for controlling, on the basis of the received control signal, the capacitance and / or the resistance of the capacitors and / or the resistors connected to the oscillating frequency of the RC oscillating circuit. In the clock signal control module in the present invention, harmonic noise of the clock signal control module at a high frequency band can be averaged, with no periodic spikes, essentially solving the problem of clock harmonic noise.

Description

Clock signal control module and RF front-end module Technical Field

[0001] The present invention relates to the field of radio frequency technology, and in particular to a clock signal control module and a radio frequency front-end module. Background Art

[0002] In RF front-end systems, control circuits often use clock signals as charge pump inputs to generate negative voltages or multiples of positive voltages, providing appropriate positive / negative voltage sources for the RF switch's control signals. The noise floor of the power amplifier or low-noise amplifier integrated into the same module as the RF switch is affected by higher-order harmonics of the clock frequency, resulting in noise spikes with a periodicity similar to the clock frequency within certain frequency bands.

[0003] To address the above issues, related technologies all reduce harmonic power by lowering the clock frequency and increasing the harmonic order of the clock's main frequency in the frequency band of interest. At the same time, to ensure the charge pump's positive / negative voltage buildup and response speed, a frequency acceleration mode is designed. When the positive / negative voltage drops below a certain reference point, the clock speed is accelerated to allow the power supply to quickly build up before switching back to a low-frequency clock. This method can only reduce harmonic power by increasing the harmonic order within a specific frequency band and does not address the issue of periodic harmonics. It may not be applicable to other application bands, and the clock may repeatedly enter acceleration mode due to factors such as switching. In this mode, periodic bumps in the background noise within a specific frequency band will reappear and there is no solution.

[0004] Summary of the Invention

[0005] The purpose of the present invention is to provide a clock signal control module and a radio frequency front-end module to solve the problem that the related art method of reducing the harmonic power by increasing the harmonic order of the clock main frequency in the frequency band of interest by reducing the clock frequency is only applicable to a specific frequency band, and the background noise in this specific frequency band may also have periodic bumps.

[0006] In order to solve the above technical problems, in a first aspect, the present invention provides a clock signal control module, which includes an RC oscillator circuit, a random sequence generation circuit, and a control circuit; wherein the RC oscillator circuit includes a capacitor and a resistor;

[0007] The input end of the random sequence generating circuit is connected to the input end of the RC oscillation circuit, and the input end of the control circuit is connected to the output end of the random sequence generating circuit;

[0008] The random sequence generating circuit is used to generate a random control signal;

[0009] The control circuit is configured to control the size of the capacitor and / or the resistor connected to the RC oscillator circuit according to the received control signal, thereby controlling the oscillation frequency of the RC oscillator circuit to randomly change the clock period of the RC oscillator circuit so that the main frequency of the RC oscillator circuit is randomly dispersed to multiple frequency points;

[0010] The RC oscillation circuit is used to generate a clock signal according to the clock period.

[0011] Preferably, the first control circuit is used to control the size of the capacitor connected to the RC oscillator circuit solely based on the received control signal; the clock signal control module also includes a second control circuit connected to the output end of the random sequence generation circuit; the second control circuit is used to control the size of the resistor connected to the RC oscillator circuit solely based on the received control signal, thereby jointly controlling the oscillation frequency of the RC oscillator circuit with the first control circuit to randomly change the clock period of the RC oscillator circuit.

[0012] Preferably, the RC oscillator circuit includes an inverter, the capacitor, the resistor, and a Schmitt trigger; the resistor includes a plurality of first resistors and a second resistor arranged in series; the capacitor includes a plurality of first capacitors and a second capacitor arranged in parallel;

[0013] One end of a plurality of first resistors sequentially connected in series is connected to the output end of the inverter, and the input end of the inverter serves as the input end of the RC oscillation circuit;

[0014] A first end of the second resistor is connected to the other end of a plurality of first resistors sequentially connected in series, and a second end of the second resistor is connected to the input end of the Schmitt trigger;

[0015] The first end of each first capacitor is connected to the second end of the second resistor, and the second end of each first capacitor is grounded.

[0016] The first end of the second capacitor is connected to the input end of the Schmitt trigger and the second end of the second resistor respectively, and the second end of the second capacitor is grounded;

[0017] The first control circuit is connected to multiple first resistors, and is used to control the conduction or closing of the multiple first resistors according to the control signal, so as to achieve the regulation function of controlling the oscillation frequency of the RC oscillation circuit; the second control circuit is connected to multiple first capacitors, and is used to control the conduction or closing of the multiple first capacitors according to the control signal, so as to achieve the regulation function of controlling the oscillation frequency of the RC oscillation circuit.

[0018] Preferably, the first control circuit includes a plurality of first switches and the plurality of first switches form a first switch array, the number of the first switches matches the number of the first resistors; the first end of each first switch is connected to the first end of one of the first resistors, and the second ends of all the first switches are connected to the first end of the second resistor.

[0019] Preferably, the second control circuit includes a plurality of second switches and the plurality of second switches form a second switch array, the number of the second switches matches the number of the first capacitors; the first end of each second switch is connected to the second end of the second resistor, and the second end of each second switch is respectively connected to the first end of one of the first capacitors.

[0020] Preferably, the random sequence generating circuit includes a multi-bit linear feedback shift register and a decoder; the input end of the multi-bit linear feedback shift register serves as the input end of the random sequence generating circuit, the input end of the decoder is connected to the output end of the multi-bit linear feedback shift register, and the output end of the decoder serves as the output end of the random sequence generating circuit; the multi-bit linear feedback shift register and the decoder are jointly used to generate the random control signal.

[0021] In a second aspect, the present invention provides a radio frequency front-end module, which includes the clock signal control module as described above.

[0022] Compared with related arts, the clock signal control module in the present invention adds a random sequence generation circuit and a control circuit to the RC oscillation circuit, so that the control circuit can control the size of the capacitor and / or resistor connected to the RC oscillation circuit according to the control signal randomly generated by the random sequence generation circuit, and then control the oscillation frequency of the RC oscillation circuit, so as to randomly change the clock period of the RC oscillation circuit, and randomly disperse the main frequency of the RC oscillation circuit to multiple frequency points to reduce the power of each main frequency, so that the harmonic noise in the high frequency band becomes average and has no periodic bumps, which essentially solves the problem of clock harmonic noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0024] Figure 1 is a circuit diagram of a clock signal control module provided by an embodiment of the present invention. 100, clock signal control module; 1, RC oscillator circuit; 11, inverter; 12, Schmitt trigger; 2, random sequence generation circuit; 21, linear feedback shift register; 22, decoder; 3, first control circuit; 4, second control circuit. DETAILED DESCRIPTION

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0026] Example 1

[0027] An embodiment of the present invention provides a clock signal control module 100 , as shown in FIG1 , which includes an RC oscillator circuit 1 , a random sequence generating circuit 2 , and a control circuit; wherein the RC oscillator circuit 1 includes a capacitor and a resistor.

[0028] The input end of the random sequence generating circuit 2 is connected to the input end of the RC oscillator circuit 1, and the input end of the control circuit is connected to the output end of the random sequence generating circuit 2; the random sequence generating circuit 2 is used to generate a random control signal V C , the control circuit is used to receive the control signal V C The size of the capacitor and / or resistor connected to the RC oscillator circuit 1 is controlled, thereby controlling the oscillation frequency of the RC oscillator circuit 1, so as to randomly change the clock period of the RC oscillator circuit 1, so that the main frequency of the RC oscillator circuit 1 is randomly dispersed to multiple frequency points; the RC oscillator circuit 1 is used to generate a clock signal CLK according to the clock period.

[0029] The input end of the RC oscillator circuit 1 is used to receive the clock signal CLK, and the output end of the RC oscillator circuit 1 is used to output the clock signal CLK after the clock period is changed.

[0030] In this embodiment, the control circuit includes a first control circuit 3 and a second control circuit 4; the first control circuit 3 is used to receive a control signal V C Control the size of the resistor connected to the RC oscillator circuit 1, and the second control circuit 4 is used to control the value of the resistor connected to the RC oscillator circuit 1 according to the received control signal V C The size of the capacitor connected to the RC oscillator circuit 1 is controlled, thereby controlling the oscillation frequency of the RC oscillator circuit 1 to randomly change the clock period of the RC oscillator circuit 1 .

[0031] Specifically, the RC oscillator circuit 1 includes an inverter 11, a capacitor and a resistor, and a Schmitt trigger 12; the resistor includes a plurality of first resistors (R1-R M ), a second resistor R0; the capacitor includes a plurality of first capacitors (C1-C M ), the second capacitor C0.

[0032] One end of the plurality of first resistors sequentially connected in series is connected to the output end of the inverter 11 , and the input end of the inverter 11 serves as the input end of the RC oscillator circuit 1 .

[0033] A first end of the second resistor R0 is connected to the other ends of the plurality of first resistors sequentially connected in series, and a second end of the second resistor R0 is connected to the input end of the Schmitt trigger 12;

[0034] The first end of each first capacitor is connected to the second end of the second resistor R0, and the second end of each first capacitor is grounded.

[0035] A first end of the second capacitor C0 is connected to the input end of the Schmitt trigger 12 and a second end of the second resistor R0 respectively, and a second end of the second capacitor C0 is grounded;

[0036] In this embodiment, the first control circuit 3 is connected to a plurality of first resistors for controlling the first resistors according to the control signal V C The first resistors are controlled to be turned on or off to adjust the oscillation frequency of the RC oscillator circuit 1; the second control circuit 4 is connected to the first capacitors and is used to adjust the oscillation frequency of the RC oscillator circuit 1 according to the control signal V C The on or off state of the plurality of first capacitors is controlled to achieve a regulating function of controlling the oscillation frequency of the RC oscillator circuit 1 .

[0037] The output terminal of the Schmitt trigger 12 serves as the output terminal of the RC oscillation circuit 1 .

[0038] When the clock signal CLK is at a low level, the power supply VDD charges the RC array composed of multiple first resistors and second resistors R0 and multiple first capacitors and second capacitors C0 through the field effect transistor Mp connected to it in the inverter 11. When the voltage V RC When the voltage reaches the flip-flop level of the Schmitt trigger 12, the voltage of the clock frequency output by the Schmitt trigger 12 flips to a high level.

[0039] When the clock signal CLK is at a high level, the charge on the RC capacitor array composed of multiple first capacitors and second capacitors C0 is discharged to the ground through the grounded field effect transistor Mn in the inverter 11 and the RC resistor array composed of multiple first resistors and second resistors R0. When the voltage VRC When the voltage reaches the down-flip level of the Schmitt trigger 12, the voltage of the clock frequency output by the Schmitt trigger 12 flips to a low level, thereby generating a continuously flipping clock signal CLK.

[0040] Specifically, the random sequence generating circuit 2 includes a multi-bit linear feedback shift register 21 and a decoder 22; the input end of the multi-bit linear feedback shift register 21 serves as the input end of the random sequence generating circuit 2, the input end of the decoder 22 is connected to the output end of the multi-bit linear feedback shift register 21, and the output end of the decoder 22 serves as the output end of the random sequence generating circuit 2; the multi-bit linear feedback shift register 21 and the decoder 22 are used together to generate a random control signal V C .

[0041] The multi-bit linear feedback shift register 21 is a K-bit linear feedback shift register 21; the decoder 22 is an N-bit linear feedback shift register 22. N Bit decoder 22.

[0042] The multi-bit linear feedback shift register 21 internally consists of K bit registers. Each time the clock signal rises, the value stored in the K-1 bit register is uniformly transferred to the register on the left or right. If a left shift is used, the registers from bits K-1 to 1 transfer their values ​​to the registers from bits K-2. The register value for bit 1 is the value obtained by extracting the code values ​​of several bits from the K-bit code and performing an XOR operation. If a right shift is used, the registers from bits K-2 transfer their values ​​to the registers from bits K-1 to 1. The register value for bit K is the value obtained by extracting the code values ​​of several bits from the K-bit code and performing an XOR operation. The number of bits extracted is determined by the number of bits K in the multi-bit linear feedback shift register 21 to ensure that the K-bit code does not repeat after 2K right shifts.

[0043] This is equivalent to the multi-bit linear feedback shift register 21 shifting the internal register left or right at the rising edge of the clock signal CLK, that is, updating the code value of the output N-bit code. The selection of the N-bit code must ensure that 2 N During the output cycle, 2 N The output code value is not repeated and is 2 N When the output is one cycle, the code value of each cycle does not appear cyclically and is regarded as a pseudo-random sequence.

[0044] The N-bit pseudo-random sequence is converted into M=2 in binary form by the decoder 22. N bit, amplitude 0 or power supply VDD control signal V C , then the control signal V C M is also represented by the number of first resistors and first capacitors.

[0045] The first control circuit 3 and the second control circuit 4 are connected by an M-bit random control signal V C To adjust the resistance or capacitance in the RC oscillator circuit 1 so as to control the oscillation frequency of the RC oscillator circuit 1 .

[0046] Specifically, the first control circuit 3 includes a plurality of first switches (S R，1 -S R,M ); the number of the first switches matches the number of the first resistors; the first end of each first switch is connected to the first end of one of the first resistors, and the second ends of all the first switches are connected to the first end of the second resistor R0.

[0047] Among them, a plurality of first switches form a first switch matrix. When the control signal V C When the voltage is high, the corresponding first switch is turned on, that is, the first resistor connected at both ends of the first switch is short-circuited. When the first resistor is short-circuited, the charging and discharging time of the RC capacitor array will be shortened, and the corresponding clock frequency will be increased.

[0048] A plurality of first switches (S R，1 -S R,M ) respectively correspond to the resistance value after conduction V C [1-M].

[0049] Specifically, the second control circuit 4 includes a plurality of second switches (S C，1 -S C,M ); the number of the second switches matches the number of the first capacitors; the first end of each second switch is connected to the second end of the second resistor R0, and the second end of each second switch is respectively connected to the first end of one of the first capacitors.

[0050] Among them, a plurality of second switches form a second switch matrix. When the control signal V C When the level is low, the corresponding second switch is turned on, that is, the first capacitor on the second switch path is connected to the circuit. When the first capacitor is connected, the charging and discharging time of the RC capacitor array will be slowed down, and the corresponding clock frequency will be reduced.

[0051] A plurality of second switches (S C，1 -S C,M ) respectively correspond to the resistance value after conduction V C [1-M], of course, multiple second switches (S C，1 -S C,M ) respectively correspond to the resistance value after conduction V C [1-M] and multiple first switches (S R，1 -S R,M ) respectively correspond to the resistance value after conduction V C [1-M] is the resistance value in two parts.

[0052] In addition, the first control circuit 3 and the second control circuit 4 can also be used separately to achieve the effect of controlling the oscillation frequency of the RC oscillator circuit 1 to randomly change the clock period of the RC oscillator circuit 1; compared with when the first control circuit 3 and the second control circuit 4 are used together, the frequency variation range will be narrower.

[0053] The clock signal control module 100 of this embodiment uses a pseudo-random control signal V C , making the resistor array and capacitor array inconsistent within each clock signal CLK cycle, so that the cycle time of each clock signal CLK will produce random changes, thereby widening the clock frequency from a single frequency point to a frequency band composed of multiple frequency points, thereby reducing the power of each frequency point, making its harmonic noise in the high frequency band average, and without periodic bumps, essentially solving the problem of clock harmonic noise.

[0054] Compared with the related art, the clock signal control module 100 in this embodiment adds a random sequence generating circuit 2 and a control circuit to the RC oscillator circuit 1, so that the control circuit can generate a random signal V according to the random sequence generating circuit 2. C To control the size of the capacitor and / or resistor connected to the RC oscillator circuit 1, and then control the oscillation frequency of the RC oscillator circuit 1, so as to randomly change the clock period of the RC oscillator circuit 1, and randomly disperse the main frequency of the RC oscillator circuit 1 to multiple frequency points to reduce the power of each main frequency, so that the harmonic noise in the high frequency band becomes average and has no periodic bumps, which essentially solves the problem of clock harmonic noise.

[0055] Example 2

[0056] This embodiment provides a radio frequency front-end module, which includes the clock signal control module 100 in Example 1. Since the radio frequency front-end module in this embodiment includes the clock signal control module 100 in Example 1, it can also achieve the technical effects achieved by the clock signal control module 100 in Example 1, and will not be described in detail here.

[0057] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A clock signal control module, characterized in that: The clock signal control module includes an RC oscillator circuit, a random sequence generation circuit and a control circuit; wherein the RC oscillator circuit includes a capacitor and a resistor; The input end of the random sequence generating circuit is connected to the input end of the RC oscillating circuit, and the input end of the control circuit is connected to the output end of the random sequence generating circuit; The random sequence generating circuit is used to generate a random control signal; The control circuit is used to control the size of the capacitor and / or the resistor connected to the RC oscillator circuit according to the received control signal, thereby controlling the oscillation frequency of the RC oscillator circuit to randomly change the clock period of the RC oscillator circuit so that the main frequency of the RC oscillator circuit is randomly dispersed to multiple frequency points; The RC oscillation circuit is used to generate a clock signal according to the clock cycle.

2. The clock signal control module according to claim 1, wherein: The control circuit includes a first control circuit and a second control circuit; the first control circuit is used to control the size of the resistor connected to the RC oscillator circuit according to the received control signal, and the second control circuit is used to control the size of the capacitor connected to the RC oscillator circuit according to the received control signal, thereby controlling the oscillation frequency of the RC oscillator circuit.

3. The clock signal control module according to claim 2, wherein: The RC oscillator circuit includes an inverter, the capacitor, the resistor, and a Schmitt trigger; the resistor includes a plurality of first resistors and a second resistor arranged in series; the capacitor includes a plurality of first capacitors and a second capacitor arranged in parallel; One end of a plurality of first resistors sequentially connected in series is connected to the output end of the inverter, and the input end of the inverter serves as the input end of the RC oscillation circuit; A first end of the second resistor is connected to the other end of a plurality of first resistors sequentially connected in series, and a second end of the second resistor is connected to the input end of the Schmitt trigger; The first end of each of the first capacitors is respectively connected to the second end of the second resistor, and the second end of each of the first capacitors is respectively grounded; The first end of the second capacitor is connected to the input end of the Schmitt trigger and the second end of the second resistor respectively, and the second end of the second capacitor is grounded; The first control circuit is connected to multiple first resistors, and is used to control the conduction or closing of the multiple first resistors according to the control signal, so as to achieve the regulation of the oscillation frequency of the RC oscillation circuit; the second control circuit is connected to multiple first capacitors, and is used to control the conduction or closing of the multiple first capacitors according to the control signal, so as to achieve the regulation of the oscillation frequency of the RC oscillation circuit.

4. The clock signal control module according to claim 3, wherein: The first control circuit includes a plurality of first switches and the plurality of first switches form a first switch array, wherein the number of the first switches matches the number of the first resistors; a first end of each of the first switches is respectively connected to a first end of one of the first resistors, and second ends of all of the first switches are connected to a first end of the second resistor.

5. The clock signal control module according to claim 3, wherein: The second control circuit includes a plurality of second switches and the plurality of second switches form a second switch array, wherein the number of the second switches matches the number of the first capacitors; the first end of each of the second switches is connected to the second end of the second resistor, and the second end of each of the second switches is respectively connected to the first end of one of the first capacitors.

6. The clock signal control module according to claim 1, wherein: The random sequence generating circuit comprises a multi-bit linear feedback shift register and a decoder; the input end of the multi-bit linear feedback shift register serves as the input end of the random sequence generating circuit, the input end of the decoder is connected to the output end of the multi-bit linear feedback shift register, and the output end of the decoder serves as the output end of the random sequence generating circuit; the multi-bit linear feedback shift register and the decoder are used together to generate the random control signal.

7. A radio frequency front-end module, characterized in that: The RF front-end module includes the clock signal control module as described in any one of claims 1 to 6.

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