Shift register and driving method therefor, gate drive circuit, and display device

Abstract

Disclosed are a shift register and a driving method therefor, a gate drive circuit, and a display device. The shift register comprises: an input sub-circuit, configured to transmit a signal of an input end to a first node in response to a first level signal of a first clock signal end; a first output sub-circuit, configured to transmit a first level signal of a first level signal end to an output end in response to a first level signal of the first node; a first control sub-circuit, configured to transmit a signal of a second level signal end to a second node in response to a first level signal of the input end; a second control sub-circuit, configured to transmit a signal of the first level signal end to a third node in response to the first level signal of the first clock signal end, and transmit the signal of the second level signal end to the third node in response to a first level signal of a second clock signal end; a storage sub-circuit, configured to store a voltage between the second node and the third node; and a second output sub-circuit.

Description

Shift register and driving method thereof, gate driving circuit, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] With the continuous development of display technology, the development of displays in recent years has gradually shown a trend of high integration and low cost. One of the most important technologies is the mass production of Gate Driver on Array (GOA) technology.

[0003] A shift register circuit composed of thin film transistors (TFTs) is integrated on an array substrate of a display substrate using GOA technology to form a scan drive for the display substrate.

[0004] Summary of the Invention

[0005] The present disclosure provides a shift register and a driving method thereof, a gate driving circuit, and a display device.

[0006] In a first aspect, the present disclosure provides a shift register, comprising:

[0007] an input sub-circuit configured to transmit a signal at the input terminal to the first node in response to a first level signal at the first clock signal terminal;

[0008] a first output sub-circuit configured to transmit the first level signal of the first level signal terminal to the output terminal in response to the first level signal of the first node;

[0009] a first control subcircuit configured to transmit a second level signal from a second level signal terminal to a second node in response to a first level signal from the input terminal;

[0010] a second control subcircuit configured to transmit the first-level signal of the first-level signal terminal to a third node in response to the first-level signal of the first clock signal terminal; and to transmit the second-level signal of the second-level signal terminal to the third node in response to the first-level signal of the second clock signal terminal;

[0011] a storage sub-circuit configured to store a voltage between the second node and the third node;

[0012] The second output sub-circuit is configured to connect the second-level signal terminal to the output terminal in response to the second-level signal of the first node and the first-level signal of the second node; and to maintain the on-off state between the second-level signal terminal and the output terminal in response to the second-level signal of the first node and the second-level signal of the second node.

[0013] In some embodiments, the first control subcircuit includes:

[0014] A second transistor, wherein the control electrode of the second transistor is electrically connected to the input terminal, the first electrode is electrically connected to the second level signal terminal, and the second electrode is electrically connected to the second node.

[0015] In some embodiments, the second control subcircuit includes:

[0016] a fifth transistor, wherein a control electrode of the fifth transistor is electrically connected to the first clock signal terminal, a first electrode is electrically connected to the first level signal terminal, and a second electrode is electrically connected to the third node;

[0017] A sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the second clock signal terminal, a first electrode is electrically connected to the second level signal terminal, and a second electrode is electrically connected to the third node.

[0018] In some embodiments, the storage sub-circuit comprises:

[0019] A first capacitor, wherein two ends of the first capacitor are electrically connected to the third node and the second node respectively.

[0020] In some embodiments, the input subcircuit comprises:

[0021] A first transistor, wherein a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode is electrically connected to the input terminal, and a second electrode is electrically connected to the first node.

[0022] In some embodiments, the first output sub-circuit includes:

[0023] an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the first node, a first electrode is electrically connected to the first level signal terminal, and a second electrode is electrically connected to the output terminal;

[0024] A second capacitor, wherein two ends of the second capacitor are electrically connected to the output end and the first node respectively.

[0025] In some embodiments, the second output sub-circuit includes:

[0026] a first control unit configured to transmit the first level signal of the first level signal terminal or the signal of the first clock signal terminal to a fourth node in response to the first level signal of the second node;

[0027] a second control unit configured to transmit the second level signal from the second level signal terminal to the fourth node in response to the first level signal of the first node;

[0028] The output unit is configured to transmit the second level signal of the second level signal terminal to the output terminal in response to the first level signal of the fourth node.

[0029] In some embodiments, the first control unit includes:

[0030] a third transistor, wherein a control electrode of the third transistor is electrically connected to the second node, a first electrode is electrically connected to the first level signal terminal or the first clock signal terminal, and a second electrode is electrically connected to the fourth node.

[0031] In some embodiments, the second control unit includes:

[0032] A fourth transistor, wherein a control electrode of the fourth transistor is electrically connected to the first node, a first electrode is electrically connected to the second level signal terminal, and a second electrode is electrically connected to the fourth node.

[0033] In some embodiments, the output unit includes:

[0034] A seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the fourth node, a first electrode is electrically connected to the second level signal terminal, and a second electrode is electrically connected to the output terminal.

[0035] In a second aspect, the present disclosure provides a driving method for the shift register, comprising:

[0036] In the first phase, the input terminal and the second-level signal terminal provide a first-level signal, the first clock signal terminal provides a second-level signal, the first control subcircuit transmits the second-level signal from the second-level signal terminal to the second node; the second control subcircuit transmits the second-level signal from the second-level signal terminal to the third node; and the second output subcircuit connects the second-level signal terminal to the output terminal.

[0037] In the second phase, the input terminal and the first clock signal terminal provide a first-level signal, the second clock signal terminal provides a second-level signal, the input sub-circuit transmits the signal of the input terminal to the first node; the first output sub-circuit transmits the first-level signal of the first-level signal terminal to the output terminal; the first control sub-circuit transmits the second-level signal of the second-level signal terminal to the second node; and the second control sub-circuit transmits the first-level signal of the first-level signal terminal to the third node.

[0038] In the third phase, the input terminal and the first clock signal terminal provide a second-level signal, the second clock signal terminal provides a first-level signal, the first output subcircuit transmits the first-level signal of the first-level signal terminal to the output terminal; and the second control subcircuit transmits the second-level signal of the second-level signal terminal to the third node.

[0039] In the fourth stage, the input terminal and the second clock signal terminal provide a second-level signal, the first clock signal terminal provides a first-level signal, and the second control sub-circuit transmits the first-level signal of the first-level signal terminal to the third node; the storage sub-circuit stabilizes the voltage between the second node and the third node so that the potential of the second node changes with the change of the third node; the second output sub-circuit connects the second-level signal terminal and the output terminal.

[0040] In a third aspect, the present disclosure further provides a gate driving circuit, which includes a plurality of cascaded shift registers, and the shift registers are the shift registers described above.

[0041] In a fourth aspect, the present disclosure further provides a display device comprising the above-mentioned gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0043] FIG1 is a schematic diagram of a shift register provided in some embodiments of the present disclosure.

[0044] FIG2 is a schematic diagram of a shift register provided in some other embodiments of the present disclosure.

[0045] FIG3 is a schematic diagram of a shift register provided in some other embodiments of the present disclosure.

[0046] FIG4 is a timing diagram of a shift register provided in some embodiments of the present disclosure.

[0047] FIG5 is a waveform diagram of output terminals corresponding to different threshold voltage offsets provided in some embodiments of the present disclosure.

[0048] FIG6 is a schematic diagram of a driving method of a shift register provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0049] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0050] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0051] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0052] It should be noted that the transistors used in the embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, their source and drain are indistinguishable. In the embodiments of the present disclosure, to distinguish the source and drain of the transistor, one electrode is referred to as the first electrode, the other electrode is referred to as the second electrode, and the gate is referred to as the control electrode. Furthermore, transistors can be divided into N-type and P-type types based on their characteristics. The following embodiments are described using N-type transistors. When an N-type transistor is used, the first electrode is the source of the N-type transistor, and the second electrode is the drain of the N-type transistor. When the gate input is high, the source and drain are conductive, while the P-type is reversed. It is conceivable that the use of P-type transistors is something that a person skilled in the art could easily come up with without inventive effort, and therefore falls within the scope of protection of the embodiments of the present disclosure. Furthermore, based on the material of the active layer in the transistor, transistors can be divided into types such as oxide thin-film transistors and low-temperature polysilicon thin-film transistors. Generally, oxide thin-film transistors are N-type transistors, while low-temperature polysilicon thin-film transistors are P-type transistors.

[0053] In the present disclosure, "first-level signal" / "first-level potential" refers to a signal / potential that can control the conduction of a transistor after being input to the control electrode of a transistor, and "second-level signal" refers to a signal / potential that can control the cutoff of a transistor after being input to the control electrode of a transistor. In some embodiments, the first-level signal can be a high-level signal, and the first-level potential is a high-level potential; the second-level signal can be a low-level signal, and the second-level potential is a low-level potential; in other embodiments, the first-level signal is a low-level signal, and the first-level potential is a low-level potential; the second-level signal is a high-level signal, and the second-level potential is a high-level potential. For an N-type transistor, the first-level signal is a high-level signal, and the first-level potential is a high-level potential; the second-level signal is a low-level signal, and the second-level potential is a low-level potential. For a P-type transistor, the first-level signal is a low-level signal, and the first-level potential is a low-level potential; the second-level signal is a high-level signal, and the second-level potential is a high-level potential.

[0054] In the display substrate, a plurality of gate lines and a plurality of data lines intersect in the display area to define a plurality of pixels. A pixel circuit and a light-emitting device are provided in each pixel. The working phases of the pixel circuit include a data writing phase and a light-emitting phase. In the data writing phase, the pixel circuit responds to the scanning signal on the gate line to write the data voltage and the threshold voltage into the storage capacitor, thereby performing threshold compensation; in the light-emitting phase, the pixel circuit responds to the light-emitting control signal on the light-emitting control line to provide a driving current for the light-emitting device. Among them, the structure of the above-mentioned light-emitting device includes multiple types, which can be selected and set according to actual needs. For example, the above-mentioned light-emitting device can be an OLED (Organic Light-Emitting Diode), a quantum dot light-emitting diode (QLED) or a micro light-emitting diode (Micro Light Emitting Diode, Micro LED), etc.

[0055] The peripheral area of ​​the display substrate is provided with multiple gate drive circuits, each of which includes multiple cascaded shift registers. For example, the peripheral area is provided with a first gate drive circuit and a second gate drive circuit. The first gate drive circuit includes multiple cascaded first shift registers, which are connected to the gate lines and sequentially provide scanning signals to the multiple gate lines. The second gate drive circuit includes multiple cascaded second shift registers, which are connected to the light control lines and sequentially provide light control signals to the multiple light control lines.

[0056] Among them, how to reduce the power consumption of the shift register has always been a concern in this field.

[0057] Figure 1 is a schematic diagram of a shift register provided in some embodiments of the present disclosure. As shown in Figure 1, the shift register includes: an input sub-circuit 10, a first output sub-circuit 20, a first control sub-circuit 40, a second control sub-circuit 60, a storage sub-circuit 50 and a second output sub-circuit 30.

[0058] The input sub-circuit 10 is electrically connected to the input terminal IN of the shift register, the first clock signal terminal GCK, and the first node N1. The input sub-circuit 10 is configured to transmit the signal of the input terminal IN to the first node N1 in response to the first level signal of the first clock signal terminal GCK.

[0059] The first output sub-circuit 20 is connected to the first node N1, the first level signal terminal VGH, and the output terminal OUT of the shift register. The first output sub-circuit 20 is configured to transmit the first level signal of the first level signal terminal VGH to the output terminal OUT in response to the first level signal of the first node N1.

[0060] The first control subcircuit 40 is electrically connected to the input terminal IN, the second level signal terminal VGL and the second node N2. The first control subcircuit 40 is configured to transmit the second level signal of the second level signal terminal VGL to the second node N2 in response to the first level signal of the input terminal IN.

[0061] The second control sub-circuit 60 is electrically connected to the first clock signal terminal GCK, the third node N3, the second clock signal terminal GCB, the first level signal terminal VGH and the second level signal terminal VGL. The second control sub-circuit 60 is configured to transmit the first level signal of the first level signal terminal VGH to the third node N3 in response to the first level signal of the first clock signal terminal GCK; and transmit the second level signal of the second level signal terminal VGL to the third node N3 in response to the first level signal of the second clock signal terminal GCB.

[0062] The storage sub-circuit 50 is electrically connected to the second node N2 and the third node N3 and is configured to store a voltage between the second node N2 and the third node N3 .

[0063] The second output sub-circuit 30 is electrically connected to the second node N2, the second-level signal terminal VGL, the output terminal OUT, the first-level signal terminal VGH, and the first node N1. The second output sub-circuit 30 is configured to connect the second-level signal terminal VGL to the output terminal OUT in response to the second-level signal at the first node N1 and the first-level signal at the second node N2; and to maintain the connection state between the second-level signal terminal VGL and the output terminal OUT in response to the second-level signal at the second node N2 and the second-level signal at the first node N1. In some embodiments, the second output sub-circuit 30 is further configured to disconnect the output terminal OUT from the second-level signal terminal VGL in response to the first-level signal at the first node N1.

[0064] In the embodiment of the present disclosure, the working process of the shift register may include at least the first stage to the fourth stage: in the first stage, the input terminal IN and the second clock signal terminal GCB provide a first level signal, and the first clock signal terminal GCK provides a second level signal; the first node N1 maintains the second level potential of the previous stage, and the input sub-circuit 10 transmits the second level signal of the second level signal terminal VGL to the second node N2; the second control sub-circuit 60 transmits the second level signal of the second level signal terminal VGL to the third node N3; the second output sub-circuit 30 keeps the second level signal terminal VGL and the output terminal OUT conductive, and the output terminal OUT outputs the second level signal.

[0065] In the second phase, the input terminal IN and the first clock signal terminal GCK provide a first-level signal, and the second clock signal terminal GCB provides a second-level signal. The input sub-circuit 10 transmits the first-level signal from the input terminal IN to the first node N1. The first output sub-circuit 20 transmits the first-level signal from the first-level signal terminal VGH to the output terminal OUT, causing the output terminal OUT to output the first-level signal. The first control sub-circuit 40 transmits the second-level signal from the second-level signal terminal VGL to the second node N2, and the second control sub-circuit 60 transmits the first-level signal from the first-level signal terminal VGH to the third node N3.

[0066] In the third phase, the input terminal IN and the first clock signal terminal GCK provide a second-level signal, the second clock signal terminal GCB provides a first-level signal, the input terminal IN is disconnected from the first node N1, and the first node N1 maintains the first-level potential. The first output sub-circuit 20 transmits the first-level signal from the first-level signal terminal VGH to the output terminal OUT, and the second output sub-circuit 30 disconnects the output terminal OUT from the second-level signal terminal VGL. The second control sub-circuit 60 transmits the second-level signal from the second-level signal terminal VGL to the third node N3.

[0067] In the fourth stage, the first clock signal terminal GCK provides a first-level signal, the input terminal IN and the second clock signal terminal GCB provide a second-level signal; the input sub-circuit 10 transmits the second-level signal of the input terminal IN to the first node N1, and the second control sub-circuit 60 transmits the first-level signal of the first-level signal terminal VGH to the third node N3; since the second node N2 is floating, the potential of the second node N2 changes with the potential of the third node N3, changing from the second-level potential to the first-level potential; the second output sub-circuit 30 transmits the second-level signal of the second-level signal terminal VGL to the output terminal OUT.

[0068] It can be seen that the input terminal IN provides the first level signal from the start time of the first stage and stops providing the first level signal at the start time of the third stage; and the output terminal OUT starts outputting the first level signal at the start time of the second stage and stops outputting the first level signal at the start time of the fourth stage, thereby realizing the shift function.

[0069] In the embodiment of the present disclosure, the second control sub-circuit 60 responds to the signals of the first clock signal terminal GCK and the second clock signal terminal GCB, and transmits the first level signal of the first level signal terminal VGH or the second level signal of the second level signal terminal VGL to the storage sub-circuit 50, which is equivalent to using direct current to charge the storage sub-circuit 50. Compared with the method of directly using the clock signal of the clock signal terminal to charge the storage sub-circuit 50, the embodiment of the present disclosure can reduce the power consumption of the shift register.

[0070] Figure 2 is a schematic diagram of a shift register provided in other embodiments of the present disclosure, and the shift register shown in Figure 2 is a specific implementation scheme of Figure 1. Figure 3 is a schematic diagram of a shift register provided in other embodiments of the present disclosure, and the shift register shown in Figure 3 is another specific implementation scheme of Figure 1.

[0071] As shown in Figures 2 and 3, the input sub-circuit 10 includes a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the first clock signal terminal GCK, the first electrode is electrically connected to the input terminal IN, and the second electrode is electrically connected to the first node N1. When the first clock signal terminal GCK provides a first level signal, the first electrode and the second electrode of the first transistor T1 are turned on, thereby transmitting the signal from the input terminal IN to the first node N1.

[0072] In some embodiments, as shown in FIG2 , the first output sub-circuit 20 includes a second capacitor C2 and an eighth transistor T8 . The eighth transistor T8 has a control electrode electrically connected to the first node N1 , a first electrode electrically connected to the first level signal terminal VGH , and a second electrode electrically connected to the output terminal OUT . The two ends of the second capacitor C2 are electrically connected to the output terminal OUT and the first node N1 , respectively.

[0073] When the first node N1 provides a first-level signal (i.e., when the first node N1 is at a first-level potential), the first and second electrodes of the eighth transistor T8 are conductive, thereby electrically connecting the first-level signal terminal VGH to the output terminal OUT. When the first node N1 is floating, the voltage between the first node N1 and the output terminal OUT remains constant due to the voltage regulation of the second capacitor C2.

[0074] In some embodiments, as shown in Figures 2 and 3, the first control sub-circuit 40 includes a second transistor T2, wherein the control electrode of the second transistor T2 is electrically connected to the input terminal IN, the first electrode is electrically connected to the second-level signal terminal VGL, and the second electrode is electrically connected to the second node N2. When the input terminal IN provides a first-level signal, the first electrode and the second electrode of the second transistor T2 are turned on, thereby transmitting the second-level signal from the second-level signal terminal VGL to the second node N2.

[0075] In some embodiments, as shown in FIG. 2 and FIG. 3 , the storage sub-circuit 50 includes a first capacitor C1 , wherein both ends of the first capacitor C1 are electrically connected to a third node N3 and a second node N2 , respectively.

[0076] In some embodiments, as shown in Figures 2 and 3, the second output sub-circuit 30 includes: a first control unit 31, a second control unit 32 and an output unit 33, wherein the first control unit 31 is electrically connected to the second node N2 and the fourth node N4, and the first control unit 31 is also electrically connected to the first level signal terminal VGH or the first clock signal terminal GCK. The first control unit 31 is configured to transmit the first level signal of the first level signal terminal VGH or the signal of the first clock signal terminal GCK to the fourth node N4 in response to the first level signal of the second node N2.

[0077] The second control unit 32 is electrically connected to the first node N1 , the fourth node N4 and the second level signal terminal VGL and is configured to transmit the second level signal of the second level signal terminal VGL to the fourth node N4 in response to the first level signal of the first node N1 .

[0078] The output unit 33 is electrically connected to the fourth node N4 , the second level signal terminal VGL and the output terminal OUT, and is configured to transmit the second level signal of the second level signal terminal VGL to the output terminal OUT in response to the first level signal of the fourth node N4 .

[0079] When the first node N1 provides a first-level signal, the first control unit 31 transmits the first-level signal of the first-level signal terminal VGH to the output terminal OUT. Simultaneously, the second control unit 32 transmits the second-level signal of the second-level signal terminal VGL to the fourth node N4. The output unit 33 disconnects the second-level signal terminal VGL from the output terminal OUT based on the second-level signal of the fourth node N4. When the second node N2 provides a first-level signal, for example, in the fourth stage described above, the first control unit 31 transmits the first-level signal of the first-level signal terminal VGH or the first-level signal of the first clock signal terminal GCK to the fourth node N4. The output unit 33 connects the second-level signal terminal VGL to the output terminal OUT based on the first-level signal of the fourth node N4. When the first node N1 and the second node N2 provide a second level signal, the second control unit 32 disconnects the second level signal terminal VGL from the fourth node N4, and the first control unit 31 disconnects the first level signal terminal VGH or the first clock signal terminal GCK from the fourth node N4. At this time, the fourth node N4 maintains the previous first level potential, so that the output unit 33 keeps connecting the second level signal terminal VGL to the output terminal OUT.

[0080] In some embodiments, as shown in FIG2 , the first control unit 31 includes: a third transistor T3, wherein the control electrode of the third transistor T3 is electrically connected to the second node N2, the first electrode is electrically connected to the first level signal terminal VGH, and the second electrode is electrically connected to the fourth node N4. Alternatively, as shown in FIG3 , the first control unit 31 includes: a third transistor T3, wherein the control electrode of the third transistor T3 is electrically connected to the second node N2, the first electrode is electrically connected to the first clock signal terminal GCK, and the second electrode is electrically connected to the fourth node N4.

[0081] As shown in FIG2 and FIG3 , the second control unit 32 includes a fourth transistor T4 , a control electrode of which is electrically connected to the first node N1 , a first electrode of which is electrically connected to the second level signal terminal VGL, and a second electrode of which is electrically connected to the fourth node N4 .

[0082] As shown in Figures 2 and 3, the output unit 33 includes a seventh transistor T7. The control electrode of the seventh transistor T7 is electrically connected to the fourth node N4, the first electrode is electrically connected to the second level signal terminal VGL, and the second electrode is electrically connected to the output terminal OUT. The seventh transistor T7 can have a large width-to-length ratio to form a certain parasitic capacitance. In this way, when the fourth node N4 is floating, the parasitic capacitance of the seventh transistor T7 can maintain the potential of the fourth node N4 consistent with the previous stage.

[0083] In other embodiments, in addition to the seventh transistor T7, the output unit 33 may also include a third capacitor (not shown), and the two ends of the third capacitor are electrically connected to the second level signal terminal VGL and the fourth node N4, respectively. When the fourth node N4 is floating, the third capacitor can keep the potential of the fourth node N4 consistent with the previous stage.

[0084] FIG4 is a timing diagram of a shift register provided in some embodiments of the present disclosure. The operation of the shift register in the embodiments of the present disclosure will be described below in conjunction with FIG2 to FIG4 . The description will be given using an example in which each transistor in the shift register is an N-type transistor. In this case, a high-level signal serves as a first-level signal, and a low-level signal serves as a second-level signal.

[0085] During the first phase t1, the input terminal IN and the second clock signal terminal GCB provide a high-level signal, while the first clock signal terminal GCK provides a low-level signal. At this time, the second transistor T2 is turned on, and the low-level signal from the second-level signal terminal VGL is transmitted to the second node N2. Furthermore, the sixth transistor T6 is turned on, and the low-level signal from the second-level signal terminal VGL is transmitted to the third node N3. The first transistor T1, the third transistor T3, and the fifth transistor T5 are all turned off, and the first node N1 maintains the low-level potential from the previous phase, thereby keeping the eighth transistor T8 off. The fourth node N4 maintains the high-level potential from the previous phase, thereby turning on the seventh transistor T7, and the low-level signal from the second-level signal terminal VGL is output from the output terminal OUT.

[0086] In the second phase t2, the input terminal IN and the first clock signal terminal GCK provide high-level signals, and the second clock signal terminal GCB provides a low-level signal. At this time, the first transistor T1 is turned on, and the high-level signal from the input terminal IN is transmitted to the first node N1, thereby controlling the eighth transistor T8 to turn on. As a result, the high-level signal from the first-level signal terminal VGH is transmitted to the output terminal OUT. Simultaneously, the second transistor T2 is turned on, and the low-level signal from the second-level signal terminal VGL is transmitted to the second node N2. The fifth transistor T5 is turned on, and the high-level signal from the first-level signal terminal VGH is transmitted to the third node N3, thereby charging the first capacitor C1. Because the second node N2 is at a low potential and the first node N1 is at a high potential, the third transistor T3 is turned off, and the fourth transistor T4 is turned on. The low-level signal from the second-level signal terminal VGL is transmitted to the fourth node N4, thereby controlling the seventh transistor T7 to turn off, preventing the high-level output from the output terminal OUT from being affected.

[0087] During the first hold phase t11, the input terminal IN and the second clock signal terminal GCB provide high-level signals, while the first clock signal terminal GCK provides a low-level signal. At this point, the first transistor T1 is turned off, and the first node N1 maintains the high-level potential from the previous phase, causing the eighth transistor T8 to remain on, and the high-level signal from the first-level signal terminal VGH is transmitted to the output terminal OUT. Simultaneously, the second transistor T2 is turned on, and the low-level signal from the second-level signal terminal VGL is transmitted to the second node N2. The fifth transistor T5 is turned off, and the sixth transistor T6 is turned on, transmitting the low-level signal from the second-level signal terminal VGL to the third node N3. Because the second node N2 is at a low-level potential, the third transistor T3 is turned off. Since the first node N1 is at a high-level potential, the fourth transistor T4 is turned on, transmitting the low-level signal from the second-level signal terminal VGL to the fourth node N4, causing the seventh transistor T7 to remain off.

[0088] During the second hold phase t12, the input terminal IN and the first clock signal terminal GCK provide high-level signals, while the second clock signal terminal GCB provides a low-level signal. At this point, the first transistor T1 is turned on, and the high-level signal from the input terminal IN is transmitted to the first node N1, thereby causing the eighth transistor T8 to remain on and the high-level signal from the first-level signal terminal VGH to be transmitted to the output terminal OUT. Simultaneously, the second transistor T2 is turned on, and the low-level signal from the second-level signal terminal VGL is transmitted to the second node N2. The sixth transistor T6 is turned off, and the fifth transistor T5 is turned on, thereby transmitting the high-level signal from the first-level signal terminal VGH to the third node N3. The third transistor T3, the fourth transistor T4, and the seventh transistor T7 all maintain their switching states from the previous phase, and the output terminal OUT continues to output a high-level signal.

[0089] In the third phase t3, the input terminal IN and the first clock signal terminal GCK provide low-level signals, and the second clock signal terminal GCB provides a high-level signal. At this time, the first transistor T1 is turned off, and the first node N1 maintains the high-level potential of the previous phase, thereby causing the eighth transistor T8 to remain on, and the high-level signal of the first-level signal terminal VGH is transmitted to the output terminal OUT. At the same time, the second transistor T2 is turned off; the fifth transistor T5 is turned off, and the sixth transistor T6 is turned on, thereby transmitting the low-level signal of the second-level signal terminal VGL to the third node N3. Under the voltage regulation effect of the first capacitor C1, the second node N2 maintains the low-level potential of the previous phase, thereby causing the third transistor T3 to remain off. The fourth transistor T4 and the seventh transistor T7 both maintain the switching state of the previous phase, and the output terminal OUT continues to output a high-level signal.

[0090] In the fourth phase t4, the input terminal IN and the second clock signal terminal GCB provide low-level signals, while the first clock signal terminal GCK provides a high-level signal. At this point, the first transistor T1 is turned on, and the low-level signal from the input terminal IN is transmitted to the first node N1, thereby turning off the eighth transistor T8 and the fourth transistor T4. Simultaneously, the fifth transistor T5 is turned on, and the sixth transistor T6 is turned off, thereby transmitting the high-level signal from the first-level signal terminal VGH to the third node N3, causing the third node N3 to jump from the low-level potential in the previous phase to the high-level potential. Since the second transistor T2 is turned off, the second node N2 is floating. Therefore, the bootstrap effect of the first capacitor C1 causes the potential of the second node N2 to change with the change in the third node N3, from the low-level potential in the previous phase to the high-level potential. This controls the third transistor T3 to turn on, and the high-level signal from the first-level signal terminal VGH is transmitted to the fourth node N4. This in turn turns on the seventh transistor T7, and the low-level signal from the second-level signal terminal VGL is transmitted to the output terminal OUT.

[0091] After the fourth phase t4, when the first clock signal terminal GCK provides a low-level signal and the second clock signal terminal GCB provides a high-level signal, the first node N1 maintains the low-level potential of the previous phase, thereby controlling the fourth transistor T4 and the eighth transistor T8 to be off. Simultaneously, the fifth transistor T5 is off, the sixth transistor T6 is on, and the third node N3 receives the low-level signal from the second-level signal terminal VGL. Since the second transistor T2 is off under the control of the low-level signal from the input terminal IN, the second node N2 is floating. Therefore, the bootstrap effect of the first capacitor C1 causes the potential of the second node N2 to change with the change of the third node N3, from the high-level potential in the previous phase to the low-level potential, thereby controlling the third transistor T3 to be off. The fourth node N4 maintains the high-level potential in the previous phase, thereby turning on the seventh transistor T7, and the output terminal OUT outputs the low-level signal from the second-level signal terminal VGL.

[0092] After the fourth stage t4, when the first clock signal terminal GCK provides a high-level signal and the second clock signal terminal GCB provides a low-level signal, the potential of each node is consistent with the fourth stage, the switching state of each transistor is consistent with the fourth stage, and the output terminal OUT continues to output a low-level signal.

[0093] FIG5 is a waveform diagram of the output terminal OUT corresponding to different threshold voltage offsets provided in some embodiments of the present disclosure. As shown in FIG5 , when the offset of the threshold voltage Vth of each transistor is between -3V and 4V, the output terminal OUT can output normally.

[0094] FIG6 is a schematic diagram of a driving method of a shift register provided in some embodiments of the present disclosure. The shift register is the shift register in the above-mentioned embodiment. As shown in FIG6 , the driving method of the shift register includes:

[0095] S1. In the first stage, the input terminal and the second-level signal terminal provide a first-level signal, the first clock signal terminal provides a second-level signal, the first control sub-circuit transmits the second-level signal of the second-level signal terminal to the second node; the second control sub-circuit transmits the second-level signal of the second-level signal terminal to the third node; the second output sub-circuit keeps the second-level signal terminal and the output terminal conductive.

[0096] S2. In the second stage, the input terminal and the first clock signal terminal provide a first-level signal, the second clock signal terminal provides a second-level signal, the input sub-circuit transmits the signal of the input terminal to the first node; the first output sub-circuit transmits the first-level signal of the first-level signal terminal to the output terminal; the first control sub-circuit transmits the second-level signal of the second-level signal terminal to the second node; the second control sub-circuit transmits the first-level signal of the first-level signal terminal to the third node.

[0097] S3. In the third stage, the input terminal and the first clock signal terminal provide a second-level signal, the second clock signal terminal provides a first-level signal, the first output sub-circuit transmits the first-level signal of the first-level signal terminal to the output terminal; the second control sub-circuit transmits the second-level signal of the second-level signal terminal to the third node.

[0098] S4. In the fourth stage, the input terminal and the second clock signal terminal provide a second-level signal, the first clock signal terminal provides a first-level signal, and the second control sub-circuit transmits the first-level signal of the first-level signal terminal to the third node; the storage sub-circuit stabilizes the voltage between the second node and the third node so that the potential of the second node changes with the change of the third node; the second output sub-circuit connects the second-level signal terminal and the output terminal.

[0099] The present disclosure also provides a gate drive circuit comprising a plurality of cascaded shift registers, wherein each shift register is a shift register in the above embodiment, wherein in two adjacent shift registers, the output end of the upper shift register is electrically connected to the input end of the lower shift register.

[0100] An embodiment of the present disclosure further provides a display device, which includes the above-mentioned gate driving circuit.

[0101] In some embodiments, the display device is an OLED display device, which includes a display substrate, the display substrate including a base substrate and a plurality of pixel units disposed on the base substrate, each pixel unit including a light-emitting device and a pixel circuit electrically connected to the light-emitting device, and the plurality of pixel circuits can be arranged in an array, with each row of pixel circuits electrically connected to a gate line and a light-emitting control line to receive a scanning signal from the gate line and a light-emitting control signal from the light-emitting control line. The gate drive circuit in the above embodiment can be disposed on the base substrate and sequentially provide light-emitting control signals to the plurality of light-emitting control lines.

[0102] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A shift register, wherein: include: an input subcircuit configured to transmit a signal at an input terminal to a first node in response to a first level signal at a first clock signal terminal; a first output sub-circuit configured to transmit a first level signal from a first level signal terminal to an output terminal in response to a first level signal from the first node; a first control subcircuit configured to transmit a second level signal at a second level signal terminal to a second node in response to a first level signal at the input terminal; a second control subcircuit configured to transmit the first level signal of the first level signal terminal to a third node in response to the first level signal of the first clock signal terminal; and transmitting a second level signal from the second level signal terminal to the third node in response to the first level signal from the second level signal terminal; a storage subcircuit configured to store a voltage between the second node and the third node; A second output sub-circuit, configured to connect the second level signal terminal to the output terminal in response to a second level signal of the first node and a first level signal of the second node; And in response to the second level signal of the first node and the second level signal of the second node, the on-off state between the second level signal terminal and the output terminal is maintained.

2. The shift register according to claim 1, wherein: The first control subcircuit comprises: A second transistor, wherein a control electrode of the second transistor is electrically connected to the input terminal, a first electrode is electrically connected to the second level signal terminal, and a second electrode is electrically connected to the second node.

3. The shift register according to claim 1, wherein: The second control subcircuit comprises: a fifth transistor, wherein a control electrode of the fifth transistor is electrically connected to the first clock signal terminal, The first electrode is electrically connected to the first level signal terminal, and the second electrode is electrically connected to the third node; A sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the second clock signal terminal, a first electrode is electrically connected to the second level signal terminal, and a second electrode is electrically connected to the third node.

4. The shift register according to claim 1, wherein: The storage sub-circuit comprises: A first capacitor, wherein two ends of the first capacitor are electrically connected to the third node and the second node respectively.

5. The shift register according to any one of claims 1 to 4, wherein: The input subcircuit comprises: A first transistor, wherein a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode is electrically connected to the input terminal, and a second electrode is electrically connected to the first node.

6. The shift register according to any one of claims 1 to 4, wherein: The first output sub-circuit comprises: an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the first node, a first electrode is electrically connected to the first level signal terminal, and a second electrode is electrically connected to the output terminal; A second capacitor, wherein two ends of the second capacitor are electrically connected to the output end and the first node respectively.

7. The shift register according to any one of claims 1 to 4, wherein: The second output sub-circuit comprises: a first control unit configured to transmit the first level signal of the first level signal terminal or the signal of the first clock signal terminal to a fourth node in response to the first level signal of the second node; The second control unit is configured to respond to the first level signal of the first node The second level signal of the second level signal terminal is transmitted to the fourth node; The output unit is configured to transmit the second level signal of the second level signal terminal to the output terminal in response to the first level signal of the fourth node.

8. The shift register according to claim 7, wherein: The first control unit comprises: A third transistor, wherein a control electrode of the third transistor is electrically connected to the second node, a first electrode is electrically connected to the first level signal terminal or the first clock signal terminal, and a second electrode is electrically connected to the fourth node.

9. The shift register according to claim 7, wherein: The second control unit comprises: A fourth transistor, wherein a control electrode of the fourth transistor is electrically connected to the first node, a first electrode is electrically connected to the second level signal terminal, and a second electrode is electrically connected to the fourth node.

10. The shift register according to claim 7, wherein: The output unit comprises: A seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the fourth node, a first electrode is electrically connected to the second level signal terminal, and a second electrode is electrically connected to the output terminal.

11. A method for driving a shift register according to any one of claims 1 to 10, comprising: In the first stage, the input terminal and the second level signal terminal provide a first level signal, the first clock signal terminal provides a second level signal, and the first control subcircuit transmits the second level signal of the second level signal terminal to the second node; The second control subcircuit transmits the second level signal at the second level signal terminal to the third node; The second output subcircuit connects the second level signal terminal to the output terminal; In the second stage, the input terminal and the first clock signal terminal provide a first level signal, the second clock signal terminal provides a second level signal, and the input sub-circuit converts the input terminal's The signal is transmitted to the first node; The first output subcircuit transmits the first level signal at the first level signal end to the output end; The first control subcircuit transmits the second level signal at the second level signal terminal to the second node; The second control subcircuit transmits the first level signal of the first level signal terminal to the third node; In the third stage, the input terminal and the first clock signal terminal provide a second level signal, the second clock signal terminal provides a first level signal, and the first output subcircuit transmits the first level signal of the first level signal terminal to the output terminal; The second control subcircuit transmits the second level signal at the second level signal terminal to the third node; In the fourth stage, the input terminal and the second clock signal terminal provide a second level signal, the first clock signal terminal provides a first level signal, and the second control subcircuit transmits the first level signal of the first level signal terminal to the third node; The storage sub-circuit stabilizes the voltage between the second node and the third node so that the potential of the second node changes with the change of the third node; The second output sub-circuit connects the second level signal terminal to the output terminal. 12 . A gate driving circuit, comprising a plurality of cascaded shift registers, wherein the shift register is the shift register according to claim 1 .

13. A display device comprising the gate driving circuit according to claim 12.

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