Shift register, gate drive circuit, and display device

Abstract

The present disclosure relates to the technical field of display, and provides a shift register, a gate drive circuit, and a display device, which can solve the problem that existing shift registers cannot output a forward shift signal. The shift register of the present disclosure comprises a first input sub-circuit, a second input sub-circuit, a first control sub-circuit, a second control sub-circuit, a first cascade sub-circuit, a third control sub-circuit, a first output sub-circuit, and a second output sub-circuit; the first output sub-circuit is configured to transmit a second level signal to a signal output end in response to the voltage of a first node; the second output sub-circuit is configured to transmit a first clock signal or a first level signal to the signal output end in response to the voltage of a cascade signal end.

Description

Shift register, gate drive circuit and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a shift register, a gate driving circuit, and a display device. Background Art

[0002] With the continuous development of display technology, the development of displays in recent years has gradually shown a trend of high integration and low cost. One of the most important technologies is the mass production of Gate Driver on Array (GOA) technology.

[0003] GOA technology is used to integrate a shift register circuit composed of thin film transistors (TFTs) on the array substrate of the display substrate to form a scan drive for the display substrate, thereby eliminating the gate drive integrated circuit part. It can not only reduce product costs in terms of material costs and manufacturing processes, but also achieve an aesthetically pleasing design of the display substrate with a narrow bezel.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a shift register, a gate drive circuit and a display device.

[0006] In a first aspect, an embodiment of the present disclosure provides a shift register, wherein the shift register includes: a first input subcircuit, a second input subcircuit, a first control subcircuit, a second control subcircuit, a first cascade subcircuit, a third control subcircuit, a first output subcircuit, and a second output subcircuit;

[0007] The first input sub-circuit is configured to transmit the second level signal to the first node in response to the first clock signal; or, in response to the second clock signal, transmit the second clock signal to the first node;

[0008] The second input sub-circuit is configured to transmit the input signal to the second node in response to the first clock signal;

[0009] The first control subcircuit is configured to transmit a first level signal to the first node in response to a voltage of the second node; or, in response to a voltage of the second node, transmit a first level signal to the first node and the first input subcircuit;

[0010] The second control subcircuit is configured to transmit a first level signal to the second node in response to the voltage of the first node and the second clock signal;

[0011] The first cascade sub-circuit is configured to transmit a second clock signal to the cascade signal terminal in response to a voltage of the second node;

[0012] The first output sub-circuit is configured to transmit a second level signal to the signal output terminal in response to the voltage of the first node;

[0013] The second output sub-circuit is configured to transmit a first clock signal or a first level signal to the signal output terminal in response to a voltage at the cascade signal terminal.

[0014] Optionally, the first input sub-circuit includes: a first transistor;

[0015] The control electrode of the first transistor is connected to the first clock signal terminal, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the first node.

[0016] Optionally, the first input sub-circuit includes: a first transistor and a first storage capacitor;

[0017] The control electrode of the first transistor is connected to one end of the first storage capacitor, the first electrode is connected to the second clock signal terminal and the other end of the first storage capacitor, and the second electrode is connected to the first node;

[0018] One end of the first storage capacitor is connected to the control electrode of the first transistor, and the other end is connected to the second clock signal end and the first electrode of the first transistor.

[0019] Optionally, the second input sub-circuit includes: a second transistor;

[0020] The control electrode of the second transistor is connected to the first clock signal terminal, the first electrode is connected to the signal input terminal, and the second electrode is connected to the first control subcircuit and the second node.

[0021] Optionally, the first control subcircuit includes: a fourth transistor and a fourth sub-transistor;

[0022] The control electrode of the fourth transistor is connected to the second node and the control electrode of the fourth sub-transistor, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the fourth sub-transistor;

[0023] The control electrode of the fourth sub-transistor is connected to the second node and the control electrode of the fourth transistor, the first electrode is connected to the second electrode of the fourth transistor, and the second electrode is connected to the first node.

[0024] Optionally, the first control subcircuit further includes: a fifteenth transistor;

[0025] The control electrode of the fifteenth transistor is connected to the first node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the second electrode of the fourth transistor and the first electrode of the fourth sub-transistor.

[0026] Optionally, the first control subcircuit includes: a fourth transistor;

[0027] The control electrode of the fourth transistor is connected to the second node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first node.

[0028] Optionally, the first control subcircuit includes: a third transistor and a fourth transistor;

[0029] The control electrode of the third transistor is connected to the second node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first input sub-circuit;

[0030] The control electrode of the fourth transistor is connected to the second node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first node.

[0031] Optionally, the second control subcircuit includes: a fifth transistor and a sixth transistor;

[0032] The control electrode of the fifth transistor is connected to the first node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the sixth transistor;

[0033] The control electrode of the sixth transistor is connected to the second clock signal terminal, the first electrode is connected to the second electrode of the fifth transistor, and the second electrode is connected to the second node.

[0034] Optionally, the first cascade sub-circuit includes: a seventh transistor, an eighth transistor and a second storage capacitor;

[0035] The control electrode of the seventh transistor is connected to the second level signal terminal, the first electrode is connected to the second node, and the second electrode is connected to the control electrode of the eighth transistor and one end of the second storage capacitor;

[0036] The control electrode of the eighth transistor is connected to the second electrode of the seventh transistor and one end of the second storage capacitor, the first electrode is connected to the second clock signal end, and the second electrode is connected to the cascade signal end and the other end of the second storage capacitor.

[0037] Optionally, the first output sub-circuit includes: an eleventh transistor and a third storage capacitor;

[0038] The control electrode of the eleventh transistor is connected to the first node and one end of the third storage capacitor, the first electrode is connected to the second level signal end, and the second electrode is connected to the signal output end;

[0039] One end of the third storage capacitor is connected to the first node and the control electrode of the eleventh transistor, and the other end is connected to the first electrode and the second level signal end of the eleventh transistor, or the other end is connected to the first clock signal end.

[0040] Optionally, the first output sub-circuit further includes: a twelfth transistor;

[0041] The control electrode of the twelfth transistor is connected to the second level signal terminal, the first electrode is connected to the first node, and the second electrode is connected to one end of the third storage capacitor and the control electrode of the eleventh transistor.

[0042] Optionally, the second output sub-circuit includes: a thirteenth transistor and a fourth storage capacitor;

[0043] The control electrode of the thirteenth transistor is connected to the cascade signal terminal and one end of the fourth storage capacitor, the first electrode is connected to the first clock signal terminal or the first level signal terminal, and the second electrode is connected to the signal output terminal and the other end of the fourth storage capacitor;

[0044] One end of the fourth storage capacitor is connected to the cascade signal terminal and the control electrode of the thirteenth transistor, and the other end is connected to the second electrode of the thirteenth transistor and the signal output terminal.

[0045] Optionally, the second output sub-circuit further includes: a fourteenth transistor;

[0046] The control electrode of the fourteenth transistor is connected to the second level signal terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to one end of the fourth storage capacitor and the control electrode of the thirteenth transistor.

[0047] Optionally, the shift register further includes: a third control subcircuit;

[0048] The third control subcircuit is configured to transmit the first level signal to the cascade signal terminal in response to the voltage of the first node and the second clock signal;

[0049] Optionally, the third control subcircuit includes: a ninth transistor and a tenth transistor;

[0050] The control electrode of the ninth transistor is connected to the second node, the first electrode is connected to the second clock signal terminal, and the second electrode is connected to the second electrode of the tenth transistor and the second output sub-circuit;

[0051] The control electrode of the tenth transistor is connected to the first node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the second electrode of the ninth transistor and the second output sub-circuit.

[0052] Optionally, the third control subcircuit includes: a ninth transistor and a tenth transistor;

[0053] The control electrode of the ninth transistor is connected to the first node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the tenth transistor;

[0054] The control electrode of the tenth transistor is connected to the second clock signal terminal, the first electrode is connected to the second electrode of the ninth transistor, and the second electrode is connected to the second output sub-circuit and the cascade signal terminal.

[0055] Optionally, the third control subcircuit includes: a tenth transistor;

[0056] The control electrode of the tenth transistor is connected to the second clock signal terminal, the first electrode is connected to the second control sub-circuit, and the second electrode is connected to the second output sub-circuit and the cascade signal terminal.

[0057] Optionally, the shift register further comprises: a second cascade sub-circuit;

[0058] The second cascade sub-circuit is configured to transmit a first level signal to the cascade signal terminal in response to a voltage of the first node.

[0059] Optionally, the second cascade sub-circuit includes: a sixteenth transistor and a fifth storage capacitor;

[0060] The control electrode of the sixteenth transistor is connected to the first node and one end of the fifth storage capacitor, the first electrode is connected to the first level signal end and the other end of the fifth storage capacitor, and the second electrode is connected to the cascade signal end.

[0061] In a second aspect, an embodiment of the present disclosure provides a shift register driving method for driving the shift register provided above, wherein the shift register driving method includes:

[0062] In response to the first clock signal, transmitting the second level signal to the first node;

[0063] transmitting an input signal to a second node in response to a first clock signal;

[0064] transmitting a first level signal to the first node in response to a voltage of the second node;

[0065] transmitting a first level signal to a second node in response to a voltage of the first node and a second clock signal;

[0066] transmitting a second clock signal to the cascade signal terminal in response to a voltage of the second node;

[0067] transmitting a second level signal to a signal output terminal in response to a voltage of the first node;

[0068] In response to the voltage of the cascade signal terminal, the first clock signal or the first level signal is transmitted to the signal output terminal.

[0069] In a third aspect, an embodiment of the present disclosure provides a gate driving circuit, wherein the gate driving circuit comprises: a plurality of shift registers provided above in cascade connection;

[0070] The signal input end of the shift register at this stage is connected to the signal output end of the shift register at the previous stage.

[0071] In a fourth aspect, an embodiment of the present disclosure provides a display device, wherein the display device includes the gate driving circuit provided above. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] FIG1 is a schematic structural diagram of an exemplary pixel circuit.

[0073] FIG2 is an operation timing diagram of the pixel circuit shown in FIG1 .

[0074] FIG3 is a schematic diagram of the structure of an exemplary shift register.

[0075] FIG4 is an operation timing diagram of the shift register shown in FIG3 .

[0076] FIG5 is a block diagram of a shift register provided by an embodiment of the present disclosure.

[0077] FIG6 is a schematic diagram of the circuit structure of the first shift register provided by an embodiment of the present disclosure.

[0078] FIG7 is an operation timing diagram of the shift register shown in FIG6 .

[0079] FIG8 is a schematic diagram of the circuit structure of a second shift register provided in an embodiment of the present disclosure.

[0080] FIG9 is a schematic diagram of the circuit structure of a third shift register provided in an embodiment of the present disclosure.

[0081] FIG10 is an operation timing diagram of the shift register shown in FIG9 .

[0082] FIG11 is a schematic diagram of the circuit structure of the fourth shift register provided in an embodiment of the present disclosure.

[0083] FIG12 is a schematic diagram of the circuit structure of the fifth shift register provided in an embodiment of the present disclosure.

[0084] FIG13 is an operation timing diagram of the shift register shown in FIG12 .

[0085] FIG14 is a schematic diagram of the circuit structure of the sixth shift register provided in an embodiment of the present disclosure.

[0086] FIG15 is a schematic diagram of the circuit structure of the seventh shift register provided in an embodiment of the present disclosure.

[0087] FIG16 is an operation timing diagram of the shift register shown in FIG15 .

[0088] FIG17 is a schematic diagram of the circuit structure of the eighth shift register provided in an embodiment of the present disclosure.

[0089] FIG18 is a schematic diagram of the circuit structure of the ninth shift register provided in an embodiment of the present disclosure.

[0090] FIG19 is a schematic structural diagram of a gate drive circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0091] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0092] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0093] It should be noted here that the transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. In this embodiment, the coupling mode of the drain and source of each transistor can be interchangeable. Therefore, there is actually no difference between the drain and source of each transistor in the embodiments of the present disclosure. Here, only to distinguish the two poles of the transistor other than the control pole (i.e., the gate), one of the poles is called the drain and the other pole is called the source. The thin film transistors used in the embodiments of the present disclosure are all P-type transistors. The first pole can be the source and the second pole can be the drain. For P-type transistors, when the gate inputs a low-level signal, the source and drain are connected, and when the gate inputs a high-level signal, the source and drain are closed.

[0094] In the present disclosure, "first level signal" refers to a high level signal, and "second level signal" refers to a low level signal. The first clock signal and the second clock signal are both pulse signals with a certain duty cycle, wherein the high level signal in the first clock signal corresponds to the low level signal in the second clock signal. At the same stage, the potentials of the first clock signal and the second clock signal are opposite.

[0095] Figure 1 is a structural schematic diagram of an exemplary pixel circuit, and Figure 2 is an operating timing diagram of the pixel circuit shown in Figure 1. As shown in Figure 1, the pixel circuit includes: a data writing transistor QTFT, a driving transistor DTFT, a sensing transistor STFT, a storage capacitor Cst and a light-emitting device OLED.

[0096] The data write transistor QTFT has a gate connected to the first gate line G1, a source connected to the data signal line Data, and a drain connected to the first node G. The drive transistor DTFT has a gate connected to the first node G, a source connected to the first power supply voltage terminal ELVDD, and a drain connected to the second node S. One end of the storage capacitor Cst is connected to the first node G, and the other end is connected to the second node S. The sense transistor STFT has a gate connected to the second gate line G2, a source connected to the sense signal line Sense, and a drain connected to the second node S. The anode of the light-emitting device OLED is connected to the second node S, and the drain is connected to the second power supply voltage terminal ELVSS.

[0097] As shown in Figure 2, the working process of the pixel circuit includes: a data writing stage and a light-emitting stage; wherein, in the data writing stage, the first gate line G1 controls the gate of the data writing transistor QTFT so that its source and drain are turned on, and the data line Data writes the data voltage Vdata to the gate of the driving transistor DTFT (the first node G); in the light-emitting stage, the driving transistor DTFT outputs a corresponding driving current according to the voltage at its own control electrode to drive the light-emitting element OLED to emit light. The working process of the pixel circuit also includes: a sensing stage (not shown in the figure). After the display time of one frame ends in the sensing stage, the sensing transistor STFT senses the driving transistor DTFT and the light-emitting element OLED in the pixel circuit, and performs external compensation on the pixel circuit based on the sensing results. The specific external compensation process belongs to the conventional technology in this field and will not be repeated here.

[0098] The gate drive signals of the first gate line G1 and the second gate line G2 shown in FIG2 are provided by a gate drive circuit including a plurality of cascaded shift registers. In order to achieve a narrow frame design and reduce the area occupied by the gate drive circuit, the transistors therein can all be P-type transistors.

[0099] FIG3 is a schematic diagram of the structure of an exemplary shift register. As shown in FIG3 , the shift register includes: first to eighth transistors T1 to T8, and first and second storage capacitors C1 and C2. The first to eighth transistors T1 to T8 are all low-temperature polysilicon (LTPS) thin-film transistors (TFTs), i.e., P-type TFTs, with a negative threshold voltage Vth. When the voltage difference Vgs between the gate and source of the TFT is less than Vth, the TFT is turned on. The shift register unit is used to output gate drive signals for the first gate line G1 and the second gate line G2 required to drive the pixel circuit shown in FIG1 .

[0100] The source of the first transistor T1 is connected to the low-level signal terminal VGL, the gate is connected to the first clock signal terminal CKA, and the drain is connected to the first node N1; the source of the second transistor T2 is connected to the signal input terminal, which may be the cascade signal terminal CR(N-1) of the previous stage, the gate is connected to the first clock signal terminal CKA, and the drain is connected to the second node N2; the source of the third transistor T3 is connected to the second node N2, the gate is connected to the low-level signal terminal VGL, and the drain is connected to the third node N3; the source of the fourth transistor T4 is connected to the high-level signal terminal VGH, the gate is connected to the first node N1, and the drain is connected to the signal output terminal G(N) of the shift register unit; the source of the fifth transistor T5 is connected to the second clock signal terminal The first transistor T6 has a source connected to the first clock signal terminal CKA, a gate connected to the second node N2, and a drain connected to the drain of the first transistor T1; the seventh transistor T7 has a source connected to the high-level signal terminal VGH, a gate connected to the first node N1, and a drain connected to the fourth node N4; the eighth transistor T8 has a source connected to the fourth node N4, a gate connected to the second clock signal terminal CKB, and a drain connected to the second node N2; the two ends of the first storage capacitor C1 are respectively connected to the gate and source of the fourth transistor T4; the two ends of the second storage capacitor C2 are respectively connected to the gate and drain of the fifth transistor T5.

[0101] FIG4 is a working timing diagram of the shift register shown in FIG3 . As shown in FIG4 , the working process of the shift register is divided into a first stage, a second stage, a third stage, a fourth stage and a fifth stage.

[0102] Phase 1: The first clock signal and the cascade signal from the previous stage are both low (active), and the second clock signal is high (inactive). The first and second transistors T1 and T2 are turned on under the control of the first clock signal. The cascade signal from the previous stage is derived through the drain of the second transistor T2, writing a low-level signal to the second node N2. The third transistor T3 is turned on under the control of the low-level signal, and the low-level signal written to the second node N2 is continuously written to the third node N3, thereby turning on the fifth transistor T5. The second clock signal (high) is derived through the drain of the fifth transistor T5, and the signal output terminal G(N) of the shift register unit outputs a high-level signal. Simultaneously, a low-level signal is derived through the drain of the first transistor T1, writing a low-level signal to the first node N1, turning on the fourth transistor T4. A high-level signal is derived through the drain of the fourth transistor T4, and the first node N1 is low, turning on the seventh transistor T7. Simultaneously, the second clock signal is high, and the eighth transistor T8 is turned off. At this point, the signal output terminal G(N) of the shift register unit outputs a high-level signal.

[0103] Phase 2: The first clock signal and the cascade signal of the previous stage are both high (inactive), and the second clock signal is low (active). Because the third node N3 (possibly due to the action of the second storage capacitor C2) maintains the low level of the first phase, the fifth transistor T5 remains on. After the second clock signal switches, the signal output terminal G(N) of the shift register unit now outputs a low-level signal. At the same time, because the second node N2 (possibly due to the action of the first storage capacitor C1) maintains the low level of the first phase, the sixth transistor T6 is turned on. The first clock signal is extracted through the drain of the sixth transistor T6 and written to the first node N1, pulling the voltage of the first node N1 higher, causing the fourth transistor T4 and the seventh transistor T7 to turn off.

[0104] Phase 3: The first clock signal is at a low level (active level), the cascade signal of the previous stage and the second clock signal are both at a high level (inactive level), the first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal, the cascade signal of the previous stage is output through the drain of the second transistor T2, and high-level signals are written to the second node N2 and the third node N3 in sequence, and the fifth transistor T5 is turned off. At the same time, a low-level signal is output through the drain of the first transistor T1, and a low-level signal is written to the first node N1, turning on the fourth transistor T4, and a high-level signal is output through the drain of the fourth transistor T4. At this time, the signal output terminal G(N) of the shift register unit outputs a high-level signal.

[0105] The fourth stage: the first clock signal and the cascade signal of the previous stage are both high level (invalid level), and the second clock signal is low level (valid level). Because the second node N2 and the third node N3 both maintain the high level of the third stage (the effect of the second storage capacitor C2), the fifth transistor T5 and the sixth transistor T6 are both turned off, the first node N1 maintains the low level of the third stage (the effect of the first storage capacitor C1), the fourth transistor T4 is turned on, and the high level signal is derived through the drain of the fourth transistor T4. At this time, the signal output terminal G(N) of the shift register unit outputs a high level signal.

[0106] Phase 5: The first clock signal is at a low level (active level), the cascade signal of the previous stage and the second clock signal are both at a high level (inactive level), the first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal, the cascade signal of the previous stage is output through the drain of the second transistor T2, and high-level signals are written to the second node N2 and the third node N3 in sequence, and the fifth transistor T5 is turned off. At the same time, a low-level signal is output through the drain of the first transistor T1, and a low-level signal is input to the first node N1, turning on the fourth transistor T4. A high-level signal is output through the drain of the fourth transistor T4. At this time, the signal output terminal G(N) of the shift register unit outputs a high-level signal.

[0107] 3 outputs a gate drive signal with a low level signal as the effective level signal, which does not meet the waveform of the forward shift signal of the first gate line G1 and the second gate line G2 shown in FIG. 2 .

[0108] In order to solve at least one of the above-mentioned technical problems, the embodiments of the present disclosure provide a shift register, a gate drive circuit and a display device. The shift register, gate drive circuit and display device provided by the embodiments of the present disclosure will be further described in detail below in combination with the accompanying drawings and specific implementation methods.

[0109] In a first aspect, an embodiment of the present disclosure provides a shift register. FIG5 is a block diagram of a shift register provided by an embodiment of the present disclosure. As shown in FIG5 , the shift register includes: a first input sub-circuit 501, a second input sub-circuit 502, a first control sub-circuit 503, a second control sub-circuit 504, a first cascade sub-circuit 505, a first output sub-circuit 507, and a second output sub-circuit 508; the first input sub-circuit 501 is configured to transmit a low-level signal to the first node N1 in response to a first clock signal; or, transmit the second clock signal to the first node N1 in response to a second clock signal; the second input sub-circuit 502 is configured to transmit the input signal to the second node N2 in response to the first clock signal; the first control sub-circuit 503 is configured to transmit a high-level signal to the first node N1 in response to a voltage of the second node N2; or, transmit a high-level signal to the first node N1 and the first input sub-circuit 501 in response to a voltage of the second node N2; The control sub-circuit 504 is configured to transmit a high-level signal to the second node N2 in response to the voltage of the first node N1 and the second clock signal; the first cascade sub-circuit 505 is configured to transmit the second clock signal to the cascade signal terminal CR(N) in response to the voltage of the second node N2; the first output sub-circuit 507 is configured to transmit a low-level signal to the signal output terminal G(N) in response to the voltage of the first node N1; the second output sub-circuit 508 is configured to transmit the first clock signal or the high-level signal to the signal output terminal G(N) in response to the voltage of the cascade signal terminal CR(N).

[0110] In the shift register that the disclosed embodiment provides, the first input subcircuit 501 can transmit low level signal or the second clock signal to the first node N1, the second input subcircuit 502 can transmit input signal to the second node N2, this input signal can specifically be the cascade signal or the initial signal (for example: STV) of the previous stage, the first control subcircuit 503 and the second control subcircuit 504 can adjust the potential of the first node N1 and the second node N2, so that the cascade signal end CR (N) connected by the first cascade subcircuit 505 outputs the cascade signal with the first timing, and this cascade signal is effective level signal with low level signal.The signal output end output that the first output subcircuit 507 and the second output subcircuit 508 are connected has the output signal of the second timing.In the same stage, the output signal of this second timing is opposite to the potential of the cascade signal of the first timing.Like this, output signal can be carried out anti-phase control so that output signal meets the waveform of the forward shift signal of the first gate line G1 and the second gate line G2 shown in Figure 2.

[0111] In some embodiments, as shown in FIG5 , the shift register further includes a second cascade sub-circuit 509 ; the second cascade sub-circuit 509 is configured to transmit the first level signal to the cascade signal terminal CR(N) in response to the voltage of the first node N1 .

[0112] The shift register provided by the embodiment of the present disclosure will be described in further detail below in combination with a specific circuit structure and timing.

[0113] Figure 6 is a schematic diagram of the circuit structure of the first shift register provided in an embodiment of the present disclosure. As shown in Figure 6, the first input sub-circuit 501 includes: a first transistor T1; the gate of the first transistor T1 is connected to the first clock signal terminal CKA, the source is connected to the second level signal terminal VGL, and the drain is connected to the first node N1.

[0114] The second input sub-circuit 502 includes: a second transistor T2; the gate of the second transistor T2 is connected to the first clock signal terminal CKA, the source is connected to the signal input terminal CR(N-1), and the drain is connected to the first control sub-circuit 503 and the second node N2.

[0115] The first control sub-circuit 503 includes: a fourth transistor T4 and a fourth sub-transistor T4'; the gate of the fourth transistor T4 is connected to the second node N2 and the gate of the fourth sub-transistor T4', the source is connected to the first level signal terminal VGH, and the drain is connected to the source of the fourth sub-transistor T4'; the gate of the fourth sub-transistor T4' is connected to the second node N2 and the gate of the fourth transistor T4, the source is connected to the drain of the fourth transistor T4, and the drain is connected to the first node N1.

[0116] The first control sub-circuit 503 further includes a fifteenth transistor T15 ; the gate of the fifteenth transistor T15 is connected to the first node N1 , the source is connected to the second level signal terminal VGL, and the drain is connected to the drain of the fourth transistor T4 and the source of the fourth sub-transistor T4 ′.

[0117] The second control subcircuit 504 includes: a fifth transistor T5 and a sixth transistor T6; the gate of the fifth transistor T5 is connected to the first node N1, the source is connected to the first level signal terminal VGH, and the drain is connected to the source of the sixth transistor T6; the gate of the sixth transistor T6 is connected to the second clock signal terminal CKB, the source is connected to the drain of the fifth transistor T5, and the drain is connected to the second node N2.

[0118] The first cascade sub-circuit 505 includes: a seventh transistor T7, an eighth transistor T8, and a second storage capacitor C2; the gate of the seventh transistor T7 is connected to the second level signal terminal VGL, the source is connected to the second node N2, and the drain is connected to the gate of the eighth transistor T8 and one end of the second storage capacitor C2; the gate of the eighth transistor T8 is connected to the drain of the seventh transistor T7 and one end of the second storage capacitor C2, the source is connected to the second clock signal terminal CKB, and the drain is connected to the cascade signal terminal CR(N) and the other end of the second storage capacitor C2. The connection point between the drain of the seventh transistor T7, the gate of the eighth transistor T8, and one end of the second storage capacitor C2 is a third node N3.

[0119] The third control sub-circuit 506 includes a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 has a gate connected to the second node N2, a source connected to the second clock signal terminal CKB, and a drain connected to the drain of the tenth transistor T10 and the second output sub-circuit 508. The tenth transistor T10 has a gate connected to the first node N1, a source connected to the first level signal terminal VGH, and a drain connected to the drain of the ninth transistor T9 and the second output sub-circuit 508. The connection point between the drain of the ninth transistor T9, the drain of the tenth transistor T10, and the second output sub-circuit 508 is a fourth node N4.

[0120] The first output sub-circuit 507 includes: an eleventh transistor T11 and a third storage capacitor C3; the gate of the eleventh transistor T11 is connected to the first node N1 and one end of the third storage capacitor C3, the source is connected to the second level signal terminal VGL, and the drain is connected to the signal output terminal G(N); one end of the third storage capacitor C3 is connected to the first node N1 and the gate of the eleventh transistor T11, and the other end is connected to the first clock signal terminal CLKA.

[0121] The first output sub-circuit 507 further includes a twelfth transistor T12 ; the gate of the twelfth transistor T12 is connected to the second level signal terminal VGL, the source is connected to the first node N1 , and the drain is connected to one end of the third storage capacitor C3 and the gate of the eleventh transistor T11 .

[0122] The second output sub-circuit 508 includes: a thirteenth transistor T13 and a fourth storage capacitor C4; the gate of the thirteenth transistor T13 is connected to the fifth node N5 and one end of the fourth storage capacitor C4, the source is connected to the first clock signal terminal CKA, and the drain is connected to the signal output terminal G(N) and the other end of the fourth storage capacitor C4; one end of the fourth storage capacitor C4 is connected to the fifth node N5 and the gate of the thirteenth transistor T13, and the other end is connected to the drain of the thirteenth transistor T13 and the signal output terminal G(N).

[0123] The second output sub-circuit 508 further includes: a fourteenth transistor T14 ; the gate of the fourteenth transistor is connected to the second level signal terminal VGL, the source is connected to the third node N4 , and the drain is connected to the fifth node N5 .

[0124] It can be seen that the fourth node N4 and the fifth node N5 are the connection points of the source and drain of the fourteenth transistor T14, respectively. Since the gate of the fourteenth transistor T14 is connected to the low-level signal terminal VGL, its source and drain are always in a conductive state, and the potentials of the fourth node N4 and the fifth node N5 are the same. Furthermore, the source and gate of the eighth transistor T8 and the ninth transistor T9 are connected to the same signal terminal. The drain of one is connected to the cascade signal terminal CR(N), and the drain of the other is connected to the fourth node N4. Therefore, the potentials of the cascade signal terminal CR(N), the fourth node N4, and the fifth node N5 are also the same.

[0125] The second cascade sub-circuit 509 includes: a sixteenth transistor T16 and a fifth storage capacitor C5; the gate of the sixteenth transistor T16 is connected to the first node N1 and one end of the fifth storage capacitor C5, the source is connected to the first level signal terminal VGH and the other end of the fifth storage capacitor C5, and the drain is connected to the cascade signal terminal CR(N).

[0126] FIG7 is a working timing diagram of the shift register shown in FIG6 . As shown in FIG7 , the working process of the shift register is divided into a first stage, a second stage, a third stage, a fourth stage and a fifth stage.

[0127] Phase 1: The first clock signal and the cascade signal of the previous stage are both low (active), and the second clock signal is high (inactive). The first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal. The cascade signal of the previous stage is derived through the drain of the second transistor T2, and a low-level signal is written to the second node N2. The seventh transistor T7 is turned on under the control of the low-level signal, and the low-level signal written to the second node N2 is continuously written to the third node N3, thereby turning on the eighth transistor T8. The second clock signal (high) is derived through the drain of the eighth transistor T8, and the cascade signal terminal CR(N) of the shift register unit outputs a high-level signal. At the same time, the low-level signal is derived through the drain of the first transistor T1, and a low-level signal is written to the first node N1, turning on the sixteenth transistor T16. The high-level signal is derived through the drain of the sixteenth transistor T16, and the cascade signal terminal CR(N) of the shift register unit outputs a high-level signal. The ninth transistor T9 is turned on under the control of the voltage at the third node N3, and the tenth transistor T10 is turned on under the control of the voltage at the first node N1. The second clock signal (high level) is output to the fourth node N4 through the drain of the ninth transistor T9, and the high level signal is output to the fourth node N4 through the drain of the tenth transistor T10. The fourteenth transistor T14 is turned on under the control of the low level signal, so that the voltage at the fourth node N4 is transmitted to the gate of the thirteenth transistor T13, turning the thirteenth transistor T13 off. Simultaneously, the twelfth transistor T12 is turned on under the control of the low level signal, transmitting the low level signal at the first node N1 to the gate of the eleventh transistor T11, turning the eleventh transistor T11 on. The low level signal is output through the drain of the eleventh transistor T11, and the signal output terminal G(N) of the shift register outputs a low level signal.

[0128] Phase 2: The first clock signal and the cascade signal from the previous stage are both high (inactive), while the second clock signal is low (active). Because the third node N3 (possibly due to the action of the second storage capacitor C2) maintains the low level of the first phase, the eighth transistor T8 remains on. After the second clock signal switches, the cascade signal terminal CR(N) of the shift register now outputs a low signal. Simultaneously, because the second node N2 (possibly due to the action of the second storage capacitor C2) maintains the low level of the first phase, the fourth transistor T4 and the fourth sub-transistor T4' are turned on. The high-level signal is output through the drain of the fourth sub-transistor T4' and written to the first node N1, raising the voltage of the first node N1 and turning off the fifth transistor T5, the sixteenth transistor T16, the tenth transistor T10, and the eleventh transistor T11. The ninth transistor T9, controlled by the voltage of the third node N3, turns on, and the second clock signal (low) is output to the fourth node N4 through the drain of the ninth transistor T9. The fourteenth transistor T14 is turned on under the control of the low-level signal, so that the voltage of the fourth node N4 is transmitted to the gate of the thirteenth transistor T13, turning on the thirteenth transistor T13. The first clock signal (high level) is derived through the drain of the thirteenth transistor T13, and the signal output terminal G(N) of the shift register outputs a high-level signal.

[0129] Phase 3: The first clock signal is at a low level (active level), and the cascade signal and second clock signal of the previous stage are both at a high level (inactive level). The first and second transistors T1 and T2 are turned on under the control of the first clock signal. The cascade signal of the previous stage is output through the drain of the second transistor T2, and high-level signals are written to the second node N2 and the third node N3, respectively. The eighth transistor T8 is turned off. Simultaneously, a low-level signal is output through the drain of the first transistor T1, and a low-level signal is written to the first node N1, turning on the sixteenth transistor T16. A high-level signal is output through the drain of the sixteenth transistor T16. At this time, the cascade signal terminal CR(N) of the shift register unit outputs a high-level signal. The ninth transistor T9 is turned off under the control of the voltage at the third node N3. The tenth transistor T10 is turned on under the control of the voltage at the first node N1, and the high-level signal is output to the fourth node N4 through the drain of the tenth transistor T10. The fourteenth transistor T14 is turned on under the control of the low-level signal, causing the voltage at the fourth node N4 to be transmitted to the gate of the thirteenth transistor T13, turning off the thirteenth transistor T13. At the same time, the twelfth transistor T12 is turned on under the control of the low-level signal to transmit the low-level signal of the first node N1 to the gate of the eleventh transistor T11, so that the eleventh transistor T11 is turned on, and the low-level signal is derived through the drain of the eleventh transistor T11. At this time, the signal output terminal G(N) of the shift register outputs a low-level signal.

[0130] Phase 4: The first clock signal and the cascade signal of the previous stage are both high (inactive), and the second clock signal is low (active). Because the second node N2 and the third node N3 both maintain the high level of the third phase (due to the second storage capacitor C2), the eighth transistor T8, the fourth transistor T4, and the fourth sub-transistor T4' are all off. The first node N1 maintains the low level of the third phase (due to the fifth storage capacitor C5). The sixteenth transistor T16 is turned on, and the high-level signal is output through the drain of the sixteenth transistor T16. At this time, the cascade signal terminal CR(N) of the shift register unit outputs a high-level signal. The ninth transistor T9 is turned off under the control of the voltage of the third node N3. The tenth transistor T10 is turned on under the control of the voltage of the first node N1. The high-level signal is output through the drain of the tenth transistor T10 to the fourth node N4. The fourteenth transistor T14 is turned on under the control of the low-level signal, causing the voltage of the fourth node N4 to be transmitted to the gate of the thirteenth transistor T13, turning the thirteenth transistor T13 off. At the same time, the twelfth transistor T12 is turned on under the control of the low-level signal to transmit the low-level signal of the first node N1 to the gate of the eleventh transistor T11, so that the eleventh transistor T11 is turned on, and the low-level signal is derived through the drain of the eleventh transistor T11. At this time, the signal output terminal G(N) of the shift register outputs a low-level signal.

[0131] Phase 5: The first clock signal is at a low level (active level), the cascade signal of the previous stage and the second clock signal are both at a high level (inactive level). The first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal. The cascade signal of the previous stage is output through the drain of the second transistor T2, and a high-level signal is written to the second node N2 and the third node N3 in sequence. The eighth transistor T8 is turned off. Simultaneously, a low-level signal is output through the drain of the first transistor T1, and a low-level signal is input to the first node N1, turning on the sixteenth transistor T16. A high-level signal is output through the drain of the sixteenth transistor T16. At this time, the cascade signal terminal CR(N) of the shift register unit outputs a high-level signal. The ninth transistor T9 is turned off under the control of the voltage of the third node N3. The tenth transistor T10 is turned on under the control of the voltage of the first node N1, and the high-level signal is output to the fourth node N4 through the drain of the tenth transistor T10. The fourteenth transistor T14 is turned on under the control of the low-level signal, so that the voltage of the fourth node N4 is transmitted to the gate of the thirteenth transistor T13, turning off the thirteenth transistor T13. At the same time, the twelfth transistor T12 is turned on under the control of the low-level signal to transmit the low-level signal of the first node N1 to the gate of the eleventh transistor T11, turning on the eleventh transistor T11. The low-level signal is then output through the drain of the eleventh transistor T11. At this time, the signal output terminal G(N) of the shift register outputs a low-level signal.

[0132] It can be seen from the circuit structure and working sequence of the above shift register that in the shift register provided by the embodiment of the present disclosure, at the same stage, the output signal terminal G <n>The output signal of the cascade signal terminal CR <n>In this way, the output signal can be inverted and controlled so that the output signal satisfies the waveform of the forward shift signal of the first gate line G1 and the second gate line G2 shown in FIG2 .

[0133] In some embodiments, according to FIG. 7 and FIG, the cascade signal of the upper stage cascade signal terminal CR(N-1) of the shift register is at a low level in the first stage, that is, the maintenance time of the upper stage cascade signal is 1H.

[0134] FIG8 is a schematic diagram of the circuit structure of a second shift register provided by an embodiment of the present disclosure. As shown in FIG8 , the structure of this shift register is similar to that shown in FIG6 . The first input subcircuit 501, the second input subcircuit 502, the second control subcircuit 504, the first cascade subcircuit 505, the first output subcircuit 507, and the second output subcircuit 508 are identical to those shown in FIG6 . The difference between this shift register and the shift register shown in FIG6 is that, in the shift register shown in FIG8 , the first control subcircuit 503 only includes: a fourth transistor T4; the gate of the fourth transistor T4 is connected to the second node N2, the source is connected to the high-level signal terminal VGH, and the drain is connected to the first node N1. The third control subcircuit 506 only includes: a tenth transistor T10; the gate of the tenth transistor T10 is connected to the second clock signal terminal CKB, the source is connected to the drain of the fifth transistor T5, and the drain is connected to the cascade signal terminal CR(N). This eliminates the need for the fourth sub-transistor T4', the ninth transistor M9, the sixteenth transistor M16, the twelfth transistor M12, the fourteenth transistor M14, and the like, thereby reducing the number of transistors and facilitating a narrow frame design. The operating timing and operating principle of the shift register shown in FIG6 can be found above and will not be further described here.

[0135] FIG9 is a schematic diagram of the circuit structure of a third shift register provided in an embodiment of the present disclosure. As shown in FIG9 , the structure of the shift register is similar to that shown in FIG6 , and the second input subcircuit 502, the second control subcircuit 504, the first cascade subcircuit 505, the first output subcircuit 507, and the second output subcircuit 508 are identical to those shown in FIG6 . The difference between the shift register and the shift register shown in FIG6 is that the first input subcircuit 501 includes: a first transistor T1 and a first storage capacitor C1; the gate of the first transistor T1 is connected to one end of the first storage capacitor C1, the source is connected to the second clock signal terminal CKB and the other end of the first storage capacitor C1, and the drain is connected to the first node N1; one end of the first storage capacitor C1 is connected to the gate of the first transistor T1, and the other end is connected to the second clock signal terminal CKB and the source of the first transistor T1. The first control sub-circuit 503 includes a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 is connected to the second node N2, the source is connected to the high-level signal terminal VGH, and the drain is connected to the first input sub-circuit 501. The gate of the fourth transistor T4 is connected to the second node N2, the source is connected to the high-level signal terminal VGH, and the drain is connected to the first node N1. The third control sub-circuit 506 includes a ninth transistor T9 and a tenth transistor T10. The gate of the ninth transistor T9 is connected to the first node N1, the source is connected to the high-level signal terminal VGH, and the drain is connected to the source of the tenth transistor T10. The gate of the tenth transistor T10 is connected to the second clock signal terminal CKB, the source is connected to the drain of the ninth transistor T9, and the drain is connected to the second output sub-circuit 508 and the cascade signal terminal CR(N).

[0136] FIG10 is a timing diagram of the operation of the shift register shown in FIG9 . As shown in FIG10 , due to the addition of the first storage capacitor C1 in the first input sub-circuit 501, the first storage capacitor C1 has a holding effect on the voltage of the first node N1, so that the maintenance time of the previous stage cascade signal is 2 hours, which is 1 hour longer than the effective level maintenance time of the previous stage cascade signal in FIG7 . Its operation timing and working principle can be referred to the above description of the shift register shown in FIG6 , and will not be described in detail here. The difference between the operation timing shown in FIG10 and the operation timing shown in FIG7 is that the maintenance time of the output signal is also 2 hours, and the output signals of the two adjacent stages of the shift register overlap for 1 hour.

[0137] FIG11 is a schematic diagram of the circuit structure of the fourth shift register provided in an embodiment of the present disclosure. As shown in FIG11 , the structure of the shift register is similar to that shown in FIG9 . The first input subcircuit 501, the second input subcircuit 502, the first control subcircuit 503, the second control subcircuit 504, the first cascade subcircuit 505, the first output subcircuit 507, and the second output subcircuit 508 are the same as those shown in FIG9 . The difference is that, in the shift register shown in FIG11 , the third control subcircuit 506 only includes: a tenth transistor T10; the gate of the tenth transistor T10 is connected to the second clock signal terminal CKB, the source is connected to the drain of the fifth transistor T5, and the drain is connected to the cascade signal terminal CR(N). In this way, there is no need to set up structures such as the ninth transistor M9, which can reduce the number of transistors and facilitate the realization of a narrow frame design. Its working timing and working principle can refer to the above description of the shift register shown in FIG9 , and will not be described in detail here.

[0138] FIG12 is a schematic diagram of the circuit structure of the fifth shift register provided in an embodiment of the present disclosure. As shown in FIG12 , the structure of the shift register is similar to that shown in FIG9 . The first input subcircuit 501, the second input subcircuit 502, the first control subcircuit 503, the second control subcircuit 504, the first cascade subcircuit 505, the third control subcircuit 506, and the first output subcircuit 507 are identical to those shown in FIG9 . The difference is that in the shift register shown in FIG12 , the source of the thirteenth transistor T13 in the second output subcircuit 508 is connected to the first clock signal terminal CKA instead of the source of the high-level signal terminal VGH. FIG13 is an operating timing diagram of the shift register shown in FIG12 , which is similar to the operating timing diagram shown in FIG10 . The operating principle will not be described in detail. The difference is that the output signals of the two adjacent shift registers in FIG13 do not overlap, and their hold time is 1H.

[0139] FIG14 is a schematic diagram of the circuit structure of the sixth shift register provided in an embodiment of the present disclosure. As shown in FIG14 , the structure of the shift register is similar to that shown in FIG12 , and the first input subcircuit 501, the second input subcircuit 502, the first control subcircuit 503, the second control subcircuit 504, the first cascade subcircuit 505, the first output subcircuit 507, and the second output subcircuit 508 are the same as those shown in FIG12 . The difference is that the third control subcircuit 506 only includes: a tenth transistor T10; the gate of the tenth transistor T10 is connected to the second clock signal terminal CKB, the source is connected to the drain of the fifth transistor T5, and the drain is connected to the cascade signal terminal CR(N). Its working timing and working principle can be referred to the above description of the shift register shown in FIG12 , and will not be described in detail here.

[0140] FIG15 is a schematic diagram of the circuit structure of the seventh shift register provided in an embodiment of the present disclosure. As shown in FIG15 , the structure of the shift register is similar to that shown in FIG12 . The second input subcircuit 502, the second control subcircuit 504, the first cascade subcircuit 505, the third control subcircuit 506, the first output subcircuit 507, and the second output subcircuit 508 are identical to those shown in FIG12 . The difference is that the first input subcircuit 501 includes: a first transistor T1; the gate of the first transistor T1 is connected to the first clock signal terminal CKA, the source is connected to the low-level signal terminal VGL, and the drain is connected to the first node N1. The first control subcircuit 503 includes: a fourth transistor T4; the gate of the fourth transistor T4 is connected to the second node N2, the source is connected to the high-level signal terminal VGH, and the drain is connected to the first node N1. FIG16 is an operating timing diagram of the shift register shown in FIG15 . As shown in FIG16 , its operating timing and operating principle can be referred to the above description of the shift register shown in FIG6 , and will not be described in detail here.

[0141] FIG17 is a schematic diagram of the circuit structure of the eighth shift register provided in an embodiment of the present disclosure. As shown in FIG17 , the structure of the shift register is similar to that shown in FIG15 . The first input subcircuit 501, the second input subcircuit 502, the first control subcircuit 503, the second control subcircuit 504, the first cascade subcircuit 505, the first output subcircuit 507, and the second output subcircuit 508 are identical to those shown in FIG15 . The difference is that the third control subcircuit 506 only includes: a tenth transistor T10; the gate of the tenth transistor T10 is connected to the first node N1, the source is connected to the high-level signal terminal VGH, and the drain is connected to the cascade signal terminal CR(N). Its operating timing and operating principle can be referred to the above description of the shift register shown in FIG15 , and will not be described in detail here.

[0142] FIG18 is a schematic diagram of the circuit structure of a ninth shift register provided in an embodiment of the present disclosure. As shown in FIG18 , the structure of this shift register is similar to that shown in FIG6 , except that the shift register shown in FIG18 does not require the fourth sub-transistor T4′, the fifteenth transistor T15, and other structures. This reduces the number of transistors and facilitates a narrow-frame design. The operating timing and operating principle of this shift register can be found in the description of the shift register shown in FIG6 , and will not be further described here.

[0143] In the second aspect, an embodiment of the present disclosure provides a driving method for a shift register, which is used to drive the shift register provided above, wherein the driving process of the shift register includes the first stage, the second stage, the third stage, the fourth stage and the fifth node. The driving method provided by the embodiment of the present disclosure will be further described in detail below using the shift register shown in Figure 6 and the working timing diagram shown in Figure 7 as examples.

[0144] Phase 1: The first clock signal and the cascade signal of the previous stage are both low (active), and the second clock signal is high (inactive). The first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal. The cascade signal of the previous stage is derived through the drain of the second transistor T2, and a low-level signal is written to the second node N2. The seventh transistor T7 is turned on under the control of the low-level signal, and the low-level signal written to the second node N2 is continuously written to the third node N3, thereby turning on the eighth transistor T8. The second clock signal (high) is derived through the drain of the eighth transistor T8, and the cascade signal terminal CR(N) of the shift register unit outputs a high-level signal. At the same time, the low-level signal is derived through the drain of the first transistor T1, and a low-level signal is written to the first node N1, turning on the sixteenth transistor T16. The high-level signal is derived through the drain of the sixteenth transistor T16, and the cascade signal terminal CR(N) of the shift register unit outputs a high-level signal. The ninth transistor T9 is turned on under the control of the voltage at the third node N3, and the tenth transistor T10 is turned on under the control of the voltage at the first node N1. The second clock signal (high level) is output to the fourth node N4 through the drain of the ninth transistor T9, and the high level signal is output to the fourth node N4 through the drain of the tenth transistor T10. The fourteenth transistor T14 is turned on under the control of the low level signal, so that the voltage at the fourth node N4 is transmitted to the gate of the thirteenth transistor T13, turning the thirteenth transistor T13 off. Simultaneously, the twelfth transistor T12 is turned on under the control of the low level signal, transmitting the low level signal at the first node N1 to the gate of the eleventh transistor T11, turning the eleventh transistor T11 on. The low level signal is output through the drain of the eleventh transistor T11, and the signal output terminal G(N) of the shift register outputs a low level signal.

[0145] Phase 2: The first clock signal and the cascade signal from the previous stage are both high (inactive), while the second clock signal is low (active). Because the third node N3 (possibly due to the action of the second storage capacitor C2) maintains the low level of the first phase, the eighth transistor T8 remains on. After the second clock signal switches, the cascade signal terminal CR(N) of the shift register now outputs a low signal. Simultaneously, because the second node N2 (possibly due to the action of the second storage capacitor C2) maintains the low level of the first phase, the fourth transistor T4 and the fourth sub-transistor T4' are turned on. The high-level signal is output through the drain of the fourth sub-transistor T4' and written to the first node N1, raising the voltage of the first node N1 and turning off the fifth transistor T5, the sixteenth transistor T16, the tenth transistor T10, and the eleventh transistor T11. The ninth transistor T9, controlled by the voltage of the third node N3, turns on, and the second clock signal (low) is output to the fourth node N4 through the drain of the ninth transistor T9. The fourteenth transistor T14 is turned on under the control of the low-level signal, so that the voltage of the fourth node N4 is transmitted to the gate of the thirteenth transistor T13, turning on the thirteenth transistor T13. The first clock signal (high level) is derived through the drain of the thirteenth transistor T13, and the signal output terminal G(N) of the shift register outputs a high-level signal.

[0146] Phase 3: The first clock signal is at a low level (active level), and the cascade signal and second clock signal of the previous stage are both at a high level (inactive level). The first and second transistors T1 and T2 are turned on under the control of the first clock signal. The cascade signal of the previous stage is output through the drain of the second transistor T2, and high-level signals are written to the second node N2 and the third node N3, respectively. The eighth transistor T8 is turned off. Simultaneously, a low-level signal is output through the drain of the first transistor T1, and a low-level signal is written to the first node N1, turning on the sixteenth transistor T16. A high-level signal is output through the drain of the sixteenth transistor T16. At this time, the cascade signal terminal CR(N) of the shift register unit outputs a high-level signal. The ninth transistor T9 is turned off under the control of the voltage at the third node N3. The tenth transistor T10 is turned on under the control of the voltage at the first node N1, and the high-level signal is output to the fourth node N4 through the drain of the tenth transistor T10. The fourteenth transistor T14 is turned on under the control of the low-level signal, causing the voltage at the fourth node N4 to be transmitted to the gate of the thirteenth transistor T13, turning off the thirteenth transistor T13. At the same time, the twelfth transistor T12 is turned on under the control of the low-level signal to transmit the low-level signal of the first node N1 to the gate of the eleventh transistor T11, so that the eleventh transistor T11 is turned on, and the low-level signal is derived through the drain of the eleventh transistor T11. At this time, the signal output terminal G(N) of the shift register outputs a low-level signal.

[0147] Phase 4: The first clock signal and the cascade signal of the previous stage are both high (inactive), and the second clock signal is low (active). Because the second node N2 and the third node N3 both maintain the high level of the third phase (due to the second storage capacitor C2), the eighth transistor T8, the fourth transistor T4, and the fourth sub-transistor T4' are all off. The first node N1 maintains the low level of the third phase (due to the fifth storage capacitor C5). The sixteenth transistor T16 is turned on, and the high-level signal is output through the drain of the sixteenth transistor T16. At this time, the cascade signal terminal CR(N) of the shift register unit outputs a high-level signal. The ninth transistor T9 is turned off under the control of the voltage of the third node N3. The tenth transistor T10 is turned on under the control of the voltage of the first node N1. The high-level signal is output through the drain of the tenth transistor T10 to the fourth node N4. The fourteenth transistor T14 is turned on under the control of the low-level signal, causing the voltage of the fourth node N4 to be transmitted to the gate of the thirteenth transistor T13, turning the thirteenth transistor T13 off. At the same time, the twelfth transistor T12 is turned on under the control of the low-level signal to transmit the low-level signal of the first node N1 to the gate of the eleventh transistor T11, so that the eleventh transistor T11 is turned on, and the low-level signal is derived through the drain of the eleventh transistor T11. At this time, the signal output terminal G(N) of the shift register outputs a low-level signal.

[0148] Phase 5: The first clock signal is at a low level (active level), the cascade signal of the previous stage and the second clock signal are both at a high level (inactive level). The first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal. The cascade signal of the previous stage is output through the drain of the second transistor T2, and a high-level signal is written to the second node N2 and the third node N3 in sequence. The eighth transistor T8 is turned off. Simultaneously, a low-level signal is output through the drain of the first transistor T1, and a low-level signal is input to the first node N1, turning on the sixteenth transistor T16. A high-level signal is output through the drain of the sixteenth transistor T16. At this time, the cascade signal terminal CR(N) of the shift register unit outputs a high-level signal. The ninth transistor T9 is turned off under the control of the voltage of the third node N3. The tenth transistor T10 is turned on under the control of the voltage of the first node N1, and the high-level signal is output to the fourth node N4 through the drain of the tenth transistor T10. The fourteenth transistor T14 is turned on under the control of the low-level signal, so that the voltage of the fourth node N4 is transmitted to the gate of the thirteenth transistor T13, turning off the thirteenth transistor T13. At the same time, the twelfth transistor T12 is turned on under the control of the low-level signal to transmit the low-level signal of the first node N1 to the gate of the eleventh transistor T11, turning on the eleventh transistor T11. The low-level signal is then output through the drain of the eleventh transistor T11. At this time, the signal output terminal G(N) of the shift register outputs a low-level signal.

[0149] Thirdly, embodiments of the present disclosure provide a gate drive circuit. FIG19 is a schematic structural diagram of a gate drive circuit according to an embodiment of the present disclosure. As shown in FIG19 , the gate drive circuit includes a cascade of multiple shift registers, such as those provided in any of the aforementioned embodiments, with the signal input terminals of the shift registers in one stage connected to the signal output terminals of the shift registers in the previous stage. The implementation principle is similar to that of the aforementioned shift registers and will not be further elaborated here.

[0150] Fourthly, embodiments of the present disclosure provide a display device comprising a gate drive circuit according to any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a television, mobile phone, monitor, laptop computer, digital photo frame, or navigation system. The implementation principles of this device are similar to those of the aforementioned shift register and gate drive circuit and will not be further elaborated here.

[0151] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.< / n> < / n>

Claims

1. [Corrected 13.08.2024 in accordance with Rule 91] A shift register, wherein: The shift register comprises: a first input subcircuit, a second input subcircuit, a first control subcircuit, a second control subcircuit, a first cascade subcircuit, a first output subcircuit and a second output subcircuit; The first input subcircuit is configured to transmit the second level signal to the first node in response to the first clock signal; or, in response to the second clock signal, transmit the second clock signal to the first node; The second input subcircuit is configured to transmit the input signal to the second node in response to the first clock signal; The first control subcircuit is configured to transmit a first level signal to the first node in response to a voltage of the second node; or, in response to a voltage of the second node, transmit a first level signal to the first node and the first input subcircuit; The second control subcircuit is configured to transmit a first level signal to a second node in response to a voltage of the first node and a second clock signal; The first cascade subcircuit is configured to transmit a second clock signal to the cascade signal terminal in response to a voltage of the second node; The first output subcircuit is configured to transmit a second level signal to the signal output terminal in response to the voltage of the first node; The second output sub-circuit is configured to transmit a first clock signal or a first level signal to the signal output terminal in response to a voltage at the cascade signal terminal.

2. The shift register according to claim 1, wherein: The first input subcircuit comprises: a first transistor; The control electrode of the first transistor is connected to the first clock signal terminal, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the first node.

3. The shift register according to claim 1, wherein: The first input subcircuit comprises: a first transistor and a first storage capacitor; The control electrode of the first transistor is connected to one end of the first storage capacitor, the first electrode is connected to the second clock signal end and the other end of the first storage capacitor, and the second electrode is connected to the first node; One end of the first storage capacitor is connected to the control electrode of the first transistor, and the other end is connected to the second clock signal end and the first electrode of the first transistor.

4. The shift register according to claim 1, wherein: The second input subcircuit includes: a second transistor; The control electrode of the second transistor is connected to the first clock signal terminal, the first electrode is connected to the signal input terminal, and the second electrode is connected to the first control subcircuit and the second node.

5. The shift register according to claim 1, wherein: The first control subcircuit includes: a fourth transistor and a fourth sub-transistor; The control electrode of the fourth transistor is connected to the second node and the control electrode of the fourth sub-transistor, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the fourth sub-transistor; The control electrode of the fourth sub-transistor is connected to the second node and the control electrode of the fourth transistor, the first electrode is connected to the second electrode of the fourth transistor, and the second electrode is connected to the first node.

6. The shift register according to claim 5, wherein: The first control subcircuit further includes: a fifteenth transistor; The control electrode of the fifteenth transistor is connected to the first node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the second electrode of the fourth transistor and the first electrode of the fourth sub-transistor.

7. The shift register according to claim 1, wherein: The first control subcircuit includes: a fourth transistor; The control electrode of the fourth transistor is connected to the second node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first node.

8. The shift register according to claim 1, wherein: The first control subcircuit includes: a third transistor and a fourth transistor; The control electrode of the third transistor is connected to the second node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first input sub-circuit; The control electrode of the fourth transistor is connected to the second node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first node.

9. The shift register according to claim 1, wherein: The second control subcircuit includes: a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is connected to the first node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the sixth transistor; The control electrode of the sixth transistor is connected to the second clock signal terminal, the first electrode is connected to the second electrode of the fifth transistor, and the second electrode is connected to the second node.

10. The shift register according to claim 1, wherein: The first cascade sub-circuit includes: a seventh transistor, an eighth transistor and a second storage capacitor; The control electrode of the seventh transistor is connected to the second level signal terminal, the first electrode is connected to the second node, and the second electrode is connected to the control electrode of the eighth transistor and one end of the second storage capacitor; The control electrode of the eighth transistor is connected to the second electrode of the seventh transistor and one end of the second storage capacitor, the first electrode is connected to the second clock signal end, and the second electrode is connected to the cascade signal end and the other end of the second storage capacitor.

11. The shift register according to claim 1, wherein: The first output sub-circuit comprises: an eleventh transistor and a third storage capacitor; The control electrode of the eleventh transistor is connected to the first node and one end of the third storage capacitor, the first electrode is connected to the second level signal end, and the second electrode is connected to the signal output end; One end of the third storage capacitor is connected to the first node and the control electrode of the eleventh transistor, and the other end is connected to the first electrode and the second level signal end of the eleventh transistor, or the other end is connected to the first clock signal end.

12. The shift register according to claim 11, wherein: The first output sub-circuit further includes: a twelfth transistor; The control electrode of the twelfth transistor is connected to the second level signal terminal, the first electrode is connected to the first node, and the second electrode is connected to one end of the third storage capacitor and the control electrode of the eleventh transistor.

13. The shift register according to claim 1, wherein: The second output sub-circuit comprises: a thirteenth transistor and a fourth storage capacitor; The control electrode of the thirteenth transistor is connected to the cascade signal terminal and one end of the fourth storage capacitor, the first electrode is connected to the first clock signal terminal or the first level signal terminal, and the second electrode is connected to the signal output terminal and the other end of the fourth storage capacitor; One end of the fourth storage capacitor is connected to the cascade signal end and the control electrode of the thirteenth transistor, and the other end is connected to the second electrode of the thirteenth transistor and the signal output end.

14. The shift register according to claim 13, wherein: The second output sub-circuit further includes: a fourteenth transistor; The control electrode of the fourteenth transistor is connected to the second level signal terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to one end of the fourth storage capacitor and the control electrode of the thirteenth transistor.

15. [Corrected 13.08.2024 as per Rule 91] A shift register according to claim 1, wherein The shift register further includes: a third control subcircuit; The third control subcircuit is configured to transmit a first level signal to the cascade signal terminal in response to the voltage of the first node and the second clock signal.

16. The shift register according to claim 15, wherein: The third control subcircuit comprises: a ninth transistor and a tenth transistor; The control electrode of the ninth transistor is connected to the second node, the first electrode is connected to the second clock signal terminal, and the second electrode is connected to the second electrode of the tenth transistor and the second output sub-circuit; The control electrode of the tenth transistor is connected to the first node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the second electrode of the ninth transistor and the second output sub-circuit.

17. The shift register according to claim 15, wherein: The third control subcircuit comprises: a ninth transistor and a tenth transistor; The control electrode of the ninth transistor is connected to the first node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the tenth transistor; The control electrode of the tenth transistor is connected to the second clock signal terminal, the first electrode is connected to the second electrode of the ninth transistor, and the second electrode is connected to the second output subcircuit and the cascade signal terminal.

18. The shift register according to claim 15, wherein: The third control subcircuit comprises: a tenth transistor; The control electrode of the tenth transistor is connected to the second clock signal terminal, the first electrode is connected to the second control subcircuit, and the second electrode is connected to the second output subcircuit and the cascade signal terminal.

19. The shift register according to claim 1, wherein: The shift register further comprises: a second cascade sub-circuit; The second cascade sub-circuit is configured to transmit a first level signal to the cascade signal terminal in response to a voltage of the first node.

20. The shift register according to claim 19, wherein: The second cascade sub-circuit comprises: a sixteenth transistor and a fifth storage capacitor; The control electrode of the sixteenth transistor is connected to the first node and one end of the fifth storage capacitor, the first electrode is connected to the first level signal end and the other end of the fifth storage capacitor, and the second electrode is connected to the cascade signal end.

21. A shift register driving method, used for driving the shift register according to any one of claims 1 to 20, wherein: The driving method of the shift register comprises: In response to the first clock signal, transmitting a second level signal to the first node; transmitting an input signal to a second node in response to a first clock signal; transmitting a first level signal to the first node in response to a voltage of the second node; In response to the voltage of the first node and the second clock signal, transmitting the first level signal to the second node; transmitting a second clock signal to the cascade signal terminal in response to a voltage of the second node; In response to the voltage of the first node, transmitting the second level signal to the signal output terminal; In response to the voltage of the cascade signal terminal, a first clock signal or a first level signal is transmitted to the signal output terminal.

22. A gate drive circuit, wherein: The gate driving circuit comprises: a plurality of shift registers according to any one of claims 1 to 20 connected in cascade; The signal input end of the shift register at this stage is connected to the signal output end of the shift register at the previous stage.

23. A display device, wherein: The display device comprises the gate driving circuit as claimed in claim 22.

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