Inter-processor communication method and apparatus for system on chip, and storage medium and electronic device

Abstract

Provided in the present disclosure are an inter-processor communication method and apparatus for a system on chip, and a storage medium and an electronic device. The inter-processor communication method for a system on chip comprises: generating a communication request for performing inter-processor communication between a first processor and a second processor; determining a target media access controller on the basis of the communication request; on the basis of the communication request and the target media access controller, reading inter-processor communication data from a first address space corresponding to the first processor; and on the basis of the target media access controller, transmitting the inter-processor communication data to a second address space corresponding to the second processor, wherein the first address space and the second address space correspond to different address spaces in a memory. Thus, address spaces accessed by a first processor and a second processor are mutually independent, which can improve the security and stability of communication; in addition, parallel communication can be performed by means of a plurality of channels of a media access controller, such that large-data-volume inter-processor communication can be implemented, thereby improving the high efficiency and flexibility of inter-processor communication.

Description

Inter-core communication method, device, storage medium and electronic equipment of system on chip

[0001] This disclosure claims priority to Chinese patent application number 202310923624.X filed on July 26, 2023, entitled “Inter-core communication method, device, storage medium and electronic device for system on chip”, the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of chip technology, and in particular to an inter-core communication method, device, storage medium, and electronic device for a system on a chip. Background Art

[0003] In recent years, processor performance in System on Chip (SoC) systems has become increasingly powerful, ushering in the era of multi-core processors for both general-purpose and embedded processors. Multi-core processors require inter-processor communication (IPC) to achieve collaborative operation and maximize the overall performance of the chip. Related technologies can employ either shared memory or internal buses for inter-core communication. Using shared memory for inter-core communication fails to guarantee resource independence between multiple virtual machines running on the multi-core processor, impacting virtual machine stability. Using internal buses for inter-core communication, however, lacks flexibility in bidirectional communication and cannot support inter-core communication of large data volumes.

[0004] Summary of the Invention

[0005] In order to solve the above technical problems, the present disclosure provides an inter-core communication method, device, storage medium and electronic device of a system on a chip to realize inter-core communication with independent multi-core access address spaces, which can improve the security, stability, efficiency and flexibility of inter-core communication.

[0006] A first aspect of an embodiment of the present disclosure provides a method for inter-core communication in a system on chip, including:

[0007] generating a communication request for inter-core communication between the first processing core and the second processing core;

[0008] determining a target media access controller based on the communication request;

[0009] Reading inter-core communication data from a first address space corresponding to the first processing core based on the communication request and the target media access controller;

[0010] Based on the target media access controller, the inter-core communication data is transmitted to a second address space corresponding to the second processing core; wherein the first address space and the second address space correspond to different address spaces in the memory.

[0011] A second aspect of the present disclosure provides an inter-core communication device of a system on chip, including:

[0012] a generating module, configured to generate a communication request for inter-core communication between the first processing core and the second processing core;

[0013] A first determining module, configured to determine a target media access controller based on the communication request;

[0014] a first reading module, configured to read inter-core communication data from a first address space corresponding to the first processing core based on the communication request and the target media access controller;

[0015] A transmission module is used to transmit the inter-core communication data to a second address space corresponding to a second processing core based on the target media access controller; wherein the first address space and the second address space correspond to different address spaces in the memory.

[0016] According to a third aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program for executing the inter-core communication method of the system on chip provided in the embodiment of the first aspect of the present disclosure.

[0017] According to the fourth aspect of the embodiments of the present disclosure, an electronic device is provided, comprising: a processor; a memory for storing instructions executable by the processor; and the processor for reading the instructions from the memory and executing the instructions to implement the inter-core communication method of the on-chip system provided in the embodiment of the first aspect of the present disclosure.

[0018] A fifth aspect of the embodiments of the present disclosure provides a computer program product, which, when an instruction processor in the computer program product executes the inter-core communication method of the system-on-chip provided by the embodiment of the first aspect of the present disclosure, executes.

[0019] The present disclosure provides an inter-core communication method for a system on chip. When a first processing core in the system on chip needs to communicate with a second processing core, a communication request is generated, and a target media access controller is determined based on the communication request. Then, based on the communication request, inter-core communication data is read from a first address space corresponding to the first processing core through the target media access controller, and the inter-core communication data is transmitted to a second address space corresponding to the second processing core. The first address space and the second address space correspond to different address spaces in a memory, ensuring that the address spaces accessed by the first processing core and the second processing core are independent of each other, thereby improving the security and stability of communication. In addition, multiple channels of the media access controller can communicate in parallel, thereby realizing inter-core communication of large amounts of data, thereby improving the efficiency and flexibility of inter-core communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1A is a schematic diagram of an inter-core communication method provided by an exemplary embodiment of the present disclosure applied to an intra-chip multi-core communication scenario;

[0021] FIG1B is a schematic diagram of an inter-core communication method provided by an exemplary embodiment of the present disclosure applied to an inter-chip multi-core communication scenario;

[0022] FIG1C is a schematic diagram of a scenario in which a processing core communicates with an external device according to an exemplary embodiment of the present disclosure;

[0023] FIG2 is a flow chart of an inter-core communication method of a system on chip provided by an exemplary embodiment of the present disclosure;

[0024] FIG3 is a flow chart of an inter-core communication method of a system on chip provided by another exemplary embodiment of the present disclosure;

[0025] FIG4 is a flow chart of an inter-core communication method of a system on chip provided by another exemplary embodiment of the present disclosure;

[0026] FIG5 is a flow chart of an inter-core communication method of a system on chip provided by another exemplary embodiment of the present disclosure;

[0027] FIG6 is a flow chart of an inter-core communication method of a system on chip provided by another exemplary embodiment of the present disclosure;

[0028] FIG7 is a flow chart of an inter-core communication method of a system on chip provided by another exemplary embodiment of the present disclosure;

[0029] FIG8 is a flow chart of an inter-core communication method of a system on chip provided by another exemplary embodiment of the present disclosure;

[0030] FIG9 is a flow chart of an inter-core communication method of a system on chip provided by another exemplary embodiment of the present disclosure;

[0031] FIG10 is a flow chart of an inter-core communication method of a system on chip provided by yet another exemplary embodiment of the present disclosure;

[0032] FIG11 is a flow chart of an inter-core communication method of a system on chip provided by another exemplary embodiment of the present disclosure;

[0033] FIG12 is a schematic diagram of the structure of an inter-core communication device of a system on chip provided by an exemplary embodiment of the present disclosure;

[0034] FIG13 is a schematic diagram showing the structure of an inter-core communication device of a system on chip provided by another exemplary embodiment of the present disclosure;

[0035] FIG14 is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0037] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0038] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0039] Overview of the Disclosure

[0040] Multi-core processors are increasingly being used in various technical fields due to their powerful parallel computing capabilities, low power consumption, and high integration. Inter-Processor Communication (IPC) is required between the cores in a multi-core processor to achieve collaborative work. In related technologies, inter-core communication mainly adopts the following two methods: The first is inter-core communication based on shared memory. With this method, multiple cores can read shared memory data, but the address spaces accessed by multiple cores cannot be guaranteed to be independent of each other, affecting the security and stability of communication. The second is inter-core communication based on the internal bus, which uses serial communication of a low-speed peripheral interface. This results in inflexible two-way communication and the inability to achieve inter-core communication with large amounts of data. How to achieve high-speed, efficient, and stable inter-core communication has become one of the urgent problems that multi-core processor chips need to solve.

[0041] In order to solve the problem in related technologies that inter-core communication cannot take into account security, stability, efficiency and flexibility, the present disclosure provides an inter-core communication method for a system on a chip. The method realizes communication between multiple cores through a media access controller. The address space corresponding to each core is different, ensuring that the address space accessed between cores is independent of each other. This can avoid mutual influence between multiple processing cores, improve the security and stability of communication, and multiple channels based on the media access controller can communicate in parallel, which can realize inter-core communication of large amounts of data, thereby improving the efficiency and flexibility of inter-core communication.

[0042] Exemplary Systems

[0043] In practical scenarios, the multiple processing cores that communicate can be located in the same system-on-chip (SoC) or in different SoCs. In the disclosed embodiments, communication between multiple processing cores in the same SoC is referred to as intra-chip multi-core communication; communication between multiple processing cores in different SoCs is referred to as inter-chip multi-core communication. Processing cores in a SoC can also communicate with external devices. The following provides exemplary descriptions of the communication application scenarios for these three types of processing cores.

[0044] Figure 1A is a schematic diagram of an inter-core communication method provided by an exemplary embodiment of the present disclosure applied to an on-chip multi-core communication scenario. As shown in Figure 1A, a system-on-chip (SoC) 10 includes two processing cores (101 and 102) for inter-core communication and a media access controller (MAC) 103.

[0045] In order to distinguish the two processing cores, the processing core that actively initiates communication is referred to as the first processing core 101 , and the processing core that passively receives communication is referred to as the second processing core 102 .

[0046] The memory 20 includes a first address space 201 and a second address space 202 , wherein the first address space 201 is an address space pre-allocated to the first processing core 101 , and the second address space 202 is an address space pre-allocated to the second processing core 102 .

[0047] MAC 103 is used for intra-chip multi-core communication and includes multiple channels (not all of which are shown in FIG1A ). A first channel 1031 is a channel pre-assigned to the first processing core 101, a second channel 1032 is a channel pre-assigned to the second processing core 102, and a loopback channel 1033 is used for intra-chip multi-core communication. The loopback channel 1033 is coupled to the first channel 1031 and the second channel 1032, respectively.

[0048] During inter-core communication, first processing core 101 generates a communication request for inter-core communication with second processing core 102. Based on the communication request, first channel 1031 of MAC 103 reads inter-core communication data from first address space 201, transmits it to second channel 1032 via loopback channel 1033, and then transmits the inter-core communication data to second address space 202 via second channel 1032.

[0049] In the embodiment of the present disclosure, the second address space 202 and the first address space 201 are different address spaces in the memory 20, so that the address spaces accessed by the first processing core 101 and the second processing core 102 are independent of each other. This can avoid mutual influence between multiple processing cores, improve the security and stability of communication, and enable parallel communication through multiple channels of the MAC 103, thereby achieving high-speed transmission of large amounts of data, thereby improving the efficiency and flexibility of inter-core communication.

[0050] In some embodiments, after the inter-core communication data is transmitted to the second address space 202, the MAC 103 may generate an interrupt message and send the interrupt message to the second processing core 102 via the second channel 1032 of the MAC 103. The second processing core 102 reads the inter-core communication data from the second address space 202 according to the interrupt message and processes it.

[0051] Figure 1B is a schematic diagram of an inter-core communication method provided by an exemplary embodiment of the present disclosure applied to an inter-chip multi-core communication scenario. As shown in Figure 1B, SoC 10 and SoC 11 each include a processing core and a MAC.

[0052] In order to distinguish the two processing cores and the two MACs, the processing core on the SoC 10 that actively initiates communication is referred to as the first processing core 101 , and the processing core on the SoC 11 that passively receives communication is referred to as the second processing core 111 .

[0053] The memory 20 includes a first address space 201 and a second address space 202. The first address space 201 is an address space pre-allocated to the first processing core 101, and the second address space 202 is an address space pre-allocated to the second processing core 111.

[0054] MAC 104 on SoC 10 and MAC 112 on SoC 11 are used for inter-chip multi-core communication. MAC 104 includes multiple channels (not all of which are shown in FIG1B ), of which first channel 1041 is a channel pre-assigned for first processing core 101. Transmit channel 1042 is used to send inter-core communication data to other SoCs (such as SoC 11 in FIG1B ). First channel 1041 and transmit channel 1042 are coupled. MAC 112 also includes multiple channels (not all of which are shown in FIG1B ), of which second channel 1121 is a channel pre-assigned for second processing core 111. Receive channel 1122 is used to receive inter-core communication data sent by other SoCs (such as SoC 10 in FIG1B ). Second channel 1121 and receive channel 1122 are coupled.

[0055] During inter-core communication, first processing core 101 on SoC 10 generates a communication request for inter-core communication with second processing core 111 on SoC 11. Based on the communication request, first channel 1041 of MAC 104 on SoC 10 reads inter-core communication data from first address space 201 and transmits the inter-core communication data to receive channel 1122 of MAC 112 on SoC 11 via transmit channel 1042 of MAC 104. MAC 112 then stores the inter-core communication data transmitted via receive channel 1122 in second address space 202 via second channel 1121.

[0056] In the embodiment of the present disclosure, the second address space 202 and the first address space 201 are different address spaces in the memory 20, so that the address spaces accessed by the first processing core 101 and the second processing core 111 are independent of each other. This can avoid mutual influence between the multiple processing cores, improve the security and stability of communication, and enable parallel communication through the multiple channels of MAC 104 and MAC 112, which can achieve high-speed transmission of large amounts of data, thereby improving the efficiency and flexibility of inter-core communication.

[0057] In some embodiments, after the inter-core communication data is transmitted to the second address space 202, the MAC 112 may generate an interrupt message and send the interrupt message to the second processing core 111 via the second channel 1121 of the MAC 112. The second processing core 111 reads the inter-core communication data from the second address space 202 according to the interrupt message and processes it.

[0058] In some embodiments, a first virtual machine (VM) VM1 may run on the first processing core 101, and a second virtual machine VM2 may run on the second processing core 111. The first address space 201 corresponding to the first processing core 101 and the second address space 202 corresponding to the second processing core 111 are different. When performing multi-core communication, the address spaces accessed by VM1 and VM2 can be guaranteed to be independent of each other, thereby preventing an abnormality in one VM from affecting other VMs, so that other VMs can run stably, thereby improving the reliability and stability of the entire system.

[0059] Figure 1C is a schematic diagram of a scenario in which a processing core communicates with an external device, according to an exemplary embodiment of the present disclosure. As shown in Figure 1C, the system-on-chip (SoC) 10 includes a first processing core 101 for communication and a media access controller (MAC) 104. MAC 104 is used to communicate between the processing core and the external device and includes multiple channels (not all of which are shown in Figure 1C). A first channel 1041 is a channel pre-allocated to the first processing core 101, and a transmit channel 1042 is used to transmit communication data.

[0060] The memory 20 includes a first address space 201 , which is an address space pre-allocated to the first processing core 101 .

[0061] The external device 40 may be a controller, a decoder, an external processor or other device, and is configured to execute corresponding processing tasks according to the communication data sent by the first processing core 101 .

[0062] The connection device 30 is used to connect the SoC 10 and the external device 40. For example, the connection device 30 can be a physical layer (PHY) or a switch. The transmission channel 1042 of the MAC 104 can be coupled to the PHY or switch to transmit communication data to the external device 30 through the PHY or switch.

[0063] During communication, the first processing core 101 of the SoC 10 generates a communication request for communicating with the external device 30. Based on the communication request, the first channel 1041 of the MAC 104 of the SoC 10 reads communication data from the first address space 201 and transmits the communication data to the connection device 30 via the transmit channel 1042 of the MAC 104. The connection device 30 transmits the communication data to the external device 40, which processes the received communication data.

[0064] In the disclosed embodiment, the SOC 10 can transmit communication data in parallel through multiple channels of the MAC 104, enabling high-speed transmission of large amounts of data, thereby improving the efficiency and flexibility of inter-core communication.

[0065] Exemplary Methods

[0066] FIG2 is a flow chart of an inter-core communication method for a system on chip provided by an exemplary embodiment of the present disclosure. The inter-core communication method can be executed by an inter-core communication device on a SoC. As shown in FIG2 , the inter-core communication method includes the following steps:

[0067] Step S201 : Generate a communication request for inter-core communication between a first processing core and a second processing core.

[0068] A first processing core on a system-on-chip (SoC) generates a communication request for inter-core communication with a second processing core. The second processing core may be located on the same SoC as the first processing core, or on a different SoC. When the first and second processing cores are located on the same SoC, the communication request is an intra-chip communication request; when the first and second processing cores are located on different SoCs, the communication request is an inter-chip communication request.

[0069] In the embodiment of the present disclosure, the communication request carries at least an identifier of the first processing core and an identifier of the second processing core.

[0070] Step S202: Determine a target media access controller based on the communication request.

[0071] The SoC can be equipped with multiple media access controllers (MACs), each of which can implement different functions. For example, MAC 103 shown in FIG1A can implement intra-chip multi-core communication, while MAC 104 shown in FIG1B can implement inter-chip multi-core communication. Based on the communication request generated by the first processing core, one of the multiple MACs is determined as the target MAC. For example, if the communication request is for intra-chip communication, MAC 103 is used as the target MAC; if the communication request is for inter-chip communication, MAC 104 is used as the target MAC.

[0072] Step S203 : Based on the communication request and the target media access controller, read the inter-core communication data from the first address space corresponding to the first processing core.

[0073] A first address space is pre-allocated in the memory for the first processing core. The target MAC determines an access address for accessing the first address space based on the communication request, and reads inter-core communication data to be transmitted based on the access address.

[0074] Step S204 : transmitting the inter-core communication data to a second address space corresponding to the second processing core based on the target media access controller.

[0075] After the target MAC reads the inter-core communication data, it transmits the data to the second address space allocated to the second processing core, so that the second processing core reads the inter-core communication data from the second address space and processes the data.

[0076] In the embodiment of the present disclosure, the first address space and the second address space correspond to different address spaces in the memory. For example, the first processing core reads and writes the 0-2G address space in the memory, and the second processing core reads and writes the 2-4G address space in the memory. Since the address spaces for the first processing core and the second processing core to read and write are different, the address spaces accessed by the first processing core and the second processing core are independent of each other. This can avoid mutual influence between multiple processing cores and improve the security and stability of communication. The first processing core and the second processing core communicate between the cores through MAC, and high-speed transmission of large amounts of data can be achieved based on parallel communication of multiple channels, thereby improving the efficiency and flexibility of inter-core communication.

[0077] As shown in FIG3 , based on the embodiment shown in FIG2 , step S202 “determining a target media access controller based on the communication request” may include steps S2021 and S2022:

[0078] Step S2021 : determining a relative relationship between the system on chip and the second processing core based on the identifier of the second processing core in the communication request.

[0079] The first processing core can generate a communication request based on its own identification, the identification of the second processing core to be communicated, and the virtual address corresponding to the data to be transmitted. The inter-core communication device determines whether the second processing core is located on the same SoC as the first processing core based on the identification of the second processing core in the communication request. When the second processing core and the first processing core are located on the same SoC (as shown in Figure 1A), the relative relationship is determined as the second processing core is on the SoC; when the second processing core and the first processing core are located on different SoCs (as shown in Figure 1B), the relative relationship is determined as the second processing core is not on the SoC. It should be noted that the SoC here specifically refers to the SoC where the first processing core is located, and the second processing core is not on the SoC, which means that the second processing core is not on the SoC where the first processing core is located, and the second processing core is on other SoCs.

[0080] Step S2022 : determining a target media access controller from a plurality of media access controllers of the system on chip based on the relative relationship.

[0081] In the embodiment of the present disclosure, the target MACs determined by different relative relationships are different. Using different MACs can realize multiple inter-core communication modes such as intra-chip multi-core communication and inter-chip multi-core communication, thereby improving the flexibility of inter-core communication.

[0082] In some embodiments, when the relative relationship is that the second processing core is on a system on a chip, the target MAC address may be determined according to the following steps:

[0083] Step S20221 : In response to the relative relationship that the second processing core is on the system on chip, determining that the type of the communication request is an intra-chip communication type.

[0084] When the first processing core and the second processing core are located on the same SoC, the communication request is determined to be an intra-chip communication request. In this case, the type of the communication request is an intra-chip communication type, such as the multi-core communication scenario shown in FIG1A .

[0085] Step S20222: Select a media access controller for intra-chip communication from a plurality of media access controllers in the system on chip as a target media access controller.

[0086] The SoC may be provided with multiple MACs, and different MACs implement different functions. When intra-chip multi-core communication is required, a MAC for intra-chip communication (such as MAC 103 shown in FIG1A ) is selected from the multiple MACs as the target MAC.

[0087] In some embodiments, when the relative relationship is that the second processing core is not on the system on chip, the target MAC may be determined according to the following steps:

[0088] Step S20223 : In response to the relative relationship that the second processing core is not on the system on chip, determining that the type of the communication request is an inter-chip communication type.

[0089] When the first processing core and the second processing core are located on different SoCs, the communication request is determined to be an inter-chip communication request. In this case, the type of the communication request is an inter-chip communication type, as shown in the multi-core communication scenario in FIG1B .

[0090] Step S20224: Select a media access controller for inter-chip communication from a plurality of media access controllers in the system on chip as a target media access controller.

[0091] The SoC may be provided with multiple MACs, and different MACs implement different functions. When inter-chip multi-core communication is required, a MAC for inter-chip communication (such as MAC 104 shown in FIG. 1B ) is selected from the multiple MACs as the target MAC.

[0092] The method provided by the embodiment of the present disclosure determines the communication type through the relative relationship between the system on chip and the second processing core, and determines the corresponding target MAC based on the communication type, thereby enabling adaptive determination of the target MAC.

[0093] As shown in FIG4 , based on the above embodiment, step S203 “reading inter-core communication data from the first address space corresponding to the first processing core based on the communication request and the target media access controller” may include the following steps S2031 and S2032:

[0094] Step S2031 : Based on the identifier of the first processing core in the communication request, determine a first channel corresponding to the identifier of the first processing core from multiple channels of the target media access controller.

[0095] The inter-core communication device determines the first channel CH1 (the first channel 1031 shown in Figure 1A) corresponding to the first processing core among the multiple channels of the target MAC according to the identifier of the first processing core in the communication request. The CH1 is a channel pre-allocated to the first processing core, and data transmission between the first processing core and the target MAC is realized based on the CH1.

[0096] Step S2032: Based on the communication request, read inter-core communication data from the first address space corresponding to the first processing core through the first channel.

[0097] After the inter-core communication device determines that the channel pre-allocated to the first processing core in the target MAC is the first channel, the target MAC receives the communication request through the first channel and reads the inter-core communication data from the first address space corresponding to the first processing core based on the communication request.

[0098] The method provided by the embodiment of the present disclosure reads data from the memory through MAC. Multiple channels of MAC can communicate in parallel, thereby enabling high-speed reading of large amounts of data, thereby improving the efficiency of inter-core communication.

[0099] In actual applications, since the processor uses virtual addresses to read and write memory, that is, the access address carried in the communication request is a virtual address, the virtual address needs to be mapped to a physical address before the first channel can read the inter-core communication data from the first address space.

[0100] In one implementation, the target MAC can read the inter-core communication data from the first address space via a system memory management unit (SMMU) on the SoC. In the disclosed embodiment, the SMMU is a hardware device that provides direct memory access (DMA) address translation and memory isolation functions, allowing only specific devices to perform DMA transactions in specific memory areas and preventing them from accessing memory address spaces outside of the specific memory areas.

[0101] As shown in FIG5 , based on the above embodiment, step S2032 “reading inter-core communication data from the first address space corresponding to the first processing core through the first channel based on the communication request” may include the following steps S321 to S323:

[0102] Step S321 : Determine the permission to access the first address space corresponding to the first processing core based on the virtual address in the communication request and the identifier of the first processing core.

[0103] The MAC transmits the first processing core identifier and virtual address carried in the communication request to the SMMU via the first channel. The SMMU determines whether the access permission is granted based on the first processing core identifier and virtual address. In one implementation, the SMMU may determine the access permission by:

[0104] Step S3211 : determining a target address mapping table corresponding to the identifier of the first processing core from a plurality of preset address mapping tables.

[0105] A virtual address space is allocated to each processing core in advance, and a correspondence between the virtual address space of each processing core and the physical address space in the memory is specified, and each correspondence is stored in the SMMU in the form of an address mapping table.

[0106] After the SMMU receives the first processing core identifier and virtual address sent by the first channel, it first searches for the address mapping table corresponding to the first processing core in multiple address mapping tables based on the identifier of the first processing core. If the search is successful, the found address mapping table is determined as the target address mapping table, which includes the correspondence between the virtual address space corresponding to the first processing core and the first address space. If the search fails, it means that the SMMU has not pre-established an address mapping table for the first processing core. In this case, the first processing core does not have access rights to the memory and cannot read the inter-core communication data to be transmitted, resulting in inter-core communication failure between the first processing core and the second processing core.

[0107] After finding the target address mapping table, it is determined whether the virtual address is within the virtual address space of the target address mapping table, that is, whether the virtual address space contains the virtual address. If the virtual address space contains the virtual address, it indicates that the virtual address to be accessed is within the first address space corresponding to the first processing core, and the process proceeds to step S3212. If the virtual address space does not contain the virtual address, it indicates that the virtual address to be accessed is not within the first address space corresponding to the first processing core, and the process proceeds to step S3213.

[0108] Step S3212 : In response to the virtual address space containing the virtual address, determining that the user has permission to access the first address space corresponding to the first processing core.

[0109] When it is determined that the first processing core has the permission to access the first address space, the process proceeds to step S322 .

[0110] Step S3213 : In response to the virtual address space not including the virtual address, it is determined that the user does not have permission to access the first address space corresponding to the first processing core.

[0111] When it is determined that the first processing core does not have permission to access the first address space, the first processing core cannot read the inter-core communication data to be transmitted, and the inter-core communication between the first processing core and the second processing core fails.

[0112] Step S322: In response to having permission to access the first address space, determining a physical address corresponding to the virtual address in the first address space.

[0113] Since the first processing core generates a virtual address and the memory stores a physical address, after determining that the first processing core has permission to access the first address space, the SMMU translates the virtual address according to the target address mapping table to obtain a physical address. The data stored in the physical address is the inter-core communication data.

[0114] Step S323: read the inter-core communication data from the physical address through the first channel.

[0115] The first channel of the MAC reads the inter-core communication data from the physical address through the SMMU. The MAC can then store the read inter-core communication data in the first cache corresponding to the first channel.

[0116] The method provided by the embodiment of the present disclosure can successfully read the inter-core communication data only under the premise of determining that the virtual address in the communication request has the permission to access the first address space, thereby realizing hard isolation between the processing core and the memory and improving communication security; and the first processor can only access the first address space and cannot access other address spaces in the memory, thereby realizing isolation of memory access between processing cores, thus avoiding multiple processing cores from reading and writing data at the same physical address and improving communication stability.

[0117] As shown in FIG6 , based on the above embodiment, step S204 “transmitting the inter-core communication data to the second address space corresponding to the second processing core based on the target media access controller” may include the following steps S2041 to S2043:

[0118] Step S2041 : In response to the target media access controller being a media access controller for intra-chip communication, determining a second channel corresponding to the identifier of the second processing core from a plurality of channels of the target media access controller.

[0119] When the target MAC is a MAC used for intra-chip communication (MAC 103 as shown in FIG1A ), the inter-core communication device determines, based on the identifier of the second processing core in the communication request, a second channel CH2 (second channel 1032 as shown in FIG1A ) corresponding to the second processing core among the multiple channels of MAC 103 . This CH2 is a channel pre-allocated to the second processing core, and data transmission between the second processing core and MAC1 is implemented based on CH2.

[0120] Step S2042 : Based on the loopback channel of the target media access controller, the inter-core communication data in the first cache corresponding to the first channel is transmitted to the second cache corresponding to the second channel.

[0121] When performing intra-chip multi-core communication, data can be transmitted using a loopback channel (LoopBack Channel) among the multiple channels of MAC 103. A loopback channel generally refers to physically connecting a sending channel and a receiving channel so that all data sent through the loopback channel will be received by the receiving channel.

[0122] CH1 transfers inter-core communication data in the first cache to the loopback channel's transmit queue (TX). Due to the loopback channel's self-transmitting and receiving characteristics, inter-core communication data enters the loopback channel's receive queue (RX). The loopback channel then transfers the inter-core communication data in the receive queue to the second cache. This second cache corresponds to CH2.

[0123] Step S2043: storing the inter-core communication data in the second cache to the second address space corresponding to the second processing core through the second channel.

[0124] Since the second processing core has been allocated the second address space and CH2 in advance, after receiving the inter-core communication data, CH2 knows that the data is to be transmitted to the second processing core, and therefore stores the inter-core communication data in the second cache corresponding to CH2 in the second address space corresponding to the second processing core.

[0125] The method provided by the embodiment of the present disclosure can use the loopback channel of MAC 103 for data transmission when performing on-chip multi-core communication, which can reduce communication delay and communication reliability.

[0126] Based on the above embodiments, the present disclosure further provides an inter-core communication method of a system on chip. FIG7 is a flow chart of the inter-core communication method of a system on chip provided by another exemplary embodiment of the present disclosure. As shown in FIG7 , the inter-core communication method includes the following steps:

[0127] Step S701: Determine an interrupt message generated by a target media access controller based on an identifier of a second channel.

[0128] After CH2 of MAC 103 stores the inter-core communication data in the second address space corresponding to the second processing core, it generates an interrupt message, which is used to trigger the second processing core to process the inter-core communication data.

[0129] Step S702 : In response to the interrupt message, the second processing core reads the inter-core communication data from the second address space, and processes the inter-core communication data to obtain inter-core reply data.

[0130] After receiving the interrupt message sent by CH2, the second processing core parses it to obtain the identifier of the second channel. Based on the identifier of the second channel, the second processing core can determine the storage address. Then, based on the storage address, the second processing core reads the inter-core communication data from the second address space and processes it.

[0131] In one example, the second processing core processes the inter-core communication data, and the second processing core can continue to send the inter-core communication data to other processing cores on the chip, or to an external electronic device (such as a terminal device such as a computer or server), and the other processing cores on the chip or the external electronic device calculate the inter-core communication data to obtain a calculation result. In another example, the second processing core processes the inter-core communication data, and the second processing core calculates the inter-core communication data to obtain a calculation result.

[0132] In the disclosed embodiment, the second processing core can determine inter-core reply data based on the calculation results and store the inter-core reply data in a second address space, thereby implementing inter-core data transmission and processing. The second address space where the second processing core stores the inter-core reply data and the first address space where the first processing core reads the inter-core communication data correspond to different address spaces in the memory, allowing the first and second processing cores to independently read and write, thereby improving the security and stability of communication.

[0133] Based on the above embodiments, the present disclosure further provides a method for inter-core communication in a system on chip. FIG8 is a flow chart of the method for inter-core communication in a system on chip provided by another exemplary embodiment of the present disclosure. As shown in FIG8 , the method for inter-core communication includes the following steps:

[0134] Step S801 : reading inter-core reply data from a second address space corresponding to a second processing core through a second channel.

[0135] In practical applications, it may be necessary to transmit inter-core reply data back to the first processing core. In this case, the second processing core generates a communication reply request, requesting inter-core reply communication with the first processing core. As shown in Figure 1A , CH2 (i.e., second channel 1032) in MAC 103 reads the inter-core reply data from the second address space corresponding to the second processing core based on the received communication reply request and temporarily stores it in the second cache.

[0136] Step S802 : Based on the loop channel, the inter-core reply data in the second cache corresponding to the second channel is transmitted to the first cache corresponding to the first channel.

[0137] The inter-core reply data in the second cache is transferred to the first cache corresponding to CH1 of the MAC 103 by using the loopback channel in the MAC 103 .

[0138] Step S803 : storing the inter-core reply data in the first cache to the first address space corresponding to the first processing core via the first channel.

[0139] After CH1 stores the inter-core reply data in the first address space, it can generate an interrupt message and send it to the first processing core. After receiving the interrupt message sent by CH1, the first processing core reads the inter-core reply data from the first address space.

[0140] The method provided by the embodiment of the present disclosure enables bidirectional communication among multiple processing cores within a chip, and can realize bidirectional communication services that take into account both sending and receiving. In addition, the address spaces accessed by the multiple processing cores are independent of each other, which can improve the security and stability of communication.

[0141] As shown in FIG9 , based on the above embodiment, step S204 “transmitting the inter-core communication data to the second address space corresponding to the second processing core based on the target media access controller” can be implemented through steps S2044 and S2045:

[0142] Step S2044 : In response to the target media access controller being a media access controller for inter-chip communication, the inter-core communication data in the first cache corresponding to the first channel is transmitted to a sending channel of the target media access controller.

[0143] When the target MAC is a MAC for inter-chip communication (such as MAC 104 as shown in FIG. 1B ), the inter-core communication device determines the transmission channel to be the sending channel of MAC 104 .

[0144] Step S2045 : sending the inter-core communication data through the sending channel, so that the media access controller of the system on chip where the second processing core is located receives the inter-core communication data and stores the inter-core communication data in the second address space corresponding to the second processing core.

[0145] The inter-core communication data is sent via the transmission channel of the MAC 104 in the SoC 10, so that the media access controller MAC (MAC 112 in FIG. 1B ) in the system-on-chip (SoC 11 in FIG. 1B ) where the second processing core resides receives the inter-core communication data and stores the inter-core communication data in the second address space corresponding to the second processing core. This implements inter-chip multi-core communication.

[0146] The method provided by the embodiments of the present disclosure enables inter-chip multi-core communication by using the transmit channel of MAC 104 on SoC 10 to transmit inter-core communication data, which is then received by the receive channel of MAC 112 on SoC 11. This enables inter-chip multi-core communication. Multiple MAC channels can communicate in parallel, enabling efficient transmission of large amounts of data, thereby improving the efficiency and flexibility of inter-core communication.

[0147] After receiving the inter-core communication data, the receive channel of MAC 112 on SoC 11 transmits it via the receive channel to the second cache of MAC 112's second channel CH2 (shown as second channel 1121 in FIG1B ), which is pre-allocated for the second processing core. MAC 112's second channel stores the inter-core communication data in the second cache in the second address space. MAC 112 then generates a second interrupt message, which triggers the second processing core on SoC 11 to process the inter-core communication data. After receiving the second interrupt message sent by MAC 112's CH2, the second processing core on SoC 11 parses it to obtain the identifier of the second channel. Based on the identifier of the second channel, the second processing core determines a storage address. Based on this storage address, the second processing core then reads the inter-core communication data from the second address space and processes it to obtain inter-core reply data.

[0148] In some embodiments, the second processing core on SoC 11 needs to send inter-core reply data back to the first processing core on SoC 10. The following steps are then performed: the second processing core on SoC 11 generates a communication reply request, requesting inter-core reply communication with the first processing core on SoC 10. Based on the received communication reply request, CH2 in MAC 112 reads the inter-core reply data from the second address space and temporarily stores it in the second cache. The inter-core reply data is then sent using a transmit channel (not shown in FIG. 1B ) in MAC 112.

[0149] After the transmit channel of the MAC 112 on the SoC 11 sends the inter-core reply data, the MAC 104 on the SoC 10 continues to execute the following steps shown in FIG. 10 :

[0150] Step S1001 : receiving inter-core reply data sent by a media access controller in a system on chip where a second processing core is located, based on a receiving channel of a target media access controller.

[0151] The receiving channel (not shown in FIG. 1B ) of the MAC 104 on the SoC 10 receives the inter-core reply data sent by the transmitting channel of the MAC 112 on the SoC 11 .

[0152] Step S1002 : Transmit the inter-core reply data to the first cache corresponding to the first channel.

[0153] The received inter-core reply data is transmitted to the first channel CH1 of MAC 104 (the first channel 1041 shown in FIG. 1B ) via the receiving channel of MAC 104 , and then stored in the first buffer corresponding to CH1 of MAC 104 by CH1 .

[0154] Step S1003 : storing the inter-core reply data in the first cache into the first address space corresponding to the first processing core.

[0155] Since the first processing core and CH1 are already allocated in advance, upon receiving the inter-core reply data, CH1 knows that the data is to be transmitted to the first processing core, and therefore stores the inter-core reply data in the first cache corresponding to CH1 into the first address space corresponding to the first processing core.

[0156] The method provided by the embodiment of the present disclosure can use the receiving channel of MAC 104 to receive data transmitted by other SoCs when performing inter-chip multi-core communication, thereby realizing bidirectional communication between inter-chip multi-cores and achieving a bidirectional communication service that takes both sending and receiving into consideration.

[0157] Based on the above embodiments, the present disclosure further provides an inter-core communication method of a system on chip. FIG11 is a flow chart of the inter-core communication method of a system on chip provided by another exemplary embodiment of the present disclosure. As shown in FIG11 , the inter-core communication method includes the following steps:

[0158] Step S1101 : determining first configuration information corresponding to a first virtual machine running on a first processing core, and second configuration information corresponding to a second virtual machine running on a second processing core.

[0159] In the disclosed embodiment, a first virtual machine (VM1) may run on a first processing core, and a second virtual machine (VM2) may run on a second processing core. VM1 and VM2 may be managed by a virtual machine monitor (Hypervisor). When the SoC boots and executes the Hypervisor, the Hypervisor obtains first configuration information corresponding to VM1 and second configuration information corresponding to VM2, and allocates resources to VM1 and VM2 based on these configuration information.

[0160] Step S1102 : Based on the address configuration information in the first configuration information and the address configuration information in the second configuration information, allocate a first address space for the first processing core and allocate a second address space for the second processing core in the memory.

[0161] Step S1103 : Allocate a first channel to the first processing core and allocate a second channel to the second processing core based on the channel configuration information in the first configuration information and the channel configuration information in the second configuration information.

[0162] The resources allocated by the hypervisor to the VMs may include memory and MAC channels. Therefore, the first configuration information and the second configuration information may include address configuration information and channel configuration information. Based on the first configuration information, the hypervisor allocates a first address space in the memory and a first channel in the MAC address to VM1, and based on the second configuration information, allocates a second address space in the memory and a second channel in the MAC address to VM2. VM1 and VM2 are started based on the address spaces and channels configured by the hypervisor.

[0163] In the embodiment of the present disclosure, based on the address configuration information in the configuration information, a first address space is configured for the first processing core running VM1, and a second address space is configured for the second processing core running VM2. The first address space and the second address space are different address spaces in the memory, so that the address spaces accessed by the first processing core and the second processing core are independent of each other. This can avoid mutual influence between multiple processing cores and improve the security and stability of communication. Based on the channel configuration information in the configuration information, different channels in the MAC are allocated to the first processing core and the second processing core. In the case of multi-core communication, multiple channels based on the MAC communicate in parallel, which can achieve high-speed transmission of large amounts of data, thereby improving the efficiency and flexibility of inter-core communication.

[0164] Exemplary devices

[0165] FIG12 is a schematic diagram of the structure of an inter-core communication device of a system on chip provided by an exemplary embodiment of the present disclosure. As shown in FIG12 , the inter-core communication device 1200 of the system on chip may include:

[0166] A generating module 1201 is configured to generate a communication request for inter-core communication between a first processing core and a second processing core;

[0167] A first determining module 1202 is configured to determine a target media access controller based on the communication request generated by the generating module 1201;

[0168] A first reading module 1203 is configured to read inter-core communication data from a first address space corresponding to the first processing core based on the communication request generated by the generating module 1201 and the target media access controller determined by the first determining module 1202;

[0169] The transmission module 1204 is used to transmit the inter-core communication data read by the first reading module 1203 to the second address space corresponding to the second processing core based on the target media access controller determined by the first determination module 1202; wherein the first address space and the second address space correspond to different address spaces in the memory.

[0170] As shown in FIG13 , based on the embodiment shown in FIG12 , the first determining module 1202 may include:

[0171] A first determining unit 12021 is configured to determine a relative relationship between the system on chip and the second processing core based on the identifier of the second processing core in the communication request;

[0172] The second determining unit 12022 is configured to determine a target media access controller from the plurality of media access controllers of the system on chip based on the relative relationship.

[0173] In some embodiments, the second determining unit 12022 may include:

[0174] a first determining subunit, configured to determine, in response to the relative relationship being that the second processing core is on the system on chip, that the type of the communication request is an intra-chip communication type;

[0175] The first selection subunit is configured to select a media access controller for intra-chip communication from a plurality of media access controllers of the system on chip as a target media access controller.

[0176] In some embodiments, the first determining subunit is further configured to, in response to the relative relationship being that the second processing core is not on the system on chip, determine that the type of the communication request is an inter-chip communication type;

[0177] The first selection subunit is further configured to select a media access controller for inter-chip communication from a plurality of media access controllers of the system on chip as a target media access controller.

[0178] In some embodiments, the first reading module 1203 may include:

[0179] a third determining unit 12031, configured to determine, based on the identifier of the first processing core in the communication request, a first channel corresponding to the identifier of the first processing core from the plurality of channels of the target media access controller;

[0180] The reading unit 12032 is configured to read inter-core communication data from the first address space corresponding to the first processing core through the first channel based on the communication request.

[0181] In some embodiments, the reading unit 12032 may include:

[0182] a second determining subunit, configured to determine permission to access a first address space corresponding to the first processing core based on the virtual address in the communication request and the identifier of the first processing core;

[0183] a third determining subunit, configured to determine a physical address corresponding to the virtual address in the first address space in response to having permission to access the first address space;

[0184] A reading subunit is used to read inter-core communication data from the physical address through the first channel.

[0185] In some embodiments, the third determination sub-unit is further used to: determine a target address mapping table corresponding to the identifier of the first processing core from a plurality of preset address mapping tables, the target address mapping table including a correspondence between the virtual address space corresponding to the first processing core and the first address space; in response to the virtual address space containing the virtual address, determine that the user has permission to access the first address space corresponding to the first processing core.

[0186] In some embodiments, the transmission module 1204 may include:

[0187] a fourth determining unit 12041 configured to, in response to the target media access controller being a media access controller for intra-chip communication, determine a second channel corresponding to the identifier of the second processing core from a plurality of channels of the target media access controller;

[0188] A first transmission unit 12042 is configured to transmit the inter-core communication data in the first cache corresponding to the first channel to the second cache corresponding to the second channel based on the loopback channel of the target media access controller;

[0189] The first storage unit 12043 is configured to store the inter-core communication data in the second cache to a second address space corresponding to the second processing core through the second channel.

[0190] In some embodiments, the inter-core communication device 1200 of the system on chip may further include:

[0191] A second determining module, configured to determine an interrupt message generated by the target media access controller based on an identifier of the second channel;

[0192] The second reading module is used to respond to the interrupt message, read the inter-core communication data from the second address space through the second processing core, and process the inter-core communication data to obtain inter-core reply data.

[0193] In some embodiments, the transmission module 1204 may include:

[0194] a second transmission unit 12044 configured to transmit the inter-core communication data in the first cache corresponding to the first channel to a sending channel of the target media access controller in response to the target media access controller being a media access controller for inter-chip communication;

[0195] The sending unit 12045 is used to send the inter-core communication data through the sending channel so that the media access controller in the on-chip system where the second processing core is located receives the inter-core communication data and stores the inter-core communication data in the second address space corresponding to the second processing core.

[0196] In some embodiments, the transmission module 1204 may include:

[0197] The receiving unit 12046 is configured to receive, based on a receiving channel of the target media access controller, inter-core reply data sent by the media access controller in the system-on-chip where the second processing core is located;

[0198] A third transmission unit 12047 is configured to transmit the inter-core reply data to a first cache corresponding to the first channel;

[0199] The second storage unit 12048 is configured to store the inter-core reply data in the first cache into a first address space corresponding to the first processing core.

[0200] In some embodiments, the inter-core communication device 1200 of the system on chip may further include:

[0201] a third determining module, configured to determine first configuration information corresponding to a first virtual machine running on the first processing core, and second configuration information corresponding to a second virtual machine running on the second processing core;

[0202] a first allocation module, configured to allocate the first address space to the first processing core and allocate the second address space to the second processing core in the memory based on the address configuration information in the first configuration information and the address configuration information in the second configuration information;

[0203] The second allocation module is configured to allocate a first channel to the first processing core and allocate a second channel to the second processing core based on the channel configuration information in the first configuration information and the channel configuration information in the second configuration information.

[0204] The beneficial technical effects corresponding to the exemplary embodiments of the device disclosed herein can be found in the corresponding beneficial technical effects of the exemplary method section above, which will not be repeated here.

[0205] Exemplary electronic devices

[0206] FIG14 is a schematic diagram of the composition structure of an electronic device provided by an exemplary embodiment of the present disclosure. As shown in FIG14 , the electronic device 1400 includes at least one processor 1401 and a memory 1402 .

[0207] The processor 1401 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1400 to perform desired functions.

[0208] The memory 1402 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1401 may execute the one or more computer program instructions to implement the inter-core communication method and / or other desired functions of the system-on-chip of each embodiment of the present disclosure described above.

[0209] In one example, the electronic device 1400 may further include an input device 1403 and an output device 1404 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0210] The input device 1403 may also include, for example, a keyboard, a mouse, etc.

[0211] The output device 1404 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and its connected remote output devices, etc.

[0212] Of course, for simplicity, FIG14 only shows some of the components related to the present disclosure in the electronic device 1400, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 1400 may further include any other appropriate components depending on the specific application.

[0213] Exemplary computer program products and computer-readable storage media

[0214] In addition to the above-mentioned methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the plug-in processing method or data processing method of the neural network model of various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.

[0215] The computer program product may be written in any combination of one or more programming languages ​​to implement the program code for performing the operations of the disclosed embodiments. Programming languages ​​include object-oriented programming languages ​​such as Java, C++, and the like, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0216] In addition, embodiments of the present disclosure may also provide a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the processor executes the steps of the plug-in processing method or data processing method of the neural network model of various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.

[0217] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or component comprising electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0218] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, the advantages, strengths, and effects mentioned in this disclosure are merely illustrative and not restrictive, and should not be considered as essential to each embodiment of the present disclosure. Furthermore, the specific details disclosed above are provided for illustrative purposes and to facilitate understanding, rather than as limitations. These details do not limit the present disclosure to necessarily being implemented using these specific details.

[0219] Each embodiment in this specification is described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. References to the same or similar parts between the various embodiments are sufficient. For system embodiments, since they largely correspond to method embodiments, their description is relatively simple. For relevant parts, references to the description of the method embodiments are sufficient.

[0220] The block diagrams of the devices, devices, equipment, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, equipment, and systems can be connected, arranged, or configured in any manner. Words such as "include," "comprise," "have," and the like are open-ended words, meaning "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or" and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0221] The methods and apparatus of the present disclosure may be implemented in many ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless otherwise specified. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, which include machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers recording media that store programs for executing the methods according to the present disclosure.

[0222] It should also be noted that in the apparatus, device, and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0223] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0224] The above description has been provided for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method for inter-core communication of a system on chip, comprising: generating a communication request for inter-core communication between the first processing core and the second processing core; Based on the communication request, determining a target media access controller; Based on the communication request and the target media access controller, reading inter-core communication data from a first address space corresponding to the first processing core; Based on the target media access controller, the inter-core communication data is transmitted to a second address space corresponding to a second processing core; wherein the first address space and the second address space correspond to different address spaces in a memory.

2. The method according to claim 1, wherein: The step of determining a target media access controller based on the communication request comprises: Determining a relative relationship between the system on chip and the second processing core based on the identifier of the second processing core in the communication request; Based on the relative relationship, a target media access controller is determined from a plurality of media access controllers of the system on chip.

3. The method according to claim 2, wherein: The step of determining a target media access controller from a plurality of media access controllers of the system on chip based on the relative relationship comprises: In response to the relative relationship being that the second processing core is on the system on chip, determining that the type of the communication request is an intra-chip communication type; A media access controller for intra-chip communication is selected from a plurality of media access controllers of the system on chip as a target media access controller.

4. The method according to claim 2, wherein: The step of determining a target media access controller from a plurality of media access controllers of the system on chip based on the relative relationship comprises: In response to the relative relationship being that the second processing core is not on the system on chip, determining that the type of the communication request is an inter-chip communication type; A media access controller for inter-chip communication is selected from a plurality of media access controllers of the system-on-chip as a target media access controller.

5. The method according to claim 1, wherein: The reading inter-core communication data from a first address space corresponding to the first processing core based on the communication request and the target media access controller includes: Based on the identification of the first processing core in the communication request, determining a first channel corresponding to the identification of the first processing core from a plurality of channels of the target media access controller; Based on the communication request, inter-core communication data is read from a first address space corresponding to the first processing core through the first channel.

6. The method according to claim 5, wherein: The reading inter-core communication data from a first address space corresponding to the first processing core through the first channel based on the communication request includes: Determining, based on the virtual address in the communication request and the identifier of the first processing core, permission to access a first address space corresponding to the first processing core; In response to having permission to access the first address space, determining a physical address corresponding to the virtual address in the first address space; Inter-core communication data is read from the physical address through the first channel.

7. The method according to claim 6, wherein: The determining, based on the virtual address in the communication request and the identifier of the first processing core, the permission to access the first address space corresponding to the first processing core includes: Determine a target address mapping table corresponding to the identifier of the first processing core from a plurality of preset address mapping tables, wherein the target address mapping table includes a correspondence between a virtual address space corresponding to the first processing core and a first address space; In response to the virtual address space containing the virtual address, it is determined that there is permission to access a first address space corresponding to the first processing core.

8. The method according to any one of claims 1 to 7, wherein: The transmitting the inter-core communication data to a second address space corresponding to a second processing core based on the target media access controller includes: In response to the target media access controller being a media access controller for intra-chip communication, determining a second channel corresponding to the identifier of the second processing core from a plurality of channels of the target media access controller; Based on the loopback channel of the target media access controller, transmitting the inter-core communication data in the first cache corresponding to the first channel to the second cache corresponding to the second channel; The inter-core communication data in the second cache is stored in a second address space corresponding to the second processing core through the second channel.

9. The method according to claim 8, further comprising: determining an interrupt message generated by the target media access controller based on an identifier of the second channel; In response to the interrupt message, the inter-core communication data is read from the second address space by the second processing core, and the inter-core communication data is processed to obtain inter-core reply data.

10. The method according to any one of claims 1 to 7, wherein: The transmitting the inter-core communication data to a second address space corresponding to a second processing core based on the target media access controller includes: In response to the target media access controller being a media access controller for inter-chip communication, transmitting the inter-core communication data in the first cache corresponding to the first channel to a sending channel of the target media access controller; The inter-core communication data is sent through the sending channel, so that a media access controller in the on-chip system where the second processing core is located receives the inter-core communication data and stores the inter-core communication data in a second address space corresponding to the second processing core.

11. The method according to claim 10, further comprising: Receiving, based on a receiving channel of the target media access controller, inter-core reply data sent by a media access controller in the system on chip where the second processing core is located; Transmitting the inter-core reply data to a first cache corresponding to the first channel; The inter-core reply data in the first cache is stored in a first address space corresponding to the first processing core.

12. The method according to any one of claims 1 to 7, further comprising: Determine first configuration information corresponding to a first virtual machine running on the first processing core, and second configuration information corresponding to a second virtual machine running on the second processing core; Allocate the first address space for the first processing core and allocate the second address space for the second processing core in the memory based on the address configuration information in the first configuration information and the address configuration information in the second configuration information; Based on the channel configuration information in the first configuration information and the channel configuration information in the second configuration information, a first channel is allocated to the first processing core, and a second channel is allocated to the second processing core.

13. An inter-core communication device of a system on chip, comprising: A generating module, used to generate a communication request for the first processing core to perform inter-core communication with the second processing core; A first determination module, configured to determine a target media access controller based on the communication request; A first reading module, configured to read inter-core communication data from a first address space corresponding to the first processing core based on the communication request and the target media access controller; A transmission module is used to transmit the inter-core communication data to a second address space corresponding to a second processing core based on the target media access controller; wherein the first address space and the second address space correspond to different address spaces in a memory.

14. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the inter-core communication method of the system on chip as claimed in any one of claims 1 to 12.

15. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is used to read the instructions from the memory and execute the instructions to implement the inter-core communication method of the system on chip as described in any one of claims 1-12.

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