Silicon capacitor and preparation method therefor, and chip and preparation method therefor

Abstract

The present application provides a silicon capacitor and a preparation method therefor, and a chip and a preparation method therefor. The silicon capacitor comprises a silicon substrate and two solder points arranged at an interval on one side of the silicon substrate. The center distance between the two solder points is a preset distance, and the preset distance is made equal to the center distance between two adjacent solder pads in a packaging substrate. According to the present application, the center distance between the two solder points is made equal to the center distance between two solder pads, so that the silicon capacitor can be conveniently soldered to a packaging substrate and the wiring design in the packaging substrate would not be affected, thus guaranteeing a shortest power supply path without increasing the packaging area. The increase in the overall size of a chip due to the increase in the wiring length of a packaging substrate caused by the unequalness between the center distance between two solder pads in the packaging substrate and the two solder points in the silicon capacitor is avoided. In addition, the decoupling effect and the signal performance can further be improved.

Description

Silicon capacitor and its manufacturing method, chip and its manufacturing method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 24, 2023, with application number 202310914678.X and application name “Silicon capacitor and its preparation method, chip and its preparation method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the field of capacitor technology, and specifically relates to silicon capacitors and methods for preparing the same, chips and methods for preparing the same. Background Art

[0003] Currently, capacitors are typically mounted on the surface or back of the package substrate to reduce the voltage drop. However, due to the difference in pitch between the capacitor solder joints and the solder balls on the package substrate, as the pin density on the package substrate continues to increase, the traditional method of mounting standard capacitors requires rerouting the interconnection between the package substrate and the pads. This requires additional capacitor pads and wiring, which takes up a lot of wiring space, resulting in an increase in chip area and a significant decrease in electrical performance.

[0004] Summary of the Invention

[0005] In view of this, the first aspect of the present application provides a silicon capacitor, which includes a silicon substrate and two solder joints arranged on one side of the silicon substrate and spaced apart. The center distance between the two solder joints is a preset distance, and the preset distance is used to be equal to the center distance between two adjacent solder pads in the packaging substrate.

[0006] The silicon capacitor provided in the first aspect of the present application has two solder joints in the silicon capacitor used to be soldered to two adjacent solder pads in the package substrate, thereby realizing electrical connection between the silicon capacitor and the package substrate. The present application adjusts the center distance between the two solder joints so that the center distance between the two solder joints is equal to the center distance between the two solder pads. This not only facilitates soldering the silicon capacitor to the package substrate, but also does not affect the routing design in the package substrate, thereby ensuring the shortest power supply path and not increasing the package area. This avoids increasing the routing length of the package substrate due to the inequality between the center distance between the two solder pads in the package substrate and the center distance between the two solder joints in the silicon capacitor, thereby increasing the overall size of the chip. It can also improve the decoupling effect and signal performance.

[0007] Wherein, the preset distance is 0.35mm or 0.4mm.

[0008] Wherein, any one of the two welding points approaches the other welding point so that the center distance between the two welding points is the preset distance; or, each of the two welding points approaches the other welding point so that the center distance between the two welding points is the preset distance.

[0009] Among them, the silicon substrate includes a silicon substrate layer and a redistribution layer arranged on one side of the silicon base layer. The redistribution layer is provided with two connecting parts on the side away from the silicon substrate layer. Each of the solder joints is arranged on one of the connecting parts, and the center distance between the two connecting parts is the preset distance.

[0010] A second aspect of the present application provides a method for preparing a silicon capacitor, the method comprising:

[0011] Provide wafers;

[0012] performing sputtering, electroplating, and ball planting on the wafer in sequence to obtain a wafer containing a silicon capacitor group;

[0013] Performing a half-cutting process on one side surface of the wafer containing the silicon capacitor group;

[0014] A grinding process is performed on the other side surface of the wafer containing the silicon capacitor group to obtain a plurality of silicon capacitors separated from each other; wherein each of the silicon capacitors includes a silicon substrate and two solder joints arranged on one side of the silicon substrate and spaced apart, and the center distance between the two solder joints is a preset distance, and the preset distance is used to be equal to the center distance between two adjacent pads in the packaging substrate.

[0015] The third aspect of the present application provides a silicon capacitor dicing process, which solves the problem of cutting the shape of ultra-thin silicon capacitors by first cutting the dicing grooves between the silicon capacitors of each chip to half the depth, and then slicing each silicon capacitor by grinding. It solves the problem of cutting the shape of ultra-thin silicon capacitors and reduces the difficulty of preparing silicon capacitors. And the silicon capacitor provided by the above-mentioned embodiment of the present application can be prepared by the above-mentioned preparation process, so that the center distance between the two solder joints of the silicon capacitor is equal to the center distance between the two pads when the silicon capacitor is welded to the packaging substrate. This not only facilitates the welding of the silicon capacitor to the packaging substrate, but also does not affect the routing design in the packaging substrate, ensures the shortest power supply path, and does not increase the packaging area. Avoid increasing the routing length of the packaging substrate due to the unequal center distance between the two pads in the packaging substrate and the center distance between the two solder joints in the silicon capacitor, thereby increasing the overall size of the chip. And it can also improve the decoupling effect and signal performance.

[0016] The fourth aspect of the present application provides a chip, which includes a packaging substrate and a silicon capacitor as provided in the first aspect of the present application, wherein the packaging substrate includes a substrate, a plurality of solder pads arranged on one side of the substrate and spaced apart, and a plurality of solder balls arranged on one side of the substrate and spaced apart, the center distance between two adjacent solder pads being equal to the center distance between two adjacent solder balls, and being equal to the preset distance between two solder points in the silicon capacitor, and the solder points being soldered to the solder pads.

[0017] The chip provided in the fourth aspect of the present application can improve the decoupling effect and signal performance without increasing the overall size of the chip by adopting the silicon capacitor provided in the first aspect of the present application.

[0018] The solder joint includes a base provided on the silicon substrate of the silicon capacitor and a soldering portion provided on a side of the base away from the silicon substrate, and an orthographic projection of the soldering portion on the substrate is located within the solder pad.

[0019] The center of the orthographic projection of the welding portion on the substrate coincides with the center of the welding pad.

[0020] Wherein, in a direction perpendicular to the arrangement of the two solder joints, the width of the silicon substrate is smaller than the width of the solder pad; or, the width of the silicon substrate is greater than or equal to the width of the solder pad.

[0021] A fifth aspect of the present application provides a method for preparing a chip, the method comprising:

[0022] Providing a packaging substrate, and attaching a bare chip to one side of the packaging substrate;

[0023] performing a molding process on one side of the packaging substrate;

[0024] Providing the silicon capacitor according to the first aspect of the present application, and soldering the silicon capacitor to the other side of the packaging substrate;

[0025] The packaging substrate on which the silicon capacitor is welded is subjected to a cutting process to obtain a chip.

[0026] The preparation method provided in the fifth aspect of the present application can improve the decoupling effect and signal performance without increasing the overall size of the chip by adopting the silicon capacitor provided in the first aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments of the present application will be described below.

[0028] FIG1 is a schematic structural diagram of a silicon capacitor in one embodiment of the present application.

[0029] FIG2 is a schematic diagram of the packaging substrate structure in one embodiment of the present application.

[0030] FIG3 is a schematic structural diagram of the silicon capacitor shown in FIG1 when it cooperates with the package substrate shown in FIG2 .

[0031] FIG4 shows the changing process of the solder joints of the silicon capacitor in one embodiment of the present application.

[0032] FIG5 shows the changing process of the solder joints of a silicon capacitor in another embodiment of the present application.

[0033] FIG6 is a schematic structural diagram of a silicon capacitor in another embodiment of the present application.

[0034] FIG. 7 is a process flow chart of a method for preparing a silicon capacitor in one embodiment of the present application.

[0035] FIG8 is a top view of a chip in one embodiment of the present application.

[0036] FIG9 is a schematic structural diagram of a chip in another embodiment of the present application.

[0037] FIG10 is a top view of a chip in another embodiment of the present application.

[0038] FIG11 is a top view of a chip in another embodiment of the present application.

[0039] FIG12 is a process flow chart of a chip preparation method according to one embodiment of the present application.

[0040] Description of labels:

[0041] Chip-1, silicon capacitor-10, silicon substrate-11, silicon substrate layer-111, redistribution layer-112, connection part-1120, solder joint-12, base-121, welding part-122, package substrate-20, substrate-21, pad-22, solder ball-23. DETAILED DESCRIPTION

[0042] The following are preferred implementations of the present application. It should be noted that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present application. These improvements and modifications are also considered to be within the scope of protection of the present application.

[0043] Before introducing the technical solutions of the present application, the technical problems in the related technologies are introduced in detail.

[0044] In traditional package chip de-coupling (Decap) solutions, surface mount capacitors or back-mounted standard capacitors are usually used to reduce the IR drop and ensure power supply capacity. A capacitor usually includes a substrate and two solder joints provided on the substrate. Traditional capacitors, such as those with industry-standard 0201 / 0402 dimensions, have center-to-center spacing of 0.45mm and 0.775mm, respectively. The spacing between two pads in the package substrate is usually 0.35mm, 0.4mm, etc., so the center-to-center spacing between the two solder joints is inconsistent with the spacing between the two pads.

[0045] With the continuous increase in the pin density on the package substrate, the traditional method of mounting standard capacitors requires re-routing and interconnecting the package substrate and the pads, which requires adding capacitor pads and wiring, and taking up layout space. For example, surface-mounted capacitors on the front of the package substrate will occupy a large amount of wiring space, making the chip package size larger, increasing the signal wiring length, affecting signal performance, and not meeting market and cost requirements. Back-mounted capacitors will occupy a large amount of wiring space on the back, making the chip package size larger, and a certain number of solder balls need to be removed according to the capacitor size. For example, for a traditional 0402 capacitor with a 0.35mm pad spacing design, 15 solder balls need to be removed, reducing the number of solder ball signals, thereby reducing the number of effective signal transmissions, causing problems such as degradation of electrical performance, affecting signal performance, and not meeting market and cost requirements.

[0046] In summary, in the chips of the related art, since the center distance between the two solder points in the capacitor is not equal to the center distance between the two pads in the package substrate, the chip area increases and the electrical performance, such as signal performance and decoupling effect, is greatly reduced.

[0047] In view of this, in order to solve the above problems, the present application provides a silicon capacitor. Please refer to Figures 1 to 3. Figure 1 is a schematic diagram of the structure of a silicon capacitor in one embodiment of the present application. Figure 2 is a schematic diagram of the structure of a package substrate in one embodiment of the present application. Figure 3 is a schematic diagram of the structure of the silicon capacitor shown in Figure 1 when it is matched with the package substrate shown in Figure 2. The silicon capacitor 10 provided in this embodiment includes a silicon substrate 11, and two solder joints 12 arranged on one side of the silicon substrate 11 and spaced apart. The center distance between the two solder joints 12 is a preset distance (as shown by L in Figure 1), and the preset distance is used to be equal to the center distance between two adjacent pads 22 in the package substrate 20.

[0048] The silicon capacitor 10 provided in this embodiment is suitable for application in the field of chip 1 due to its small size, good stability, excellent high-frequency and temperature characteristics, extremely low bias characteristics, high reliability, and low profile. Specifically, the silicon capacitor 10 can be soldered to the packaging substrate 20 to obtain the corresponding chip 1.

[0049] The silicon capacitor 10 includes a silicon substrate 11 and two solder joints 12, wherein the silicon substrate 11 is the main structure of the silicon capacitor 10. It is worth noting that the silicon substrate 11 does not have only one layer structure, but includes a variety of different layer structures, such as a silicon substrate layer, a redistribution layer, and the like. The solder joints 12 are mainly used to solder the silicon substrate 11 to other components, thereby realizing electrical connection between the silicon substrate 11 and other components, such as by soldering the solder joints 12 to the packaging substrate 20, so that the silicon capacitor 10 is electrically connected to the packaging substrate 20. It is worth noting that the solder joint 12 is not a point, but a columnar structure of a certain size. The material of the solder joint 12 includes but is not limited to copper, tin, and the like.

[0050] As can be seen from the above, in the related art, the center-to-center spacing between two solder joints 12 is not equal to the center-to-center spacing between two solder pads 22. The center-to-center spacing between two solder joints 12 can also be referred to as pad pitch, and the center-to-center spacing between two solder pads 22 can also be referred to as pad pitch or ball grid array pitch (BGA pitch). Hereinafter, the center-to-center spacing between two solder joints 12 will be replaced by solder joint pitch, and the center-to-center spacing between two solder pads 22 will be replaced by pad pitch. This embodiment redesigns the solder joint spacing, specifically making the solder joint spacing a preset distance. The preset distance is equal to the pad spacing, or in other words, the solder joint spacing is equal to the pad spacing. This not only facilitates soldering the silicon capacitor 10 to the package substrate 20, but also does not affect the routing design in the package substrate 20, ensuring the shortest power supply path without increasing the package area. This avoids increasing the routing length of the package substrate 20 due to the inequality between the pad spacing and the solder joint spacing in the package substrate 20, thereby increasing the overall size of the chip 1. Furthermore, the decoupling effect and signal performance can be improved.

[0051] Specifically, in this embodiment, the preset distance is 0.35mm or 0.4mm, that is, the solder joint spacing is 0.35mm or 0.4mm. In other words, this embodiment can maintain the standard design of the package substrate 20, but instead changes the solder joint spacing to match the pad spacing in the package substrate 20. This embodiment is only illustrated with a solder joint spacing of 0.35mm. In other embodiments, the solder joint spacing can also be 0.4mm.

[0052] It is worth noting that the present application belongs to the physical characteristics of the silicon capacitor 10 itself. When using the silicon capacitor 10, the user can directly solder the silicon capacitor 10 to the packaging substrate 20 without any operation. The functional effects brought by the present application will be automatically realized. In addition, the user can see the technical characteristics of the present application from the appearance.

[0053] Please refer to Figures 4 and 5. Figure 4 shows the change process of the solder joints of the silicon capacitor in one embodiment of the present application. Figure 5 shows the change process of the solder joints of the silicon capacitor in another embodiment of the present application. In this embodiment, any one of the two solder joints 12 approaches the other solder joint 12 so that the center distance between the two solder joints 12 is the preset distance. Alternatively, each of the two solder joints 12 approaches the other solder joint 12 so that the center distance between the two solder joints 12 is the preset distance.

[0054] As can be seen from the above, this embodiment can match the center-to-center distance between the two pads 22 in the package substrate 20 by adjusting the center-to-center distance between the two solder joints 12. Specifically, as shown in Figure 4, in one embodiment, one of the two solder joints 12 can be kept stationary, that is, still in the position in the related art, and then the other solder joint 12 is moved closer to the stationary solder joint 12, thereby changing the center-to-center distance between the two solder joints 12, that is, the solder joint distance. This can reduce the design difficulty and reduce the complexity of the change of the partial layer structure in the silicon substrate 11. As shown in Figure 5, in another embodiment, the two solder joints 12 can be moved relative to each other in a direction close to each other, thereby changing the center-to-center distance between the two solder joints 12, that is, the solder joint distance. This can make the overall structure of the silicon capacitor 10 more symmetrical, which facilitates the subsequent welding of the silicon capacitor 10 to the package substrate 20.

[0055] In addition, it is worth noting that when there are multiple silicon capacitors 10, all of them can have two solder joints 12 close to each other, or all of them can have one solder joint 12 stationary and the other solder joint 12 close to each other, or some of them can have two solder joints 12 close to each other, and the rest can have one solder joint 12 stationary and the other solder joint 12 close to each other.

[0056] Please refer to Figure 6, which is a schematic diagram of the structure of a silicon capacitor in another embodiment of the present application. In this embodiment, the silicon substrate 11 includes a silicon substrate layer 111 and a redistribution layer 112 provided on one side of the silicon substrate. The redistribution layer 112 is provided with two connecting portions 1120 on a side facing away from the silicon substrate layer 111. Each solder joint 12 is provided on one of the connecting portions 1120, and the center-to-center distance between the two connecting portions 1120 is the predetermined distance.

[0057] The silicon substrate 11 includes but is not limited to a silicon substrate layer 111 and a redistribution layer 112, wherein the silicon substrate layer 111 may still include multiple layer structures. Therefore, the silicon substrate layer 111 in this embodiment is only a general term and does not mean that the silicon substrate layer 111 has only one layer. A redistribution layer 112 (RDL) is provided on one side of the silicon substrate layer 111. A plurality of traces are designed in the redistribution layer 112, and two connecting portions 1120 are provided on the side of the redistribution layer 112 facing away from the silicon substrate layer 111. The solder joints 12 are provided on the connecting portions 1120. In other words, one solder joint 12 is provided on one connecting portion 1120, and the other solder joint 12 is provided on the other connecting portion 1120. The solder joints 12 are electrically connected to the connecting portion 1120 and the components inside the silicon substrate layer 111 through the traces.

[0058] Therefore, the center-to-center spacing between two solder joints 12 can be determined by the center-to-center spacing between the two connecting portions 1120. In this embodiment, the center-to-center spacing between the two connecting portions 1120 is a predetermined distance, allowing the solder pads 22 on the surface of the silicon capacitor 10 to be positioned at the predetermined spacing. Consequently, after solder joints 12 are subsequently positioned on the connecting portions 1120, it is easier to maintain the predetermined center-to-center spacing between the two solder joints 12, thereby reducing the design complexity of the silicon capacitor 10.

[0059] Please refer to Figure 7, which is a process flow chart of a method for preparing a silicon capacitor according to one embodiment of the present application. This embodiment provides a method for preparing a silicon capacitor 10, comprising steps S110, S120, S130, and S140. Steps S110, S120, S130, and S140 are described in detail below.

[0060] S110, provide wafers.

[0061] S120 , performing sputtering, electroplating, and ball planting on the wafer in sequence to obtain a wafer containing a silicon capacitor group.

[0062] S130: performing a half-cutting process on one side surface of the wafer containing the silicon capacitor group.

[0063] S140, performing a grinding process on the other side surface of the wafer containing the silicon capacitor group to obtain a plurality of silicon capacitors 10 separated from each other; wherein each of the silicon capacitors 10 includes a silicon substrate 11, and two solder joints 12 arranged on one side of the silicon substrate 11 and spaced apart, and the center distance between the two solder joints 12 is a preset distance, and the preset distance is used to be equal to the center distance between two adjacent pads 22 in the packaging substrate 20.

[0064] In this embodiment, a wafer is first provided, and then wafer incoming inspection, plasma cleaning, sputtering, photolithography, electroplating, soldering, photoresist stripping, etching, reflow, and plasma cleaning are sequentially performed to complete the bumping process and obtain a wafer containing 10 groups of silicon capacitors, wherein the silicon capacitor 10 groups contain a plurality of connected silicon capacitors 10. Subsequently, a back grinding process (Dicing Before Grinding, DBG) is performed, wherein the back grinding process can also be referred to as a first cutting and then a thinning process. Specifically, the wafer containing 10 groups of silicon capacitors is sequentially subjected to a wafer incoming inspection, a scribe groove between each silicon capacitor 10 unit is cut to half its depth, also referred to as a half cut, and a surface film is applied on the cut side. The wafer after film lamination is turned over, and the other side surface of the wafer containing the silicon capacitor 10 group is ground (Inline Grinding), and the wafer is gradually thinned until the groove is exposed. At this time, the multiple silicon capacitors 10 originally connected are separated from each other, and the silicon capacitor 10 provided in the above embodiment of the present application is obtained. Specifically, each silicon capacitor 10 includes a silicon substrate 11, and two solder joints 12 provided on one side of the silicon substrate 11 and spaced apart. The center distance between the two solder joints 12 is a preset distance, and the preset distance is used to be equal to the center distance between the two adjacent pads 22 in the packaging substrate 20. Subsequently, inspection (AOI), ultraviolet irradiation (UV), tape wrapping (Tape & Reel), visual inspection (FVI), and packaging (Packing) are carried out, and the silicon capacitor 10 can be delivered to the hands of each user in need.

[0065] In summary, this embodiment provides a dicing process for a silicon capacitor 10. By first cutting the dicing grooves between the silicon capacitors 10 of each chip 1 to half the depth, and then dicing each silicon capacitor 10 by grinding, the problem of cutting the outer shape of the ultra-thin silicon capacitor 10 is solved, and the difficulty of preparing the silicon capacitor 10 is reduced. And the silicon capacitor 10 provided in the above embodiment of the present application can be prepared by the above preparation process, so that the center distance between the two solder joints 12 when the silicon capacitor 10 is soldered to the packaging substrate 20 is equal to the center distance between the two solder pads 22. This not only facilitates the soldering of the silicon capacitor 10 to the packaging substrate 20, but also does not affect the routing design in the packaging substrate 20, ensuring the shortest power supply path and not increasing the packaging area. Avoid increasing the routing length of the packaging substrate 20 due to the unequal center distance between the two solder pads 22 in the packaging substrate 20 and the center distance between the two solder joints 12 in the silicon capacitor 10, thereby increasing the overall size of the chip 1. And it can also improve the decoupling effect and signal performance.

[0066] Please refer to Figures 1 to 3, as well as Figure 8, which is a top view of a chip in one embodiment of the present application. This embodiment provides a chip 1, which includes a packaging substrate 20, and a silicon capacitor 10 provided in the above embodiment of the present application, wherein the packaging substrate 20 includes a substrate 21, a plurality of pads 22 provided on one side of the substrate 21 and spaced apart, and a plurality of solder balls 23 provided on one side of the substrate 21 and spaced apart, wherein the center distance between two adjacent pads 22 is equal to the center distance between two adjacent solder balls 23, and is equal to the preset distance between two solder joints 12 in the silicon capacitor 10, and the solder joints 12 are soldered to the pads 22.

[0067] The chip 1 provided in this embodiment consists of a silicon capacitor 10 soldered to a packaging substrate 20. The packaging substrate 20 includes a substrate 21 and a plurality of solder pads 22 arranged at intervals on one side of the substrate 21, as well as a plurality of solder balls 23 arranged at intervals on one side of the substrate 21. The above content can be understood as that a plurality of solder balls 23 were originally to be arranged evenly and in an array on one side of the substrate 21, but because the capacitor needs to be soldered, the position where the solder balls 23 were originally set may not be set, exposing the solder pads 22 on the surface of the substrate 21, thereby facilitating the subsequent soldering of the silicon capacitor 10 to the solder pads 22. Therefore, the center-to-center distance between two adjacent solder pads 22 is equal to the center-to-center distance between two adjacent solder balls 23, that is, the position of the solder pads 22 should originally be the position of the solder balls 23. Therefore, the center-to-center distance between the two solder points 12 in the silicon capacitor 10, that is, the preset distance, is equal to the center-to-center distance between the two solder pads 22, which is equal to the center-to-center distance between the two solder balls 23. Optionally, the solder pads 22 and the solder balls 23 are arranged on the back of the substrate 21, so that the silicon capacitor 10 is attached to the packaging substrate 20 from the back.

[0068] This embodiment, by using the silicon capacitor 10 provided in the above embodiment, can ensure that the center-to-center spacing between the two solder joints 12 of the silicon capacitor 10 is equal to the center-to-center spacing between the two solder pads 22 when the silicon capacitor 10 is soldered to the packaging substrate 20. This not only facilitates soldering the silicon capacitor 10 to the packaging substrate 20, but also does not affect the routing design in the packaging substrate 20, ensuring the shortest power supply path without increasing the packaging area. This avoids increasing the routing length of the packaging substrate 20 due to the unequal center-to-center spacing between the two solder pads 22 in the packaging substrate 20 and the center-to-center spacing between the two solder joints 12 in the silicon capacitor 10, thereby increasing the overall size of the chip 1. Furthermore, it can also improve decoupling effect and signal performance.

[0069] It is worth noting that the silicon capacitor 10 provided in this embodiment can be applied to all Flip-Chip Chip Scale Package (FCCSP) packaged chips 1 with a pad pitch of 0.35 mm or 0.4 mm.

[0070] Please refer to Figure 9, which is a schematic diagram of the chip structure in another embodiment of the present application. In this embodiment, the solder joint 12 includes a base 121 provided on the silicon substrate 11 of the silicon capacitor 10, and a soldering portion 122 provided on the side of the base 121 facing away from the silicon substrate 11. The orthographic projection of the soldering portion 122 on the substrate 21 is located within the solder pad 22.

[0071] The solder joint 12 includes a base 121 disposed on the silicon substrate 11, and a soldering portion 122 disposed on the base 121. The base 121 is used to connect to the silicon substrate 11, and the soldering portion 122 is used to solder to the solder pad 22 in the package substrate 20. In this embodiment, on the basis of ensuring that the solder joint spacing is equal to the solder pad spacing, the orthographic projection of the soldering portion 122 on the substrate 21 is located within the solder pad 22. In other words, the soldering portion 122 directly corresponds to the solder pad 22 and the area of ​​the soldering portion 122 is smaller than the area of ​​the solder pad 22, thereby facilitating the solder joint 12 to be soldered to the solder pad 22.

[0072] Furthermore, please refer to Figure 9 again. This embodiment can also make the center of the positive projection of the welding portion 122 on the substrate 21 coincide with the center of the welding pad 22, that is, the center of the welding portion 122 coincides with the center of the welding pad 22, thereby further facilitating the welding of the welding point 12 to the welding pad 22.

[0073] Please refer to Figures 8, 10, and 11. Figure 10 is a top view of a chip in another embodiment of the present application. Figure 11 is a top view of a chip in yet another embodiment of the present application. In this embodiment, in a direction perpendicular to the arrangement of the two solder joints 12, the width of the silicon substrate 11 is less than the width of the solder pads 22; alternatively, the width of the silicon substrate 11 is greater than or equal to the width of the solder pads 22.

[0074] From the above, it can be seen that the solder joints 12 are provided on the silicon substrate 11, and the size of the solder joints 12 is smaller than the size of the silicon substrate 11. Therefore, the overall length and width of the silicon capacitor 10 are the length and width of the silicon substrate 11. In this embodiment, the arrangement direction of the two solder joints 12 can be regarded as the length direction of the silicon capacitor 10, and the arrangement direction perpendicular to the two solder joints 12 can be regarded as the width direction of the silicon capacitor 10. As shown in FIG10, in one embodiment, the width of the silicon substrate 11 can be made smaller than the width of the solder pad 22. In this case, the overall appearance size of the silicon capacitor 10 can be reduced, thereby reducing the capacity of the silicon capacitor 10. As shown in FIG8 and FIG11, in another embodiment, the width of the silicon substrate 11 can be made not less than the width of the solder pad 22. In this case, the overall appearance size of the silicon capacitor 10 can be increased, thereby improving the capacity of the silicon capacitor 10.

[0075] In summary, in this embodiment, users can make appropriate adjustments based on capacitance requirements to meet different electrical performance requirements.

[0076] Please refer to Figure 12, which is a process flow chart of a chip manufacturing method according to one embodiment of the present application. This embodiment provides a chip manufacturing method 1, which includes S210, S220, S230, and S240. S210, S220, S230, and S240 are described in detail below.

[0077] S210 , providing a packaging substrate 20 , and attaching a bare chip to one side of the packaging substrate 20 .

[0078] S220 , performing a molding process on one side of the packaging substrate 20 .

[0079] S230 , providing the silicon capacitor 10 provided in the above embodiment of the present application, and soldering the silicon capacitor 10 to the other side of the packaging substrate 20 .

[0080] S240 , performing a cutting process on the package substrate 20 on which the silicon capacitor 10 is soldered to obtain the chip 1 .

[0081] In this embodiment, the silicon capacitor 10 can be mounted on the back of the packaging substrate 20 by surface mount technology (SMT). Specifically, the die (die) can be attached to the packaging substrate 20 by flip chip (FC) and wire bonding (WB). The front of the packaging substrate 20 is then packaged by a molding process (Molding Process). The back of the silicon capacitor 10 is then mounted (SMT Process) to the other side of the packaging substrate 20, for example, a silicon capacitor 10 with a solder joint spacing of 0.35 mm is directly soldered to a packaging substrate 20 with a pad spacing of 0.35 mm. Finally, the chip 1 is obtained by cutting and molding (Singulation).

[0082] The preparation method provided in this embodiment adopts the silicon capacitor 10 provided in the above embodiment of this application. When the silicon capacitor 10 is soldered to the packaging substrate 20, the center distance between the two solder joints 12 is equal to the center distance between the two solder pads 22. This not only facilitates the soldering of the silicon capacitor 10 to the packaging substrate 20, but also does not affect the routing design in the packaging substrate 20, ensuring the shortest power supply path and not increasing the packaging area. This avoids increasing the routing length of the packaging substrate 20 due to the unequal center distance between the two solder pads 22 in the packaging substrate 20 and the center distance between the two solder joints 12 in the silicon capacitor 10, thereby increasing the overall size of the chip 1. It can also improve the decoupling effect and signal performance.

[0083] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on this application.

[0084] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0085] In this application, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to connection, detachable connection, or integration. They may refer to mechanical connection or electrical connection. They may refer to direct connection or indirect connection through an intermediary. They may refer to internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0086] The above details the contents provided in the embodiments of the present application, and illustrates and describes the principles and embodiments of the present application. These explanations are only intended to help understand the method and core concept of the present application. However, the contents of this specification should not be construed as limiting the present application. Those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents.

Claims

1. A silicon capacitor, characterized in that: The silicon capacitor includes a silicon substrate and two solder joints arranged on one side of the silicon substrate and spaced apart from each other. The center distance between the two solder joints is a preset distance, which is used to be equal to the center distance between two adjacent pads in the packaging substrate.

2. The silicon capacitor according to claim 1, wherein: The preset distance is 0.35 mm or 0.4 mm.

3. The silicon capacitor according to claim 1, wherein: Any one of the two welding points approaches the other welding point so that the center distance between the two welding points is the preset distance; or each of the two welding points approaches the other welding point so that the center distance between the two welding points is the preset distance.

4. The silicon capacitor according to claim 3, characterized in that: The silicon substrate includes a silicon substrate layer and a redistribution layer arranged on one side of the silicon base layer. The redistribution layer is provided with two connecting parts on the side away from the silicon substrate layer. Each solder joint is arranged on one of the connecting parts. The center distance between the two connecting parts is the preset distance.

5. A method for preparing a silicon capacitor, characterized in that: The preparation method comprises: Provide wafers; Performing sputtering, electroplating, and ball implantation on the wafer in sequence to obtain a wafer containing a silicon capacitor group; Performing a half-cutting process on one side surface of the wafer containing the silicon capacitor group; The other side surface of the wafer containing the silicon capacitor group is subjected to a grinding process to obtain a plurality of silicon capacitors separated from each other; wherein each of the silicon capacitors includes a silicon substrate, and two solder joints arranged on one side of the silicon substrate and spaced apart, and the center distance between the two solder joints is a preset distance, and the preset distance is used to be equal to the center distance between two adjacent solder pads in the packaging substrate.

6. A chip, characterized in that: The chip includes a packaging substrate and a silicon capacitor as described in any one of claims 1-4, wherein the packaging substrate includes a substrate, a plurality of solder pads arranged on one side of the substrate and spaced apart, and a plurality of solder balls arranged on one side of the substrate and spaced apart, the center distance between two adjacent solder pads is equal to the center distance between two adjacent solder balls, and is equal to a preset distance between two solder joints in the silicon capacitor, and the solder joints are soldered on the solder pads.

7. The chip according to claim 6, characterized in that: The solder joint comprises a base arranged on a silicon substrate in the silicon capacitor and a soldering portion arranged on a side of the base away from the silicon substrate, and the orthographic projection of the soldering portion on the substrate is located within the solder pad.

8. The chip according to claim 7, characterized in that: The center of the orthographic projection of the welding portion on the substrate coincides with the center of the welding pad.

9. The chip according to claim 6, characterized in that: In a direction perpendicular to the arrangement of the two solder joints, the width of the silicon substrate is smaller than the width of the solder pad; or, the width of the silicon substrate is greater than or equal to the width of the solder pad.

10. A method for preparing a chip, characterized in that: The preparation method comprises: Providing a packaging substrate, and attaching a bare chip to one side of the packaging substrate; Performing a molding process on one side of the packaging substrate; Providing a silicon capacitor as described in any one of claims 1 to 4, and welding the silicon capacitor to the other side of the packaging substrate; The packaging substrate on which the silicon capacitor is welded is subjected to a cutting process to obtain a chip.

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