Memory page management method, system and apparatus, device, and computer non-volatile readable storage medium

Abstract

A memory page management method, system and apparatus, a device, and a computer non-volatile readable storage medium, relating to the technical field of memory management. The method comprises: acquiring a target virtual address of data to be accessed; on the basis of the target virtual address, searching an address translation cache for a physical address; if the corresponding physical address to be accessed is found from the address translation cache, reading, from the physical address to be accessed, target data to be accessed; and if the physical address to be accessed is not found from the address translation cache, on the basis of the target virtual address, concurrently searching a plurality of groups of unifiedly addressed page tables for the physical address, and if the physical address to be accessed is found, reading, from the physical address to be accessed, the target data to be accessed, wherein a local memory comprises a memory in a target node, and the other memories comprise memories in nodes other than the target node. The memory that can be used by a target processor is expanded, and the working load efficiency and performance of a processor are improved.

Description

Memory page management method, system, device, equipment and computer non-volatile readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 27, 2023, with application number 202310928102.9, entitled “A memory page management method, system, device, equipment and computer medium”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present application relate to the field of memory management technology, and in particular, to a memory page management method, system, apparatus, device, and computer non-volatile readable storage medium. Background Art

[0004] With the surge in processed data volume, computing engines' demand for memory has also increased dramatically. However, the growth rate of memory capacity lags behind the growth of processor performance. For example, the number of processor cores doubles every two years, while memory capacity doubles every three years. This causes the corresponding memory capacity of each processor core in a single node to decrease by 30% every two years, exacerbating the application's demand for expansion of the storage-to-computing ratio.

[0005] In summary, how to improve the efficiency and performance of processor workloads is an urgent problem to be solved by those skilled in the art.

[0006] Summary of the Invention

[0007] The purpose of the embodiments of the present application is to provide a memory page management method that can, to a certain extent, solve the technical problem of how to improve the efficiency and performance of processor workloads. The embodiments of the present application also provide a memory page management system, device, electronic device, and computer non-volatile readable storage medium.

[0008] According to a first aspect of an embodiment of the present application, a memory page management method is provided, which is applied to a target processor in a target node, comprising:

[0009] Get the target virtual address of the data to be accessed;

[0010] Performing a physical address lookup in an address translation cache based on the target virtual address, the address translation cache storing mappings between target physical addresses and corresponding virtual addresses in local memory and other memories;

[0011] If the physical address to be accessed corresponding to the target virtual address is found in the address translation cache, the target data to be accessed is read from the physical address to be accessed;

[0012] If the physical address to be accessed is not found in the address translation cache, a physical address search is performed in parallel in the local memory page table and other memory page tables based on the target virtual address. If the physical address to be accessed is found, the target data to be accessed is read from the physical address to be accessed.

[0013] Among them, the local memory page table includes a page table that stores the mapping relationship between the physical address in the local memory and the corresponding virtual address; the other memory page table includes a page table that stores the mapping relationship between the physical address in other memory and the corresponding virtual address; the local memory includes the memory in the target node connected to the target processor, and the other memory includes the memory in other nodes other than the target node connected to the target processor.

[0014] In an exemplary embodiment, the method further includes:

[0015] Get local memory;

[0016] Get additional memory;

[0017] The local memory and other memories are uniformly addressed to obtain the physical addresses of each memory, so as to filter out the physical addresses storing the first hot data in the local memory and other memories as the target physical addresses, where the hot data includes data that meets the hot access conditions, and generate an address translation cache based on the target physical address and the corresponding virtual address, generate a local memory page table based on the other physical addresses except the target physical address in the local memory and the corresponding virtual address, and generate other memory page tables based on the other physical addresses except the target physical address in other memories and the corresponding virtual address.

[0018] In an exemplary embodiment, the method further includes:

[0019] Based on the first kernel thread, the usage heat of the last-level cache, the address translation cache, the local memory page table, and other memory page tables is monitored to obtain a page usage hot and cold map, wherein the cold pages in the page usage hot and cold map store the mapping relationship between virtual addresses with usage heat lower than a preset value and physical addresses, and the hot pages in the page usage hot and cold map store the mapping relationship between virtual addresses with usage heat higher than a preset value and physical addresses;

[0020] According to the page usage hot and cold map, the second kernel thread is used to migrate the data corresponding to the cold pages in the local memory to other memories, and the second kernel thread is used to migrate the data corresponding to the hot pages in other memories to the local memory, and the mapping relationship between the address translation cache, the local memory page table, and the other memory page tables is updated;

[0021] The last level cache stores second hot data having a higher hotness than the first hot data.

[0022] In an exemplary embodiment, local memory and other memory are composed of dynamic random access memory and persistent memory.

[0023] In an exemplary embodiment, migrating data corresponding to a cold page in a local memory to other memories based on a second kernel thread includes:

[0024] If the persistent memory in the other memory is not full, the data corresponding to the cold page in the local memory is migrated to the persistent memory in the other memory based on the second kernel thread;

[0025] If the persistent memory in the other memory is full, the data corresponding to the cold page in the local memory is migrated to the dynamic random access memory in the other memory based on the second kernel thread.

[0026] In an exemplary embodiment, migrating data corresponding to hot pages in other memories to local memory based on the second kernel thread includes:

[0027] If the dynamic random access memory in the local memory is not full, the data corresponding to the hot pages in other memories are migrated to the dynamic random access memory in the local memory based on the second kernel thread;

[0028] If the dynamic random access memory in the local memory is full, data corresponding to hot pages in other memories are migrated to the persistent memory of the local memory based on the second kernel thread.

[0029] In an exemplary embodiment, before performing a physical address lookup in the address translation cache based on the target virtual address, the method further includes:

[0030] Perform data lookup in the last level cache based on the target virtual address;

[0031] If the target data is found in the last level cache, the search ends;

[0032] If the target data is not found in the last level cache, a step of performing a physical address search in the address translation cache based on the target virtual address is performed.

[0033] In an exemplary embodiment, local memory and other memories are uniformly addressed, including:

[0034] Use the rack base address, node base address, and node internal hardware address to uniformly address local memory and other memories;

[0035] The rack base address includes the base address of the rack where the node is located.

[0036] In an exemplary embodiment, the other memory includes a first-level memory and a second-level memory, and a distance between the first-level memory and the target processor is smaller than a distance between the second-level memory and the target processor.

[0037] In an exemplary embodiment, the target processor and the local memory are connected via a memory bus.

[0038] In an exemplary embodiment, the target processor and the first level memory are connected via a coherent interconnect protocol.

[0039] In an exemplary embodiment, the target processor and the second level memory are connected via an autonomous high-speed coherent network protocol.

[0040] In an exemplary embodiment, the first level of memory includes memory in other nodes located in the same rack as the target node.

[0041] In an exemplary embodiment, the first level memory includes at least two memories.

[0042] In an exemplary embodiment, the second level memory includes memory in other nodes that are located in a different rack than the target node.

[0043] In an exemplary embodiment, the second level of memory includes memory in at least two other nodes located in the same rack.

[0044] In an exemplary embodiment, the second level of memory includes memory in at least two other nodes located in different racks.

[0045] In an exemplary embodiment, migrating data corresponding to a cold page in a local memory to another memory based on a second kernel thread includes:

[0046] If the first-level memory is not full, the data corresponding to the cold page in the local memory is migrated to the first-level memory based on the second kernel thread;

[0047] If the first-level memory is full, the data corresponding to the cold pages in the local memory are migrated to the second-level memory based on the second kernel thread.

[0048] According to a second aspect of an embodiment of the present application, a memory page management device is provided, which is applied to a target processor in a target node, including:

[0049] A first acquisition module is configured to obtain a target virtual address of data to be accessed;

[0050] a first search module configured to perform a physical address search in an address translation cache based on a target virtual address, the address translation cache storing a mapping relationship between a target physical address and a corresponding virtual address in a local memory and other memories;

[0051] A first reading module is configured to read the target data to be accessed from the physical address to be accessed if the physical address to be accessed corresponding to the target virtual address is found in the address translation cache;

[0052] A second search module is configured to perform a parallel physical address search in a local memory page table and other memory page tables based on the target virtual address if the physical address to be accessed is not found in the address translation cache, and read the target data to be accessed from the physical address to be accessed if the physical address to be accessed is found;

[0053] Among them, the local memory page table includes a page table that stores the mapping relationship between the physical address in the local memory and the corresponding virtual address; the other memory page table includes a page table that stores the mapping relationship between the physical address in other memory and the corresponding virtual address; the local memory includes the memory in the target node connected to the target processor, and the other memory includes the memory in other nodes other than the target node connected to the target processor.

[0054] According to a third aspect of an embodiment of the present application, a memory page management system is provided, comprising at least two racks, each rack comprising at least two target nodes, each target node comprising a target processor and a memory, the target processor of the target node being connected to the memory of at least one other target node located in the same rack, and the target processor of the target node being connected to the memory of at least one target node located in a different rack;

[0055] In which, the target processor is configured to obtain a target virtual address of data to be accessed; a physical address search is performed in an address translation cache based on the target virtual address, and the address translation cache stores a mapping relationship between the target physical address and the corresponding virtual address in the local memory and other memories; if the physical address to be accessed corresponding to the target virtual address is found in the address translation cache, the target data to be accessed is read from the physical address to be accessed; if the physical address to be accessed is not found in the address translation cache, a physical address search is performed in parallel in the local memory page table and other memory page tables based on the target virtual address, and if the physical address to be accessed is found, the target data to be accessed is read from the physical address to be accessed; and the local memory page table includes a page table that stores a mapping relationship between the physical address in the local memory and the corresponding virtual address; the other memory page table includes a page table that stores a mapping relationship between the physical address in the other memory and the corresponding virtual address; the local memory includes a memory connected to the target processor in the target node, and the other memory includes a memory connected to the target processor in other nodes other than the target node.

[0056] According to a fourth aspect of the embodiments of the present application, there is provided an electronic device, including:

[0057] a memory arranged to store a computer program;

[0058] A processor is configured to implement the steps of any of the above memory page management methods when executing a computer program.

[0059] According to a fifth aspect of an embodiment of the present application, a computer non-volatile readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above memory page management methods are implemented.

[0060] A memory page management method provided by an embodiment of the present application is applied to a target processor in a target node to obtain a target virtual address of data to be accessed; a physical address search is performed in an address translation cache based on the target virtual address, and the address translation cache stores the mapping relationship between the target physical address and the corresponding virtual address in the local memory and other memories; if the physical address to be accessed corresponding to the target virtual address is found in the address translation cache, the target data to be accessed is read from the physical address to be accessed; if the physical address to be accessed is not found in the address translation cache, a physical address search is performed in parallel in the local memory page table and other memory page tables based on the target virtual address, and if the physical address to be accessed is found, the target data to be accessed is read from the physical address to be accessed; wherein, the local memory page table includes a page table that stores the mapping relationship between the physical address in the local memory and the corresponding virtual address; the other memory page table includes a page table that stores the mapping relationship between the physical address in the other memory and the corresponding virtual address; the local memory includes the memory connected to the target processor in the target node, and the other memory includes the memory connected to the target processor in other nodes other than the target node. In an embodiment of the present application, the target processor is connected to local memory and other memories, which is equivalent to expanding the capacity of the memory connected to the target processor so that the memory can match the performance of the target processor; and the physical addresses of the local memory and other memories are uniformly managed through the address translation cache, local memory page table and other memory page tables, thereby avoiding the address mapping overhead problem caused by large-scale mixed memory pooling; in addition, after the available memory of the target processor is expanded through other memories, the address translation cache can be applied to prioritize the data stored at the target physical address in the local memory and other memories for fast search, and the local memory page table and other memory page table can be applied to accurately search the data in the local memory and other memories, thereby realizing fast and accurate data management of the local memory and other memories with the help of the address translation cache, local memory page table and other memory page table, thereby improving the efficiency and performance of the processor workload. A memory page management system, device, electronic device and computer non-volatile readable storage medium provided in an embodiment of the present application also solve corresponding technical problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0062] FIG1 is a first schematic diagram of a memory page management method provided by an embodiment of the present application;

[0063] FIG2 is a second schematic diagram of a memory page management method provided by an embodiment of the present application;

[0064] FIG3 is a schematic structural diagram of a memory page management device provided in an embodiment of the present application;

[0065] FIG4 is a schematic diagram of the structure of a memory page management system provided in an embodiment of the present application;

[0066] FIG5 is a schematic diagram of a memory page management method according to an embodiment of the present application in an application scenario;

[0067] FIG6 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0068] FIG7 is another schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the embodiments of this application.

[0070] Please refer to FIG1 , which is a first schematic diagram of a memory page management method provided in an embodiment of the present application.

[0071] A memory page management method provided in an embodiment of the present application, applied to a target processor in a target node, may include the following steps:

[0072] Step S101: Obtain the target virtual address of the data to be accessed.

[0073] In actual applications, the target processor may first obtain the target virtual address of the data to be accessed, so as to subsequently read the corresponding target data from the memory according to the target virtual address.

[0074] In actual application scenarios, the target virtual address obtained by the target processor can be the virtual address of the data to be searched, determined by the user after the application in the target node is started, etc., and the embodiments of the present application are not limited here. It should be noted that the target processor in the embodiments of the present application refers to the processor running the method of the embodiments of the present application, and the target node refers to the node where the target processor is located.

[0075] Step S102: performing a physical address search in an address translation cache based on the target virtual address. The address translation cache stores mapping relationships between target physical addresses and corresponding virtual addresses in local memory and other memories.

[0076] In actual applications, after obtaining the target virtual address of the data to be accessed, the target processor can perform a physical address lookup in the address translation cache (TLB) based on the target virtual address. The address translation cache stores the mapping relationship between the target physical address in the local memory and other memories and the corresponding virtual address. In other words, in the embodiment of the present application, the mapping relationship between the target physical address in the local memory and other memories and the corresponding virtual address is stored in the address translation cache for management, and when searching for data, the address translation cache is preferentially searched, so that the corresponding data can be quickly obtained from the target physical address.

[0077] It should be noted that the physical address of the data is used to manage the data at the memory level, and the virtual address of the data is used to manage the data outside the memory, such as at the operation level. That is, a piece of data will have both a virtual address and a physical address, and the virtual address and the physical address of the data correspond one to one. Therefore, when searching for data in the memory, it is necessary to first determine the physical address of the data in the memory based on the virtual address of the data, and then read the corresponding data from the physical address of the memory. Step S103: If the physical address to be accessed corresponding to the target virtual address is found in the address translation cache, the target data to be accessed is read from the physical address to be accessed.

[0078] Step S104: If the physical address to be accessed is not found in the address translation cache, a physical address search is performed in parallel in the local memory page table and other memory page tables based on the target virtual address. If the physical address to be accessed is found, the target data to be accessed is read from the physical address to be accessed; wherein, the local memory page table includes a page table that stores the mapping relationship between the physical address in the local memory and the corresponding virtual address; the other memory page table includes a page table that stores the mapping relationship between the physical address in other memories and the corresponding virtual address; the local memory includes the memory in the target node connected to the target processor, and the other memory includes the memory in other nodes other than the target node connected to the target processor.

[0079] In actual applications, if the target processor finds the physical address to be accessed corresponding to the target virtual address in the address translation cache, the target data to be accessed is read from the memory corresponding to the physical address to be accessed and feedback is given, such as feedback to the application program. Correspondingly, if the target processor does not find the physical address to be accessed in the address translation cache, it is necessary to perform physical address searches in the local memory page table and other memory page tables in parallel based on the target virtual address. If the physical address to be accessed is found, the target data to be accessed is read from the physical address to be accessed and feedback is given. The local memory page table includes a page table that stores the mapping relationship between the physical address in the local memory and the corresponding virtual address, and the other memory page tables include a page table that stores the mapping relationship between the physical address in other memories and the corresponding virtual address. Therefore, if the target processor finds the address to be accessed in the local memory page table, the target data can be read from the address to be accessed in the local memory. If the target processor finds the address to be accessed in other memory page tables, the target data can be read from the address to be accessed in other memories.

[0080] It should be noted that the memory in the same node as the target processor is called local memory, and other memory is the memory in other nodes outside the target node. In other words, the memory in other nodes connected to the target processor is called other memory. The size, type, etc. of local memory and other memory can be determined according to the application scenario, and the embodiments of this application are not limited here.

[0081] A memory page management method provided by an embodiment of the present application is applied to a target processor in a target node to obtain a target virtual address of data to be accessed; a physical address search is performed in an address translation cache based on the target virtual address, and the address translation cache stores the mapping relationship between the target physical address and the corresponding virtual address in the local memory and other memories; if the physical address to be accessed corresponding to the target virtual address is found in the address translation cache, the target data to be accessed is read from the physical address to be accessed; if the physical address to be accessed is not found in the address translation cache, a physical address search is performed in parallel in the local memory page table and other memory page tables based on the target virtual address, and if the physical address to be accessed is found, the target data to be accessed is read from the physical address to be accessed; wherein, the local memory page table includes a page table that stores the mapping relationship between the physical address in the local memory and the corresponding virtual address; the other memory page table includes a page table that stores the mapping relationship between the physical address in the other memory and the corresponding virtual address; the local memory includes the memory connected to the target processor in the target node, and the other memory includes the memory connected to the target processor in other nodes other than the target node. In an embodiment of the present application, the target processor is connected to local memory and other memories, which is equivalent to expanding the capacity of the memory connected to the target processor so that the memory can match the performance of the target processor; and the physical addresses of the local memory and other memories are uniformly managed through the address translation cache, local memory page table and other memory page tables, avoiding the address mapping overhead problem caused by large-scale mixed memory pooling; in addition, after the available memory of the target processor is expanded through other memories, the address translation cache can be applied to prioritize the rapid search of data stored at the target physical address in the local memory and other memories, and the local memory page table and other memory page table can be applied to accurately search the data in the local memory and other memories, thereby realizing fast and accurate data management of the local memory and other memories with the help of the address translation cache, local memory page table and other memory page tables, thereby improving the efficiency and performance of the processor workload.

[0082] Please refer to Figure 2, which is a second schematic diagram of a memory page management method provided in an embodiment of the present application. A memory page management method provided in an embodiment of the present application, applied to a target processor in a target node, may include the following steps:

[0083] Step S201: Acquire the local memory connected to the target processor in the target node.

[0084] Step S202: Acquire other memories connected to the target processor, where the other memories include memories in other nodes other than the target node.

[0085] Step S203: uniformly address the local memory and other memories to obtain the physical addresses of each memory, so as to filter out the physical addresses storing the first heat data in the local memory and other memories as the target physical addresses, where the heat data includes data that meets the heat access conditions, and generate an address translation cache based on the target physical address and the corresponding virtual address, and generate a local memory page table based on the other physical addresses and the corresponding virtual addresses in the local memory except the target physical address, and generate other memory page tables based on the other physical addresses and the corresponding virtual addresses in the other memories except the target physical address.

[0086] In actual applications, after obtaining local memory and other memories, the target processor can uniformly address the local memory and other memories to obtain the physical address of each memory, so that the target processor can accurately manage each block of memory, and it is convenient for the operating system and other applications to use the physical address to generate corresponding address translation cache, local memory page table and other memory page tables.

[0087] In actual application scenarios, when uniformly addressing local memory and other memories, the rack base address, node base address, and node internal hardware address can be applied, using a tree structure to uniformly address local memory and other memories; and the rack base address includes the base address of the rack where the node is located. For example, the rack address + node address + node internal hardware address can be used as the physical address of the memory, etc. In actual applications, a virtual root node can also be introduced to expand the physical address, for example, the virtual root node + rack address + node address + node internal hardware address can be used as the physical address of the memory, etc., where the rack address can be the unique identification number of the rack, the node address can be the unique identification number of the node, and the virtual root node can be the unique identification number of an independent rack system.

[0088] In actual applications, after the target processor obtains the physical address of each memory, the operating system and the like can use the physical address of the memory to manage the memory data. In this process, considering that the memory stores hot data, hot data is data that meets the hot access conditions such as access frequency and number of accesses greater than the set value. In order to be able to quickly and accurately manage hot data and other data, and to be able to accurately manage the data in the local memory and other memories, the operating system and the like can filter out the physical address of the first hot data stored in the local memory and other memories as the target physical address, and store the mapping relationship between the target physical address and the corresponding virtual address in the address In the translation cache, the mapping relationships between physical addresses other than the target physical address in the local memory and the corresponding virtual addresses are stored in the local memory page table, and the mapping relationships between physical addresses other than the target physical address in other memories and the corresponding virtual addresses are stored in other memory page tables. Of course, the mapping relationships between all physical addresses in the local memory and the corresponding virtual addresses can also be stored in the local memory page table, and the mapping relationships between all physical addresses in other memory page tables and the corresponding virtual addresses can be stored in other memory page tables, etc., so as to perform memory page management based on the address translation cache, the local memory page table, and other memory page tables.

[0089] In actual applications, in order to speed up the efficiency of the target processor in searching for target data, the operating system, etc., before filtering out the physical address of the first hot data stored in the local memory and other memories as the target physical address, can also filter out the second hot data stored in the local memory and other memories, where the second hot data is hotter than the first hot data; directly store the second hot data in the last level cache (Last Level Cache, LLC) to perform data access processing based on the last level cache. Accordingly, before the target processor performs a physical address search in the address translation cache based on the target virtual address, it can also first perform a data search in the last level cache based on the target virtual address; if the target data is found in the last level cache, the search is terminated; if the target data is not found in the last level cache, the step of performing a physical address search in the address translation cache based on the target virtual address is executed.

[0090] In actual applications, as the number of memory accesses increases, some data will be accessed multiple times, while some data will be accessed very rarely. Furthermore, due to the access speed of local memory and other memories, the target processor will read data from local memory and other memories at inconsistent speeds. Some application scenarios require the target processor to quickly feedback the data in the memory. In order to meet such application requirements and improve the target processor's memory access and storage efficiency, considering that the target processor has a better access speed to local memory than other memories, the target processor can monitor the usage heat of the last-level cache, address translation cache, local memory page table and other memory page tables based on the first kernel thread to obtain a page usage hot and cold map. The cold pages in the page usage hot and cold map store the mapping relationship between the virtual addresses and physical addresses whose usage heat is lower than the preset value, and the hot pages in the page usage hot and cold map store the mapping relationship between the virtual addresses and physical addresses whose usage heat is higher than the preset value, that is, the cold pages are used to store the mapping relationship between the virtual addresses and physical addresses of cold data, and the hot pages are used to store the mapping relationship between the virtual addresses and physical addresses of hot data; according to the page usage hot and cold map, based on the second kernel thread, the data corresponding to the cold pages in the local memory are migrated to other memories, based on the second kernel thread, the data corresponding to the hot pages in other memories are migrated to the local memory, and the mapping relationships in the address translation cache, the local memory page table and other memory page tables are updated.

[0091] Optionally, based on the second kernel thread, cold data in the physical address recorded by the cold page in the local memory can be migrated to other memories, the mapping relationship between the virtual address of the cold data and the old physical address is deleted in the local memory page table, and the mapping relationship between the virtual address of the cold data and the latest physical address is added in the other memory page table. If the cold data was previously in the address translation cache, the mapping relationship between the virtual address of the cold data and the old physical address in the address translation cache needs to be deleted; based on the second kernel thread, hot data in the physical address recorded by the hot page in other memories can be migrated to other memories, the mapping relationship between the virtual address of the hot data and the old physical address is deleted in the other memory page table, and the mapping relationship between the virtual address of the hot data and the latest physical address is added in the local memory page table. If the hot data was previously in the address translation cache, the mapping relationship between the virtual address of the hot data and the latest physical address in the address translation cache needs to be updated; the old physical address refers to the physical address before the data migration, and the latest physical address refers to the physical address after the data migration.

[0092] In actual application scenarios, the types of local memory and other memory can be determined according to actual needs. For example, local memory and other memory can both be composed of Dynamic Random Access Memory (DRAM) and persistent memory (PM).

[0093] In actual application scenarios, considering that dynamic random access memory has better performance than persistent memory, when the target processor migrates data corresponding to cold pages in local memory to other memory based on the second kernel thread, if the persistent memory in other memory is not full, the target processor can migrate data corresponding to cold pages in local memory to the persistent memory in other memory based on the second kernel thread; if the persistent memory in other memory is full, the target processor can migrate data corresponding to cold pages in local memory to the dynamic random access memory in other memory based on the second kernel thread. Correspondingly, when migrating data corresponding to hot pages in other memory to local memory based on the second kernel thread, if the dynamic random access memory in local memory is not full, the target processor can migrate data corresponding to hot pages in other memory to the dynamic random access memory in local memory based on the second kernel thread; if the dynamic random access memory in local memory is full, the target processor can migrate data corresponding to hot pages in other memory to the persistent memory in local memory based on the second kernel thread. In this way, the target processor can give priority to reading the hot pages that are used more frequently from the dynamic random access memory of the local memory. Since the memory data corresponding to the physical address in the hot page is hot data, the target processor can obtain the recorded hot data by giving priority to the hot page, thereby improving the efficiency of obtaining hot data.

[0094] In actual application scenarios, the data corresponding to the hot pages stored in the persistent memory of the local memory can be transferred to the dynamic random access memory of the local memory, and the data corresponding to the cold pages stored in the dynamic random access memory of other memories can be transferred to the persistent memory of other memories, etc., so as to speed up the access efficiency of the target processor to the target data.

[0095] In actual applications, the types of other memories can be determined according to actual needs. For example, other memories can be classified according to the distance between the memory and the target processor. Accordingly, the target processor can obtain other memories connected to the target processor in the process of obtaining other memories connected to the target processor. Other memories include first-level memories and second-level memories, and the distance between the first-level memory and the target processor is smaller than the distance between the second-level memory and the target processor.

[0096] In practical applications, to facilitate connectivity between the target processor and memory, the target processor and local memory can be connected via a memory bus. The target processor and first-level memory can be connected via a coherent interconnect protocol. The target processor and second-level memory can be connected via an autonomous high-speed coherent network protocol.

[0097] In actual application scenarios, in order to facilitate obtaining the first-level memory, the first-level memory can be set to the memory in other nodes located in the same rack as the target node, and the first-level memory can include at least two memories.

[0098] In actual application scenarios, in order to facilitate obtaining the second-level memory, the second-level memory can be set to the memory in other nodes located in different racks from the target node, and the second-level memory can include the memory in at least two other nodes located in the same rack, or the second-level memory can include the memory in at least two other nodes located in different racks, etc.

[0099] In actual application scenarios, when the target processor migrates the data corresponding to the cold page in the local memory to other memories based on the second kernel thread, it can give priority to migrating the cold page data to the first-level memory. That is, if the first-level memory is not full, the data corresponding to the cold page in the local memory is migrated to the first-level memory based on the second kernel thread; if the first-level memory is full, the data corresponding to the cold page in the local memory is migrated to the second-level memory based on the second kernel thread.

[0100] Step S204: Obtain the target virtual address of the data to be accessed.

[0101] Step S205: performing a physical address search in an address translation cache based on the target virtual address. The address translation cache stores mapping relationships between target physical addresses and corresponding virtual addresses in local memory and other memories.

[0102] Step S206: If the physical address to be accessed corresponding to the target virtual address is found in the address translation cache, the target data to be accessed is read from the physical address to be accessed.

[0103] It should be noted that since the target physical address is the physical address where the first heat data is stored, in this embodiment, the target processor preferentially searches for heat data in the local memory and other memories from the address translation cache. In other words, the data type stored in the target physical address determines the type of data that the target processor preferentially searches for from the local memory and other memories.

[0104] Step S207: If the physical address to be accessed is not found in the address translation cache, a physical address search is performed in parallel in the local memory page table and other memory page tables based on the target virtual address. If the physical address to be accessed is found, the target data to be accessed is read from the physical address to be accessed.

[0105] Please refer to FIG3 , which is a schematic structural diagram of a memory page management device provided in an embodiment of the present application.

[0106] An embodiment of the present application provides a memory page management device, which is applied to a target processor in a target node and may include:

[0107] A first acquisition module 11 is configured to acquire a target virtual address of data to be accessed;

[0108] A first search module 12 is configured to perform a physical address search in an address translation cache based on a target virtual address, wherein the address translation cache stores a mapping relationship between a target physical address and a corresponding virtual address in a local memory and other memories;

[0109] The first reading module 13 is configured to read the target data to be accessed from the physical address to be accessed if the physical address to be accessed corresponding to the target virtual address is found in the address translation cache;

[0110] The second search module 14 is configured to perform a physical address search in parallel in the local memory page table and other memory page tables based on the target virtual address if the physical address to be accessed is not found in the address translation cache, and read the target data to be accessed from the physical address to be accessed if the physical address to be accessed is found;

[0111] Among them, the local memory page table includes a page table that stores the mapping relationship between the physical address in the local memory and the corresponding virtual address; the other memory page table includes a page table that stores the mapping relationship between the physical address in other memory and the corresponding virtual address; the local memory includes the memory in the target node connected to the target processor, and the other memory includes the memory in other nodes other than the target node connected to the target processor.

[0112] An embodiment of the present application provides a memory page management device, which is applied to a target processor in a target node and may further include:

[0113] The second acquisition module is configured to acquire the local memory before the first acquisition module acquires the target virtual address of the data to be accessed;

[0114] A third acquisition module is configured to acquire other memories;

[0115] The addressing module is configured to uniformly address the local memory and other memories, obtain the physical addresses of each memory, and filter out the physical addresses of the local memory and other memories storing the first heat data as the target physical address, the heat data including the data meeting the heat access condition, generate an address translation cache based on the target physical address and the corresponding virtual address, generate a local memory page table based on the other physical addresses and the corresponding virtual addresses in the local memory except the target physical address, and generate other memory page tables based on the other physical addresses and the corresponding virtual addresses in the other memories except the target physical address.

[0116] An embodiment of the present application provides a memory page management device, which is applied to a target processor in a target node and may further include:

[0117] The monitoring module is configured to monitor the usage heat of pages in the last-level cache, the address translation cache, the local memory page table, and other memory page tables based on the first kernel thread to obtain a page usage hot and cold map, wherein the cold pages in the page usage hot and cold map store mappings between virtual addresses with usage heat lower than a preset value and physical addresses, and the hot pages in the page usage hot and cold map store mappings between virtual addresses with usage heat higher than a preset value and physical addresses;

[0118] A migration module is configured to migrate data corresponding to cold pages in the local memory to other memories based on the second kernel thread according to the page usage hot and cold map, and migrate data corresponding to hot pages in other memories to the local memory based on the second kernel thread, and update mapping relationships among the address translation cache, the local memory page table, and the other memory page tables;

[0119] The last level cache stores second hot data having a higher hotness than the first hot data.

[0120] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, where local memory and other memories are composed of dynamic random access memory and persistent memory.

[0121] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, and a migration module is configured to: if the persistent memory in other memories is not full, migrate the data corresponding to the cold page in the local memory to the persistent memory of other memories based on the second kernel thread; if the persistent memory in other memories is full, migrate the data corresponding to the cold page in the local memory to the dynamic random access memory of other memories based on the second kernel thread.

[0122] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, and a migration module is configured to: if the dynamic random access memory in the local memory is not full, then based on the second kernel thread, migrate the corresponding hot pages in other memories to the dynamic random access memory in the local memory; if the dynamic random access memory in the local memory is full, then based on the second kernel thread, migrate the data corresponding to the hot pages in other memories to the persistent memory in the local memory.

[0123] An embodiment of the present application provides a memory page management device, which is applied to a target processor in a target node and may further include:

[0124] The third search module is configured to perform a data search in the last-level cache based on the target virtual address before the first search module performs a physical address search in the address translation cache based on the target virtual address; if the target data is found in the last-level cache, the search is terminated; if the target data is not found in the last-level cache, the management module is prompted to execute the step of performing a physical address search in the address translation cache based on the target virtual address.

[0125] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, and an addressing module is configured to uniformly address local memory and other memories using a rack base address, a node base address, and a node internal hardware address; the rack base address includes the base address of the rack in which the node is located.

[0126] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, wherein other memories include first-level memory and second-level memory, and the distance between the first-level memory and the target processor is smaller than the distance between the second-level memory and the target processor.

[0127] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, where the target processor is connected to a local memory via a memory bus.

[0128] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, where the target processor is connected to a first-level memory via a coherent interconnection protocol.

[0129] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, and the target processor is connected to the second-level memory via an autonomous high-speed consistency network protocol.

[0130] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, wherein the first-level memory includes memory in other nodes located in the same rack as the target node.

[0131] An embodiment of the present application provides a memory page management device, which is applied to a target processor in a target node, wherein the first-level memory includes at least two memories.

[0132] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, and the second-level memory includes memory in other nodes located in different racks from the target node.

[0133] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, wherein the second-level memory includes memories in at least two other nodes located in the same rack.

[0134] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, wherein the second-level memory includes memories in at least two other nodes located in different racks.

[0135] A memory page management device provided in an embodiment of the present application is applied to a target processor in a target node, and a migration module is configured to: if the first-level memory is not full, migrate the data corresponding to the cold page in the local memory to the first-level memory based on the second kernel thread; if the first-level memory is full, migrate the data corresponding to the cold page in the local memory to the second-level memory based on the second kernel thread.

[0136] Please refer to FIG. 4 , which is a schematic structural diagram of a memory page management system provided in an embodiment of the present application, showing n racks.

[0137] A memory page management system provided by an embodiment of the present application may include at least two racks, each rack including at least two target nodes, each target node including a target processor and a memory, a target processor of a target node being connected to the memory of at least one other target node located in the same rack, and a target processor of a target node being connected to the memory of at least one target node located in a different rack;

[0138] In which, the target processor is configured to obtain a target virtual address of data to be accessed; a physical address search is performed in an address translation cache based on the target virtual address, and the address translation cache stores a mapping relationship between the target physical address and the corresponding virtual address in the local memory and other memories; if the physical address to be accessed corresponding to the target virtual address is found in the address translation cache, the target data to be accessed is read from the physical address to be accessed; if the physical address to be accessed is not found in the address translation cache, a physical address search is performed in parallel in the local memory page table and other memory page tables based on the target virtual address, and if the physical address to be accessed is found, the target data to be accessed is read from the physical address to be accessed; and the local memory page table includes a page table that stores a mapping relationship between the physical address in the local memory and the corresponding virtual address; the other memory page table includes a page table that stores a mapping relationship between the physical address in the other memory and the corresponding virtual address; the local memory includes a memory connected to the target processor in the target node, and the other memory includes a memory connected to the target processor in other nodes other than the target node.

[0139] For the corresponding description of a memory page management system provided in an embodiment of the present application, please refer to the above embodiment and will not be repeated here.

[0140] Please refer to FIG5. To facilitate understanding of the embodiment of the present application, the memory page management solution of the embodiment of the present application is now described in conjunction with an application program. The process includes the following steps:

[0141] Application launch;

[0142] Determine the level of each memory node. For example, determine the memory in node 1 of rack 1 as local memory, the memory in node 2 of rack 1 as remote memory, and the memory in node 1 of rack n as remote memory.

[0143] Two kernel threads are awakened. The first kernel thread is used for real-time page heat monitoring. For example, it uses the Precise Event-Based Sampling (PEBS) mechanism to sample last-level cache and address translation cache misses, obtain recent virtual address space operation information, and generate a hot and cold map of page usage. The second kernel thread periodically reads page hot map data and cold map data alternately. If a hot map is read and is not in local memory, the page data corresponding to the hot map is moved to local memory. If it is already in local memory, it is not moved. If a cold map is read and is in local memory, the page data corresponding to the cold map is moved to far memory or remote memory. If it is not in local memory, it is not moved.

[0144] The application accesses memory for the nth time;

[0145] Determine whether the address translation cache is hit. If it is determined that the address translation cache is hit, return the multi-level memory system unified physical address obtained by addressing for access; if it is determined that the address translation cache is not hit, search the local memory page table, the far memory page table, and the remote memory page table in parallel, and return the multi-level memory system unified physical address obtained by addressing for access.

[0146] The present application also provides an electronic device and a computer non-volatile readable storage medium, both of which have the corresponding effects of the memory page management method provided in the present application.

[0147] An electronic device provided in an embodiment of the present application includes a memory 201 and a processor 202. The memory 201 stores a computer program, and when the processor 202 executes the computer program, the steps of the memory page management method described in any of the above embodiments are implemented.

[0148] Referring to FIG7 , another electronic device provided in an embodiment of the present application may further include: an input port 203 connected to the processor 202, configured to transmit commands inputted from the outside to the processor 202; a display unit 204 connected to the processor 202, configured to display the processing results of the processor 202 to the outside; and a communication module 205 connected to the processor 202, configured to enable communication between the electronic device and the outside. The display unit 204 may be a display panel, a laser scanning display, etc. The communication method adopted by the communication module 205 includes but is not limited to Mobile High-Definition Link (MHL), Universal Serial Bus (USB), High Definition Multimedia Interface (HDMI), wireless connection: Wireless Fidelity (WiFi), Bluetooth communication technology, Bluetooth low energy communication technology, and communication technology based on IEEE802.11s.

[0149] An embodiment of the present application provides a computer non-volatile readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the memory page management method described in any of the above embodiments are implemented.

[0150] The computer non-volatile readable storage medium involved in the embodiments of the present application includes random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the technical field.

[0151] For the description of the relevant parts of the memory page management system, device, electronic device, and computer non-volatile readable storage medium provided in the embodiments of the present application, please refer to the detailed description of the corresponding parts in the memory page management method provided in the embodiments of the present application, and no further description is given here. In addition, the parts of the above-mentioned technical solutions provided in the embodiments of the present application that are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail to avoid excessive elaboration.

[0152] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0153] The above description of the disclosed embodiments enables those skilled in the art to implement or use the embodiments of the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the embodiments of the present application. Therefore, the embodiments of the present application are not limited to the embodiments shown herein, but are intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory page management method, characterized in that: The target processor to be used in the target node includes: Get the target virtual address of the data to be accessed; Performing a physical address search in an address translation cache based on the target virtual address, the address translation cache storing a mapping relationship between a target physical address in a local memory and other memories and a corresponding virtual address; If a physical address to be accessed corresponding to the target virtual address is found in the address translation cache, the target data to be accessed is read from the physical address to be accessed; If the physical address to be accessed is not found in the address translation cache, a physical address search is performed in parallel in the local memory page table and other memory page tables based on the target virtual address, and if the physical address to be accessed is found, the target data to be accessed is read from the physical address to be accessed; Among them, the local memory page table includes a page table storing the mapping relationship between the physical address in the local memory and the corresponding virtual address; the other memory page table includes a page table storing the mapping relationship between the physical address in the other memory and the corresponding virtual address; the local memory includes the memory in the target node connected to the target processor, and the other memory includes the memory in other nodes other than the target node connected to the target processor.

2. The method according to claim 1, characterized in that Also includes: Acquire the local memory; obtaining the other memory; The local memory and the other memories are uniformly addressed to obtain the physical addresses of the respective memories, so as to filter out the physical addresses storing the first thermal data in the local memory and the other memories as the target physical addresses, wherein the thermal data includes data satisfying the thermal access condition, and the address translation cache is generated based on the target physical address and the corresponding virtual address, and the local memory page table is generated based on the other physical addresses in the local memory except the target physical address and the corresponding virtual address, and the other memory page table is generated based on the other physical addresses in the other memories except the target physical address and the corresponding virtual address.

3. The method according to claim 2, characterized in that Also includes: Based on the first kernel thread, the last level cache, the address translation cache, the local memory page table and the other memory page tables are used to monitor the usage heat, and obtain a page usage hot and cold map, wherein the cold pages in the page usage hot and cold map store the mapping relationship between the virtual addresses and the physical addresses whose usage heat is lower than the preset value, and the hot pages in the page usage hot and cold map store the mapping relationship between the virtual addresses and the physical addresses whose usage heat is higher than the preset value; According to the page usage hot and cold map, based on the second kernel thread, data corresponding to the cold page in the local memory is migrated to the other memory, based on the second kernel thread, data corresponding to the hot page in the other memory is migrated to the local memory, and mapping relationships in the address translation cache, the local memory page table, and the other memory page table are updated. Tie; The last level cache stores second heat data with heat higher than the first heat data.

4. The method according to claim 3, characterized in that The local memory and the other memory are both composed of dynamic random access memory and persistent memory.

5. The method according to claim 4, characterized in that The migrating the data corresponding to the cold page in the local memory to the other memory based on the second kernel thread includes: If the persistent memory in the other memory is not full, migrating the data corresponding to the cold page in the local memory to the persistent memory in the other memory based on the second kernel thread; If the persistent memory in the other memory is full, data corresponding to the cold page in the local memory is migrated to the dynamic random access memory in the other memory based on the second kernel thread.

6. The method according to claim 4, characterized in that The migrating the data corresponding to the hot page in the other memory to the local memory based on the second kernel thread includes: If the dynamic random access memory in the local memory is not full, migrating the data corresponding to the hot page in the other memory to the dynamic random access memory in the local memory based on the second kernel thread; If the dynamic random access memory in the local memory is full, data corresponding to the hot page in the other memory is migrated to the persistent memory in the local memory based on the second kernel thread.

7. The method according to claim 3, characterized in that Before performing a physical address lookup in the address translation cache based on the target virtual address, the method further includes: Performing data search in the last level cache based on the target virtual address; If the target data is found in the last level cache, the search is terminated; If the target data is not found in the last level cache, the step of performing a physical address search in the address translation cache based on the target virtual address is performed.

8. The method according to claim 3, characterized in that The unified addressing of the local memory and the other memories includes: Applying the rack base address, the node base address, and the node internal hardware address, the local memory and the other memories are uniformly addressed; The rack base address includes the base address of the rack where the node is located.

9. The method according to claim 3, characterized in that: The other memory includes a first-level memory and a second-level memory, and the distance between the first-level memory and the target processor is smaller than the distance between the second-level memory and the target processor.

10. The method according to claim 9, characterized in that The target processor is connected to the local memory via a memory bus.

11. The method according to claim 9, characterized in that The target processor is connected to the first level memory via a coherent interconnect protocol.

12. The method according to claim 9, characterized in that The target processor and the second-level memory are connected via an autonomous high-speed consistency network protocol.

13. The method according to claim 9, characterized in that The first level memory includes memory in the other nodes located in the same rack as the target node.

14. The method according to claim 13, characterized in that The first level memory includes at least two memories.

15. The method according to claim 9, characterized in that The second-level memory includes memory in the other nodes that are located in a different rack from the target node.

16. The method according to claim 15, characterized in that The second level memory includes memories in at least two of the other nodes located in the same rack.

17. The method according to claim 15, characterized in that The second level memory includes memories in at least two of the other nodes located in different racks.

18. The method according to claim 9, characterized in that The migrating the data corresponding to the cold page in the local memory to the other memory based on the second kernel thread includes: If the first-level memory is not full, migrating the data corresponding to the cold page in the local memory to the first-level memory based on the second kernel thread; If the first-level memory is full, data corresponding to the cold page in the local memory is migrated to the second-level memory based on the second kernel thread.

19. A memory page management device, characterized in that: The target processor to be used in the target node includes: A first acquisition module is configured to acquire a target virtual address of data to be accessed; A first search module is configured to perform a physical address search in an address translation cache based on the target virtual address, wherein the address translation cache stores a mapping relationship between a target physical address in a local memory and other memories and a corresponding virtual address; A first reading module is configured to read the target data to be accessed from the physical address to be accessed if the physical address to be accessed corresponding to the target virtual address is found in the address translation cache; A second search module is configured to perform a physical address parallel search in a local memory page table and other memory page tables based on the target virtual address if the physical address to be accessed is not found in the address translation cache, and read the target data to be accessed from the physical address to be accessed if the physical address to be accessed is found; The local memory page table includes a page table storing a mapping relationship between a physical address in the local memory and a corresponding virtual address; the other memory page table includes a page table storing a mapping relationship between a physical address in the other memory and a corresponding virtual address. The local memory includes the memory in the target node connected to the target processor, and the other memory includes the memory in other nodes other than the target node connected to the target processor.

20. A memory page management system, characterized in that: The system comprises at least two racks, each of the racks comprises at least two target nodes, each of the target nodes comprises a target processor and a memory, the target processor of the target node is connected to the memory of at least one other target node located in the same rack, and the target processor of the target node is connected to the memory of at least one target node located in a different rack; Wherein, the target processor is configured to obtain a target virtual address of data to be accessed; perform a physical address search in an address translation cache based on the target virtual address, the address translation cache storing a mapping relationship between a target physical address and a corresponding virtual address in a local memory and other memories; if a physical address to be accessed corresponding to the target virtual address is found in the address translation cache, the target data to be accessed is read from the physical address to be accessed; if the physical address to be accessed is not found in the address translation cache, perform a physical address search in parallel in a local memory page table and other memory page tables based on the target virtual address, and if the physical address to be accessed is found, the target data to be accessed is read from the physical address to be accessed; and the local memory page table includes a page table storing a mapping relationship between a physical address in the local memory and a corresponding virtual address; the other memory page table includes a page table storing a mapping relationship between a physical address in the other memory and a corresponding virtual address; the local memory includes a memory in the target node connected to the target processor, and the other memory includes a memory in other nodes other than the target node connected to the target processor.

21. An electronic device, characterized in that: include: a memory arranged to store a computer program; A processor is configured to implement the steps of the memory page management method as claimed in any one of claims 1 to 18 when executing the computer program.

22. A computer non-volatile readable storage medium, characterized in that: The computer non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the memory page management method according to any one of claims 1 to 18 are implemented.

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