Oxram resistive memory cell and associated manufacturing method

Abstract

The disclosure relates to an OxRAM resistive memory cell (1) comprising a first electrode (2), a second electrode (3) and an active layer (4) that extends between the first electrode (2) and the second electrode (3), wherein the active layer (4) comprises a dielectric oxide layer (12) and an active material layer (10), the dielectric oxide layer (12) is arranged on the active material layer (10), and the dielectric oxide layer (12) and the active material layer (10) are doped with a doping element, and wherein the second electrode (3) comprises a first conductive layer (20) in contact with the active layer (4), which conductive layer is chosen so as to create oxygen vacancies in the active material layer (10), and a second conductive layer (22) arranged on the first conductive layer (20). A method for manufacturing such a memory cell (1) is also disclosed.

Description

DESCRIPTION TITLE: OxRAM type resistive memory cell and associated manufacturing method TECHNICAL FIELD

[0001] The present invention relates generally to the field of microelectronics. It relates more particularly to the field of non-volatile resistive memories of the filamentary type.

[0002] In particular, the present invention relates to a resistive memory cell of the OxRAM type. It also relates to a method of manufacturing such a resistive memory cell of the OxRAM type. STATE OF THE ART

[0003] Resistive memories, in particular oxide-based resistive memories (or OxRAM, for "Oxide-based Random Access Memories" according to the commonly used acronym), are non-volatile memories intended to replace Flash-type memories. In addition to a high integration density, they offer high operating speed, high endurance and good compatibility with the manufacturing processes currently used in the microelectric industry, in particular with the end-of-line (BEOL, for "Back-End Of Line" according to the commonly used acronym) process of CMOS technology (for "Complementary Metal Oxide Semi-conductor" according to the commonly used acronym).

[0004] OxRAM resistive memories comprise a multitude of memory cells, also called memory points. Each OxRAM memory cell consists of a MlM (Metal-Insulator-Metal) capacitor comprising an active material of variable electrical resistance, generally a transition metal oxide (e.g. HfO2, Ta2Os, TiO2, etc.), placed between two metal electrodes. The memory cell switches reversibly between two resistance states, which correspond to logic values ​​"0" and "1" used to encode a bit of information. In some cases, more than two resistance states can be generated, which makes it possible to store several bits of information in a single memory cell.

[0005] Information is written to the memory cell by switching it from a highly resistive state (or HRS, for "High Resistance State" according to the commonly used acronym of Anglo-Saxon origin), also called "OFF" state, to a state low resistive (or LRS, for "Low Resistance State"), or "ON" state. Conversely, to erase the information from the memory cell, it is switched from the low resistive ("OFF") state to the high resistive ("ON") state.

[0006] The change in resistance of the memory cell is governed by the formation and rupture of a conductive filament of nanometric section between the two electrodes. This conductive filament is created thanks to the presence of oxygen vacancies present in the active layer of the memory cell. By modifying the potentials applied to the electrodes, it is possible to modify the distribution of the filament, and thus modify the electrical conduction between the two electrodes. In the active layer, the electrically conductive filament is either broken or, on the contrary, reformed to vary the resistance level of the memory cell, during write cycles and then resetting of this cell (SET operations, when the filament is reformed resulting in the LRS state, and RESET operations resulting in the HRS state, when the filament is broken again by respectively applying a SET, VSET or RESET, VRESET voltage to the terminals of the electrodes).

[0007] Immediately after its manufacture, the resistive memory cell is in a virgin state characterized by a very high (so-called initial) resistance. This initial resistance is much higher than the resistance of the cell when it is in the highly resistive state. The oxide layer is in fact insulating in its initial state. For the memory cell to be used, it is necessary to perform a so-called "forming" step. This step consists of a partially reversible breakdown of the oxide in order to generate the conductive filament for the first time (and therefore to place the memory cell in the low-resistive state). After this breakdown, the initially insulating oxide layer becomes active and the cell can switch between the low-resistive state and the high-resistive state by erasing and writing operations.

[0008] The forming step is accomplished by applying between the two electrodes of the memory cell a voltage (called "forming") of a value much higher than the nominal operating voltage of the memory cell (used during the following write-erase cycles), for example a voltage of the order of 2.5 V for a nominal voltage of the order of 1.5 V.

[0009] However, it is observed that the use of the MlM (Metal-Insulator-Metal) structure for each memory cell is not optimal to enable the switching of the memory cell (between the “OFF” state and the “ON” state and vice versa).

[0010] To solve this problem, it is known, for example, from the articles “Ultra-Scaled AIOx Diffusion Barriers for Multibit HfOx RRAM Operation” by K. -M. Persson, M.S. Ram and L. -E. Wernersson, IEEE Journal of the Electron Devices Society, vol. 9, pp. 564-569, 2021, doi: 10.1109 / JEDS.2021.3079398 and “Ultralow sub-500nA operating current high-performance TiN\AI2O3\HfO2\Hf\TiN bipolar RRAM achieved through understanding-based stack-engineering”, by L. Goux et al., 2012 Symposium on VLSI Technology (VLSIT), Honolulu, HI, USA, 2012, pp. 159-160, doi: 10.1109 / VLSIT.2012.6242510, to add a layer comprising an aluminum oxide AIOx on the layer comprising the active material. This layer comprising the aluminum oxide is therefore positioned between the layer comprising the active material and the upper metal layer.This layer then acts as a diffusion barrier for oxygen vacancies (relative to the filament) and thus improves the switching properties of the memory cell. In particular, this configuration makes it possible to improve the implementation of write and erase cycles.

[0011] However, the addition of this aluminum oxide layer makes it more difficult to carry out the forming step because the addition of this layer leads to an increase in the forming voltage required to form the conductive filament. SUMMARY OF THE INVENTION

[0012] The present invention therefore aims to improve resistive memory cells of the OxRAM type, in particular by improving their switching and retention properties and their stability (in particular temporal stability and temperature stability).

[0013] The invention then relates to a resistive memory cell of the OxRAM type comprising a first electrode, a second electrode and an active layer which extends between the first electrode and the second electrode, the active layer comprising a dielectric oxide layer and a layer of active material, the dielectric oxide layer being arranged on the layer of active material, the second electrode comprising a first conductive layer, in contact with the active layer and chosen to create oxygen vacancies in the layer of active material, and a second conductive layer arranged on the first layer conductive, the active layer being partly doped with a doping element.

[0014] The invention also relates to a resistive memory cell of the OxRAM type comprising a first electrode, a second electrode and an active layer which extends between the first electrode and the second electrode, the active layer comprising a dielectric oxide layer and a layer of active material, the dielectric oxide layer being arranged on the layer of active material, the dielectric oxide layer and the layer of active material being doped with a doping element, the second electrode comprising a first conductive layer, in contact with the active layer and chosen to create oxygen vacancies in the layer of active material, and a second conductive layer arranged on the first conductive layer.

[0015] Thus, advantageously according to the invention, the use of a doped active layer makes it possible to improve the switching properties of the memory cell. In particular, the active layer doped by the doping element makes it possible to improve the implementation of the write and erase cycles of the memory cell.

[0016] Additionally, the use of a doped active layer improves the retention properties of the memory cell.

[0017] Finally, the doped active layer improves the temperature stability of the memory cell (which is particularly advantageous in certain applications such as the automotive sector in which the memory cell is subjected to temperatures of around 150°Celsius (°C)). Temporal stability at room temperature is also improved. For example, during normal use, the memory cell can withstand temperatures of around 150°C for around ten years without its properties being degraded.The doped active layer also allows the properties of the memory cell to be preserved when it is subjected to higher temperatures of around 260°C for around ten minutes, as is the case, for example, when soldering the memory cell onto a printed circuit board (in the case of implementing surface mounting techniques or SMT for "Surface Mount Technology" according to the commonly used acronym of Anglo-Saxon origin).

[0018] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the memory cell according to one aspect of the invention can present one or more complementary characteristics among the following, considered individually or in all technically possible combinations: - the active material layer is doped by the doping element, the dielectric oxide layer not being doped by the doping element; - the doping element is chosen from silicon, tin, germanium or carbon; - the active material layer is based on hafnium dioxide; - the layer of active material has a thickness of between 3 and 10 nanometers; - the dielectric oxide layer comprises aluminum oxide or silicon dioxide; - the dielectric oxide layer has a thickness of between 0.3 and 1.5 nanometers; - the second conductive layer is formed from a conductive material comprising a transition metal; - the conductive material of the second conductive layer is chosen from titanium nitride, tantalum nitride or tungsten; - the material of the first conductive layer is chosen from titanium, tantalum or hafnium; - the first conductive layer has a thickness of between 3 and 20 nanometers; - the second conductive layer has a thickness of between 10 and 200 nanometers; and - the second conductive layer is formed from a plurality of conductive layers.

[0019] The invention also relates to a method for manufacturing a resistive memory cell of the OxRAM type, comprising the following steps: - formation of a first electrode, - deposition of a layer of active material on the first electrode, - depositing a layer of dielectric oxide on the layer of active material, so as to form an active layer comprising the layer of dielectric oxide and the layer of active material, - implantation of a doping element in the active layer so as to dope the active layer with the doping element, and - depositing a second electrode on the doped active layer, the second electrode comprising a first conductive layer, in contact with the active layer and chosen to create oxygen vacancies in the layer of active material, and a second conductive layer arranged on the first conductive layer

[0020] Thus, thanks to the invention, the implantation of the active layer makes it possible to improve the switching of the memory cell between the two states. The implantation of the active layer also makes it possible to improve the retention properties of the memory cell.

[0021] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the manufacturing method according to another aspect of the invention may have one or more additional characteristics among the following, considered individually or according to all technically possible combinations: - the implantation step is carried out at an implantation acceleration voltage of between 1 and 5 kilovolts, preferably between 1 and 2.5 kilovolts; - the doping element is silicon implanted in the active layer, an implantation dose of silicon in the active layer being between 0.5.10 15 cm -2 and 5.10 15 cm -2 ; - the implantation step is implemented at an implantation acceleration voltage of the order of 1 kilovolt and with an implantation dose of the doping element in the active layer of the order of 1.10 15 cm -2 ; - the first electrode and the second electrode are deposited by cathode sputtering; - the first electrode is formed by chemical vapor deposition; - the layer of active material is deposited by an atomic layer deposition method; - the layer of active material is deposited by cathode sputtering; - the layer of active material is deposited by a physical vapor deposition method; - the dielectric oxide layer is deposited by cathode sputtering; - the dielectric oxide layer is deposited by an atomic layer deposition method; - the dielectric oxide layer is deposited by a physical vapor deposition method; - the doping element is chosen from silicon, tin, germanium or carbon; - the active material layer is based on hafnium dioxide; - the layer of active material has a thickness of between 3 and 10 nanometers; - the dielectric oxide layer comprises aluminum oxide or silicon dioxide; - the dielectric oxide layer has a thickness of between 0.3 and 1.5 nanometers; - the second conductive layer is formed from a conductive material comprising a transition metal; - the conductive material of the second conductive layer is chosen from titanium nitride, tantalum nitride or tungsten; - the first conductive layer has a thickness of between 3 and 20 nanometers; and - the second conductive layer has a thickness between 10 and 200 nanometers.

[0022] The invention also relates to another method of manufacturing a resistive memory cell of the OxRAM type, comprising the following steps: - formation of a first electrode, - deposition of a layer of active material on the first electrode, - implantation of a doping element in the layer of active material so as to dope the layer of active material with the doping element, - depositing a dielectric oxide layer on the doped active material layer, so as to form an active layer comprising the dielectric oxide layer and the active material layer, and - depositing a second electrode on the active layer, the second electrode comprising a first conductive layer, in contact with the active layer and chosen to create oxygen vacancies in the layer of active material, and a second conductive layer arranged on the first conductive layer.

[0023] Thus, thanks to the invention, the implantation of the active material layer makes it possible to improve the switching of the memory cell between the two states. The implantation of the active material layer also makes it possible to improve the retention properties of the memory cell.

[0024] Finally, the implantation of the active material layer (but not the dielectric oxide layer) improves the temperature stability of the memory cell (which is particularly advantageous in certain applications such as the automotive sector in which the memory cell is subjected to temperatures above 150°C). Temporal stability at room temperature is also improved.

[0025] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the manufacturing method according to another aspect of the invention may have one or more additional characteristics among the following, considered individually or according to all technically possible combinations: - the implantation step is carried out at an implantation acceleration voltage of between 1 and 5 kilovolts, preferably between 1.5 and 2.5 kilovolts; - the doping element is silicon implanted in the active material layer, an implantation dose of silicon in the active material layer being between 0.5.10 15 cm' 2 and 5.10 15 cm' 2 ; - the first electrode and the second electrode are deposited by cathode sputtering; - the first electrode is formed by chemical vapor deposition; - the layer of active material is deposited by an atomic layer deposition method; - the layer of active material is deposited by cathode sputtering; - the layer of active material is deposited by a physical vapor deposition method; - the dielectric oxide layer is deposited by cathode sputtering; - the dielectric oxide layer is deposited by an atomic layer deposition method; - the dielectric oxide layer is deposited by a physical vapor deposition method; - the doping element is chosen from silicon, tin, germanium or carbon; - the active material layer is based on hafnium dioxide; - the layer of active material has a thickness of between 3 and 10 nanometers; - the dielectric oxide layer comprises aluminum oxide or silicon dioxide; - the dielectric oxide layer has a thickness of between 0.3 and 1.5 nanometers; - the second conductive layer is formed from a conductive material comprising a transition metal; - the conductive material of the second conductive layer is chosen from titanium nitride, tantalum nitride or tungsten; - the first conductive layer has a thickness of between 3 and 20 nanometers; and - the second conductive layer has a thickness between 10 and 200 nanometers. BRIEF DESCRIPTION OF THE FIGURES

[0026] Other characteristics and advantages of the invention will emerge clearly from the description given below, for information purposes only and in no way limiting, with reference to the appended figures, among which:

[0027] [Fig. 1] represents, in schematic form, an example of a memory cell according to the invention,

[0028] [Fig. 2] is a graph representing an error rate as a function of a deposition delay between the different layers of the memory cell of Figure 1,

[0029] [Fig. 3a], [Fig. 3b], [Fig. 3c] and [Fig. 3d] represent the distributions of memory cells as a function of resistance for the LRS and HRS states for two sets of memory cells considered in the present invention,

[0030] [Fig. 4a], [Fig. 4b], [Fig. 4c] and [Fig. 4d] respectively represent an enlargement of a part of Figures 3a to 3d,

[0031] [Fig. 5] represents, in the form of a flowchart, an example of a method of manufacturing a memory cell in accordance with the invention,

[0032] [Fig. 6a] and [Fig. 6b] represent the evolution of the distributions representing the LRS and HRS states in the case of two implantation acceleration voltages,

[0033] [Fig. 7] represents, in the form of a flowchart, another example of a method of manufacturing a memory cell in accordance with the invention, and

[0034] [Fig. 8] represents different implantation profiles in the memory cell according to the invention.

[0035] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT

[0036] The present invention aims to improve the manufacturing of resistive memory cells of the OxRAM type, so as to give them optimized operation. In particular, the present invention relates to a resistive memory cell in which the switching and retention properties are improved. In addition, the resistive memory cells according to the invention have improved stability (in particular temporal stability and temperature stability) compared to known resistive memory cells.

[0037] Figure 1 represents an example of a resistive memory cell 1 (also called “memory cell 1” hereinafter) according to the invention.

[0038] The memory cell 1 comprises a first electrode 2, a second electrode 3 and an active layer 4 arranged between the first electrode 2 and the second electrode 3.

[0039] As can be seen in Figure 1, the memory cell 1 is in the form of a stack of layers which extends along a z axis. The first electrode 2, the active layer 4 and the second electrode 3 form the different layers of this stack. The different layers extend parallel to each other (and parallel to a substrate, not shown, on which the memory cell 1 rests). The z axis is here perpendicular to the plane of the different layers of the stack forming the memory cell 1.

[0040] Each of the layers forming memory cell 1 is now described.

[0041] The first electrode 2 forms a lower electrode of the memory cell 1.

[0042] By convention, the terms "lower" and "upper" are used in relation to the substrate on which the memory cell 1 is fabricated. Thus, a lower layer of the memory cell will refer to a layer close to the substrate, while an upper layer will refer to a layer opposite and far from the substrate.

[0043] The first electrode 2 is formed from a conductive and inert material. This conductive material is in particular neutral with respect to oxygen atoms. The first electrode 2 comprises, for example, a metallic material. Here, it comprises titanium nitride (TiN). Alternatively, the conductive material may be tantalum nitride (TaN) or tungsten (W). Alternatively, other materials conductors can be used (and in particular, metal nitride more generally).

[0044] The first electrode 2 has, for example, a thickness of between 10 and 200 nanometers (nm).

[0045] The active layer 4 is arranged on the first electrode 2. It is here in the form of a two-layer structure. It comprises a dielectric oxide layer 12 and a layer of active material 10. As can be seen in FIG. 1, the dielectric oxide layer 12 is arranged on the layer of active material 10.

[0046] The dielectric oxide layer 12 is adapted to serve as a support for the formation of an electrically conductive filament, which passes through the active layer from one side to the other to electrically connect the first electrode 2 to the second electrode 3. This electrically conductive filament can be broken and then formed again several times successively during the successive write and erase (RESET) cycles, i.e. resetting, of the memory cell. In practice, this conductive filament is produced a first time during a sort of controlled electrical breakdown of the active layer (according to a usual operation called "forming").

[0047] The dielectric oxide layer 12 comprises, for example, a metal oxide or a semiconductor oxide. Preferably, it is an aluminum oxide AI2O3. Alternatively, it may also be silicon dioxide SiO2.

[0048] The dielectric oxide layer 12 here has a thickness of between 0.3 and 1.5 nm.

[0049] The active material layer 10 is arranged between the first electrode 2 and the dielectric oxide layer 12. The active material layer 10 also comprises a metal oxide or a semiconductor oxide. Preferably here, the active material layer 4 is based on amorphous hafnium dioxide HfC. In the present description, the expression "based on" is understood to mean that the layer concerned comprises more than 50% of the element mentioned after this expression (for example here, this means that the active material layer 4 comprises more than 50% of hafnium dioxide).

[0050] Alternatively, the active material layer may comprise tantalum(V) oxide Ta2Os.

[0051] The layer of active material 10 here has a thickness of between 3 and 10 nm.

[0052] Advantageously according to the invention, the active layer 4 is partly doped with a doping element. More particularly here, the active material layer 10 and the dielectric oxide layer 12 are both doped with the doping element. The implantation of the doping elements in the active layer of the memory cell makes it possible to improve the performance of the memory cell, and in particular the switching properties during the write and reset cycles of the memory cell (SET operation, when the filament is reformed resulting in the LRS state, and RESET resulting in the HRS state, when the filament is broken again by respective application of a SET, VSET OR RESET, VRESET voltage to the terminals of the electrodes).

[0053] Furthermore, as also described below, the implantation of the doping elements in the active layer makes it possible, during the manufacture of the memory cell, to avoid constraints on the time taken to deposit the successive layers of the memory cell.

[0054] To illustrate this, an indicator, the error rate (or BER for "Bit Error Rate" according to the commonly used acronym of Anglo-Saxon origin) on a set of memory cells is evaluated. By definition, this error rate corresponds to the percentage of memory cells in the set of memory cells considered which will not present satisfactory properties.

[0055] In practice, this error rate is evaluated by representing the distributions of the memory cells of the set considered as a function of the resistance R (in Ohm Q) for the LRS and HRS states (as represented for example in figures 3a to 3d, 4a to 4d, 6a and 6b). The distributions of the memory cells are here considered in a cumulative manner (this is the cumulative distribution function or CDF for "Cumulative Distribution Function" according to the commonly used acronym of Anglo-Saxon origin). The error rate then corresponds to the point of intersection of the distributions representing the LRS and HRS states.

[0056] As can be seen in Figure 2, in the case where the active layer is not doped by the doping element (symbols in the form of circles in Figure 2), the error rate associated with memory cells (in which the active layer is not doped) increases significantly (ratio 1 to 100) when the delay between the deposition of the active layer 4 and the second electrode 3 goes from 20 hours to 120 hours.

[0057] On the contrary, in the case where the active layer 4 is doped by the doping element (symbols in the form of triangles in FIG. 2), the delay between the deposition of the second electrode 3 and the active layer 4 has no influence on the error rate (which remains constant and very low because it is less than 0.1%). Thus, the implantation of doping elements in the active layer makes it possible to make the manufacture of the memory cell according to the present invention insensitive to the delay between the deposition of the different layers of the memory cell 1.

[0058] Preferably, the active material layer 10 is doped by the doping element, while the dielectric oxide layer is devoid of doping elements. In other words, according to a preferred embodiment, only the active material layer 10 of the active layer 4 is doped by the doping element. The dielectric oxide layer 12 is therefore not doped by the doping element.

[0059] The implantation of doping elements in the active material layer, without the dielectric oxide layer being doped, then makes it possible to improve the stability of the memory cell, in particular following the various write and reset cycles of the memory cell.

[0060] This characteristic is particularly highlighted by subjecting the memory cells (in which only the active material layer is doped or in which the doping element is also present in the dielectric oxide layer) to different heating cycles and by evaluating the error rate following each of the heating cycles.

[0061] Here, a heating cycle of a few minutes (e.g., 3 minutes) at more than 200°C is considered (preferably 260°C). The memory cells are subjected to several heating cycles (e.g., four here). The error rate is evaluated following each of the heating cycles.

[0062] Figures 3a to 3d represent the distributions of memory cells as a function of resistance for the LRS and HRS states for two sets of memory cells: a first set in which, for each memory cell, the active material layer is doped by the doping element (corresponding to the curve with the “square” symbol) and a second set in which, for each memory cell, the doping element is present in the active material layer and in the dielectric oxide layer (corresponding to the curve with the “circle” symbol). Figures 3a to 3d therefore concern the same distributions of memory cells, considered after several successive heating cycles (as described previously).

[0063] Figures 4a to 4d correspond respectively to an enlargement of a part of Figures 3a to 3d.

[0064] For each set of memory cells, the dashed line curve corresponds to the distribution (as a function of resistance) of memory cells for the LRS state and the solid line curve corresponds to the distribution (as a function of resistance) of memory cells for the HRS state.

[0065] Figures 3a and 4a correspond to the distributions obtained before a first heating cycle. Figures 3b and 4b correspond to the distributions obtained after one heating cycle. Figures 3c and 4c correspond to the distributions obtained after two heating cycles. Figures 3d and 4d correspond to the distributions obtained after three heating cycles.

[0066] As defined previously, the error rate is evaluated by the intersection of the distributions representing the LRS and HRS states. As can be seen in Figures 3a to 3d, in the case where the doping element is present only in the active material layer, the error rate remains lower than 10' 3 (regardless of the number of heating cycles applied), that is, in the first set of memory cells there is less than one memory cell whose operation is unreliable.

[0067] In the case where the doping element is present in the active material layer and in the dielectric oxide layer, the curves representing the distributions associated with the LRS and HRS states intersect from the first heating cycle. Furthermore, as can be seen more clearly in Figures 4b to 4d, the error rate is higher for the second set of memory cells than for the first set.

[0068] The degradation (due to temperature) of the memory cell of the first set, following these different heating cycles, is thus limited. Memory cells in which the active material layer is doped by the doping element (but not the dielectric oxide layer) therefore have better temperature stability.

[0069] Similar results are obtained to observe the temporal stability, at room temperature, of memory cells in which the active material layer is doped by the doping element (but not the dielectric oxide layer).

[0070] For example here, an implantation concentration of the doping element in the active material layer 10 is greater than an implantation concentration of the doping element in the dielectric oxide layer 12.

[0071] Furthermore, the implantation concentration of the doping element in the active material layer 10 is between 0.3.10 21 cm' 3 and 5.10 21 cm' 3 . Preferably, this implantation concentration of the doping element in the layer of active material 10 is between 0.5.10 21 cm' 3 and 3.5.10 21 cm' 3 . Furthermore, the implantation concentration of the doping element in the dielectric oxide layer 12 is less than 2.10 21 cm' 3 .

[0072] The doping element is preferably silicon Si. The use of silicon as a doping element makes it possible to reinforce the effect of insensitivity to the time delay between the deposition of the different layers of the memory cell. Furthermore, the use of silicon as a doping element also makes it possible to improve the retention properties of memory cells, i.e. the stored information has little risk of being altered.

[0073] In the case of silicon, the active material layer 10 is for example exposed to a dose of dopant between 0.5.10 15 cm' 2 and 5.10 15 cm' 2 in order to obtain a presence of between 0.7 and 7% of silicon atoms in the layer of active material 10 (having a thickness of between 3 and 10 nm).

[0074] Alternatively, other doping elements may be used such as tin Sn, germanium Ge or carbon C. These other doping elements also improve the switching properties of the memory cell 1.

[0075] As shown in Figure 1, the second electrode 3 (or upper electrode) is arranged on the active layer 4. It is here in the form of a bilayer structure. It comprises a first conductive layer 20 and a second conductive layer 22.

[0076] The second conductive layer 22 is arranged on the first conductive layer 20. The second conductive layer 22 is formed from a conductive material comprising a transition metal. This conductive material is by example of titanium nitride TiN. Alternatively, it can be other conductive materials such as tantalum nitride TaN or tungsten W.

[0077] The second conductive layer 22 has a thickness of between 10 and 200 nm.

[0078] The second conductive layer 22 comprises, for example, a plurality of conductive layers.

[0079] The second conductive layer 22 plays both the role of a protective layer (in particular preventing total oxidation of the first conductive layer), and the role of a contact layer allowing the memory cell 1 to be electrically connected to its electronic control and reading circuit.

[0080] The first conductive layer 20 is arranged on the active layer 4. It is in direct contact with the active layer 4. More particularly, it is in direct contact with the dielectric oxide layer 12 of the active layer 4.

[0081] The first conductive layer 20 has the particularity of being a layer suitable for creating oxygen vacancies in the active layer 4 when this first conductive layer 20 is in contact with the active layer 4. According to the commonly used Anglo-Saxon term, the first conductive layer 20 is a layer of the “Oxygen scavenging layer” type. Since the mechanism for forming the conductive filament in the dielectric oxide layer 12 generally involves a reorganization of the oxygen vacancies within the dielectric oxide, the first conductive layer 20 makes it possible to facilitate the exchange of oxygen with the active layer 4.

[0082] The first conductive layer comprises a metallic conductive material. Preferably, it comprises titanium Ti, tantalum Ta or hafnium Hf.

[0083] For example, when the second conductive layer 22 comprises titanium nitride, the first conductive layer 20 is formed from a conductive material chosen from titanium Ti or hafnium Hf.

[0084] Alternatively, when the second conductive layer 22 comprises tantalum nitride, the first conductive layer 20 is formed from a conductive material chosen from tantalum Ta or hafnium Hf.

[0085] Alternatively, when the second conductive layer 22 comprises tungsten, the first conductive layer 20 is formed from a conductive material chosen from titanium Ti, tantalum Ta or hafnium Hf.

[0086] Here, the thickness of the first conductive layer 20 is between 3 and 20 nm.

[0087] As previously indicated, advantageously, the memory cell according to the invention has improved switching properties (between LRS and HRS states) and retention. In addition, they also have improved temperature stability compared to known resistive memory cells.

[0088] The present invention also relates to a method of manufacturing a memory cell 1. Figure 5 represents, in the form of a flowchart, an example of a manufacturing method according to the invention.

[0089] As shown in this figure, the method begins with a step of forming the first electrode 2. This step therefore aims to form the first electrode 2, for example on a substrate (substrate not shown in the figures).

[0090] In practice, the first electrode 2 is for example formed by cathode sputtering in a vacuum deposition chamber. In the case where the first electrode 2 is formed from titanium nitride, this is reactive cathode sputtering.

[0091] Alternatively, the first electrode may be formed by chemical vapor deposition (e.g., titanium nitride TiN). Alternatively, the first electrode may be formed in a damascene structure.

[0092] Then, the method continues with a step of depositing the layer of active material 10 (step E4). This layer of active material 10 is formed on the first electrode 2. The deposition of the layer of active material 10 is carried out in such a way that this layer has a substantially constant thickness at all points. In this description, the term “substantially constant” means a thickness not varying by more than 20%, preferably by more than 10%, and more preferably by more than 5%.

[0093] In practice, the layer of active material 10 is deposited by an atomic layer deposition method (or ALD for “Atomic Layer Deposition” according to the commonly used acronym of Anglo-Saxon origin).

[0094] Alternatively, the active material layer may be deposited by sputtering. Alternatively, the active material layer may be deposited by a physical vapor deposition (or PVD) method. Deposition"). Alternatively, the active material layer can be deposited by an ion beam deposition (or IBD) method.

[0095] As shown in Figure 5, the method continues with step E6 of implanting the doping element in the active material layer 10 formed in step E4. The doping element is implanted, in the active material layer 10, according to a determined profile. This step then makes it possible to dope the active material layer 10 with the doping element.

[0096] In practice, the implantation step is for example implemented in a reactor different from the deposition chamber of the first electrode 2 and the layer of active material 10. This makes it possible to facilitate the manufacturing process by controlling the implantation implementation parameters more precisely (in particular concerning the implantation acceleration voltage and the implantation dose as described below).

[0097] Advantageously, the implantation step E6 is implemented at an implantation acceleration voltage of between 1 and 5 kilovolts (kV). More preferably, the implantation acceleration voltage is between 1 and 2.5 kV, preferably between 1.5 and 2.5 kV. For example, the implantation acceleration voltage is of the order of 1 kV, or 2 kV, or 3 kV or even 4 kV. More preferably, the implantation step is implemented at an implantation acceleration voltage of the order of 1 kV and with an implantation dose of the doping element in the active layer of the order of 1.10 15 cm -2 .

[0098] Figures 6a and 6b represent the evolution of the distributions representing the LRS and HRS states in the case of an implantation acceleration voltage of 4 kV (figure 6a) and 1.5 kV (figure 6b), for an implantation dose of the order of 2.10 15 cm' 2 .

[0099] As these figures show, the error rate (corresponding, in each figure, to the ordinate of the intersection of the curves associated with the LRS and HRS states) is lower in the case of a lower implantation acceleration voltage (i.e. in the case of Figure 6b). An implantation with a low implantation acceleration voltage is therefore more advantageous. It also allows better robustness of the retention properties of the memory cells.

[0100] Here, for example, it is a step of ionic implantation of silicon (which is the doping element) in the layer of active material 10. The implantation doses are for example between 0.5.10 15 cm' 2 and 5.10 15 cm' 2 . Preferably, the dose of implantation is of the order of 1.10 15 cm -2In practice, the implantation dose is adjusted according to the programming voltages used for the memory cell (and more particularly according to the forming voltage used).

[0101] Finally, step E6 therefore makes it possible to obtain a layer of active material 10 doped by the doping element.

[0102] The method then continues, in step E8, with the deposition of the dielectric oxide layer 12. This dielectric oxide layer 12 is formed on the doped active material layer 10 (obtained at the end of step E6).

[0103] In practice, the dielectric oxide layer 12 is deposited by an atomic layer deposition (or ALD) method. Alternatively, the dielectric oxide layer 12 may be deposited by sputtering. Alternatively, the dielectric oxide layer may be deposited by a physical vapor deposition (or PVD) method. Alternatively, the dielectric oxide layer may be deposited by an ion beam deposition (or IBD) method.

[0104] As described previously, the implantation of the active material layer by the doping element makes it possible to make the manufacturing process insensitive to the delay observed between the deposition of the different layers of the stack of the memory cell 1. This thus makes it possible to carry out the deposition of the first electrode and the active material layer in a first vacuum deposition chamber, then to carry out the implantation in another reactor (in order to better control the implantation parameters) and finally to deposit the dielectric oxide layer in the first vacuum deposition chamber. The implantation of the active material layer therefore makes it possible to overcome time constraints for the deposition of the different layers of the stack forming the memory cell 1.

[0105] The method finally ends with a step of depositing the second electrode 3 (step E10). The second electrode 3 is formed on the active layer 4 (formed, as indicated previously, from the active material layer 10 and the dielectric oxide layer 12). More particularly, the second electrode 3 is deposited on the dielectric oxide layer 12.

[0106] As described previously, the second electrode 3 comprises the first conductive layer 20 and the second conductive layer 22. The step of depositing the second electrode 3 therefore comprises two sub-steps here: a first sub-step E10a of depositing the first conductive layer 20 and a second sub-step E10b of depositing the second conductive layer 22.

[0107] The first conductive layer 20 is therefore first deposited on the active layer 4 (and in particular on the dielectric oxide layer 12). The first conductive layer 20 is for example formed by cathode sputtering in a vacuum deposition chamber. This is for example the same deposition chamber used for the first electrode. Preferably, the deposition of the first conductive layer 20 is carried out in another vacuum deposition chamber.

[0108] Then, the second conductive layer 22 is deposited on the first conductive layer 20 formed. The second conductive layer 22 is for example formed by cathode sputtering in a vacuum deposition chamber. In practice, the second conductive layer 22 is formed in the same deposition chamber as the first conductive layer 20.

[0109] In the case where the second conductive layer is formed from titanium nitride, it is a reactive cathode sputtering.

[0110] Alternatively, the implantation of the active layer can be implemented by several successive implantation steps in order to obtain the desired doped active layer.

[0111] Figure 7 represents, in the form of a flowchart, another example of a manufacturing method according to the invention. Only the steps different from the example described previously are presented in detail below.

[0112] As shown in this figure 7, the method begins with a step E22 of forming the first electrode 2 (this step is similar to the step E2 described previously). This step therefore aims to form the first electrode 2, for example on a substrate (substrate not shown in the figures).

[0113] Then, the method continues with a step of depositing the layer of active material 10 (step E24 similar to step E4 described previously). This layer of active material 10 is formed on the first electrode 2.

[0114] The method then continues, in step E26, with the deposition of the dielectric oxide layer 12. This dielectric oxide layer 12 is formed on the active material layer 10 (obtained at the end of step E24).

[0115] In practice, as previously described for step E8, the dielectric oxide layer 12 is deposited by an atomic layer deposition (or ALD) method. Alternatively, the dielectric oxide layer 12 may be deposited by sputtering. Alternatively, the dielectric oxide layer may be deposited by a physical vapor deposition (PVD) method. Alternatively, the dielectric oxide layer may be deposited by an ion beam deposition (IBD) method.

[0116] As shown in Figure 7, the method continues with step E28 of implanting the doping element in the active layer 4. More particularly, here, the implantation of the doping element is implemented in the active material layer 10 formed in step E24 and in the dielectric oxide layer 12 formed in step E26. The doping element is implanted, in the active material layer 10 and in the dielectric oxide layer 12, according to a determined profile (i.e. with an implantation concentration of the doping element determined as a function of the layer considered in the memory cell). This step E28 then makes it possible to dope the active layer 4 (formed by the active material layer 10 and the dielectric oxide layer 12) with the doping element.

[0117] In practice, the implantation step is for example implemented in a reactor different from the deposition chamber of the first electrode 2 and the active layer 4 (formed by the active material layer 10 and the dielectric oxide layer 12). This makes it possible to facilitate the manufacturing process by more precisely controlling the parameters for implementing the implantation (in particular concerning the implantation acceleration voltage, the implantation dose and the implantation concentration of the doping element as described below).

[0118] Advantageously, the implantation step E28 is implemented at an implantation acceleration voltage of between 1 and 5 kilovolts (kV). More preferably, the implantation acceleration voltage is between 1 and 2.5 kV, more preferably between 1.5 and 2.5 kV. For example, the implantation acceleration voltage is of the order of 1 kV, or 2 kV, or 3 kV or even 4 kV. More preferably, the implantation step is implemented at an implantation acceleration voltage of the order of 1 kV and with an implantation dose of the doping element in the active layer of the order of 1.10 15 cm' 2 .

[0119] Here, for example, it is a step of ionic implantation of silicon (which is the doping element) in the active layer 4. The implantation doses are for example between 0.5.10 15 cm' 2 and 5.10 15 cm' 2. Preferably, the implantation dose is in the order of 1.10 15 cm' 2 . In practice, the implantation dose is adjusted according to the programming voltages used for the memory cell (and more particularly according to the forming voltage used).

[0120] Figure 8 shows different implantation profiles (and more particularly the implantation concentration of the doping element) of the active layer 4 (therefore of the active material layer 10 and of the dielectric oxide layer 12) as a function of the layers of the memory cell 1. Here, the memory cell considered has a layer of active material 10 comprising hafnium dioxide with a thickness of 5 nm and a dielectric oxide layer comprising an aluminum oxide with a thickness of 0.6 nm. The first electrode 2 comprises titanium nitride. The doping element here is silicon.

[0121] Each of its implantation profiles represented here is associated with an implantation acceleration voltage of between 1 and 4 kV. More particularly, the curve associated with the “square” pattern corresponds to an implantation acceleration voltage of the order of 1 kV, that with the “circle” pattern corresponds to an implantation acceleration voltage of the order of 2 kV, that with the “triangle” pattern corresponds to an implantation acceleration voltage of the order of 3 kV and that with the “star” pattern corresponds to an implantation acceleration voltage of the order of kV. The implantation dose in doping element considered in the examples of figure 8 is of the order of 1 .10 15 cm' 2 .

[0122] Regardless of the implantation acceleration voltage (but under the conditions mentioned above), the maximum implantation concentration of the doping element in the active material layer 10 is greater than the maximum implantation concentration of the doping element in the dielectric oxide layer 12. Here, the maximum implantation concentration of the doping element in the active material layer 10 is between 1, 2.10 21 cm' 3 and 3.2.10 21 cm' 3 The maximum implantation concentration of the doping element in the dielectric oxide layer 12 is between 0.5.10 21 cm' 3 and 1,7.10 21 cm' 3 .

[0123] Furthermore, the concentration of Cions for implantation of the doping element in the active material layer 10 is between 0.3.10 21 cm' 3 and 5.10 21 cm' 3. The concentration of Cions of implantation of the doping element in the dielectric oxide layer is less than 2.10 21 cm' 3 .

[0124] As can be seen in Figure 8, under the experimental conditions mentioned previously for this case, the implantation step also leads to an implantation of the doping element in the first electrode 2. This does not deteriorate not the performance of the memory cell. Furthermore, the implantation step can be optimized, for example by adjusting the implantation acceleration voltage so that the doping element does not reach the first electrode 2. As shown in Figure 8, an implantation acceleration voltage of less than 1.5 kV (for example of the order of 1 kV), with here an implantation dose of the order of 1.10 15 cm -2 , allows the implantation to be controlled so that it does not reach the first electrode 2.

[0125] Finally, step E28 therefore makes it possible to obtain an active layer 4 doped by the doping element.

[0126] As described previously, the implantation of the active layer by the doping element makes it possible to make the manufacturing process insensitive to the delay observed between the deposition of the different layers of the stack of the memory cell 1. This thus makes it possible to carry out the deposition of the first electrode and the active layer 4 (formed by the layer of active material 10 and the layer of dielectric oxide 12) in a first vacuum deposition chamber, then to carry out the implantation in another reactor (in order to best control the implantation parameters). The implantation of the layer of active material therefore makes it possible to overcome time constraints for the deposition of the different layers of the stack forming the memory cell 1.

[0127] The method finally ends with a step of depositing the second electrode 3 (step E30 similar to step E10 described previously). The second electrode 3 is formed on the active layer 4 (formed, as indicated previously, from the active material layer 10 and the dielectric oxide layer 12). More particularly, the second electrode 3 is deposited on the dielectric oxide layer 12. In a similar manner to step E10 described previously, the step E30 of depositing the second electrode 3 here comprises two sub-steps: a first sub-step E30a of depositing the first conductive layer 20 and a second sub-step E30b of depositing the second conductive layer 22.

[0128] Alternatively, the implantation of the active layer can be implemented by several successive implantation steps in order to obtain the desired doped active layer.

[0129] Finally, advantageously according to the invention, the implantation of the doping element in the active layer makes it possible to improve the switching properties, therefore to improve the implementation of successive write and erase cycles.

[0130] In addition, the use of a low implantation acceleration voltage improves the retention properties of the memory cell 1. The risks of alteration of the information stored in the memory cell are therefore limited.

[0131] The use of a low implantation acceleration voltage also makes the manufacturing process insensitive to the waiting time observed between the deposition of the different layers of the stack forming the memory cell 1.

[0132] Finally, the implantation in the active layer 4 (formed by the active material layer 10 and the dielectric oxide layer 12) makes it possible to confer better temporal and temperature stability to the memory cell 1.

Claims

CLAIMS

1. A resistive OxRAM type memory cell (1) comprising a first electrode (2), a second electrode (3) and an active layer (4) which extends between the first electrode (2) and the second electrode (3), the active layer (4) comprising a dielectric oxide layer (12) and an active material layer (10), the dielectric oxide layer (12) being arranged on the active material layer (10), the dielectric oxide layer (12) and the active material layer (10) being doped with a doping element, and the second electrode (3) comprising a first conductive layer (20), in contact with the active layer (4) and chosen to create oxygen vacancies in the active material layer (10), and a second conductive layer (22) arranged on the first conductive layer (20).

2. Memory cell (1) according to claim 1, wherein the doping element is selected from silicon, tin, germanium or carbon.

3. Memory cell (1) according to claim 1 or 2, wherein the layer of active material (10) is based on hafnium dioxide.

4. Memory cell (1) according to any one of claims 1 to 3, in which the layer of active material (10) has a thickness of between 3 and 10 nanometers.

5. A memory cell (1) according to any one of claims 1 to 4, wherein the dielectric oxide layer (12) comprises aluminum oxide or silicon dioxide.

6. Memory cell (1) according to any one of claims 1 to 5, in which the dielectric oxide layer (12) has a thickness of between 0.3 and 1.5 nanometers.

7. Memory cell (1) according to any one of claims 1 to 6, wherein the material of the first conductive layer (20) is selected from titanium, tantalum or hafnium.

8. Memory cell (1) according to any one of claims 1 to 7, wherein the conductive material of the second conductive layer (22) is chosen from titanium nitride, tantalum nitride or tungsten.

9. Memory cell (1) according to any one of claims 1 to 8, wherein the first conductive layer (20) has a thickness of between 3 and 10 nanometers and / or the second conductive layer (22) has a thickness of between 10 and 200 nanometers.

10. Method for manufacturing a resistive memory cell (1) of the OxRAM type, comprising the following steps: - formation (E22) of a first electrode (2), - deposition (E24) of a layer of active material (10) on the first electrode (2), - deposition (E26) of a dielectric oxide layer (12) on the active material layer (10), so as to form an active layer (4) comprising the dielectric oxide layer (12) and the active material layer (10), - implantation (E28) of a doping element in the active layer (4) so ​​as to dope the active layer (4) with the doping element, and - deposition (E30) of a second electrode (3) on the doped active layer (4), the second electrode (3) comprising a first conductive layer (20), in contact with the active layer (4) and chosen to create oxygen vacancies in the layer of active material (10), and a second conductive layer (22) arranged on the first conductive layer (20).

11. A manufacturing method according to claim 10, wherein the implantation step is carried out at an implantation acceleration voltage of between 1 and 5 kilovolts, preferably between 1 and 2.5 kilovolts.

12. A manufacturing method according to claim 10 or 11, wherein the doping element is silicon implanted in the active layer (4), an implantation dose of the silicon in the active layer (4) being between 0.5.10 15 cm -2 and 5.10 15 cm -2 . Tl

13. A manufacturing method according to any one of claims 10 to 12, wherein the implantation step is carried out at an implantation acceleration voltage of the order of 1 kilovolt and with an implantation dose of the doping element in the active layer (4) of the order of 1.10 15 cm' 2 .

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