Circuit board and semiconductor package comprising same

Abstract

A circuit board of an embodiment comprises: an insulating layer having a recess in the top surface thereof; a pad arranged in the recess of the insulating layer; and a protective layer arranged on the insulating layer, wherein: the side surface of the pad includes a first side surface in contact with the insulating layer, and a second side surface in contact with the protective layer; and a first length of the first side surface in the vertical direction is different from a second length of the second side surface in the vertical direction.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a semiconductor package.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on a limited-size semiconductor package substrate. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. Accordingly, these semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are increasing the number of semiconductor elements and / or the size of each semiconductor element in line with the trend toward high integration, but the concept is expanding to semiconductor chiplets in which the functional parts of semiconductor elements are divided due to limitations of the reticle, etc.

[0005] Accordingly, intercommunication between semiconductor devices and / or semiconductor chiplets is becoming more important, and accordingly, there is a trend toward placing an interposer between the substrate of a semiconductor package and the semiconductor devices.

[0006] An interposer can function as a redistribution layer that gradually increases the width or depth of a circuit pattern from a semiconductor device toward a semiconductor package to facilitate communication between semiconductor devices and / or semiconductor chiplets, or to interconnect a semiconductor device and a semiconductor package substrate, thereby facilitating electrical signals between a semiconductor device and a semiconductor package substrate having a circuit pattern that is relatively large compared to the circuit pattern of the semiconductor device.

[0007] Meanwhile, as the number of input and output terminals of semiconductor devices increases, the width and / or spacing of terminals of semiconductor devices and / or semiconductor chiplets is trending toward narrowing. Accordingly, the width and / or spacing of wiring electrodes provided on circuit boards is also becoming smaller.

[0008] Accordingly, circuit boards are being manufactured using the Embedded Trace Substrate (ETS) process, which is advantageous in miniaturizing the width and / or spacing of the top pads connected to semiconductor devices. Circuit boards manufactured using the ETS process have a structure in which the top pads are embedded within an insulating layer, thereby eliminating circuit loss due to etching, and thus advantageous in minimizing the circuit pitch.

[0009] However, in the process of removing the seed layer in a circuit board manufactured using the ETS method, a portion of the pad may also be removed, and thus the upper surface of the pad may be positioned lower than the upper surface of the insulating layer. Accordingly, a circuit board manufactured using the conventional ETS method had to manage the height difference between the upper surface of the insulating layer and the upper surface of the pad, which had the problem of lowering the product yield. In addition, when a portion of the upper surface of a plurality of pads is removed, the degree of removal of each pad may be different, and this may cause a height difference in the upper surfaces of the plurality of pads. In this case, the semiconductor element may not be stably attached on the pad of the circuit board, and this may cause a problem in which the semiconductor element does not operate stably.

[0010] The embodiment provides a circuit board of a novel structure and a semiconductor package including the same.

[0011] In addition, the embodiment provides a circuit board advantageous for fine pitch and a semiconductor package including the same.

[0012] In addition, the embodiment provides a circuit board having an electrode portion with improved flatness and a semiconductor package including the same.

[0013] In addition, the embodiment provides a circuit board capable of preventing deformation of a pad and a semiconductor package including the same.

[0014] In addition, the embodiment provides a circuit board having improved electrical connection reliability between semiconductor elements and a semiconductor package including the same.

[0015] In addition, the embodiment provides a circuit board including a protective layer capable of alleviating thermal deformation according to a heat cycle and a semiconductor package including the same.

[0016] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0017] A circuit board of an embodiment includes an insulating layer having a recess on an upper surface; a pad disposed within the recess of the insulating layer; and a protective layer disposed on the insulating layer, wherein side surfaces of the pad include a first side in contact with the insulating layer and a second side in contact with the protective layer, and a first vertical length of the first side and a second vertical length of the second side are different from each other.

[0018] Additionally, the ratio of the first length to the second length is greater than 1:1 and less than or equal to 1:3.

[0019] Additionally, the protective layer has a through hole that overlaps the pad in a vertical direction.

[0020] Additionally, the horizontal width of the through hole is smaller than the horizontal width of the pad.

[0021] Additionally, the circuit board further includes a bonding portion disposed within the through hole of the protective layer.

[0022] Additionally, the bonding portion includes a through portion disposed within the through hole and a protrusion disposed on the through portion and protruding onto the protective layer.

[0023] Additionally, the bonding portion includes a metal material of either copper or tin.

[0024] Additionally, the circuit board further includes a barrier layer provided within the through hole of the protective layer and disposed between the pad and the bonding portion.

[0025] Additionally, the barrier layer and the pad include different metal materials.

[0026] Additionally, the pad comprises copper and the barrier layer comprises nickel.

[0027] Additionally, the upper surface of the pad has a concave crevice facing the lower surface of the pad, and the barrier layer includes an extension provided within the crevice of the pad.

[0028] Additionally, the vertical length from the upper surface of the pad to the lowest end of the crevice satisfies a range of 5% to 15% of the vertical length from the upper surface of the pad to the lower surface of the pad.

[0029] Additionally, the circuit board further includes a via electrode disposed within the insulating layer and connected to the pad, wherein a slope of a side surface of the pad is closer to a right angle than a slope of a side surface of the via electrode.

[0030] Additionally, at least one of the upper surface of the insulating layer and the lower surface of the protective layer includes at least one of a concave surface and a convex surface.

[0031] Meanwhile, a circuit board according to an embodiment includes an insulating layer having a recess on an upper surface; a pad disposed within the recess of the insulating layer; a protective layer disposed on the insulating layer; and a connecting member disposed within the insulating layer, wherein the pads include a first group of pads that vertically overlap with the connecting member and a second group of pads that do not vertically overlap with the connecting member, and each of the pads of the first group and the second group includes a first side that contacts the insulating layer and a second side that contacts the protective layer, and a first vertical length of the first side and a second vertical length of the second side are different from each other.

[0032] Additionally, the ratio of the first length to the second length is greater than 1:1 and less than or equal to 1:3.

[0033] In addition, the bonding portion is further included, which is disposed on each of the pads of the first group and the second group and includes a penetration portion penetrating the protective layer and a protrusion portion protruding above the protective layer, wherein the width of the penetration portion of the bonding portion is smaller than the width of each of the pads of the first group and the second group.

[0034] In addition, the circuit board further includes a barrier layer disposed between the through portion of the bonding portion and the pads of each of the first and second groups, wherein the barrier layer and the pads of each of the first and second groups include different metal materials, and the width of the barrier layer is smaller than the width of the pads of each of the first and second groups.

[0035] The circuit board of the embodiment includes an insulating layer having a recess on an upper surface, a pad disposed within the recess of the insulating layer, and a protective layer disposed on the insulating layer. Here, the side surfaces of the pad include a first side surface in contact with the insulating layer and a second side surface in contact with the protective layer.

[0036] That is, the circuit board of the embodiment can be manufactured through the ETS method, and thus, at least a portion of the pads arranged on the uppermost portion of the circuit board can have a structure in which they are embedded in the upper surface of the insulating layer. At this time, the embodiment can have a step difference between the upper surface of the pad and the upper surface of the insulating layer, and further, the upper surface of the pad can be positioned higher than the upper surface of the insulating layer. Accordingly, the embodiment can have at least a portion of the pad embedded in the insulating layer, while at least the remaining portion protrudes above the insulating layer. Through this, the embodiment can make it possible to refine the width of the pad and / or the spacing between the pads, and further, form a bonding portion having a uniform height on the pad. Accordingly, the embodiment can enable a semiconductor device to be stably attached to the circuit board, and further, can enable the semiconductor device to operate stably. Through this, the embodiment can improve the operational reliability of a product such as a sub to which a semiconductor package is applied.

[0037] At this time, the first vertical length of the first side of the pad and the second vertical length of the second side are different from each other. Preferably, the ratio of the first length to the second length may be more than 1:1 and less than or equal to 1:3. Through this, the embodiment can make the interface between the insulating layer and the protective layer closer to the lower surface of the pad than the upper surface of the pad. Therefore, the embodiment can prevent the stress according to the heat cycle from being concentrated at the interface between the pad and the barrier layer, thereby stably protecting the circuit board from reliability issues such as cracks. In addition, the embodiment can maximize the effect of improving the flatness of the upper surface of the plurality of bonding portions that appears by protruding a portion of the pad above the insulating layer, thereby enabling the semiconductor element to be more stably attached to the circuit board. In addition, the embodiment can solve the mechanical reliability problem of the pad being detached from the insulating layer, thereby stably protecting the pad through the insulating layer and the protective layer.

[0038] In addition, the protective layer is provided with a through hole that vertically overlaps with the pad, and the through portions of the barrier layer and the bonding portion are provided within the through hole of the protective layer. At this time, the horizontal width of the through hole of the protective layer is smaller than the horizontal width of the pad. Therefore, the horizontal width of the barrier layer and the horizontal width of the through portion of the bonding portion are smaller than the horizontal width of the pad. Through this, the embodiment can prevent a change in the shape of the pad that occurs in the process of forming the barrier layer. For example, the barrier layer may include nickel and may be disposed on the pad through an electroless plating process. Specifically, the barrier layer may be provided on the pad by applying a displacement plating method. At this time, when displacement plating is performed, a displacement reaction may occur with the pad during the process of plating the barrier layer, and thus the upper surface and side surfaces of the pad may be worn away as the barrier layer is plated. Therefore, if the horizontal width of the penetration hole of the protective layer is greater than the width of the pad, the vertical cross-sectional shape of the pad may have a shape in which the width decreases from the top surface to the bottom surface, or the side surface of the pad may have a slope. In this case, it may be difficult to stably place the bonding portion on the pad due to the reduced area of ​​the top surface of the pad, and furthermore, there may be limitations in reducing the width and / or pitch of the bonding portion.

[0039] In contrast, the embodiment minimizes changes in the shape of the pad that occur during the process of plating the barrier layer by ensuring that at least a portion of the upper surface of the pad is covered with a protective layer. This allows the embodiment to maintain the area of ​​the upper surface of the pad, thereby ensuring that the bonding portion is stably positioned on the pad, and further reduces the width and / or pitch of the bonding portion.

[0040] In addition, the upper surface of the insulating layer and the lower surface of the protective layer include at least one of a concave surface and a convex surface corresponding to the curvature of the filler provided in the insulating layer. Through this, the embodiment can increase the contact area between the insulating layer and the protective layer, and can allow the protective layer to adhere more firmly to the insulating layer. Accordingly, the embodiment can solve the problem of the protective layer being peeled off from the insulating layer, thereby improving the mechanical reliability of the circuit board and the semiconductor package.

[0041] In addition, the upper surface of the pad of the embodiment may be provided with a concave crevice facing the lower surface of the pad. At this time, the horizontal width of the crevice may be greater than the width of the through hole of the upper protective layer. In addition, the barrier layer may include an extension portion arranged within the crevice of the pad. In addition, the extension portion of the barrier layer is greater than the width of the through hole of the bonding portion. Through this, the embodiment can have the extension portion of the barrier layer function as an anchor to firmly bond between the bonding portion and the pad, thereby further enhancing the bonding strength between the bonding portion and the pad.

[0042] Fig. 1 is a cross-sectional view showing the configuration of a circuit board according to the first embodiment.

[0043] FIG. 2 is a diagram showing the configuration of a semiconductor package of the first embodiment having the circuit board illustrated in FIG. 1.

[0044] Figure 3a is an enlarged cross-sectional view of the R1 area of ​​Figure 1.

[0045] Fig. 3b is a cross-sectional view specifically showing the shape of the interface between the insulating layer and the protective layer of Fig. 3a.

[0046] FIG. 3c is an enlarged cross-sectional view of the R1 region of FIG. 1 according to another embodiment.

[0047] Figures 4a to 4c are cross-sectional views showing examples of modifications of the bonding portion shown in Figure 1.

[0048] Fig. 5 is a cross-sectional view showing the configuration of a semiconductor package according to the second embodiment.

[0049] Figures 6a to 6h are cross-sectional views for explaining the manufacturing method of the circuit board shown in Figure 1 in process order.

[0050] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0051] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0052] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0053] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0054] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0055] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0056]

[0057] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0058] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0059] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0060] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0061] These terms are intended only to distinguish a component from other components, and are not intended to limit the nature, order, or sequence of the component. Furthermore, when a component is referred to as being "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there are no other intervening components.

[0062] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0063] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0064] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0065] Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. In addition, the semiconductor package includes a circuit board having a connection member embedded therein, a semiconductor element, and a connection portion for electrically connecting the semiconductor element and the circuit board. Here, various semiconductor elements may be mounted on the semiconductor package.

[0066] The semiconductor device may include active components and / or passive components. The active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of the above-mentioned components.

[0067] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0068] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0069] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0070]

[0071] FIG. 1 is a cross-sectional view showing a configuration of a circuit board according to a first embodiment, FIG. 2 is a diagram showing a configuration of a semiconductor package according to the first embodiment having the circuit board shown in FIG. 1, FIG. 3a is an enlarged cross-sectional view of an R1 region of FIG. 1, FIG. 3b is a cross-sectional view specifically showing the shape of an interface between an insulating layer and a protective layer of FIG. 3a, FIG. 3c is an enlarged cross-sectional view of an R1 region of FIG. 1 according to another embodiment, and FIGS. 4a to 4c are cross-sectional views showing modified examples of a bonding portion shown in FIG. 1.

[0072] Referring to FIGS. 1 and 2, a semiconductor package according to a first embodiment includes a circuit board (100) that electrically connects a main board of an electronic device and semiconductor elements (410, 420), a plurality of semiconductor elements (410, 420) mounted on the circuit board (100), and a connection portion (310, 320) that electrically connects the plurality of semiconductor elements (410, 420) and the circuit board (100).

[0073] For easy explanation of the semiconductor package of the embodiment, terms referring to components included in the semiconductor package are described, and a description of each component referred to is provided below.

[0074] Referring to FIG. 1, the circuit board (100) includes an insulating layer (110), an electrode portion (150), an upper protective layer (160), and a lower protective layer (170). The insulating layer (110) may refer to a supporting substrate of the circuit board (100) on which the electrode portion (150) is formed. The insulating layer (110) is provided in a structure in which first to fourth insulating layers (111, 112, 113, 114) are sequentially laminated. The upper surface of the insulating layer (110) is provided as the upper surface of the first insulating layer (111), and the lower surface of the insulating layer (110) is provided as the lower surface of the fourth insulating layer (114). An upper protective layer (160) is provided on the upper surface of the insulating layer (110), and a lower protective layer (170) is provided on the lower surface of the insulating layer (110). The electrode portion (150) includes a wiring electrode, a via electrode, a barrier layer (140), and a bonding portion (145). The wiring electrode includes a first wiring electrode (121) disposed on an upper surface of a first insulating layer (111), a second wiring electrode (122) disposed on a lower surface of the first insulating layer (111) or an upper surface of a second insulating layer (112), a third wiring electrode (123) disposed on a lower surface of the second insulating layer (112) or an upper surface of a third insulating layer (113), a fourth wiring electrode (124) disposed on a lower surface of the third insulating layer (113) or an upper surface of a fourth insulating layer (114), and a fifth wiring electrode (125) disposed on a lower surface of the fourth insulating layer (124). The first wiring electrode (121) includes a plurality of pads connected to the via electrode or connected to the bonding portion (145). At this time, the first wiring electrode (121) of Fig. 1 only shows the pad connected to the bonding portion (145), and accordingly, the first wiring electrode (121) can be referred to as a 'pad'.The via electrode includes a first via electrode (131) penetrating the first insulating layer (111) and connecting the first wiring electrode (121) and the second wiring electrode (122), a second via electrode (132) penetrating the second insulating layer (112) and connecting the second wiring electrode (122) and the third wiring electrode (123), a third via electrode (133) penetrating the third insulating layer (113) and connecting the third wiring electrode (123) and the fourth wiring electrode (124), and a fourth via electrode (134) penetrating the fourth insulating layer (114) and connecting the fourth wiring electrode (124) and the fifth wiring electrode (125). In addition, the electrode portion (150) includes a barrier layer (140) disposed on the first wiring electrode (pad, 121). Additionally, the electrode portion (150) includes a bonding portion (145) disposed on the barrier layer (140). The bonding portion (145) includes a protrusion (145-1) protruding onto the upper protective layer (160) and a penetration portion (145-2) penetrating the upper protective layer (160) and connected to the barrier layer (140).

[0075] Also, referring to FIG. 2, the semiconductor package may include semiconductor elements (310, 320) arranged on a circuit board (100). The semiconductor elements (310, 320) may include a first semiconductor element (310) and a second semiconductor element (320), but are not limited thereto. For example, three or more semiconductor elements may be arranged on the circuit board (100), or one semiconductor element may be arranged. Also, the semiconductor package includes a connection portion (210, 220) arranged between the semiconductor elements (310, 320) and the bonding portion (145) of the circuit board (100). The connection portion (210, 220) connects between the terminals (315, 325) of the semiconductor elements (310, 320) and the bonding portion (145) of the circuit board (100). The connection portion (210, 220) electrically connects the electrode portion of the substrate and the terminal (315, 325) of the semiconductor element (310, 320) by using at least one bonding method among wire bonding, solder bonding, and direct metal bonding. The wire bonding method means electrically connecting the electrode portion of the substrate and the terminal (315, 325) of the semiconductor element (310, 320) by using a conductor such as gold (Au). The solder bonding method electrically connects the electrode portion of the substrate and the terminal (315, 325) of the semiconductor element (310, 320) by using a material including at least one of Sn, Ag, and Cu. The direct bonding method between metals means applying heat and pressure between the electrode portion of the substrate and the terminal (315, 325) of the semiconductor element (310, 320) to recrystallize without using solder, wire, conductive adhesive, etc., thereby directly bonding the electrode portion of the substrate and the terminal (315, 325) of the semiconductor element (310, 320). In this case, the connection portion (210, 220) may mean a metal layer formed between the bonding portion (145) of the circuit board (100) and the terminal (315, 325) of the semiconductor element (310, 320) by recrystallization.For example, the connection portions (210, 220) can electrically connect the bonding portions (145) of the circuit board (100) and the terminals (315, 325) of the semiconductor elements (310, 320) by a thermal compression bonding method. The thermal compression bonding method can reduce the volume of the connection portions (210, 220) and prevent short circuits between multiple connection portions. Therefore, when the terminals (315, 325) of the semiconductor elements (310, 320) and / or the bonding portions (145) of the circuit board (100) have a fine pitch, the thermal compression bonding method can be advantageous.

[0076] Each component of the circuit board (100) is described in detail as follows.

[0077] The laminated first to fourth insulating layers (111, 112, 113, 114) of the circuit board (100) may be formed of an insulating material having ease of process, excellent insulating properties, the ability to reduce loss of signals transmitted through the electrode portion (150), or the ability to create a fine gap between the electrode portions (150). In addition, the first to fourth insulating layers (111, 112, 113, 114) may all be formed of the same insulating material, but are not limited thereto, and at least one layer may be formed of an insulating material different from the other insulating layers. For example, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and FR-4, BT (Bismaleimide Triazine), and PID (Photo Image-able Dielectric resin) can also be used.

[0078] In addition, at least one of the first to fourth insulating layers (111, 112, 113, 114) may include a reinforcing member (110F) including at least one of glass fiber and GCP (Glass Core Primer). The reinforcing member (110F) may improve the rigidity of the insulating layer (110), thereby preventing the circuit board (100) and / or the semiconductor package from being bent in a specific direction. If the insulating layer (110) is bent in a specific direction during the process of forming the circuit board (100), the accuracy of the position may decrease during the process of arranging the electrode portion (150), but this problem can be solved as the rigidity of the circuit board (100) is improved. In addition, even when mounting a semiconductor element (410, 420) on a circuit board (100), it is possible to prevent problems such as electrical short circuits or open circuits of the semiconductor element (410, 420) occurring due to warpage of the circuit board (100). In addition, it is possible to prevent warpage problems caused by heat cycles occurring during operation of the semiconductor package, and thereby, products such as servers to which the semiconductor package of the embodiment is applied can operate stably, thereby improving the overall reliability of the product.

[0079] At least one of the first to fourth insulating layers (111, 112, 113, 114) may include a filler (110F) composed of an inorganic material. The diameter and content of the filler (110F) may be adjusted in consideration of the coefficient of thermal expansion, rigidity, etc. of the insulating layer (110), and to solve problems such as light scattering during a laser process for densely arranging the electrode portions (150). For example, in order to solve the above-described problems, the diameter of the filler (110F) may be applied to 0.1 ㎛ to 5.0 ㎛, and the content may be applied to 30 wt% to 40 wt% or 78 wt% to 85 wt%, but is not limited thereto.

[0080] The first to fifth wiring electrodes (121, 122, 123, 124, 125) can be designed in various shapes in consideration of the impedance for transmitting signals and power between the plurality of semiconductor elements (310, 320) and the main board of the electronic device and the warpage of the circuit board (100). The first to fifth wiring electrodes (121, 122, 123, 124, 125) can be arranged with a high density in consideration of the signals and impedance, and can be arranged with a width and interval of 2 μm to 10 μm, respectively, in order to secure adhesion with the insulating layer (110) and prevent the problem of peeling. That is, the first to fifth wiring electrodes (121, 122, 123, 124, 125) can be arranged to have various widths and intervals, from a design in which the width is 2 μm and the interval is 2 μm, to a design in which the width is 10 μm and the interval is 10 μm. However, in the embodiment, the width and interval of each wiring electrode can be applied differently in consideration of the position and function of each wiring electrode. In this case, such width and interval may mean the width and interval of the trace of the first to fifth wiring electrodes (121, 122, 123, 124, 125).

[0081] In addition, among the first to fifth wiring electrodes (121, 122, 123, 124, 125), the wiring electrode (125) provided adjacent to the main board of the electronic device can exchange signals with a semiconductor package substrate having a relatively large width and / or spacing. In addition, among the first to fifth wiring electrodes (121, 122, 123, 124, 125), the wiring electrode provided adjacent to a plurality of semiconductor elements (310, 320) can exchange signals with the semiconductor elements (310, 320) having a relatively small width and / or spacing. Accordingly, the first to fifth wiring electrodes (121, 122, 123, 124, 125) can have different widths and / or spacings. For example, the first wiring electrode (121) positioned closer to the semiconductor element (310, 320) may have a relatively small width and / or spacing. Additionally, the fifth wiring electrode (125) positioned closer to the semiconductor package substrate may have a relatively large width and / or spacing. Preferably, the embodiment may allow the width and / or spacing of the wiring electrodes to increase in a vertical direction from the upper surface to the lower surface of the insulating layer (110). For example, the wiring electrode positioned on the upper surface of the insulating layer (110) may have the smallest width and / or spacing, and the wiring electrode on the lower surface of the insulating layer (110) may have the largest width and / or spacing. Through this, the embodiment can arrange the first to fifth wiring electrodes (121, 122, 123, 124, 125) so that their widths and / or spacings gradually increase along the direction from the upper surface to the lower surface of the insulating layer (110), thereby enabling more efficient electrical connection between the semiconductor elements (310, 320) and the semiconductor package substrate. Accordingly, the embodiment can minimize signal transmission loss, and thus provide a semiconductor package with excellent communication characteristics.Through this, the embodiment can enable the semiconductor device to operate more stably, and through this, the semiconductor package can operate more stably.

[0082] At this time, the width and spacing of the first to fifth wiring electrodes (121, 122, 123, 124, 125) described above are too fine to arrange the first to fourth via electrodes (131, 132, 133, 134) for vertically connecting the first to fifth wiring electrodes (121, 122, 123, 124, 125), respectively, and the width of the first to fifth wiring electrodes (121, 122, 123, 124, 125) described above is too narrow to secure the positional alignment of the first to fourth via electrodes (131, 132, 133, 134) or to form the first to fourth via electrodes (131, 132, 133, 134). Therefore, here, vertical means the direction in which the first and second insulating layers (121, 122) are laminated, and vertical and vertical direction can be used interchangeably. In addition, the same definition applies to the vertical relationship of the components described later. Therefore, in order to secure the positional alignment of the first to fourth via electrodes (131, 132, 133, 134) and to place the first to fourth via electrodes (131, 132, 133, 134), the pads of the first to fifth wiring electrodes (121, 122, 123, 124, 125) are included, respectively. Here, each pad of the first to fifth wiring electrodes (121, 122, 123, 124, 125) means a wiring electrode that directly contacts the first to fourth via electrodes (131, 132, 133, 134) in each wiring electrode. And, each pad of the first to fifth wiring electrodes (121, 122, 123, 124, 125) has a width wider than the width of the trace of the first to fifth wiring electrodes (121, 122, 123, 124, 125) described above in order to be connected to the first to fourth via electrodes (131, 132, 133, 134). For example, each pad of the first to fifth wiring electrodes (121, 122, 123, 124, 125) may have a circular structure, and its diameter may be within 30 ㎛ to 100 ㎛.

[0083] At this time, the pad (121) corresponding to the first wiring electrode (121) is the wiring electrode arranged at the uppermost side among the wiring electrodes of the electrode part (150). At this time, at least a portion of the pad (121) is embedded in the upper surface of the insulating layer (110). For example, a recess (110R) is provided in the upper surface of the insulating layer (110), and the pad (121) may be arranged in the recess (110R) provided in the upper surface of the insulating layer (110). Through this, since the embodiment has a structure in which at least a portion of the pad (121) is embedded in the upper surface of the insulating layer (110), miniaturization of the pad (121) is possible, and accordingly, miniaturization of the bonding portion (145) arranged thereon may be possible.

[0084] In addition, the upper surface of the pad (121) may have a step difference from the upper surface of the insulating layer (110). For example, the upper surface of the pad (121) may be positioned higher than the upper surface of the insulating layer (110). That is, the pad (121) may be provided to protrude higher than the upper surface of the insulating layer (110). Through this, in practice, the bonding portion (145) can be more stably placed on the pad (121), and further, the semiconductor element can be more stably placed on the bonding portion (145).

[0085] Accordingly, the side surfaces of the pad (121) may be covered with different insulating materials. For example, a portion of the side surface of the pad (121) may be covered with an insulating layer (110). Additionally, the remaining portion of the side surface of the pad (121) may be covered with an upper protective layer (160). In this case, the embodiment controls the length of the portion of the side surface of the pad (121) covered with the insulating layer (110) and the portion covered with the upper protective layer (160), thereby forming a bonding portion (145) having a uniform thickness on the upper surfaces of the plurality of pads, while solving the problem of the plurality of pads being detached from the insulating layer (110). This will be described in more detail below.

[0086] A barrier layer (140) is disposed on the pad (121). The barrier layer (140) includes a different metal material from the pad (121). For example, the barrier layer (140) may include nickel. In addition, when the barrier layer (140) includes nickel, the adhesion between the bonding portion (145) and the pad (121) can be improved, and further, the diffusion of an intermetallic compound formed by the bonding of a connecting portion, such as solder, and the bonding portion (145) can be prevented. For example, the intermetallic compound has a problem of poor mechanical and electrical reliability. In particular, when the bonding portion (145) includes copper, mechanical reliability problems, such as cracking problems and / or deterioration of electrical characteristics caused by the intermetallic compound, and / or electrical reliability problems may be further aggravated. At this time, when the barrier layer (140) contains nickel, it is possible to prevent the intermetallic compound from penetrating into the interface between the pad (121) and the upper insulating layer (160), thereby solving the problem of peeling that occurs due to the decrease in the bonding strength therebetween. In addition, when the bonding portion (145) is directly disposed on the pad (121), oxidation of the pad (121) may occur during the manufacturing process of the circuit board (100), which may cause the bonding strength between the pad (121) and the bonding portion (145) to decrease. Therefore, the embodiment arranges the barrier layer (140) between the pad (121) and the bonding portion (145) to prevent oxidation of the pad (121) while improving the bonding strength between the pad (121) and the bonding portion (145). In addition, the circuit board (100) may be subject to stress due to expansion and / or contraction according to the heat cycle, which may be concentrated at the interface between the pad (121) and the bonding portion (145). At this time, when a barrier layer (140) is disposed between the pad (121) and the bonding portion (145), the bonding strength between them can be improved, thereby preventing cracks due to stress, and further improving the electrical and mechanical reliability of the semiconductor package.

[0087] In addition, the electrode portion (150) includes a bonding portion (145). The bonding portion (145) is disposed on the upper protective layer (160). For example, the bonding portion (145) may be a bonding area where a connection portion (210, 220) for electrically connecting a circuit board (100) and terminals (315, 325) of semiconductor elements (310, 320) are disposed. The bonding portion (145) has a protrusion (145-1) disposed on the upper protective layer (160) and a penetration portion (145-2) penetrating the upper protective layer (160). The penetration portion (145-2) of the bonding portion (145) is connected to the barrier layer (140). The bonding portion (145) has a protrusion (145-1) protruding on the upper protective layer (160), and based on this, thermal compression bonding is used to reduce the volume of the connecting portion (210, 220) such as solder while preventing short circuits between multiple bonding portions (145).

[0088] An upper protective layer (160) is disposed on the upper surface of the insulating layer (120), and a lower protective layer (170) is disposed on the lower surface of the insulating layer (120). The upper protective layer (160) and the lower protective layer (170) can have the function of protecting the pad from external moisture or contaminants, and can be provided with a photosensitive material and / or solder resist to prevent a short circuit problem between the connection parts (210, 220) when bonding between the semiconductor element and the circuit board (100) and / or the main board and the circuit board (100). In addition, the upper protective layer (160) and the lower protective layer (170) can be, for example, applied with a photosensitive solder resist. According to the present embodiment, a plurality of terminals for connecting to a circuit board (100) such as a semiconductor element (310, 320) and / or a main board of an electronic device can be arranged at a high density, and when a plurality of terminals and a bonding portion (145) of the circuit board (100) are joined, solder can be used. When solder is used, a solder short-circuit problem may occur between terminals having a high density. In order to solve this short-circuit problem, a solder resist having poor wettability with the solder is arranged to prevent diffusion or movement of the solder, thereby preventing the solder short-circuit problem between the terminals. The upper protective layer (160) and the lower protective layer (170) can be arranged with different thicknesses in consideration of the warpage or coefficient of thermal expansion of the circuit board (100).

[0089] The upper protective layer (160) is provided to surround at least a portion of the side surface of the pad (121). In addition, the upper protective layer (160) is provided to cover at least a portion of the upper surface of the pad (121). Specifically, the upper surface of the upper protective layer (160) is positioned higher than the upper surface of the pad (121). In addition, the lower surface of the upper protective layer (160) is positioned lower than the upper surface of the pad (121) and higher than the lower surface of the pad (121). That is, the interface between the lower surface of the upper protective layer (160) and the upper surface of the insulating layer (110) is positioned between the upper and lower surfaces of the pad (121).

[0090] Specifically, referring to FIG. 3A, a pad (121) is arranged in a recess (110R) provided on the upper surface of the insulating layer (110). At this time, the vertical depth of the recess (110R) may be smaller than the vertical thickness of the pad (121). Accordingly, at least a portion of the pad (121) is arranged within the recess (110R) of the insulating layer (110), and the remaining portion of the pad (121) protrudes above the insulating layer (110).

[0091] Additionally, an upper protective layer (160) is placed on the insulating layer (110). At this time, the upper protective layer (160) is placed to cover a portion of the side of the pad (121) that is not covered by the insulating layer (110).

[0092] That is, the pad (121) includes an upper surface (121T) and a lower surface (121B). In addition, the pad (121) includes a side surface (121S) connecting the upper surface (121T) and the lower surface (121B). At this time, the side surface (121S) of the pad (121) includes a first side surface (121S1) in contact with the insulating layer (110) and a second side surface (121S2) in contact with the upper protective layer (160).

[0093] The first side surface (121S1) of the pad (121) is closer to the lower surface (121B) of the pad (121) and extends from the lower surface (121B) of the pad (121) toward the upper surface (121T). In addition, the second side surface (121S2) of the pad (121) is closer to the upper surface (121T) of the pad (121) and extends from the upper surface (121T) of the pad (121) toward the lower surface (121B) of the pad (121). At this time, the first side surface (121S1) and the second side surface (121S2) of the pad (121) are directly connected to each other. Here, being directly connected does not mean that the first side (121S1) and the second side (121S2) are different sides of the pad (121) (e.g., the left side and the right side), but rather that one side is divided into a plurality of parts along the vertical direction.

[0094] At this time, the first side (121S1) of the pad (121) has a first vertical length (L1). In addition, the second side (121S2) of the pad (121) has a second vertical length (L2). At this time, the first length (L1) and the second length (L2) may be different from each other.

[0095] That is, the embodiment improves the flatness of the upper surface of the plurality of pads (121) by controlling the first length (L1) and the second length (L2) so that the bonding portion (145) having a uniform height is arranged on the plurality of pads (121) without causing mechanical reliability problems in which the pads (121) are detached from the insulating layer (110).

[0096] At this time, the first length (L1) may be smaller than the second length (L2). For example, the vertical length of the first side (121S) that contacts the insulating layer (110) on the side (121S) of the pad (121) may be smaller than the vertical length of the second side (121S2) that contacts the upper protective layer (160). This is to prevent cracks from occurring at the contact interface between the pad (121) and the barrier layer (140) due to stress acting on the circuit board (100).

[0097] For example, the coefficient of thermal expansion of the upper protective layer (160) may be greater than that of the insulating layer (110), and the upper protective layer (160) may shrink or expand more than the insulating layer (110) when expanding and / or shrinking according to the heat cycle. At this time, when stress occurs in the upper protective layer (160) due to expansion and / or shrinking according to the heat cycle, this may act in a horizontal direction toward the interface between the upper protective layer (160) and the insulating layer (110). At this time, if the interface between the protective layer (160) and the insulating layer (110) is adjacent to the upper surface (121T) of the pad (121), stress may be concentrated at the interface between the pad (121) and the barrier layer (140), and thus cracks may occur at the interface between the pad (121) and the barrier layer (140), and / or the interface between the barrier layer (140) and the bonding portion (145). Therefore, the embodiment makes it possible to improve mechanical reliability problems such as cracks by making the first length (L1) smaller than the second length (L2), and based on this, making it possible to allow the stress to act in a horizontal direction closer to the lower surface (121B) than the upper surface (121T) of the pad (121).

[0098] At this time, the ratio of the first length (L1) and the second length (L2) may be more than 1:1 and less than or equal to 1:3. When the ratio of the first length (L1) and the second length (L2) is less than or equal to 1:1, the stress according to the heat cycle may be concentrated at the interface between the pad (121) and the barrier layer (140), which may cause cracks to occur. Alternatively, when the ratio of the first length (L1) and the second length (L2) is less than or equal to 1:1, the protrusion height of the pad (121) from the insulating layer (110) may be insufficient, and thus, the flattening improvement effect of the plurality of bonding portions (145) that appears by protruding a portion of the pad (121) above the insulating layer (110) may be insufficient. In addition, when the ratio of the first length (L1) and the second length (L2) exceeds 1:3, the area of ​​the pad (121) covered with the insulating layer (110) decreases, and thus, a problem of the pad (121) being detached from the insulating layer (110) may occur during the process of manufacturing the circuit board (100).

[0099] In addition, the upper protective layer (160) is provided with a through hole that vertically overlaps the pad (121), and the through part (145-2) of the barrier layer (140) and the bonding part (145) is provided within the through hole of the upper protective layer (160).

[0100] At this time, the horizontal width of the through hole of the upper protective layer (160) is smaller than the horizontal width of the pad (121). Therefore, the horizontal width of the barrier layer (140) and the horizontal width of the through portion (145-2) of the bonding portion (145) are smaller than the horizontal width of the pad (121). Through this, the embodiment can prevent a change in the shape of the pad (121) that occurs in the process of forming the barrier layer (140). Therefore, the slope of the side surface (121S) of the pad (121) of the embodiment can be closer to a right angle than the slope of the side surface of the first via electrode (131).

[0101] For example, the barrier layer (140) may include nickel and may be disposed on the pad (121) through an electroless plating process. Specifically, the barrier layer (140) may be provided on the pad (121) by applying a displacement plating method. At this time, when displacement plating is performed, a displacement reaction may occur with the pad (121) during the process of plating the barrier layer (140), and accordingly, the upper and side surfaces of the pad (121) may be etched while the barrier layer (140) is plated. Accordingly, when the horizontal width of the through hole of the upper protective layer (160) is greater than the width of the pad (121), the vertical cross-sectional shape of the pad (121) may have a shape in which the width decreases from the upper surface to the lower surface, or the side surface of the pad (121) may have a slope. In this case, it may be difficult to stably place the bonding portion (145) on the pad (121) due to a decrease in the area of ​​the upper surface of the pad (121), and further, there may be a limit to reducing the width and / or pitch of the bonding portion (145).

[0102] In contrast, the embodiment minimizes the shape change of the pad (121) that occurs in the process of plating the barrier layer (140) by ensuring that at least a portion of the upper surface of the pad (121) is covered with an upper protective layer (160). Through this, the embodiment can maintain the area of ​​the upper surface of the pad (121), thereby ensuring that the bonding portion is stably positioned on the pad (121), and further, can reduce the width and / or pitch of the bonding portion (145).

[0103] In addition, although not shown in the drawing, the through hole of the upper protective layer (160) may be formed through a laser process. Accordingly, the through hole provided in the upper protective layer (160) may include a curved portion whose width becomes narrower at a portion adjacent to the pad (121). For example, the through hole of the upper protective layer (160) may be formed using a laser beam having a Gaussian distribution, and thus may have a shape corresponding to the laser beam having a Gaussian distribution. That is, the through hole of the upper protective layer (160) may include a first portion that is provided adjacent to the upper surface of the upper protective layer (160) and whose width has little change toward the lower surface of the upper protective layer (160), and a second portion that is provided adjacent to the lower surface of the upper protective layer (160) below the first portion and corresponds to a curved portion whose width becomes narrower toward the lower surface of the upper protective layer (160). Accordingly, the through-hole (145-2) of the bonding portion (145) may include a curved portion that is arranged within the second portion of the through-hole of the upper protective layer (160) and has a narrow width. Therefore, the embodiment may form the through-hole of the upper protective layer (160) through a laser process, thereby reducing the width of the through-hole and the pitch between the plurality of through-holes provided in the upper protective layer (160). For example, the width and pitch of the through-hole that may be formed through an exposure and development process may exceed 40 um. Alternatively, the embodiment may form the through-hole in the upper protective layer (160) through a laser process, thereby reducing the width and pitch of the through-hole to 30 um or less, 25 um or less, or even 20 um or less. In addition, the penetration portion (145-2) of the bonding portion (145) may include a curved portion with a width that is rapidly narrowed by a laser beam of Gaussian distribution in an area adjacent to the pad (121).

[0104] In addition, referring to FIG. 3b, the upper surface of the insulating layer (110) may be provided with concave and convex portions. Correspondingly, the lower surface of the upper protective layer (160) may be provided with convex and concave portions. This may be to ensure that the first side surface (121S1) of the pad (121) is covered with the insulating layer (110), and the second side surface (121S2) of the pad (121) is covered with the upper protective layer (160).

[0105] That is, the embodiment forms a pad (121) of a circuit board (100) by applying the ETS method. At this time, when the ETS method is applied, the height of the upper surface of the pad (121) is lower than or equal to the height of the upper surface of the insulating layer (110). In this case, since the pad (121) does not protrude above the insulating layer (110), the difficulty of the process of forming the bonding portion (145) on the pad (121) may increase, and accordingly, a height deviation of a plurality of bonding portions (145) may occur due to a process error in the process of plating the bonding portion (145). In contrast, the embodiment minimizes the height deviation of the bonding portion (145) by making the pad (121) protrude above the insulating layer (110) by a thickness corresponding to the second length (L2) of the second side surface (121S2) of the pad (121). Furthermore, the SAP method can be applied so that the pad (121) protrudes entirely over the insulating layer (110), but when the pad (121) is formed using the SAP method, there is a limit to miniaturization of the width and / or spacing of the pad (121), and accordingly, there is a limit to miniaturizing the circuit board (100).

[0106] Accordingly, in the embodiment, during the process of manufacturing a circuit board (100), a process of removing a portion of the upper surface of an insulating layer (110) is performed, thereby making the upper surface of the insulating layer (110) positioned lower than the upper surface of a pad (121).

[0107] At this time, a filler (110F) is provided on the insulating layer (110). In addition, in the process of removing a portion of the upper surface of the insulating layer (110), the filler (110F) may be exposed on the insulating layer (110) or may be removed from the insulating layer (110). In addition, when the process of removing a portion of the upper surface of the insulating layer (110) is performed, the upper surface of the insulating layer (110) may be removed convexly along the curvature of the filler (110F) provided therein.

[0108] Accordingly, at least a portion (110F1) of the filler (110F) provided in the insulating layer (110) can protrude above the insulating layer (110), and accordingly, the protruding filler (110F1) can be covered with the upper protective layer (160).

[0109] In addition, the upper surface of the insulating layer (110) may be provided with a concave surface (IS1) corresponding to the position where the filler (110F) has escaped (i.e., the removed position), and the lower surface of the upper protective layer (160) may be provided with a convex surface corresponding to the concave surface (IS1).

[0110] In addition, a convex surface (IS2) may be provided on the upper surface of the insulating layer (110) along the curvature of the filler (110F), and accordingly, a concave surface corresponding to the convex surface (IS2) may be provided on the lower surface of the upper protective layer (160).

[0111] Accordingly, the embodiment provides a convex surface and a concave surface at the interface between the upper surface of the insulating layer (110) and the lower surface of the upper protective layer (160), thereby increasing the contact area between the insulating layer (110) and the upper protective layer (160). Accordingly, the embodiment can solve the problem of the upper protective layer (160) being peeled off from the insulating layer (110), thereby improving the mechanical reliability of the circuit board and the semiconductor package.

[0112] In addition, referring to FIG. 3C, the upper surface of the pad (121) of the embodiment may be provided with a concave crevice (121C) facing the lower surface of the pad (121). At this time, the horizontal width of the crevice (121C) may be larger than the width of the through hole of the upper protective layer (160). In addition, the barrier layer (1140) may include an extension portion (1140C) arranged within the crevice (121C) of the pad (121). In addition, the extension portion (1140C) of the barrier layer (1140) is larger than the width of the through portion (145-2) of the bonding portion (145). Through this, the embodiment can enable the extension portion (1140C) of the barrier layer (1140) to function as an anchor to firmly connect the bonding portion (145) and the pad (121), thereby further improving the bonding strength between the bonding portion (145) and the pad (121).

[0113] At this time, the clevis (121C) provided on the upper surface of the pad (121) may have a third vertical length (L3). The third length (L3) may refer to the vertical length from the upper surface of the pad (121) to the lowermost end of the clevis (121C). In addition, the third length (L2) may satisfy a range of 5% to 15% of the length from the upper surface to the lower surface of the pad (121). If the third length (L3) is less than 5% of the length of the pad (121), the anchoring effect through the extension portion (1140C) of the barrier layer (1140) may be insufficient. In addition, if the third length (L3) exceeds 15% of the length of the pad (121), the flatness of the upper surface of the barrier layer (1140) may be reduced, and further, the flatness of the bonding portion (145) may be reduced.

[0114] Meanwhile, referring to FIG. 4A, the bonding portion (1450) of the embodiment may only have a penetration portion that penetrates the upper protective layer (160). For example, the bonding portion (1450) may not protrude above the upper protective layer (160). This may be achieved by changing the material constituting the bonding portion (1450). For example, the bonding portion (145) illustrated in FIGS. 1 to 3C may be formed of a metal material including copper. In contrast, the bonding portion (1450) of FIG. 4A may include tin. That is, the embodiment may form the bonding portion (1450) by plating tin on the barrier layer (1140). Through this, the embodiment may enable the semiconductor element to be more stably mounted on the bonding portion (1450). In addition, the embodiment can perform a process (e.g., coin process) to flatten the bonding portion (1450) after it is formed, thereby allowing the upper surface of the bonding portion (1450) to be positioned on the same plane as the upper surface of the upper protective layer (160).

[0115] Also, referring to FIG. 4B, the bonding portion (2450) of the embodiment may include a tin. At this time, unlike FIG. 4A, FIG. 4B may perform a coin process so that the bonding portion (2450) has a height higher than the upper protective layer (160), and through this, the bonding portion (2450) includes a penetration portion (2451) penetrating the upper protective layer (160) and a protrusion (2452) disposed on the penetration portion (2451) and protruding above the upper protective layer (160). At this time, the protrusion (2452) may have a slope whose width gradually decreases from the upper surface to the lower surface. Through this, the embodiment can enable the semiconductor element to be more stably mounted on the protrusion (2452), and since the protrusion (2452) has a slope whose width decreases, it can solve the problem of an electrical short circuit in which a plurality of adjacent protrusions are connected to each other.

[0116] Also, referring to FIG. 4C, the bonding portion (3450) of the embodiment may include a comment. At this time, unlike FIGS. 4A and 4B, FIG. 4C may not perform a coin process after forming the bonding portion (3450). Accordingly, the bonding portion (3450) includes a penetration portion (3451) penetrating the upper protective layer (160) and a protrusion (3452) positioned on the penetration portion (3451) and protruding onto the upper protective layer (160). At this time, the upper surface of the protrusion portion (2452) may have a convex curved surface.

[0117]

[0118] Fig. 5 is a cross-sectional view showing the configuration of a semiconductor package according to the second embodiment.

[0119] Hereinafter, referring to FIG. 5, a semiconductor package of the second embodiment will be described in detail. Regardless of the drawing reference numerals, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0120] The circuit board includes a connecting member (400) embedded in an insulating layer (110). The connecting member (400) partially overlaps with semiconductor elements (310, 320) arranged on the circuit board (100) in a vertical direction. In addition, the connecting member (400) electrically connects a portion of a terminal (315) of a first semiconductor element (310) and a portion of a terminal (325) of a second semiconductor element (320). The connecting member (400) may be formed of the same material as the semiconductor element, such as silicon, or may be formed of an organic material, such as a photosensitive resin or a thermosetting resin.

[0121] A plurality of semiconductor devices having different functions, such as a CPU and GPU, a GPU and HBM, or a chiplet unit separated according to function and / or pitch, may be mounted on a circuit board, and a connecting member (400) may function to horizontally electrically connect them.

[0122] At this time, the electrode portions of the circuit board can be broadly divided into three groups. For example, among the electrode portions of the circuit board, the electrode portions arranged on the connecting member (400) can be divided into three groups.

[0123] The electrode portion includes a first group of electrode portions (151) that vertically overlap with a connecting member (400). At this time, the first group of electrode portions includes a pad, a barrier layer, and a bonding portion that vertically overlap with the connecting member (400). The electrode portion includes a second group of electrode portions (152) that vertically overlap with a first semiconductor element without vertically overlapping with the connecting member (400). At this time, the second group of electrode portions (152) includes a pad, a barrier layer, and a bonding portion. The electrode portion includes a third group of electrode portions (153) that vertically overlap with a second semiconductor element without vertically overlapping with the connecting member (400). At this time, the third group of electrode portions (153) includes a pad, a barrier layer, and a bonding portion.

[0124] In addition, the circuit board is disposed within the insulating layer (110) and further includes an adhesive member (420) connecting the pad (121) and the connecting member (400). Specifically, the connecting member (400) is provided with a connecting electrode (410) on its upper surface. In addition, the adhesive member (420) may be provided between the lower surface of the pad of the first group of electrode portions (151) and the upper surface of the connecting electrode (410) of the connecting member (400).

[0125]

[0126] Figures 6a to 6h are cross-sectional views for explaining the manufacturing method of the circuit board shown in Figure 1 in process order.

[0127] Referring to FIG. 6A, an embodiment can prepare an insulating member that serves as a basis for manufacturing a circuit board. The insulating member may be a carrier board. For example, the insulating member may include a carrier insulating layer (CB1) and a carrier metal layer (CB2).

[0128] The carrier metal layer (CB2) is a seed layer used for electroplating the pad (121) of the embodiment. At this time, the embodiment configures the carrier metal layer (CB2) with a metal material that does not cause etching loss of the pad (121) in a process of removing the carrier metal layer (CB2) by etching after manufacturing the circuit board (100). Preferably, the carrier metal layer (CB2) may include a metal material different from the metal material composing the pad (121). For example, the carrier metal layer (CB2) may include nickel, but is not limited thereto.

[0129] Next, referring to FIG. 6B, the embodiment may proceed with a process of forming a first wiring electrode (121) under a carrier metal layer (CB2). For example, the embodiment may proceed with a process of forming a first wiring electrode (121) by laminating a dry film having an opening under the carrier metal layer (CB2) and performing electrolytic plating within the opening of the dry film. The first wiring electrode (121) may refer to a pad (121).

[0130] Next, referring to FIG. 6c, the embodiment may perform a process of laminating a first insulating layer (111) under a carrier metal layer (CB2). For example, the embodiment may perform a process of forming a first insulating layer (111) covering the first wiring electrode (121) under the carrier metal layer (CB2). Thereafter, the embodiment may perform a process of forming a first via electrode (131) penetrating the first insulating layer (111) and a second wiring electrode (122) disposed on a lower surface of the first insulating layer (111).

[0131] Next, referring to FIG. 6d, the embodiment can proceed with a process of manufacturing a multilayer circuit board by repeating the process of FIG. 6c.

[0132] Next, referring to FIG. 6e, the embodiment can proceed with a process of separating and removing the carrier insulating layer (CB1).

[0133] Next, referring to FIG. 6F, the embodiment can perform a process of removing the carrier metal layer (CB2) by etching. At this time, the carrier metal layer (CB2) includes a different metal material from the pad (121), and thus, the pad (121) is not removed when the carrier metal layer (CB2) is etched. Accordingly, the upper surface of the pad (121) and the upper surface of the first insulating layer (111) can remain arranged on the same plane.

[0134] Next, referring to FIG. 6g, the embodiment may perform a process of removing a portion of an upper region of the first insulating layer (111), thereby allowing the upper surface of the first insulating layer (111) to be positioned lower than the upper surface of the pad (121). For example, the embodiment may perform plasma etching, thereby performing a process of thinning the thickness of the first insulating layer (111). At this time, the embodiment may perform etching so that the ratio of the vertical length of the side surface of the pad (121) exposed through the etching of the first insulating layer (111) and the vertical length of the side surface of the pad (121) covered with the first insulating layer (111) satisfies a preset range. That is, the embodiment has a ratio of the vertical length of the side of the pad (121) covered with the first insulating layer (111) and the vertical length of the side of the pad (121) exposed by etching of the first insulating layer (111) in a range of more than 1:1 and less than or equal to 1:3.

[0135] Next, referring to FIG. 6h, the embodiment may perform a process of laminating an upper protective layer (160) covering a pad (121) on a first insulating layer (111). In addition, the embodiment may form a through hole in the upper protective layer (160) that overlaps the upper surface of the pad (121) in a vertical direction. At this time, the width of the through hole provided in the upper protective layer (160) is smaller than the width of the pad (121), and thus, at least a portion of the upper surface of the pad (121) may be covered with the upper protective layer (160).

[0136] Thereafter, the embodiment may proceed with a process of forming a barrier layer (140) within the through hole of the upper protective layer (160). In addition, the embodiment may proceed with a process of forming a bonding portion (145) having a through portion positioned on the barrier layer (1140) within the through hole of the upper protective layer (160) and a protrusion protruding onto the upper protective layer (160).

[0137]

[0138] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0139] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0140] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0141] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. An insulating layer having a recess on the upper surface; a pad disposed within the recess of the insulating layer; and A protective layer disposed on the insulating layer, The side of the pad includes a first side in contact with the insulating layer and a second side in contact with the protective layer, A circuit board, wherein the first vertical length of the first side and the second vertical length of the second side are different from each other.

2. In paragraph 1, A circuit board, wherein the ratio of the first length and the second length is greater than 1:1 and less than or equal to 1:

3.

3. In paragraph 1, A circuit board having a through hole, wherein the protective layer is vertically overlapped with the pad.

4. In paragraph 3, A circuit board wherein the horizontal width of the above through hole is smaller than the horizontal width of the above pad.

5. In paragraph 3, A circuit board further comprising a bonding portion positioned within a through hole of the protective layer.

6. In paragraph 5, A circuit board, wherein the bonding portion includes a through portion arranged within the through hole and a protrusion arranged on the through portion and protruding onto the protective layer.

7. In paragraph 5, A circuit board, wherein the bonding portion comprises a metal material of one of copper and tin.

8. In paragraph 5, A circuit board further comprising a barrier layer provided within the through hole of the protective layer and positioned between the pad and the bonding portion.

9. In paragraph 8, A circuit board wherein the barrier layer and the pad include different metal materials.

10. In paragraph 9, The above pad contains copper, A circuit board, wherein the barrier layer comprises nickel.

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