Distributed self-powered system-on-chip for system-in-fiber

Abstract

A fully autonomous self-powered system-on-chip (SoC) that can be distributed along a fiber strand, capable of simultaneously harvesting energy, cooperatively scaling performance, sharing power, and booting-up with other SoCs in-fiber. In some examples, a system includes at least one textile fiber comprising an embedded electrical bus. The system includes a number of SoCs electrically coupled by the embedded electrical bus. Each SoC comprises at least one processor and an energy harvesting and power management unit (EHPMU) configured for power sharing and cooperative dynamic voltage and frequency scaling (DVFS) with the other SoCs.

Description

[0001] DISTRIBUTED SELF-POWERED SYSTEM-ON-CHIP FOR SYSTEM-IN-

[0002] FIBER

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] This application claims benefit of U.S. Provisional Application Serial No. 63 / 446,563, filed on February 17, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0005] GOVERNMENT INTEREST

[0006] This invention was made with government support under FA8702-15- D-0001 awarded by the U.S. Air Force. The government has certain rights in the invention.

[0007] TECHNICAL FIELD

[0008] This specification relates generally to system-on-chips (SoCs) and in particular to SoCs for system-in-fiber.

[0009] BACKGROUND

[0010] A System-on-Chip (SoC) is an integrated circuit that integrates all the components of a computer or other electronic system onto a single chip. It combines all the necessary components, such as the central processing unit (CPU), memory, input / output interfaces, and other peripherals, into a single compact package. SoCs are commonly used in small, portable devices like smartphones and tablets, as well as in home appliances, automotive systems, and embedded systems. One advantage of using an SoC is that it helps to reduce the size and complexity of electronic systems while improving their performance and power efficiency.

[0011] SUMMARY

[0012] This document describes a fully autonomous self-powered system-on- chip (SoC) that can be distributed along a fiber strand, capable of simultaneously harvesting energy, cooperatively scaling performance, sharing power, and booting-up with other SoCs in-fiber. In some examples, a system includes at least one textile fiber comprising an embedded electrical bus. The system includes a number of SoCs electrically coupled by the embedded electrical bus. Each SoC comprises at least one processor and an energy harvesting and power management unit (EHPMU) configured for power sharing and cooperative dynamic voltage and frequency scaling (DVFS) with the other SoCs.

[0013] The computer systems described in this specification may be implemented in hardware, software, firmware, or any combination thereof. In some examples, the computer systems may be implemented using a computer readable medium having stored thereon computer executable instructions that when executed by the processor of a computer control the computer to perform steps. Examples of suitable computer readable media include non-transitory computer readable media, such as disk memory devices, chip memory devices, programmable logic devices, and application specific integrated circuits. In addition, a computer readable medium that implements the subject matter described herein may be located on a single device or computing platform or may be distributed across multiple devices or computing platforms.

[0014] BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A is a block diagram of an example system for distributed self- powered SoCs for system-in-fiber.

[0016] Figure 1 B shows the proposed NanoSiF with distributed cooperative energy harvesting, power sharing, and ripple boot-up.

[0017] Figures 1 C, 1 D, and 1 E illustrate the principle of the power sharing and cooperative DVFS.

[0018] Figure 2A shows the architecture of the proposed nanowatt system-in- fiber (NanoSiF) and the SoC

[0019] Figure 2B illustrates the power sharing control scheme.

[0020] Figure 2C shows the flow chart for the cooperative DVFS.

[0021] Figures 3A - 3G show the architecture and block diagram of the proposed EHPMU.

[0022] Figure 4A shows a benchtop testing setup. Figure 4B shows the measured waveform.

[0023] Figure 4C shows the measured ripple boot-up waveform.

[0024] Figure 4D shows the measured cooperative DVFS waveform.

[0025] Figures 5A and 5B show the measured efficiency for the EHPMU across VPV and POUT.

[0026] Figure 5C shows the minimal VPV for SoC to cold start and stay alive across 11 dies.

[0027] Figure 5D shows the system power breakdown for the full chip measured at its poorest harvesting point.

[0028] Figure 6 shows the die micrograph of the SoC and comparison with state-of-the-art switched capacitor based multi-output EHPMlls.

[0029] DETAILED DESCRIPTION

[0030] Rapid reductions in power and size of SoC have paved the way for mm- scale textile-based self-powered systems capable of sensing a variety of biological and environmental data such as sodium, glucose, temperature, and neural signals [1 ,3-6]. SoCs built for these applications need to be fully autonomous and miniaturized, capable of continuous sensing at nW-level to operate from scarce amounts of harvested energy, and able to communicate in a distributed sensing network. A prior smart E-textile system

[0001] enables self-powered Na+sensing but is built with cm-scale commercial-off-the-shelf (COTS) components that consume >4mW. A mm-scale system-in-fiber in [2] with COTS components requires batteries for >10pW power. For systems using custom SoCs with nW power and mm-scale form factor [3-6], a base station is required to provide light (>3Klux [4], >60Klux [5]) to communicate and power the devices. This leads to reduced system autonomy and an inability for direct inter-SoC communication.

[0031] We address these limitations with a fully autonomous self-powered system-on-chip (SoC) that can be distributed along a fiber strand, capable of simultaneously harvesting energy, cooperatively scaling performance, sharing power, and booting-up with other SoCs infiber.

[0032] Figure 1A is a block diagram of an example system 100 including at least one textile fiber 102 having an embedded electrical bus 104. The textile fiber 102 can be any appropriate type of fiber. For example, synthetic fibers like polyethylene naphthalate (PEN) and polyp-phenylene benzobisoxazole (PBO) offer exceptional strength and modulus. Natural fibers like silk and cellulose could be used in wearable applications, where the textile fiber 102 can be non-irritating, breathable, and moisture-wicking to ensure user comfort and safety.

[0033] The system includes a number of SoCs 106a-b electrically coupled by the embedded electrical bus 104. Each of the SoCs 106a-b includes at least one processor 108a-b and an energy harvesting and power management unit (EHPMU) 110a-b configured for power sharing and cooperative dynamic voltage and frequency scaling (DVFS) with the other SoCs.

[0034] In some examples, each of the SoCs 106a-b is configured for cooperatively scaling its computing performance and / or power based on at least one local condition and at least one adjacent SoC condition. Each of the SoCs 106a-b can pair with one of the photovoltaic cells 112a-b, and the EHPMlls 110a-b can each be configured for harvesting power from the paired photovoltaic cells 112a-b. Although photovoltaic cells 112a-b are illustrated, in general, any appropriate power source can be used.

[0035] The photovoltaic cells 112a-b can be miniaturized and seamlessly integrated into the fiber structure without compromising flexibility for weaving or knitting. For example, thin-film technologies like amorphous silicon or organic photovoltaics could be used for their inherent flexibility. For low-light efficiency, materials like perovskites or dye-sensitized solar cells could be used for their strong response to weak light. In some examples, roll-to-roll printing techniques and readily available materials like organic polymers or inorganic nanoparticles can be used for cost-effective manufacturing. Encapsulating materials and robust active layers like metal oxides or chalcogenides can be used for enhanced durability.

[0036] In some examples, the EHPMUs 110a-b of each SoC 106a-b is configured for sharing power when the harvested local energy is surplus, pulling power when the harvested local energy is scarce, and isolating the SoC if a shared voltage is collapsing. In some examples, each SoC is configured to perform a ripple boot-up function. One or more of the SoCs 106a-b can be configured to control one or more peripheral chips 114 using the embedded electrical bus in the textile fiber 102. One or more of the SoCs 106a-b can be configured to control a data flow on the textile fiber 102 to establish an inter-fiber network, and one or more of the SoCs 106a-b can be configured to change from a first communication protocol to a second communication protocol for communicating on the embedded electrical bus 104 on the textile fiber 102.

[0037] In some examples, for at least one of the SoCs 106a-b, the EHPMU 110a-b is a peripheral chip external to the SoC (e.g., peripheral chip 104). One or more of the SoCs 106a-b can include a power harvester comprising one or more of: a thermoelectric generator (TEG) for harvesting from thermal gradients, an antenna for harvesting from RF energy, a coil for harvesting from electromagnetic energy, an electromechanical device for harvesting from pressure or vibration or motion, or other harvesting modalities.

[0038] In some examples, at least one of the SoCs 106a-b is configured to pass instructions or data along the textile fiber to one or more other SoCs. At least one of the SoCs 106a-b can be configured to control a destination for instructions or data transmitted along the textile fiber.

[0039] In some examples, one or more of the SoCs 106a-b is configured to control communication to one or more adjacent fibers or buses outside the textile fiber to form an intra-fiber network or a network in-textile. The system 100 can further include at least one SoC embedded in a textile comprising a second embedded electrical bus embedded in the textile.

[0040] Figure 1 B shows the proposed NanoSiF with distributed cooperative energy harvesting, power sharing, and ripple boot-up. Figures 1 C, 1 D, and 1 E illustrate the principle of the power sharing and cooperative DVFS. Figure 1 C includes front and back views and shows a wire bond with interposer and encapsulation. Figure 1 D illustrates power sharing between SoCs using cooperative DVFS and local DVFS. Figure 1 E illustrates applications of the system 100 including wearable electronics, medical care, and cable monitoring.

[0041] In some examples, the SoC achieves 33nW power consumption for the whole chip under 92Lux light and can reduce control power down to 2.7nW for the energy harvesting and power management unit (EHPMU). With the proposed power sharing and cooperative dynamic voltage and frequency scaling (DVFS), the proposed SoC reduces the illuminance needed to stay alive by >7x down to 12Lux. The SoC can be integrated into a 2.2x1 mm crosssection polymer fiber with an embedded electrical bus via a 4.7x3.7mm interposer board, as shown in Figure 1 C. The timing waveform in Figure 1 D shows how the SoCs can cooperatively scale their performance based on both the local [7-9] and adjacent SoCs’ conditions. This allows the energy and performance of all the in-fiber SoCs to be flexibly and jointly balanced, thereby improving the system viability and adaptability.

[0042] Figure 2A shows the architecture of the proposed nanowatt system-in- fiber (NanoSiF) and the SoC. The chip supports sustainable in-fiber operations by: 1 ) distributed energy harvesting: instead of powering the system from an aggregated energy source, the proposed architecture distributes SoCs along the fiber, which enables each SoC to harvest energy simultaneously and significantly relieves the dependence on environment; 2) power sharing: the EHPMU harvests from a PV cell and provides four outputs: VDIG(~0.58V), VLDO(0.95V), VLOCAL(1 -1 ,2V), and VSHARE(1 -1 .2V). The VSHARE rail is shared by all the SoCs in-fiber. The output of the 2ndstage (buck-boost) converter can be connected to either VLOCAL or VSHARE or both rails, which allows a flexible set of power management options, including a) sharing power with VSHARE rail when the harvested energy is surplus; b) pulling power from VSHARE rail when local energy is scarce; c) isolating VLOCAL and VSHARE rails to allow the SoC to act as an isolated power island if VSHARE is collapsing. In this way, all the energy harvested along the fiber can be redistributed and reused, and local regions of the fiber can stay active even when other regions are without power; 3) ultra-low-power (ULP) digital core and sensor: for ULP sensing and processing, a digital core [7] comprising a dynamic-leakage- suppression (DLS) logic based SRAM and a scalable DLS RISC-V processor, along with a pW temperature sensor

[0010] are implemented; 4) ripple boot-up (RB): instead of programming each SoC individually [3-6], a power-gateable on-chip 492B flip-flop-based RB RAM (RBR) enables autonomous instruction memory programming via a RB procedure. Each SoC can customize the boot code provided to the next SoC along the fiber. Therefore, only one NVM is needed for all the SoCs in-fiber, achieving a minimal number of discrete components; 5) cooperative DVFS: with the proposed RBR, an SoC can read the energy conditions of adjacent SoCs and perform DVFS accordingly to share more power with SoCs in poor conditions, allowing the entire fiber system to remain operational.

[0043] Each EHPMU can be configured to connect to both a shared power rail and to at least one local power rail (or energy store) through switches. As shown in Figure 2A, an EHPMU connects both VSHARE and VLOCAL visa SW1 and SW2.

[0044] Figure 2B illustrates the power sharing control scheme. Figure 2C shows the flow chart for the cooperative DVFS.

[0045] Figures 3A - 3G show the architecture and block diagram of the proposed EHPMU. Figure 3A shows an example two-stage boost-buck-boost converter. Figure 3B shows an example power-gateable 2D-MPPT circuit, Figure 3C shows a circuit for buck-boost mode control and regulation, and Figure 3D shows a power sharing controller and supply selector circuit.

[0046] Figure 3E illustrates ripple boot-up and asynchronous communication. As shown in Figure 3E, a method can include a first SoC booting up from NVM and enabling / chaing its RAM; a second SoC booting up from the first SoC RAM and enabling changing its RAM; and a third SoC repeating the process, with potentially other SoCs repeating the process.

[0047] Figure 3F shows example waveforms for buck-boost mode control and back-tO-back switching. Figure 3G shows example fiber integration techniques. One example includes milling a pocket to expose wires in fiber, cutting the selected wire bus, and attaching an interposer and die.

[0048] Prior designs suffer from cascade efficiency loss

[0011] , demand off-chip maximum power point tracking (MPPT) and an excessive number of converters

[0012] , or do not have cold start circuits for deployability

[0013] , Our two-stage topology directly powers the load components with minimum stages of converters, which avoids cascade loss

[0011] , The sub-nW power-gateable two-dimensional MPPT [7], including a fractional-open-circuit voltage based pulse frequency modulation (PFM) and a conversion ratio modulation (CRM), maximizes the energy extracted from the PV cell. And at low VPV, the MPPT is automatically power gated with retention cells to improve the efficiency in poor conditions.

[0049] To achieve low area and ULP, the 2ndstage converter is only triggered when VDIG is above VREFH or below VREFL. A local asynchronous loop is then activated to overclock the 2ndstage converter and the mode controller to quickly regulate the VDIG rail back to VREFM. Compared to previous work, where the extra harvested power is discarded [7] or a 10MHz high-frequency clock is needed

[0013] , this design shares the surplus energy with other SoCs without any extra high-frequency clocks. The sharing controller keeps monitoring the VLOCAL and VSHARE rails to decide 2ndstage EHPMU output connection. To avoid sinking the VSHARE rail before the chip cold starts, a back-to-back switch is implemented with a default-output-high level shifter to isolate the VSHARE and VLOCAL rails, as shown in Figure 3A.

[0050] Combining all these techniques, the EHPMU achieves a 2.7nW minimum control power, >60% peak efficiency for each stage, and full autonomy with a 0.516mm2area. The RBR includes two SPI slaves and a 492B register. The SPI slave enters NVM mode once it receives a specific command to imitate the COTS NVM, allowing SoCs to boot-up from either an NVM or RBR. The fiber integration process is shown in Figure 3E. The polymer fiber is thermally drawn from a Polyetherimide (PEI) preform with six embedded copper wires. The integration technique includes: 1 ) the top layer of the PEI material is removed to create pockets and expose the copper wires; 2) the wires are cut in the middle; 3) the SoC is wire-bonded onto an interposer which is then soldered onto the exposed wires, followed by encapsulation with UV-cure epoxy.

[0051] The example SoC is fabricated in 65nm CMOS. A benchtop testing setup is shown in Figure 4A, where two SoCs are connected over VSHARE and SPI ports. Figure 4B shows the measured waveform, illustrating that the SoCs can share power with each other and isolate VLOCAL from the VSHARE rail when it droops. Figure 4C shows the measured ripple boot-up waveform, illustrating that SoC1 can cold start, boot-up from the NVM, and execute the program to turn on its RBR, followed by SoC2 booting-up from SoC1. Figure 4D shows the measured cooperative DVFS waveform, illustrating that once SoC1 gets into a dark condition, it changes its RBR value to indicate a help request. SoC2 keeps reading SoCI’s RBR value, and when it detects the request, it scales itself down to share more power with the VSHARE rail.

[0052] Figures 5A and 5B show the measured efficiency for the EHPMU across VPV and POUT. The EHPMU achieves a 62.7%, 74.8%, 72.6% peak efficiency for the boost converter and buck-boost converter in boost and buck mode, respectively, with a 2.7nW minimum control power. Figure 5C shows the minimal VPV for SoC to cold start and stay alive across 11 dies.

[0053] Figure 5D shows the system power breakdown for the full chip measured at its poorest harvesting point. The measured minimum voltage / Lux required to keep an SoC alive is 180mV / 90Lux (across 11 dies). When adjacent SoCs can share 50nW power with VSHARE rail, the required Lux for an SoC to stay alive can be decreased by >7x.

[0054] In some examples, the SoC achieves 33nW full chip power from the harvesting input and can maintain continuous sensing under the poorest of lighting conditions. With the EHPMU, the SoC achieves distributed energy harvesting and multi-chip power sharing, enabling an SoC to survive in a >7x darker environment. Thanks to the proposed ripple boot-up function, the SoCs in-fiber can boot-up and communicate with each other, which is not supported by previous work.

[0055] Figure 6 shows the die micrograph of the SoC and comparison with state-of-the-art switched capacitor based multi-output EHPMUs. The proposed EHPMU achieves the lowest control power of 2.7nW with high efficiency and a small area of 0.516mm2. With a 2.2x1 mm2cross-section fiber, the SoC is shown to be fully compatible with the post-draw integration technique for fiber integration. All these results and features make this SoC well-suited for ULP SiF applications.

[0056] Although specific examples and features have been described above, these examples and features are not intended to limit the scope of the present disclosure, even where only a single example is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure.

[0057] The scope of the present disclosure includes any feature or combination of features disclosed in this specification (either explicitly or implicitly), or any generalization of features disclosed, whether or not such features or generalizations mitigate any or all of the problems described in this specification. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority to this application) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.

[0058] References:

[0059] [1] L. Yin et al., “A Self-Sustainable Wearable Multi-Modular E-Textile Bioenergy Microgrid System,” Nature Comm., vol 12, no. 1542, Mar. 2021.

[0060] [2] G. Loke et al., “Digital Electronics in Fibres Enable Fabric-Based Machine-Learning Inference,” Nature Comm., vol 12, no. 3317, June 2021.

[0061] [3] S. O’Driscoll et al., “A 200pm x 200pm x 100pm, 63nW, 2.4GHz Injectable FullyMonolithic Wireless Bio-Sensing System,” IEEE RFIC, pp. 256-259, June 2017.

[0062] [4] X. Wu et al., “A 0.04mm’ 16nW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement,” IEEE Symp. VLSI Circuits, pp. 191 - 192, June 2018.

[0063] [5] L. Xu et al., “ A 210 x 340 x 50pm Integrated CMOS System for MicroRobots with Energy Harvesting, Sensing, Processing, Communication and Actuation,” ISSCC Dig. Tech. Papers, pp. 194-195, Feb. 2022.

[0064] [6] J. Lim et al., “A Light-Tolerant Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry,” IEEE JSSC, vol. 57, no. 4, pp. 1061 -1074, April 2022. m D. Truesdell et al., “NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling,” IEEE Symp. VLSI Circuits, pp. 210-211 , June 2022. [8] X. Liu et al., “A 194nW Energy-Performance-Aware loT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization,” ISSCC Dig. Tech. Papers, pp. 224-225, Feb. 2022.

[0065] [9] L. Lin et al., “Sub-nW Microcontroller With Dual-Mode Logic and SelfStartup for Battery-Indifferent Sensor Nodes,” IEEE JSSC, vol. 56, no. 5, pp. 1618-1629, May 2021.

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[0010] D. Truesdell and B. H. Calhoun, “A 640 pW 22 pJ / sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution,” IEEE CICC, pp. 1-4, Apr. 2019.

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[0012] J. Li, et al., “Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities,” IEEE JSSC, vol. 52, no. 10, pp. 2550-2562, Oct. 2017.

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[0013] H. Kim et al., “A Dual-Mode Continuously Scalable-Conversion-Ratio SC Energy Harvesting Interface With SC-Based PFM MPPT and Flying Capacitor Sharing Scheme,” IEEE JSSC, vol. 56, no. 9, pp. 2724-2735, Sept. 2021.

Claims

CLAIMSWhat is claimed is:1 . A system comprising: at least one textile fiber comprising an embedded electrical bus; and a plurality of system on chips (SoCs) electrically coupled by the embedded electrical bus; wherein each SoC comprises at least one processor and an energy harvesting and power management unit (EHPMU) configured for power sharing with the other SoCs.

2. The system of claim 1 , wherein each EHPMU is configured for cooperative dynamic voltage and frequency scaling (DVFS) with the other SoCs.

3. The system of claim 1 , wherein each SoC is configured for cooperatively scaling its computing performance and / or power based on at least one local condition and at least one adjacent SoC condition.

4. The system of claim 1 , wherein each SoC pairs with a photovoltaic cell and the EHPMU of the SoC is configured for harvesting power from the photovoltaic cell.

5. The system of claim 1 , wherein the EHPMU of each SoC is configured for sharing power when the harvested local energy is surplus, pulling power when the harvested local energy is scarce, and isolating the SoC if a shared voltage is collapsing.

6. The system of claim 1 , wherein each SoC is configured to perform a ripple boot-up function.

7. The system of claim 1 , wherein at least one SoC is configured to control one or more peripheral chips using the embedded electrical bus in the textile fiber.

8. The system of claim 1 , wherein at least one SoC is configured to control a data flow on the textile fiber to establish an inter-fiber network.

9. The system of claim 1 , wherein at least one SoC is configured to change from a first communication protocol to a second communication protocol for communicating on the embedded electrical bus on the textile fiber.

10. The system of claim 1 , wherein, for at least one SoC, the EHPMU is a peripheral chip external to the at least one SoC.

11. The system of claim 1 , wherein at least one SoC comprises a power harvester comprising one or more of: a thermoelectric generator (TEG) for harvesting from thermal gradients, an antenna for harvesting from RF energy, a coil for harvesting from electromagnetic energy, an electromechanical device for harvesting from pressure or vibration or motion, or other harvesting modalities.

12. The system of claim 1 , wherein at least one SoC is configured to pass instructions or data along the textile fiber to one or more other SoCs.

13. The system of claim 1 , wherein at least one SoC is configured to control a destination for instructions or data transmitted along the textile fiber.

14. The system of claim 1 , wherein at least one SoC is configured to control communication to one or more adjacent fibers or buses outside the textile fiber to form an intra-fiber network or a network in-textile.

15. The system of claim 1 , further comprising at least one SoC embedded in a textile comprising a second embedded electrical bus embedded in the textile.

16. The system of claim 1 , wherein each EHPMU is configured to connect to both a shared power rail and to at least one local power rail or energy store through one or more switches.

17. A method comprising: performing, by an energy harvesting and power management unit (EHPMU) of a first system on a chip (SoC) comprising at least one processor, power sharing with at least one second SoC, wherein the first and second SoCs are electrically coupled to an embedded electrical bus of at least one textile fiber; and performing, by the EHPMU, cooperative dynamic voltage and frequency scaling (DVFS) with the second SoC by communicating on the embedded bus.

18. The method of claim 15, comprising cooperatively scaling the computing performance and / or power of the first SoC based on at least one local condition and at least one adjacent SoC condition.

19. The method of claim 15, comprising pairing with a photovoltaic cell and harvesting power from the photovoltaic cell.

20. The method of claim 15, comprising sharing power when the harvested local energy is surplus, pulling power when the harvested local energy is scarce, and isolating the SoC if a shared voltage is collapsing.

21. The method of claim 15, comprising performing, by the first SoC and the second SoC, a ripple boot-up function.

22. The method of claim 15, comprising controlling one or more peripheral chips using the embedded electrical bus in the textile fiber.

23. A method comprising: performing, by an energy harvesting and power management unit (EHPMU) of a first system on a chip (SoC) comprising at least one processor, power sharing with at least one second SoC, wherein the first and second SoCs are electrically coupled to an embedded electrical bus of at least one textile fiber; and performing, by the first SoC and the second SoC, a ripple boot-up function.

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