Array substrate and display panel

Abstract

An array substrate and a display panel. The array substrate uses a flip architecture, and among two adjacent rows of pixel areas (PA), a compensation capacitor is arranged in the row of pixel areas (PA) having smaller capacitance, so that the capacitance of two adjacent rows of pixel areas (PA) tends to be consistent. Additionally, a raising portion (dg1) is arranged between an extension section (d11) of an output electrode (d1) of a first thin film transistor (T1) and a protruding section (c1) of a scan line (scan), and the raising portion (dg1) overlaps with part of the extension section (d11) to raise the extension section (d11) of the output electrode (d1) of the first thin film transistor (T1).

Description

Array substrate and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In the related art, the pixel arrangements of LCD panels mainly include stripe and flip architectures. In the stripe architecture, pixels are column-inverted, with one data line driving pixels of the same color in the same column. In the flip architecture, pixels are dot-inverted, with one data line driving pixels of two colors in two adjacent columns simultaneously. The thin-film transistor openings in adjacent rows face opposite directions.

[0003] As shown in Figure 1, in a flip-chip architecture, when fabricating an array substrate, if the second metal layer M2 is offset to the right relative to the first metal layer M1, the compensation capacitance of the even-numbered rows (left side) increases, while the compensation capacitance of the odd-numbered rows (right side) decreases. The compensation capacitance between adjacent rows varies. SUMMARY OF THE INVENTION

[0004] The embodiments of the present application provide an array substrate and a display panel, which can improve the uniformity of compensation capacitors in two adjacent rows.

[0005] An embodiment of the present application provides an array substrate, comprising:

[0006] Scan lines and data lines, the scan lines and the data lines are arranged in different layers, and the scan lines and the data lines are arranged to cross each other to form a plurality of pixel areas; and

[0007] A pixel electrode, the pixel electrode is arranged in the pixel area, and the pixel electrode includes a first pixel electrode and a second pixel electrode;

[0008] In two adjacent rows of pixel electrodes, the first pixel electrode is arranged in row N, and the second pixel electrode is arranged in row N+1, where N is a positive integer, the first pixel electrode is connected to the data line through a first thin film transistor, and the second pixel electrode is connected to the data line through a second thin film transistor;

[0009] In two adjacent rows of pixel areas, one data line is connected to the input electrode of the first thin film transistor and the input electrode of the second thin film transistor at the same time, the first thin film transistor and the second thin film transistor are located on opposite sides of the one data line, and an overlapping area between the output electrode of the first thin film transistor and the gate of the first thin film transistor is smaller than an overlapping area between the output electrode of the second thin film transistor and the gate of the second thin film transistor;

[0010] The extension section of the output electrode of the first thin film transistor overlaps with the protruding section of the scan line to form a compensation capacitor. A padding portion is provided between the extension section and the protruding section, and the padding portion overlaps with a portion of the extension section.

[0011] Optionally, in some embodiments of the present application, the output electrode of the first thin-film transistor includes an output main segment, a first connecting segment and the extension segment connected in sequence, the first connecting segment is connected to the first pixel electrode, and the extension segment is connected to the side of the first connecting segment away from the output main segment. The first thin-film transistor also includes an active part, and a portion of the output main segment is stacked on the active part, and the raised part and the active part are in the same layer and are arranged at intervals.

[0012] Optionally, in some embodiments of the present application, the input electrode of the first thin-film transistor includes a second connecting segment, a middle segment, and a first side segment, one end of the second connecting segment is connected to the data line, the other end of the second connecting segment is connected to the middle segment, the middle segment is arranged opposite to an end of the output main segment, and the first side segment is connected to one side of the middle segment and is arranged opposite to a side surface of the output main segment;

[0013] The array substrate further includes a first redundant portion overlapping the raised portion. The first redundant portion and the extending section are in the same layer and spaced apart. The first redundant portion is opposite to a side surface of the extending section.

[0014] Optionally, in some embodiments of the present application, the input electrode of the first thin film transistor also includes a second side segment, which is connected to the other side of the middle segment and is arranged opposite to the other side of the output main segment. The array substrate also includes a second redundant portion overlapping with the raised portion, and the second redundant portion is in the same layer as the extension segment and is arranged at intervals, and the second redundant portion is arranged opposite to the other side of the extension segment.

[0015] Optionally, in some embodiments of the present application, the raised portion is insulated from the first redundant portion, the extension section and the second redundant portion respectively.

[0016] Optionally, in some embodiments of the present application, the array substrate includes a substrate, a first insulating layer, a second insulating layer, and a third insulating layer; the scan line and the gate of the first thin film transistor are arranged on the same layer on the substrate; the first insulating layer covers the scan line and the gate of the first thin film transistor; the active part and the raised part are arranged on the first insulating layer; the second insulating layer covers the active part and the raised part; the data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part are arranged on the second insulating layer; the third insulating layer covers the data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part; and the pixel electrode is arranged on the third insulating layer.

[0017] Optionally, in some embodiments of the present application, the raised portion is connected to the first redundant portion, the extension section and the second redundant portion respectively.

[0018] Optionally, in some embodiments of the present application, the array substrate includes a substrate, a first insulating layer and a second insulating layer, the scan line and the gate of the first thin film transistor are arranged on the same layer on the substrate, the first insulating layer covers the scan line and the gate of the first thin film transistor, the active part and the raised part are arranged on the first insulating layer, the input electrode and the output electrode of the first thin film transistor are connected and arranged on the active part, the extension section of the output electrode, the first redundant part and the second redundant part are connected and arranged on the raised part, the second insulating layer covers the data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part, and the pixel electrode is arranged on the second insulating layer.

[0019] Optionally, in some embodiments of the present application, the extension direction of the output main segment is parallel to or coincides with the extension direction of the extension segment.

[0020] Optionally, in some embodiments of the present application, the distance from the boundary of the active portion to the boundary of the gate of the first thin film transistor is a first distance, the distance from the boundary of the raised portion to the boundary of the protruding segment is a second distance, and the first distance is equal to the second distance.

[0021] Optionally, in some embodiments of the present application, in the extension direction of the scan line, the raised portion has a first width, the active portion has a second width, the portion where the active portion overlaps with the output main segment has a third width, and the first width is greater than or equal to the third width and less than or equal to the second width.

[0022] Accordingly, an embodiment of the present application further provides a display panel, which includes the array substrate according to any one of the above embodiments, wherein the array substrate includes:

[0023] Scan lines and data lines, the scan lines and the data lines are arranged in different layers, and the scan lines and the data lines are arranged to cross each other to form a plurality of pixel areas; and

[0024] A pixel electrode, the pixel electrode is arranged in the pixel area, and the pixel electrode includes a first pixel electrode and a second pixel electrode;

[0025] In two adjacent rows of pixel electrodes, the first pixel electrode is arranged in row N, and the second pixel electrode is arranged in row N+1, where N is a positive integer, the first pixel electrode is connected to the data line through a first thin film transistor, and the second pixel electrode is connected to the data line through a second thin film transistor;

[0026] In two adjacent rows of pixel areas, one data line is connected to the input electrode of the first thin film transistor and the input electrode of the second thin film transistor at the same time, the first thin film transistor and the second thin film transistor are located on opposite sides of the one data line, and an overlapping area between the output electrode of the first thin film transistor and the gate of the first thin film transistor is smaller than an overlapping area between the output electrode of the second thin film transistor and the gate of the second thin film transistor;

[0027] The extension section of the output electrode of the first thin film transistor overlaps with the protruding section of the scan line to form a compensation capacitor. A padding portion is provided between the extension section and the protruding section, and the padding portion overlaps with a portion of the extension section.

[0028] Optionally, in some embodiments of the present application, the output electrode of the first thin-film transistor includes an output main segment, a first connecting segment and the extension segment connected in sequence, the first connecting segment is connected to the first pixel electrode, and the extension segment is connected to the side of the first connecting segment away from the output main segment. The first thin-film transistor also includes an active part, and a portion of the output main segment is stacked on the active part, and the raised part and the active part are in the same layer and are arranged at intervals.

[0029] Optionally, in some embodiments of the present application, the input electrode of the first thin-film transistor includes a second connecting segment, a middle segment, and a first side segment, one end of the second connecting segment is connected to the data line, the other end of the second connecting segment is connected to the middle segment, the middle segment is arranged opposite to an end of the output main segment, and the first side segment is connected to one side of the middle segment and is arranged opposite to a side surface of the output main segment;

[0030] The array substrate further includes a first redundant portion overlapping the raised portion. The first redundant portion and the extending section are in the same layer and spaced apart. The first redundant portion is opposite to a side surface of the extending section.

[0031] Optionally, in some embodiments of the present application, the input electrode of the first thin film transistor also includes a second side segment, which is connected to the other side of the middle segment and is arranged opposite to the other side of the output main segment. The array substrate also includes a second redundant portion overlapping with the raised portion, and the second redundant portion is in the same layer as the extension segment and is arranged at intervals, and the second redundant portion is arranged opposite to the other side of the extension segment.

[0032] Optionally, in some embodiments of the present application, the raised portion is insulated from the first redundant portion, the extension section and the second redundant portion respectively.

[0033] Optionally, in some embodiments of the present application, the array substrate includes a substrate, a first insulating layer, a second insulating layer, and a third insulating layer; the scan line and the gate of the first thin film transistor are arranged on the same layer on the substrate; the first insulating layer covers the scan line and the gate of the first thin film transistor; the active part and the raised part are arranged on the first insulating layer; the second insulating layer covers the active part and the raised part; the data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part are arranged on the second insulating layer; the third insulating layer covers the data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part; and the pixel electrode is arranged on the third insulating layer.

[0034] Optionally, in some embodiments of the present application, the raised portion is connected to the first redundant portion, the extension section and the second redundant portion respectively.

[0035] Optionally, in some embodiments of the present application, the array substrate includes a substrate, a first insulating layer and a second insulating layer, the scan line and the gate of the first thin film transistor are arranged on the same layer on the substrate, the first insulating layer covers the scan line and the gate of the first thin film transistor, the active part and the raised part are arranged on the first insulating layer, the input electrode and the output electrode of the first thin film transistor are connected and arranged on the active part, the extension section of the output electrode, the first redundant part and the second redundant part are connected and arranged on the raised part, the second insulating layer covers the data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part, and the pixel electrode is arranged on the second insulating layer.

[0036] Optionally, in some embodiments of the present application, the extension direction of the output main segment is parallel to or coincides with the extension direction of the extension segment.

[0037] Optionally, in some embodiments of the present application, the distance from the boundary of the active portion to the boundary of the gate of the first thin film transistor is a first distance, the distance from the boundary of the raised portion to the boundary of the protruding segment is a second distance, and the first distance is equal to the second distance.

[0038] Optionally, in some embodiments of the present application, in the extension direction of the scan line, the raised portion has a first width, the active portion has a second width, the portion where the active portion overlaps with the output main segment has a third width, and the first width is greater than or equal to the third width and less than or equal to the second width. Beneficial effects

[0039] The array substrate of the embodiment of the present application adopts a flip architecture. In two adjacent rows of pixel areas, a compensation capacitor is set in a row of pixel areas with smaller capacitance, so that the capacitance of the two adjacent rows of pixel areas tends to be consistent. In addition, a padding portion is set between the extension section of the output electrode of the first thin film transistor and the protruding section of the scanning line. The padding portion and the extension section are partially overlapped to pad the extension section of the output electrode of the first thin film transistor, so that the terrain of the extension section tends to be consistent with the terrain of the output main section of the output electrode of the first thin film transistor. When etching to form the output electrode of the first thin film transistor, the etching liquid has a similar etching effect at the above two similar terrains, so as to reduce the risk of the width of the extension section of the output electrode of the first thin film transistor being too small, thereby reducing the risk of the compensation capacitance being too small. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic structural diagram of an array substrate provided by the prior art;

[0041] FIG2 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0042] FIG3 is a schematic diagram of a partially enlarged structure of an array substrate provided in an embodiment of the present application;

[0043] FIG4 is an enlarged view of portion M in FIG3 ;

[0044] FIG5 is a schematic diagram of the cross-sectional structure along line AA in FIG3 ;

[0045] FIG6 is a schematic diagram of the cross-sectional structure along line BB in FIG3 ;

[0046] FIG7 is another schematic cross-sectional view of the array substrate provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as labels and do not impose numerical requirements or establish an order.

[0048] The embodiments of the present application provide an array substrate and a display panel, which are described in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.

[0049] 2 to 4 , an embodiment of the present application provides an array substrate 100 , which includes scan lines scan, data lines data, and pixel electrodes pix.

[0050] The scan lines scan and the data lines data are arranged in different layers and are arranged to cross each other to form a plurality of pixel areas PA.

[0051] The pixel electrode pix is ​​disposed in the pixel area PA and includes a first pixel electrode p1 and a second pixel electrode p2.

[0052] In two adjacent rows of pixel electrodes pix, the first pixel electrode p1 is arranged in row N, and the second pixel electrode p2 is arranged in row N+1, where N is a positive integer. The first pixel electrode p1 is connected to the data line data via a first thin-film transistor T1. The second pixel electrode p2 is connected to the data line data via a second thin-film transistor T2.

[0053] In two adjacent rows of pixel areas PA, a data line data simultaneously connects the input electrode s1 of the first thin-film transistor T1 and the input electrode s2 of the second thin-film transistor T2. The first thin-film transistor T1 and the second thin-film transistor T2 are located on opposite sides of the data line data. The output electrode d1 of the first thin-film transistor T1 overlaps with the gate electrode g1 of the first thin-film transistor T1 to form a first capacitor. The output electrode d2 of the second thin-film transistor T2 overlaps with the gate electrode g2 of the second thin-film transistor T2 to form a second capacitor. The overlapping area between the output electrode d1 of the first thin-film transistor T1 and the gate electrode g1 of the first thin-film transistor T1 is smaller than the overlapping area between the output electrode d2 of the second thin-film transistor T2 and the gate electrode g2 of the second thin-film transistor T2.

[0054] The extension section d11 of the output electrode d1 of the first thin film transistor T1 overlaps with the protruding section c1 of the scan line scan to form a compensation capacitor. A raised portion dg1 is provided between the extension section d11 and the protruding section c1. The raised portion dg1 partially overlaps with the extension section d11.

[0055] It should be noted that when N is an odd number, the Nth row is an odd row, and the N+1th row is an even row; when N is an even number, the Nth row is an even row, and the N+1th row is an odd row. Furthermore, during the array substrate manufacturing process, regardless of whether the second metal layer is offset to the left or right relative to the first metal layer, the capacitor in the Nth row is defined as the first capacitor.

[0056] The array substrate of the embodiment of the present application adopts a flip architecture. In two adjacent rows of pixel areas PA, a compensation capacitor is provided in the row of pixel areas PA with smaller capacitance, so that the capacitances of the two adjacent rows of pixel areas PA tend to be consistent. In addition, a padding portion dg1 is provided between the extension segment d11 of the output electrode d1 of the first thin-film transistor T1 and the protruding segment c1 of the scan line scan. The padding portion dg1 partially overlaps with the extension segment d11 to raise the extension segment d11 of the output electrode d1 of the first thin-film transistor T1, so that the terrain of the extension segment d11 tends to be consistent with the terrain of the output main segment d12 of the output electrode d1 of the first thin-film transistor T1. When etching to form the output electrode d1 of the first thin-film transistor T1, the etching liquid has a similar etching effect at the above two similar terrains, thereby reducing the risk of the width of the extension segment d11 of the first thin-film transistor T1 being too small, thereby reducing the risk of the compensation capacitance being too small.

[0057] It is understandable that the amount of etching solution in low-lying areas is greater than that in high-lying areas, resulting in a higher etching rate in low-lying areas than in high-lying areas. Therefore, under the same etching time, the features formed in low-lying areas are smaller in size. Therefore, the embodiments of the present application use a raised portion dg1 to increase the topography of the upper plate (extension section d11) in the compensation capacitor, thereby reducing the etching rate in the compensation capacitor area and forming a larger extension section d11. As the size of extension section d11 increases, the overlapping area between extension section d11 and protruding section c1 also increases, thereby increasing the capacitance of the compensation capacitor.

[0058] In addition, when the potential of the compensation capacitor region is higher than that of the first thin film transistor T1, there is a risk that too much etching solution will flow into the first thin film transistor T1 region, causing the size of the source and drain to be reduced. Therefore, the height of the raised portion dg1 is optionally equal to the height of the active portion ad1.

[0059] In some embodiments, the height of the elevated portion dg1 may be slightly smaller than the height of the active portion ad1 .

[0060] Optionally, the first thin film transistor T1 and the second thin film transistor T2 may be N-type or P-type thin film transistors, or other types of thin film transistors. This embodiment is described by taking both being N-type thin film transistors as an example, but is not limited thereto.

[0061] Optionally, the input electrodes of the first thin-film transistor T1 and the second thin-film transistor T2 are sources, and the output electrodes of the first thin-film transistor T1 and the second thin-film transistor T2 are drains. In some embodiments, the input electrodes of the first thin-film transistor T1 and the second thin-film transistor T2 may be drains, and the output electrodes of the first thin-film transistor T1 and the second thin-film transistor T2 may be sources.

[0062] Optionally, referring to Figure 4 , in one embodiment, the output electrode d1 of the first thin-film transistor T1 includes an output main segment d12, a first connecting segment d13, and an extension segment d11, which are connected in sequence. The first connecting segment d13 is connected to the first pixel electrode p1. The extension segment d11 is connected to the side of the first connecting segment d13 that is away from the output main segment d12. The first thin-film transistor T1 also includes an active portion ad1, with a portion of the output main segment d12 stacked on the active portion ad1. The raised portion dg1 is disposed on the same layer as the active portion ad1 and spaced apart from it.

[0063] The output main segment d12 is connected to the drain region of the active portion ad1. Placing the raised portion dg1 on the same layer as the active portion ad1 saves one photomask. That is, the active portion ad1 and the raised portion dg1 are formed simultaneously using a single photomask process, and the raised portion dg1 and the active portion ad1 are made of the same material.

[0064] Optionally, the material of the active portion ad1 includes at least one of single crystal silicon, polycrystalline silicon, or an oxide semiconductor.

[0065] In some embodiments, the raised portion dg1 is also made of other materials, such as organic materials or inorganic materials.

[0066] In some embodiments, the raised portion dg1 may also be any film layer before the extension segment d11 is formed. For example, a process of forming any film layer may be added between the substrate 11 and the extension segment d11 during the original preparation process to form the raised portion dg1.

[0067] Optionally, in one embodiment, the input electrode s1 of the first thin-film transistor T1 includes a second connecting segment s11, a middle segment s12, and a first side segment s13. One end of the second connecting segment s11 is connected to the data line data, and the other end of the second connecting segment s11 is connected to the middle segment s12. The middle segment s12 is disposed opposite an end of the output main segment d12. The first side segment s13 is connected to one side of the middle segment s12 and is disposed opposite a side surface of the output main segment d12.

[0068] The array substrate 100 further includes a first redundant portion d31 overlapping the raised portion dg1 . The first redundant portion d31 is disposed on the same layer as the extension section d11 and spaced apart from the extension section d11 . The first redundant portion d31 is disposed opposite to a side surface of the extension section d11 .

[0069] In this embodiment, a first redundant portion d31 is provided in the compensation capacitor region and is arranged opposite to one side surface of the extension segment d11, so that the preparation topography of the extension segment d11 is close to the preparation topography of the output main segment d12 of the output electrode d1, so that the flow topography of the etching liquid is close to the same in the compensation capacitor region and the first thin-film transistor T1 region, thereby making the width n1 of the extension segment d11 close to the width n2 of the output main segment d12, thereby reducing the risk of the extension segment d11 being too small.

[0070] Optionally, in some embodiments of the present application, the input electrode s1 of the first thin-film transistor T1 further includes a second side segment s14. The second side segment s14 is connected to the other side of the middle segment s12 and is disposed opposite the other side of the output main segment d12. The array substrate 100 further includes a second redundant portion d32 overlapping the elevated portion dg1. The second redundant portion d32 is disposed on the same layer as the extended segment d11 and spaced apart from the extended segment d11. The second redundant portion d32 is disposed opposite the other side of the extended segment d11.

[0071] In this embodiment, a second redundant portion d32 is provided in the compensation capacitor region and is arranged opposite to the other side surface of the extension segment d11, so that the preparation topography of the extension segment d11 is close to the preparation topography of the output main segment d12 of the output electrode d1, so that the flow topography of the etching liquid is close to the same in the compensation capacitor region and the first thin-film transistor T1 region, thereby making the width of the extension segment d11 close to the width of the output main segment d12, reducing the risk of the extension segment d11 being too small.

[0072] Optionally, the output electrodes d1 / d2, input electrodes s1 / s2, data line data, first redundant portion d31, and second redundant portion d32 are disposed on the same layer and made of the same material. The first redundant portion d31, second redundant portion d32, output electrodes d1 / d2, input electrodes s1 / s2, and data line data are formed using the same photomask, saving process steps.

[0073] Optionally, the scan line scan, gate g1 / g2, output electrode d1 / d2, input electrode s1 / s2, data line data, first redundant portion d31, and second redundant portion d32 may be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co), an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. Furthermore, the scan line scan, gate g1 / g2, output electrode d1 / d2, input electrode s1 / s2, data line data, first redundant portion d31, and second redundant portion d32 may have a single-layer structure or a stacked structure of two or more layers.

[0074] Optionally, in one embodiment, the extension direction of the output main section d12 is parallel to or coincides with the extension direction of the extension section d11 .

[0075] Optionally, in one embodiment, the distance from the boundary of the active portion ad1 to the boundary of the gate g1 of the first thin film transistor T1 is a first distance L1, and the distance from the boundary of the raised portion dg1 to the boundary of the protruding segment c1 is a second distance L2. The first distance L1 is equal to the second distance L2.

[0076] In this embodiment, the extension direction of the extension segment d11 in the compensation capacitor region is parallel to or coincides with the extension direction of the output main segment d12, and the first distance L1 is equal to the second distance L2, so that the preparation topography of the extension segment d11 is similar to the preparation topography of the output main segment d12 of the output electrode d1, so that the flow topography of the etching liquid is consistent in the compensation capacitor region and the first thin-film transistor T1 region, and thus the width of the extension segment d11 is similar to the width of the output main segment d12, thereby reducing the risk of the extension segment d11 and the output main segment d12 being too small in size.

[0077] Optionally, in one embodiment, in the extension direction of the scan line scan, the raised portion dg1 has a first width k1, the active portion ad1 has a second width k2, and the portion where the active portion ad1 overlaps with the output main segment d12 has a third width k3. The first width k1 is greater than or equal to the third width k3 and less than or equal to the second width k2.

[0078] It can be understood that when the first width k1 is equal to the second width k2, the topography of the extension segment d11 of the compensation capacitor region and the topography of the output main segment d12 of the first thin-film transistor T1 region are most similar, allowing the width of the extension segment d11 to be equal to the width of the output main segment d12. When the first width k1 is equal to the second width k3, the aperture ratio can be increased while ensuring that the width of the extension segment d11 is increased.

[0079] Optionally, in one embodiment, the raised portion dg1 is insulated from the first redundant portion d31 , the extended section d11 and the second redundant portion d32 , respectively.

[0080] Optionally, referring to Figures 5 and 6, in one embodiment, the array substrate 100 includes a substrate 11, a first insulating layer 12, a second insulating layer 13, and a third insulating layer 14. The scan line scan and the gate g1 of the first thin-film transistor T1 are disposed on the same layer on the substrate 11. The first insulating layer 12 covers the scan line scan and the gate g1 of the first thin-film transistor T1. The active portion ad1 and the padding portion gd1 are disposed on the first insulating layer 12. The second insulating layer 13 covers the active portion ad1 and the padding portion gd1. The data line data, the input electrode s1 and the output electrode d1 of the first thin-film transistor T1, the first redundant portion d31 and the second redundant portion d32 are disposed on the second insulating layer 13. The third insulating layer 14 covers the data line data, the input electrode s1 and the output electrode d1 of the first thin-film transistor T1, the first redundant portion d31 and the second redundant portion d32. The pixel electrode pix is ​​disposed on the third insulating layer 14.

[0081] The preparation process of the array substrate 100 is as follows:

[0082] A patterned first metal layer is formed on the substrate 11 , and the first metal layer includes scan lines scan, gates g1 / g2 , and protruding segments c1 .

[0083] A first insulating layer 12 is formed on the first metal layer.

[0084] A patterned active layer is formed on the first insulating layer 12 , and the active layer includes an active portion ad1 and a padding portion dg1 .

[0085] A second insulating layer 13 is formed on the active layer.

[0086] A patterned second metal layer is formed on the second insulating layer 13 , and the second metal layer includes output electrodes d1 / d2 , input electrodes s1 / s2 , a data line data, a first redundant portion d31 , and a second redundant portion d32 .

[0087] A third insulating layer 14 is formed on the second metal layer.

[0088] A patterned pixel electrode pix is ​​formed on the third insulating layer 14 . The pixel electrode pix is ​​connected to the output electrode d1 / d2 through a via hole in the third insulating layer 14 .

[0089] Optionally, referring to FIG. 7 , in another embodiment of the present application, compared with the above embodiment, the difference of this embodiment is that the raised portion dg1 is respectively connected to the first redundant portion d31 , the extension section d11 and the second redundant portion d32 .

[0090] Because the raised portion dg1 is made of semiconductor material, it has a certain degree of conductivity. Since the extension segment d11 is connected to the raised portion dg1, the raised portion dg1, the first redundant portion d31, the extension segment d11, and the second redundant portion d32 collectively form the upper electrode plate of the compensation capacitor. Compared to the previous embodiment, this embodiment increases the overlap area between the upper electrode plate and the protruding segment c1, thereby increasing the capacitance of the compensation capacitor.

[0091] Optionally, in one embodiment, the array substrate 100 includes a substrate 11, a first insulating layer 12, and a second insulating layer 13. The scan line scan and the gate g1 of the first thin-film transistor T1 are disposed on the same layer on the substrate 11. The first insulating layer 12 covers the scan line scan and the gate g1 of the first thin-film transistor T1. The active portion ad1 and the raised portion dg1 are disposed on the first insulating layer 12. The input electrode s1 and the output electrode d1 of the first thin-film transistor T1 are connected and disposed on the active portion ad1. The extended section d11 of the output electrode d1, the first redundant portion d31, and the second redundant portion d32 are connected and disposed on the raised portion dg1. The second insulating layer 13 covers the data line data, the input electrode s1 and the output electrode d1 of the first thin-film transistor T1, the first redundant portion d31, and the second redundant portion d32. The pixel electrode pix is ​​disposed on the second insulating layer 13.

[0092] The preparation process of the array substrate 100 of this embodiment is as follows:

[0093] A patterned first metal layer is formed on the substrate 11 , and the first metal layer includes scan lines scan, gates g1 / g2 , and protruding segments c1 .

[0094] A first insulating layer 12 is formed on the first metal layer.

[0095] A patterned active layer is formed on the first insulating layer 12 , and the active layer includes an active portion ad1 and a padding portion dg1 .

[0096] A patterned second metal layer is formed on the active layer, and the second metal layer includes output electrodes d1 / d2 , input electrodes s1 / s2 , a data line data, a first redundant portion d31 , and a second redundant portion d32 .

[0097] A second insulating layer 13 is formed on the second metal layer.

[0098] A patterned pixel electrode pix is ​​formed on the second insulating layer 13 . The pixel electrode pix is ​​connected to the output electrode d1 / d2 through a via hole in the second insulating layer 13 .

[0099] Optionally, based on the embodiment corresponding to FIG. 5 , the raised portion dg1 may be connected to the first redundant portion d31 , the extended section d11 , and the second redundant portion d32 through vias.

[0100] Correspondingly, an embodiment of the present application further provides a display panel, which includes the array substrate 100 as described in any one of the above embodiments.

[0101] Wherein, the display panel is a liquid crystal panel.

[0102] The display panel of the embodiment of the present application adopts an array substrate with a flip structure. In two adjacent rows of pixel areas, a compensation capacitor is set in a row of pixel areas with smaller capacitance, so that the capacitance of the two adjacent rows of pixel areas tends to be consistent; in addition, a padding portion is set between the extension section of the output electrode of the first thin film transistor and the protruding section of the scanning line. The padding portion and the extension section are partially overlapped to pad the extension section of the output electrode of the first thin film transistor, so that the terrain of the extension section tends to be consistent with the terrain of the output main section of the output electrode of the first thin film transistor. When etching the output electrode of the first thin film transistor, the etching liquid has a similar etching effect at the above two similar terrains, so as to reduce the risk of the width of the output electrode extension section of the first thin film transistor being too small, thereby reducing the risk of the compensation capacitance being too small.

[0103] The above is a detailed introduction to an array substrate and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, comprising: Scan lines and data lines, the scan lines and the data lines are arranged in different layers, and the scan lines and the data lines are arranged to cross each other to form a plurality of pixel areas; as well as A pixel electrode, wherein the pixel electrode is disposed in the pixel area, and the pixel electrode includes a first pixel electrode and a second pixel electrode; In two adjacent rows of pixel electrodes, the first pixel electrode is arranged in the Nth row, the second pixel electrode is arranged in the N+1th row, N is a positive integer, the first pixel electrode is connected to the data line through a first thin film transistor, and the second pixel electrode is connected to the data line through a second thin film transistor; In two adjacent rows of pixel areas, one of the data lines is connected to the input electrode of the first thin film transistor and the input electrode of the second thin film transistor at the same time, the first thin film transistor and the second thin film transistor are located on opposite sides of one of the data lines, and the overlapping area between the output electrode of the first thin film transistor and the gate of the first thin film transistor is smaller than the overlapping area between the output electrode of the second thin film transistor and the gate of the second thin film transistor; The extension section of the output electrode of the first thin film transistor overlaps with the protruding section of the scan line to form a compensation capacitor, and a padding portion is arranged between the extension section and the protruding section, and the padding portion is arranged to overlap with part of the extension section.

2. The array substrate according to claim 1, wherein: The output electrode of the first thin film transistor includes an output main section, a first connecting section and the extension section which are connected in sequence, the first connecting section is connected to the first pixel electrode, the extension section is connected to a side of the first connecting section away from the output main section, the first thin film transistor also includes an active part, a part of the output main section is stacked on the active part, and the raised part and the active part are in the same layer and are arranged at intervals.

3. The array substrate according to claim 2, wherein: The input electrode of the first thin film transistor includes a second connecting segment, a middle segment and a first side segment, one end of the second connecting segment is connected to the data line, the other end of the second connecting segment is connected to the middle segment, the middle segment is arranged opposite to the end of the output main segment, and the first side segment is connected to one side of the middle segment and is arranged opposite to one side surface of the output main segment; The array substrate further includes a first redundant portion overlapping the raised portion, the first redundant portion and the extending section being in the same layer and spaced apart, and the first redundant portion being opposite to a side surface of the extending section.

4. The array substrate according to claim 3, wherein: The input electrode of the first thin film transistor also includes a second side segment, which is connected to the other side of the middle segment and is arranged opposite to the other side of the output main segment. The array substrate also includes a second redundant portion overlapping the raised portion, the second redundant portion is in the same layer as the extension segment and is arranged at an interval, and the second redundant portion is arranged opposite to the other side of the extension segment.

5. The array substrate according to claim 4, wherein: The raised portion is insulated from the first redundant portion, the extending section and the second redundant portion respectively.

6. The array substrate according to claim 5, wherein: The array substrate includes a substrate, a first insulating layer, a second insulating layer, and a third insulating layer. The scan line and the gate of the first thin film transistor are arranged on the substrate in the same layer. The first insulating layer covers the scan line and the gate of the first thin film transistor. The active part and the raised part are arranged on the first insulating layer. The second insulating layer covers the active part and the raised part. The data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part are arranged on the second insulating layer. The third insulating layer covers the data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part. The pixel electrode is arranged on the third insulating layer.

7. The array substrate according to claim 4, wherein: The raised portion is respectively connected to the first redundant portion, the extending section and the second redundant portion.

8. The array substrate according to claim 7, wherein: The array substrate includes a substrate, a first insulating layer and a second insulating layer, the scan line and the gate of the first thin film transistor are arranged on the substrate in the same layer, the first insulating layer covers the scan line and the gate of the first thin film transistor, the active part and the raised part are arranged on the first insulating layer, the input electrode and the output electrode of the first thin film transistor are connected and arranged on the active part, the extension section of the output electrode, the first redundant part and the second redundant part are connected and arranged on the raised part, the second insulating layer covers the data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part, and the pixel electrode is arranged on the second insulating layer.

9. The array substrate according to claim 1, wherein: The extension direction of the output main section is parallel to or coincides with the extension direction of the extension section.

10. The array substrate according to claim 2, wherein: The distance from the boundary of the active portion to the boundary of the gate of the first thin film transistor is a first distance, the distance from the boundary of the raised portion to the boundary of the protruding segment is a second distance, and the first distance is equal to the second distance.

11. The array substrate according to claim 2, wherein: In the extension direction of the scan line, the raised portion has a first width, the active portion has a second width, the overlapping portion of the active portion and the output main segment has a third width, and the first width is greater than or equal to the third width and less than or equal to the second width.

12. A display panel, comprising an array substrate, the array substrate comprising: Scan lines and data lines, the scan lines and the data lines are arranged in different layers, and the scan lines and the data lines are arranged to cross each other to form a plurality of pixel areas; as well as A pixel electrode, wherein the pixel electrode is disposed in the pixel area, and the pixel electrode includes a first pixel electrode and a second pixel electrode; In two adjacent rows of pixel electrodes, the first pixel electrode is arranged in the Nth row, the second pixel electrode is arranged in the N+1th row, N is a positive integer, the first pixel electrode is connected to the data line through a first thin film transistor, and the second pixel electrode is connected to the data line through a second thin film transistor; In two adjacent rows of pixel areas, one of the data lines is connected to the input electrode of the first thin film transistor and the input electrode of the second thin film transistor at the same time, the first thin film transistor and the second thin film transistor are located on opposite sides of one of the data lines, and the overlapping area between the output electrode of the first thin film transistor and the gate of the first thin film transistor is smaller than the overlapping area between the output electrode of the second thin film transistor and the gate of the second thin film transistor; The extension section of the output electrode of the first thin film transistor overlaps with the protruding section of the scan line to form a compensation capacitor, and a padding portion is arranged between the extension section and the protruding section, and the padding portion is arranged to overlap with part of the extension section.

13. The display panel according to claim 12, wherein: The output electrode of the first thin film transistor includes an output main section, a first connecting section and the extension section which are connected in sequence, the first connecting section is connected to the first pixel electrode, the extension section is connected to a side of the first connecting section away from the output main section, the first thin film transistor also includes an active part, a part of the output main section is stacked on the active part, and the raised part and the active part are in the same layer and are arranged at intervals.

14. The display panel according to claim 13, wherein: The input electrode of the first thin film transistor includes a second connecting segment, a middle segment and a first side segment, one end of the second connecting segment is connected to the data line, the other end of the second connecting segment is connected to the middle segment, the middle segment is arranged opposite to the end of the output main segment, and the first side segment is connected to one side of the middle segment and is arranged opposite to one side surface of the output main segment; The array substrate further includes a first redundant portion overlapping the raised portion, the first redundant portion and the extending section being in the same layer and spaced apart, and the first redundant portion being opposite to a side surface of the extending section.

15. The display panel according to claim 14, wherein: The input electrode of the first thin film transistor also includes a second side segment, which is connected to the other side of the middle segment and is arranged opposite to the other side of the output main segment. The array substrate also includes a second redundant portion overlapping the raised portion, the second redundant portion is in the same layer as the extension segment and is arranged at an interval, and the second redundant portion is arranged opposite to the other side of the extension segment.

16. The display panel according to claim 15, wherein: The raised portion is insulated from the first redundant portion, the extending section and the second redundant portion respectively.

17. The display panel according to claim 16, wherein: The array substrate includes a substrate, a first insulating layer, a second insulating layer, and a third insulating layer. The scan line and the gate of the first thin film transistor are arranged on the substrate in the same layer. The first insulating layer covers the scan line and the gate of the first thin film transistor. The active part and the raised part are arranged on the first insulating layer. The second insulating layer covers the active part and the raised part. The data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part are arranged on the second insulating layer. The third insulating layer covers the data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part. The pixel electrode is arranged on the third insulating layer.

18. The display panel according to claim 15, wherein: The raised portion is connected to the first redundant portion, the extending section and the second redundant portion respectively.

19. The display panel according to claim 18, wherein: The array substrate includes a substrate, a first insulating layer and a second insulating layer, the scan line and the gate of the first thin film transistor are arranged on the substrate in the same layer, the first insulating layer covers the scan line and the gate of the first thin film transistor, the active part and the raised part are arranged on the first insulating layer, the input electrode and the output electrode of the first thin film transistor are connected and arranged on the active part, the extension section of the output electrode, the first redundant part and the second redundant part are connected and arranged on the raised part, the second insulating layer covers the data line, the input electrode and the output electrode of the first thin film transistor, the first redundant part and the second redundant part, and the pixel electrode is arranged on the second insulating layer.

20. The display panel according to claim 12, wherein: The extension direction of the output main section is parallel to or coincides with the extension direction of the extension section.

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