QR decomposition method and apparatus

Abstract

The present application provides a QR decomposition method and apparatus. The QR decomposition apparatus comprises a systolic array of computing units; the systolic array of computing units comprises A diagonal element processing units and AB-A(A-1) / 2 non-diagonal element processing units, wherein A is the number of processing units comprised in a column which has the maximum number of processing units and which is comprised in the systolic array of computing units, B is the number of processing units comprised in a row which has the maximum number of processing units and which is comprised in the systolic array of computing units, and A and B are integers greater than or equal to 1; each row in the systolic array of computing units comprises one diagonal element processing unit, and the i-th row comprises B-i non-diagonal element processing units, wherein i is any integer from 1 to A; the systolic array of computing units is used for decomposing a channel matrix into an R matrix and a QH matrix.

Description

QR decomposition method and device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202310957437.3 filed with the China Patent Office on July 31, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present application relate to, but are not limited to, the field of communication technology. Background Art

[0004] With the widespread adoption of Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) technologies in wireless communication systems, the computational complexity of baseband signal processing algorithms has increased exponentially. To ensure reliable communication with multiple users simultaneously and within the same frequency band, Multiple User Multiple Input Multiple Output (MU-MIMO) systems have become the preferred solution for future wireless communication systems. These new technologies place extremely high demands on baseband signal processors. In particular, MIMO and MU-MIMO technologies require baseband signal processors to perform real-time computations on large numbers of matrices for the first time. Massive MIMO, one of the most critical technologies for next-generation mobile communication systems, will introduce real-time computations on even larger matrices in baseband signal processing. Compared to current baseband signal processing matrix sizes, future baseband signal processing matrix sizes are expected to increase by tens or even hundreds of times, leading to a dramatic increase in the complexity of future wireless baseband signal processing.

[0005] MU-MIMO technology will become one of the key technologies in the baseband signal processing of most future wireless communications. Although it can increase spectrum efficiency and data rates exponentially, the introduction of MU-MIMO technology will greatly increase the complexity of baseband signal processing algorithms. The real-time calculation of these complex algorithms will seriously restrict the performance of future wireless communication systems.

[0006] QR decomposition is a key component of the renowned Tomlinson-Harashima (THP) precoding algorithm and the Standard Deviation (SD) algorithm. Its computational process inherently relies on data and iterates, making it a bottleneck in the baseband signal processing chain for MU-MIMO wireless communications. Current QR decomposition hardware results in significant hardware overhead.

[0007] Summary of the Invention

[0008] The embodiments of the present application provide a QR decomposition method and apparatus.

[0009] In a first aspect, an embodiment of the present application provides a QR decomposition device, comprising: a computing unit systolic array; wherein the computing unit systolic array comprises: A diagonal element processing units and AB-A(A-1) / 2 off-diagonal element processing units; wherein A is the number of processing units contained in the column with the largest number of processing units contained in the computing unit systolic array, and B is the number of processing units contained in the row with the largest number of processing units contained in the computing unit systolic array, and A and B are integers greater than or equal to 1; wherein each row in the computing unit systolic array comprises 1 of the diagonal element processing units, and the i-th row comprises Bi of the off-diagonal element processing units; wherein i is any integer from 1 to A; the computing unit systolic array is used to realize the decomposition of the channel matrix into an R matrix and a Q matrix. H matrix.

[0010] In a second aspect, the embodiment of the present application provides a QR decomposition method, comprising: decomposing the channel matrix into an R matrix and a Q matrix by a systolic array of computing units. H A matrix; wherein the computing unit systolic array includes: A diagonal element processing units and AB-A(A-1) / 2 off-diagonal element processing units; wherein A is the number of processing units contained in the column with the largest number of processing units contained in the computing unit systolic array, and B is the number of processing units contained in the row with the largest number of processing units contained in the computing unit systolic array, and A and B are integers greater than or equal to 1; wherein each row in the computing unit systolic array includes one of the diagonal element processing units, and the i-th row includes Bi of the off-diagonal element processing units; wherein i is any integer from 1 to A. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a block diagram of a QR decomposition device provided in an embodiment of the present application;

[0012] FIG2 is a schematic diagram of a QR decomposition device provided in an embodiment of the present application, including two systolic subarrays of computing units;

[0013] FIG3 is a diagram of a systolic subarray of computing units provided in an embodiment of the present application for decomposing two or more channel matrices into corresponding R matrices and Q H Schematic diagram of the matrix;

[0014] FIG4 is a block diagram of a diagonal element processing unit according to an embodiment of the present application;

[0015] FIG5 is a block diagram of a non-diagonal element processing unit according to an embodiment of the present application;

[0016] FIG6 is a block diagram of a computing subunit according to an embodiment of the present application;

[0017] FIG7 is a block diagram of a computing subunit according to an embodiment of the present application;

[0018] FIG8 is a flowchart of the QR decomposition method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solution of the present application, the QR decomposition method and device provided by the present application are described in detail below with reference to the accompanying drawings.

[0020] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the scope of this application to those skilled in the art.

[0021] In the absence of conflict, the various embodiments of the present application and the various features therein may be combined with each other.

[0022] As used herein, the term "and / or" includes any and all combinations of at least one of the associated listed items.

[0023] The terms used herein are used only to describe specific embodiments and are not intended to limit this application. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of at least one other feature, whole, step, operation, element, component, and / or group thereof is not excluded.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0025] In a wireless communication network, when a communication device performs wireless communication, the receiving device needs to perform signal detection based on the received signal to obtain a transmitted signal. The signal detection process includes a QR decomposition process. Therefore, the QR decomposition method of an embodiment of the present application can be applied to any receiving device, and the receiving device may include a QR decomposition device.

[0026] FIG1 is a block diagram of the QR decomposition device provided in an embodiment of the present application.

[0027] In a first aspect, referring to FIG1 , an embodiment of the present application provides a QR decomposition apparatus, comprising: a computing unit systolic array 101; wherein the computing unit systolic array 101 comprises: A diagonal element processing units and AB-A(A-1) / 2 off-diagonal element processing units; wherein A is the number of processing units included in the column with the largest number of processing units in the computing unit systolic array, and B is the number of processing units included in the row with the largest number of processing units in the computing unit systolic array, and A and B are integers greater than or equal to 1; wherein each row in the computing unit systolic array comprises one diagonal element processing unit, and the i-th row comprises Bi off-diagonal element processing units; wherein i is any integer from 1 to A; the computing unit systolic array is used to decompose a channel matrix into an R matrix and a Q matrix. H matrix.

[0028] In some exemplary embodiments, the diagonal element processing units are R11, R21, Rx1, Rn1, etc. in FIG. 1 .

[0029] In some exemplary embodiments, the non-diagonal element processing units are such as R12,…, R1n, R22,…, R2(n-1), Rx2,…, Rx(n-x+1), Q11, Q12,…, Q1m, Q21, Q22,…, Q2m, Qx1, Qx2,…, Qxm, Qn1, Qn2,…, Qnm, etc. in Figure 1.

[0030] In some exemplary embodiments, the computation unit systolic array includes at least one computation unit systolic subarray; each computation unit systolic subarray is configured to decompose at least one channel matrix into corresponding R matrices and Q matrices. HA matrix; wherein the computing unit systolic subarray includes n diagonal element processing units and (m+n)nn(n-1) / 2 off-diagonal element processing units; wherein n is the number of processing units included in the column with the largest number of processing units in the computing unit systolic subarray, and m+n is the number of processing units included in the row with the largest number of processing units in the computing unit systolic subarray; n is less than or equal to A, and m+n is less than or equal to B; wherein each row in the computing unit systolic subarray includes one diagonal element processing unit, and the j1th row includes m-j1 off-diagonal element processing units; wherein j1 is any integer from 1 to n.

[0031] As shown in FIG1 , the computing unit systolic array can be considered to include one computing unit systolic sub-array.

[0032] FIG2 shows a schematic diagram of a computing unit systolic array including two computing unit systolic subarrays as an example. As shown in FIG2, assuming that the two computing unit systolic subarrays are computing unit systolic subarray 1 and computing unit systolic subarray 2, then computing unit systolic subarray 1 is used to decompose the channel matrix H into the corresponding R0 matrix and Q0 matrix. H Matrix, the computational unit systolic subarray 2 is used to decompose the channel matrix A into the corresponding R1 matrix and Q1 H matrix.

[0033] In some exemplary embodiments, m is the number of rows of the channel matrix, and n is the number of columns of the channel matrix.

[0034] In some exemplary embodiments, as shown in FIG1 , a systolic subarray in a computing unit is used to implement the decomposition of a channel matrix into corresponding R matrices and Q H In the case of a channel matrix, the diagonal element processing units in the first row processing units in the systolic subarray of the computing unit are used to perform real number processing and elimination processing on the first column elements of the channel matrix.

[0035] The k1th off-diagonal element processing unit in the 1st row of processing units in the systolic subarray of the computing unit is used to perform equivalent real number processing and equivalent elimination processing on the k1+1th column elements of the channel matrix, and send the 2nd row elements to the nth row elements in the processed k1+1th column elements to the k1th processing unit in the 2nd row of processing units; where k1 is any integer from 1 to n-1.

[0036] The diagonal element processing units in the j2-th row processing units in the computational unit systolic subarray are used to perform real number processing and elimination processing on the elements in the second row to the n-j2+1-th row of column elements processed by the first off-diagonal element processing unit in the j2-1-th row; where j2 is any integer from 2 to n.

[0037] The k2th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the k2+1th non-diagonal element processing unit in the j2-1th row, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k2th processing unit in the j2+1th row processing unit; where k2 is any integer from 1 to n-j2.

[0038] The k3th off-diagonal element processing unit in the first row of processing units in the systolic subarray of the computing unit is used to perform equivalent real number processing and equivalent elimination processing on the k3-nth column elements of the identity matrix, and send the processed second row elements to the nth row elements in the k3-nth column elements to the k3-1th processing unit in the second row of processing units; where k3 is any integer from n+1 to m+n.

[0039] The k4th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the k4+1th non-diagonal element processing unit in the j2-1th row, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k4-1th processing unit in the j2+1th row processing unit; where k4 is any integer from n-j2+1 to m+n-j2+1.

[0040] In some exemplary embodiments, as shown in FIG3 , a systolic subarray in a computing unit is used to decompose two or more channel matrices into corresponding R matrices and Q matrices. H In the case of a matrix, the diagonal element processing unit in the first row processing unit in the systolic subarray of the computing unit is used to perform real number processing and elimination processing on the first column elements of two or more channel matrices in a time division multiplexing manner.

[0041] The k1th off-diagonal element processing unit in the first row of processing units in the systolic subarray of the computing unit is used to perform equivalent real number processing and equivalent elimination processing on the k1+1th column elements of two or more channel matrices in a time division multiplexing manner, and send the processed second row elements to the nth row elements in the k1+1th column elements to the k1th processing unit in the second row of processing units; where k1 is any integer between 1 and n-1.

[0042] The diagonal element processing units in the j2-th row processing units in the computational unit systolic subarray are configured to perform real number conversion and elimination processing on the elements in the second row to the n-j2+1-th row of column elements processed by two or more first off-diagonal element processing units in the j2-1-th row, using a time division multiplexing method; wherein j2 is any integer between 2 and n.

[0043] The k2-th non-diagonal element processing unit in the j2-th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2-th row elements to the n-j2+1-th row elements in the column elements processed by two or more j2-1-th row k2+1-th non-diagonal element processing units in a time division multiplexing manner, and send the 2-th row elements to the n-j2+1-th row elements in the processed column elements to the k2-th processing unit in the j2+1-th row processing unit; where k2 is any integer from 1 to n-j2.

[0044] The k3th off-diagonal element processing unit in the first row of processing units in the systolic subarray of the computing unit is used to perform equivalent real number processing and equivalent elimination processing on the k3-nth column elements of two or more unit matrices in a time division multiplexing manner, and send the processed second row elements to the nth row elements in the k3-nth column elements to the k3-1th processing unit in the second row of processing units; where k3 is any integer from n+1 to m+n.

[0045] The k4th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by two or more j2-1th row k4+1th non-diagonal element processing units in a time division multiplexing manner, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k4-1th processing unit in the j2+1th row processing unit; where k4 is any integer from n-j2+1 to m+n-j2+1.

[0046] In some exemplary embodiments, the QR decomposition device further includes: a controller configured to input the k5th column element of the channel matrix to the k5th processing unit in the first row of processing units; wherein k5 is any integer from 1 to n; and input the k6-nth column element in the identity matrix to the k6th processing unit in the first row of processing units; wherein k6 is any integer from n+1 to m+n.

[0047] In some exemplary embodiments, when the diagonal element processing units in the 1st row processing units in the computing unit systolic subarray perform real number processing on the 1st column elements of the channel matrix, the controller sequentially inputs the 1st column elements of the channel matrix from the 1st row elements to the mth row elements to the diagonal element processing units in the 1st row processing units, one element at a time.

[0048] In some exemplary embodiments, when the diagonal element processing units in the 1st row processing units in the systolic subarray of the computing units perform elimination processing on the 1st column elements of the channel matrix, the diagonal element processing units in the 1st row processing units perform real number processing on the 1st row elements and the 2nd row elements in the 1st column elements, and then perform elimination processing based on the real number processed 1st row elements and the real number processed 2nd row elements, that is, the real number processed 2nd row elements are changed to 0; after the diagonal element processing units in the 1st row processing units perform real number processing on the 1st row elements and the 3rd row elements in the 1st column elements, they perform elimination processing based on the real number processed 1st row elements and the real number processed 3rd row elements, that is, the real number processed 3rd row elements are changed to 0; and so on, until the real number processed mth row elements are changed to 0.

[0049] In some exemplary embodiments, the diagonal element processing unit in the first row processing unit in the systolic subarray of the computing unit performs real number processing on each element in the first column of the channel matrix using a coordinate rotation digital computer (CORDIC) algorithm to perform real number processing on each element, that is, using the formula x n+1 =x n cosθ-y n sinθ and y n+1 =y n cosθ+x n sinθ calculates the coordinates after each rotation, where (x n+1 ,y n+1 ) is the coordinate after the nth rotation, (x n ,y n ) is the coordinate before the nth rotation, θ is the angle of rotation, and during the first rotation, the real part of the element to be processed is used as the y value and the imaginary part is used as the x value.

[0050] In some exemplary embodiments, the formula x may also be used. n+1 =x n -y n tanθ and y n+1 =y n +x n tanθ calculates the coordinates after each rotation.

[0051] In some exemplary embodiments, when performing elimination processing based on the first row elements after real number processing and the third row elements after real number processing, the CORDIC algorithm can be used for elimination processing, that is, using the formula x n+1 =x n cosθ-y n sinθ and y n+1 =y n cosθ+x n sinθ calculates the coordinates after each rotation, where (x n+1 ,y n+1 ) is the coordinate after the nth rotation, (x n ,y n ) is the coordinate before the nth rotation, θ is the rotation angle, and during the first rotation, the first row of elements after the real numbering process is used as the y value, and the third row of elements after the real numbering process is used as the x value. The rest of the elimination process is similar and will not be repeated here.

[0052] In some exemplary embodiments, the formula x may also be used. n+1 =x n -y n tanθ and y n+1 =y n +x n tanθ calculates the coordinates after each rotation.

[0053] In some exemplary embodiments, during the real number conversion and elimination processes, the angle θ of each rotation is sent to the next non-diagonal element processing unit.

[0054] In some exemplary embodiments, the non-diagonal element processing unit performs equivalent real number processing and equivalent elimination processing according to the received rotation angle θ, that is, performs the same processing as the real number processing and elimination processing on the received elements.

[0055] In some exemplary embodiments, as shown in FIG4 , the diagonal element processing unit includes: a realization subunit 401 configured to perform realization processing on each input element; and an elimination subunit 402 configured to perform elimination processing on each element after realization processing.

[0056] As shown in FIG5 , the off-diagonal element processing unit includes: an equivalent real numbering subunit 501 configured to perform equivalent real numbering on each input element; and an equivalent elimination subunit 502 configured to perform equivalent elimination on each element after equivalent real numbering.

[0057] In some exemplary embodiments, any one of the real digitization subunit, the elimination subunit, the equivalent real digitization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; wherein, as shown in FIG6 , a set of calculation subunits includes: four multipliers, one adder, and one subtractor.

[0058] Among them, the two input terminals of multiplier 1 are connected to cosθ and x n The output terminal is connected to one input terminal of the subtractor, and the two input terminals of the multiplier 2 are connected to sinθ and y n The output is connected to the other input of the subtractor, and the subtractor outputs x n+1 .

[0059] The two input terminals of multiplier 3 are connected to cosθ and y n The output terminal is connected to one input terminal of the adder, and the two input terminals of the multiplier 4 are connected to sinθ and x n The output is connected to the other input of the adder, and the adder outputs y n+1 .

[0060] In some exemplary embodiments, any one of the real digitization subunit, the elimination subunit, the equivalent real digitization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; wherein, as shown in Figure 7, a set of calculation subunits includes: two shifters, an adder, a subtractor, and at least one multiplier (not shown).

[0061] Among them, the input of shifter 1 is connected to y n The output is connected to one input of the subtractor, and the other input of the subtractor is connected to x n Connection, subtractor output x n+1 .

[0062] The input of shifter 2 is connected to x n The output is connected to one input of the adder, and the other input of the adder is connected to y n Connect, adder output y n+1 .

[0063] The QR decomposition device provided in the embodiment of the present application implements QR decomposition based on a systolic array of computing units, thereby reducing hardware implementation overhead.

[0064] FIG8 is a flowchart of the QR decomposition method provided in an embodiment of the present application.

[0065] In the second aspect, referring to FIG8 , the embodiment of the present application provides a QR decomposition method, comprising: step 800, decomposing the channel matrix into an R matrix and a Q matrix by a systolic array of computing units. H matrix.

[0066] The computing unit systolic array includes: A diagonal element processing units and AB-A(A-1) / 2 off-diagonal element processing units; wherein A is the number of processing units included in the column with the largest number of processing units in the computing unit systolic array, B is the number of processing units included in the row with the largest number of processing units in the computing unit systolic array, and A and B are integers greater than or equal to 1.

[0067] Each row in the systolic array of computing units includes one diagonal element processing unit, and the i-th row includes Bi non-diagonal element processing units; wherein i is any integer from 1 to A.

[0068] In some exemplary embodiments, the diagonal element processing units are R11, R21, Rx1, Rn1, etc. in FIG. 1 .

[0069] In some exemplary embodiments, the non-diagonal element processing units are such as R12,…, R1n, R22,…, R2(n-1), Rx2,…, Rx(n-x+1), Q11, Q12,…, Q1m, Q21, Q22,…, Q2m, Qx1, Qx2,…, Qxm, Qn1, Qn2,…, Qnm, etc. in Figure 1.

[0070] In some exemplary embodiments, the computing unit systolic array includes at least one computing unit systolic sub-array.

[0071] The channel matrix is ​​decomposed into R matrix and Q matrix by computing unit systolic array. H The matrix includes: decomposing at least one channel matrix into corresponding R matrix and Q matrix respectively through each computing unit systolic subarray H matrix.

[0072] The computing unit systolic subarray includes n diagonal element processing units and (m+n)nn(n-1) / 2 off-diagonal element processing units; wherein n is the number of processing units included in the column with the largest number of processing units included in the computing unit systolic subarray, and m+n is the number of processing units included in the row with the largest number of processing units included in the computing unit systolic subarray; n is less than or equal to A, and m+n is less than or equal to B.

[0073] Each row in the systolic subarray of computing units includes one diagonal element processing unit, and the j1th row includes m-j1 off-diagonal element processing units; wherein j1 is any integer from 1 to n.

[0074] As shown in FIG1 , the computing unit systolic array can be considered to include one computing unit systolic sub-array.

[0075] FIG2 shows a schematic diagram of a computing unit systolic array including two computing unit systolic subarrays as an example. As shown in FIG2, assuming that the two computing unit systolic subarrays are computing unit systolic subarray 1 and computing unit systolic subarray 2, then computing unit systolic subarray 1 is used to decompose the channel matrix H into the corresponding R0 matrix and Q0 matrix. H Matrix, the computational unit systolic subarray 2 is used to decompose the channel matrix A into the corresponding R1 matrix and Q1 H matrix.

[0076] In some exemplary embodiments, m is the number of rows of the channel matrix, and n is the number of columns of the channel matrix.

[0077] In some exemplary embodiments, as shown in FIG1 , a systolic subarray in a computing unit is used to implement the decomposition of a channel matrix into corresponding R matrices and Q H In the case of a matrix, at least one channel matrix is ​​decomposed into corresponding R matrices and Q matrices by each computational unit systolic subarray. H The matrix includes: a diagonal element processing unit in a first row processing unit in a systolic subarray of a computing unit performs real number processing and elimination processing on a first column element of the channel matrix.

[0078] The k1th non-diagonal element processing unit in the 1st row processing unit in the systolic subarray of the computing unit performs equivalent real number processing and equivalent elimination processing on the k1+1th column element of the channel matrix, and sends the 2nd row element to the nth row element in the processed k1+1th column element to the k1th processing unit in the 2nd row processing unit; where k1 is any integer from 1 to n-1.

[0079] The diagonal element processing units in the j2-th row processing units in the computational unit systolic subarray perform real number conversion and elimination on the elements in the second row to the n-j2+1-th row of the column elements processed by the first off-diagonal element processing unit in the j2-1-th row; where j2 is any integer from 2 to n.

[0080] The k2th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray performs equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the k2+1th non-diagonal element processing unit in the j2-1th row, and sends the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k2th processing unit in the j2+1th row processing unit; where k2 is any integer from 1 to n-j2.

[0081] The k3th off-diagonal element processing unit in the first row of processing units in the systolic subarray of the computing unit performs equivalent real number conversion and equivalent elimination on the k3-nth column elements of the identity matrix, and sends the processed elements from the second row to the nth row elements in the k3-nth column elements to the k3-1th processing unit in the second row of processing units; where k3 is any integer from n+1 to m+n.

[0082] The k4th off-diagonal element processing unit in the j2th row processing unit in the computational unit systolic subarray performs equivalent real number conversion and equivalent elimination on the elements in the second row to the n-j2+1th row of column elements processed by the k4+1th off-diagonal element processing unit in the j2-1th row, and sends the elements in the second row to the n-j2+1th row of the processed column elements to the k4-1th processing unit in the j2+1th row of processing units; where k4 is any integer from n-j2+1 to m+n-j2+1.

[0083] In some exemplary embodiments, as shown in FIG3 , a systolic subarray in a computing unit is used to decompose two or more channel matrices into corresponding R matrices and Q matrices. H In the case of a matrix, at least one channel matrix is ​​decomposed into corresponding R matrices and Q matrices by each computational unit systolic subarray. H The matrix includes:

[0084] The diagonal element processing units in the first row processing units in the systolic subarray of the computing unit perform real number processing and elimination processing on the first column elements of two or more channel matrices in a time division multiplexing manner.

[0085] The k1th off-diagonal element processing unit in the first row of processing units in the systolic subarray of the computing unit performs equivalent real number processing and equivalent elimination processing on the k1+1th column elements of two or more channel matrices in a time division multiplexing manner, and sends the processed second row elements to the nth row elements in the k1+1th column elements to the k1th processing unit in the second row of processing units; where k1 is any integer from 1 to n-1.

[0086] The diagonal element processing units in the j2-th row processing units in the computational unit systolic subarray perform real number conversion and elimination on the elements in the second row to the n-j2+1-th row of column elements processed by two or more first off-diagonal element processing units in the j2-1-th row, using a time division multiplexing method; where j2 is any integer from 2 to n.

[0087] The k2-th non-diagonal element processing unit in the j2-th row processing unit in the computing unit systolic subarray uses a time division multiplexing method to perform equivalent real number processing and equivalent elimination processing on the 2-th row elements to the n-j2+1-th row elements in the column elements processed by two or more j2-1-th row k2+1-th non-diagonal element processing units, and sends the 2-th row elements to the n-j2+1-th row elements in the processed column elements to the k2-th processing unit in the j2+1-th row processing unit; where k2 is any integer from 1 to n-j2.

[0088] The k3th off-diagonal element processing unit in the first row of processing units in the systolic subarray of the computing unit performs equivalent real number processing and equivalent elimination processing on the k3-nth column elements of two or more unit matrices in a time division multiplexing manner, and sends the processed second row elements to the nth row elements in the k3-nth column elements to the k3-1th processing unit in the second row of processing units; where k3 is any integer from n+1 to m+n.

[0089] The k4th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray uses a time division multiplexing method to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by two or more j2-1th row k4+1th non-diagonal element processing units, and sends the processed 2nd row elements to the n-j2+1th row elements in the column elements to the k4-1th processing unit in the j2+1th row processing unit; where k4 is any integer from n-j2+1 to m+n-j2+1.

[0090] In some exemplary embodiments, it also includes: the controller inputs the k5th column element of the channel matrix to the k5th processing unit in the 1st row processing unit; wherein k5 is any integer from 1 to n; and inputs the k6-nth column element in the unit matrix to the k6th processing unit in the 1st row processing unit; wherein k6 is any integer from n+1 to m+n.

[0091] In some exemplary embodiments, when the diagonal element processing units in the 1st row processing units in the computing unit systolic subarray perform real number processing on the 1st column elements of the channel matrix, the controller sequentially inputs the 1st column elements of the channel matrix from the 1st row elements to the mth row elements to the diagonal element processing units in the 1st row processing units, one element at a time.

[0092] In some exemplary embodiments, when the diagonal element processing units in the 1st row processing units in the systolic subarray of the computing units perform elimination processing on the 1st column elements of the channel matrix, the diagonal element processing units in the 1st row processing units perform real number processing on the 1st row elements and the 2nd row elements in the 1st column elements, and then perform elimination processing based on the real number processed 1st row elements and the real number processed 2nd row elements, that is, the real number processed 2nd row elements are changed to 0; after the diagonal element processing units in the 1st row processing units perform real number processing on the 1st row elements and the 3rd row elements in the 1st column elements, they perform elimination processing based on the real number processed 1st row elements and the real number processed 3rd row elements, that is, the real number processed 3rd row elements are changed to 0; and so on, until the real number processed mth row elements are changed to 0.

[0093] In some exemplary embodiments, the diagonal element processing unit in the first row processing unit in the systolic subarray of the computing unit performs real number processing on each element in the first column of the channel matrix using a coordinate rotation digital computer (CORDIC) algorithm to perform real number processing on each element, that is, using the formula x n+1 =x n cosθ-y n sinθ and y n+1 =y n cosθ+x n sinθ calculates the coordinates after each rotation, where (x n+1 ,y n+1 ) is the coordinate after the nth rotation, (x n ,y n ) is the coordinate before the nth rotation, θ is the angle of rotation, and during the first rotation, the real part of the element to be processed is used as the y value and the imaginary part is used as the x value.

[0094] In some exemplary embodiments, the formula x may also be used. n+1 =x n -y n tanθ and y n+1 =y n +x n tanθ calculates the coordinates after each rotation.

[0095] In some exemplary embodiments, when performing elimination processing based on the first row elements after real number processing and the third row elements after real number processing, the CORDIC algorithm can be used for elimination processing, that is, using the formula x n+1 =x n cosθ-y n sinθ and yn+1 =y n cosθ+x n sinθ calculates the coordinates after each rotation, where (x n+1 ,y n+1 ) is the coordinate after the nth rotation, (x n ,y n ) is the coordinate before the nth rotation, θ is the rotation angle, and during the first rotation, the first row of elements after the real numbering process is used as the y value, and the third row of elements after the real numbering process is used as the x value. The rest of the elimination process is similar and will not be repeated here.

[0096] In some exemplary embodiments, the formula x may also be used. n+1 =x n -y n tanθ and y n+1 =y n +x n tanθ calculates the coordinates after each rotation.

[0097] In some exemplary embodiments, during the real number conversion and elimination processes, the angle θ of each rotation is sent to the next non-diagonal element processing unit.

[0098] In some exemplary embodiments, the non-diagonal element processing unit performs equivalent real number processing and equivalent elimination processing according to the received rotation angle θ, that is, performs the same processing as the real number processing and elimination processing on the received elements.

[0099] In some exemplary embodiments, as shown in FIG4 , the diagonal element processing unit includes: a realization subunit 401 configured to perform realization processing on each input element; and an elimination subunit 402 configured to perform elimination processing on each element after realization processing.

[0100] As shown in FIG5 , the off-diagonal element processing unit includes: an equivalent real numbering subunit 501 configured to perform equivalent real numbering on each input element; and an equivalent elimination subunit 502 configured to perform equivalent elimination on each element after equivalent real numbering.

[0101] In some exemplary embodiments, any one of the real digitization subunit, the elimination subunit, the equivalent real digitization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; wherein, as shown in FIG6 , a set of calculation subunits includes: four multipliers, one adder, and one subtractor.

[0102] Among them, the two input terminals of multiplier 1 are connected to cosθ and x nThe output terminal is connected to one input terminal of the subtractor, and the two input terminals of the multiplier 2 are connected to sinθ and y n The output is connected to the other input of the subtractor, and the subtractor outputs x n+1 .

[0103] The two input terminals of multiplier 3 are connected to cosθ and y n The output terminal is connected to one input terminal of the adder, and the two input terminals of the multiplier 4 are connected to sinθ and x n The output is connected to the other input of the adder, and the adder outputs y n+1 .

[0104] In some exemplary embodiments, any one of the real digitization subunit, the elimination subunit, the equivalent real digitization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; wherein, as shown in Figure 7, a set of calculation subunits includes: two shifters, an adder, a subtractor, and at least one multiplier (not shown).

[0105] Among them, the input of shifter 1 is connected to y n The output is connected to one input of the subtractor, and the other input of the subtractor is connected to x n Connection, subtractor output x n+1 .

[0106] The input of shifter 2 is connected to x n The output is connected to one input of the adder, and the other input of the adder is connected to y n Connect, adder output y n+1 .

[0107] The QR decomposition method provided in the embodiment of the present application implements QR decomposition based on a systolic array of computing units, thereby reducing hardware implementation overhead.

[0108] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0109] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present application as set forth in the appended claims.

Claims

1. A QR decomposition device, comprising: a systolic array of computing units; The computing unit systolic array includes: A diagonal element processing units and AB-A(A-1) / 2 off-diagonal element processing units; wherein A is the number of processing units in the column with the largest number of processing units in the computing unit systolic array, B is the number of processing units in the row with the largest number of processing units in the computing unit systolic array, and A and B are integers greater than or equal to 1; Each row of the computing unit systolic array includes one diagonal element processing unit, and the i-th row includes Bi non-diagonal element processing units; wherein i is any integer from 1 to A; The computing unit systolic array is used to decompose the channel matrix into an R matrix and a Q H matrix.

2. The QR decomposition device according to claim 1, wherein: The computing unit systolic array includes at least one computing unit systolic subarray; Each of the systolic subarrays of the computing units is used to decompose at least one channel matrix into corresponding R matrices and Q matrices. H matrix; The computing unit systolic subarray includes n diagonal element processing units and (m+n)nn(n-1) / 2 off-diagonal element processing units; wherein n is the number of processing units in the column with the largest number of processing units in the computing unit systolic subarray, and m+n is the number of processing units in the row with the largest number of processing units in the computing unit systolic subarray; n is less than or equal to A, and m+n is less than or equal to B; Each row of the computing unit systolic subarray includes one diagonal element processing unit, and the j1th row includes m-j1 non-diagonal element processing units; wherein j1 is any integer from 1 to n.

3. The QR decomposition device according to claim 2, wherein: In a computing unit, the systolic subarray is used to implement the decomposition of a channel matrix into corresponding R matrices and Q H In the case of a matrix, the diagonal element processing unit in the first row processing unit in the systolic subarray of the computing unit is used to perform real number processing and elimination processing on the first column elements of the channel matrix; The k1th non-diagonal element processing unit in the 1st row processing unit in the systolic subarray of the computing unit is used to perform equivalent real number processing and equivalent elimination processing on the k1+1th column elements of the channel matrix, and send the processed 2nd row elements to the nth row elements in the k1+1th column elements to the k1th processing unit in the 2nd row processing unit; wherein k1 is any integer from 1 to n-1; The diagonal element processing unit in the j2-th row processing unit in the computing unit systolic subarray is used to perform real number processing and elimination processing on the elements in the second row to the n-j2+1-th row of the column elements processed by the first non-diagonal element processing unit in the j2-1-th row; wherein j2 is any integer from 2 to n; The k2th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the k2+1th non-diagonal element processing unit in the j2-1th row, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k2th processing unit in the j2+1th row processing unit; wherein k2 is any integer from 1 to n-j2; The k3th off-diagonal element processing unit in the first row of processing units in the systolic subarray of the computational unit Used to perform equivalent real number processing and equivalent elimination processing on the k3-nth column elements of the identity matrix, and send the 2nd row elements to the nth row elements in the processed k3-nth column elements to the k3-1th processing unit in the 2nd row processing unit; wherein k3 is any integer from n+1 to m+n; The k4th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the k4+1th non-diagonal element processing unit in the j2-1th row, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k4-1th processing unit in the j2+1th row processing unit; wherein k4 is any integer from n-j2+1 to m+n-j2+1.

4. The QR decomposition device according to claim 2, wherein: In one of the computing units, the systolic subarray is used to decompose two or more channel matrices into corresponding R matrices and Q H In the case of a matrix, the diagonal element processing unit in the first row processing unit in the systolic subarray of the computing unit is used to perform real number processing and elimination processing on the first column elements of two or more channel matrices in a time division multiplexing manner; The k1th non-diagonal element processing unit in the 1st row processing unit in the systolic subarray of the computing unit is used to perform equivalent real number processing and equivalent elimination processing on the k1+1th column elements of two or more channel matrices in a time division multiplexing manner, and send the processed 2nd row elements to the nth row elements in the k1+1th column elements to the k1th processing unit in the 2nd row processing unit; wherein k1 is any integer from 1 to n-1; The diagonal element processing unit in the j2-th row processing unit in the computing unit systolic subarray is used to perform real number processing and elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by the first non-diagonal element processing unit in the j2-1-th row in a time division multiplexing manner; wherein j2 is any integer from 2 to n; The k2th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by two or more j2-1th row k2+1th non-diagonal element processing units in a time division multiplexing manner, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k2th processing unit in the j2+1th row processing unit; wherein k2 is any integer from 1 to n-j2; The k3th non-diagonal element processing unit in the 1st row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the k3-nth column elements of two or more unit matrices in a time division multiplexing manner, and send the processed 2nd row elements to the nth row elements in the k3-nth column elements to the k3-1th processing unit in the 2nd row processing unit; wherein k3 is any integer from n+1 to m+n; The k4th non-diagonal element processing unit in the j2th row processing unit in the computing unit systolic subarray is used to perform equivalent real number processing and equivalent elimination processing on the 2nd row elements to the n-j2+1th row elements in the column elements processed by two or more j2-1th row k4+1th non-diagonal element processing units in a time division multiplexing manner, and send the 2nd row elements to the n-j2+1th row elements in the processed column elements to the k4-1th processing unit in the j2+1th row processing unit; wherein k4 is any integer from n-j2+1 to m+n-j2+1.

5. The QR decomposition device according to any one of claims 3 to 4, further comprising: The controller is configured to input the k5th column element of the channel matrix to the k5th processing unit in the first row of processing units; wherein k5 is any integer from 1 to n; and input the k6-nth column element of the identity matrix to the k5th processing unit in the first row of processing units. Input to the k6th processing unit in the first row of processing units; wherein k6 is any integer from n+1 to m+n.

6. The QR decomposition device according to any one of claims 3 to 4, wherein: The diagonal element processing unit comprises: A real numbering subunit, configured to perform real numbering on each input element; an elimination subunit, configured to perform elimination processing on each element after the real number processing; The off-diagonal element processing unit comprises: An equivalent real numbering subunit is configured to perform equivalent real numbering processing on each input element; The equivalent elimination subunit is configured to perform equivalent elimination processing on each element after the equivalent real number processing.

7. The QR decomposition device according to claim 6, wherein: Any one of the realization subunit, the elimination subunit, the equivalent realization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; Among them, a set of the computing subunits includes: four multipliers, an adder, and a subtractor.

8. The QR decomposition device according to claim 6, wherein: Any one of the realization subunit, the elimination subunit, the equivalent realization subunit, and the equivalent elimination subunit includes at least one set of calculation subunits; Among them, a set of the computing subunits includes: two shifters, an adder, a subtractor, and at least one multiplier.

9. A QR decomposition method, comprising: The channel matrix is ​​decomposed into R matrix and Q matrix by computing unit systolic array. H matrix; The computing unit systolic array includes: A diagonal element processing units and AB-A(A-1) / 2 off-diagonal element processing units; wherein A is the number of processing units in the column with the largest number of processing units in the computing unit systolic array, B is the number of processing units in the row with the largest number of processing units in the computing unit systolic array, and A and B are integers greater than or equal to 1; Each row in the computing unit systolic array includes one diagonal element processing unit, and the i-th row includes Bi non-diagonal element processing units; wherein i is any integer from 1 to A.

10. The QR decomposition method according to claim 9, wherein: The computing unit systolic array includes at least one computing unit systolic subarray; The channel matrix is ​​decomposed into R matrix and Q matrix by computing unit systolic array. H The matrix includes: At least one channel matrix is ​​decomposed into corresponding R matrix and Q matrix by each of the systolic subarrays of the computing unit. H matrix; The computing unit systolic subarray includes n diagonal element processing units and (m+n)nn(n-1) / 2 off-diagonal element processing units; wherein n is the number of processing units in the column with the largest number of processing units in the computing unit systolic subarray, and m+n is the number of processing units in the row with the largest number of processing units in the computing unit systolic subarray; n is less than or equal to A, and m+n is less than or equal to B; Each row of the computing unit systolic subarray includes one diagonal element processing unit, and the j1th row includes m-j1 non-diagonal element processing units; wherein j1 is any integer from 1 to n.

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