Display substrate and preparation method therefor, and display apparatus

Abstract

A display substrate and a preparation method therefor, and a display apparatus, which relate to, but are not limited to, the technical field of display. The display substrate comprises: an active layer (12), which is disposed on one side of a base (101) and comprises a channel region; a grid electrode (13), which is disposed on the side of the active layer (12) far away from the base (101) and at least part of which is overlapped with the orthographic projection of the channel region on the base (101); and a light-shielding layer (11), which is disposed on the side of the active layer (12) close to the base (101) and at least part of which is overlapped with the orthographic projection of the channel region on the base (101).

Description

Display substrate, manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310967015.4 and invention name “A display substrate, its preparation method, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically to a display substrate and a method for preparing the same, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] As users' demands for products such as narrow bezels and high PPI continue to increase, higher requirements are placed on the performance of thin film transistor (TFT) devices. At present, the semiconductor materials in TFT devices generally use amorphous silicon (a-Si), metal oxides (such as IGZO) and low-temperature polycrystalline silicon (LTPS). The effective mobility of metal oxides is low compared to that of low-temperature polycrystalline silicon. In order to improve the mobility of metal oxide materials, solutions such as increasing the indium (In) content in metal oxides, removing zinc (Zn) in metal oxides, or adding tin (Sn) elements to metal oxides are generally adopted to improve the mobility of metal oxide materials. However, the band gap width of high-mobility metal oxide materials is small and they are highly sensitive to light.

[0005] Summary of the Invention

[0006] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0007] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0008] an active layer disposed on one side of the substrate, wherein the active layer includes a channel region;

[0009] a gate, disposed on a side of the active layer away from the substrate, wherein at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate;

[0010] A light shielding layer is provided on a side of the active layer close to the substrate, and at least a portion of the light shielding layer overlaps with an orthographic projection of the channel region on the substrate.

[0011] In an exemplary embodiment, the gate includes a main portion and a protrusion disposed on the main portion, the protrusion overlaps an orthographic projection of the channel region on the substrate, and the main portion does not overlap an orthographic projection of the channel region on the substrate.

[0012] In an exemplary embodiment, a space is provided between an edge of the body portion on a side close to the channel region and an edge of the channel region on a side close to the body portion.

[0013] In an exemplary embodiment, the main body portion is in a strip shape, the active layer is in a strip shape, and an extending direction of the main body portion is substantially the same as an extending direction of the active layer.

[0014] In an exemplary embodiment, the protrusion has a block or bar shape.

[0015] In an exemplary embodiment, the active layer has a stripe shape, the active layer extends along the second direction, the gate has a stripe shape, the gate extends along a first direction, and the first direction intersects the second direction.

[0016] In an exemplary embodiment, the active layer further includes a first doping region and a second doping region, and the first doping region and the second doping region are connected through the channel region.

[0017] In an exemplary embodiment, a first electrode and a second electrode are further included, wherein the first electrode and the second electrode are both arranged on a side of the active layer away from the substrate, the first electrode is connected to the first doped region through a first via hole, and the second electrode is connected to the second doped region through a second via hole.

[0018] In an exemplary embodiment, a pixel electrode is further included. The pixel electrode is disposed on a side of the first electrode and the second electrode away from the substrate, and the pixel electrode is connected to the second electrode through a third via hole.

[0019] In an exemplary embodiment, the orthographic projections of the second via hole and the third via hole on the substrate overlap.

[0020] In an exemplary embodiment, an organic dielectric layer is further included. The organic dielectric layer is disposed between the pixel electrode and the second electrode. A fourth via hole is disposed in the organic dielectric layer. The orthographic projection of the third via hole on the substrate is located within the orthographic projection of the fourth via hole on the substrate.

[0021] In an exemplary embodiment, a common electrode is further included. The common electrode is disposed on a side of the pixel electrode close to the substrate, and the common electrode is connected to the pixel electrode through a fifth via hole.

[0022] In an exemplary embodiment, a touch electrode is further included. The touch electrode is disposed between the common electrode and the pixel electrode, and the touch electrode is connected to the pixel electrode through the fifth via hole.

[0023] In a second aspect, an embodiment of the present disclosure further provides a display device comprising the display substrate described above.

[0024] In a third aspect, the present disclosure also provides a method for preparing a display substrate, comprising:

[0025] forming a light-shielding layer on the substrate;

[0026] forming an active layer on a side of the light-shielding layer away from the substrate, wherein the active layer includes a channel region, and at least a portion of the light-shielding layer overlaps with an orthographic projection of the channel region on the substrate;

[0027] A gate is formed on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate.

[0028] In an exemplary embodiment, further comprising:

[0029] forming a second via hole and a second electrode on a side of the active layer away from the substrate, wherein the second via hole exposes the active layer, and the second electrode is connected to the active layer through the second via hole;

[0030] A third via hole and a pixel electrode are formed on a side of the second electrode away from the substrate, the third via hole exposes the second electrode, the pixel electrode is connected to the second electrode through the third via hole, and the second via hole and the third via hole have overlapping orthographic projections on the substrate.

[0031] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0033] FIG1 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] FIG2 is a schematic cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] FIG3 a is a schematic diagram of an exemplary embodiment of the present disclosure after a light shielding layer is formed in a display substrate preparation process;

[0036] FIG3 b is a schematic diagram of an exemplary embodiment of the present disclosure after an active layer is formed in a process of preparing a display substrate;

[0037] FIG3 c is a schematic diagram of an exemplary embodiment of the present disclosure after a gate is formed in a display substrate preparation process;

[0038] FIG3 d is a schematic diagram of a first electrode and a second electrode in a process of preparing a display substrate according to an exemplary embodiment of the present disclosure;

[0039] FIG3e is a schematic diagram of an exemplary embodiment of the present disclosure after forming a third inorganic dielectric layer, an organic dielectric layer, and a fourth via hole in a process of preparing a display substrate;

[0040] FIG3 f is a schematic diagram of an exemplary embodiment of the present disclosure after forming a common electrode in a display substrate preparation process;

[0041] FIG3g is a schematic diagram of a display substrate after touch electrodes are formed during preparation of the display substrate according to an exemplary embodiment of the present disclosure;

[0042] FIG3h is a schematic diagram of an exemplary embodiment of the present disclosure after forming a third via hole and a fifth via hole in a process of preparing a display substrate;

[0043] FIG4 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure;

[0044] FIG5 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0045] FIG6 is a schematic diagram of the planar structure of the gate in FIG5 ;

[0046] FIG7 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0047] FIG8 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0049] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0050] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0051] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0052] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0053] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0054] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0055] In this specification, "connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0056] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0057] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0058] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0059] Research by the inventors of this disclosure has revealed that the active layer in metal oxide thin film transistors (MOSTs) generally uses indium gallium zinc oxide (IGZO), which has the characteristics of good uniformity and high mobility. However, for MOSTs with a top-gate structure, since the backlight source is on the lower side of the TFT substrate, the light emitted by the backlight source can illuminate the MOST, causing the gate threshold voltage (Vth) of the MOST to be negatively biased, causing the MOST to turn on prematurely, resulting in leakage problems and causing poor display issues such as sand and mura. Furthermore, light exposure can increase new defects in the MOST, reduce the negative bias temperature illumination stress (NBTIS) of the MOST, and shorten the life of the display substrate.

[0060] An exemplary embodiment of the present disclosure provides a display substrate, including:

[0061] an active layer disposed on one side of the substrate, wherein the active layer includes a channel region;

[0062] a gate, disposed on a side of the active layer away from the substrate, wherein at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate;

[0063] A light shielding layer is provided on a side of the active layer close to the substrate, and at least a portion of the light shielding layer overlaps with an orthographic projection of the channel region on the substrate.

[0064] The solution of this embodiment is illustrated below through some examples.

[0065] Figure 1 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a thin-film transistor within the display substrate. In this exemplary embodiment, the display substrate includes at least a light-shielding layer 11 disposed sequentially on a substrate, an active layer 12 disposed on a side of the light-shielding layer 11 away from the substrate, a gate 13 disposed on a side of the active layer 12 away from the substrate, and a first electrode 14 and a second electrode 15 disposed on a side of the gate 13 away from the substrate.

[0066] In an exemplary embodiment, the active layer 12 may be strip-shaped and extend along the second direction Y. The active layer 12 includes a channel region and first and second doped regions located on opposite sides of the channel region in the second direction Y. The first and second doped regions may be connected via the channel region. The first and second doped regions are both conductorized regions of the active layer 12.

[0067] In an exemplary embodiment, the gate 13 may be in the shape of a strip, extending along a first direction X, with at least a portion of the gate 13 overlapping with an orthographic projection of the channel region of the active layer 12 on the substrate. The first direction X and the second direction Y are both parallel to the substrate, and the first direction X intersects the second direction Y. For example, the first direction X is perpendicular to the second direction Y.

[0068] In an exemplary embodiment, the light-shielding layer 11 can be shaped like a rectangular block. The light-shielding layer 11 is located on the side of the active layer 12 close to the substrate. At least part of the light-shielding layer 11 overlaps with the orthographic projection of the channel region of the active layer 12 on the substrate, so that the light-shielding layer 11 can block the light emitted toward the channel region and prevent the light from directly irradiating the channel region.

[0069] In an exemplary embodiment, the orthographic projection of the channel region of the active layer 12 on the substrate is located within the orthographic projection of the light shielding layer 11 on the substrate, so that the light shielding layer 11 can completely shield the channel region.

[0070] The disclosed embodiment of the display substrate shields the channel region of the active layer through a shielding layer to prevent light from directly irradiating the channel region, thereby reducing the negative bias of the transistor gate threshold voltage (Vth) caused by light, solving the leakage problem of the display substrate, and ensuring the negative bias temperature illumination stress (NBTIS) stability, thereby improving the life of the display substrate.

[0071] In an exemplary embodiment, at least a portion of the light shielding layer 11 overlaps with an orthographic projection of the gate 13 on the substrate.

[0072] In an exemplary embodiment, the first electrode 14 may be block-shaped. The first electrode 14 is located on one side of the gate 13 in the second direction Y and does not overlap with the orthographic projection of the gate 13 on the substrate. The first electrode 14 overlaps with the orthographic projection of the first doped region of the active layer 12 on the substrate, and the first electrode 14 is connected to the first doped region of the active layer 12 through the first via 21.

[0073] In an exemplary embodiment, the second electrode 15 may be strip-shaped and extend along the first direction X. The second electrode 15 is located on the side of the gate 13 opposite the second direction Y and does not overlap with the orthographic projection of the gate 13 on the substrate. The first end of the second electrode 15 overlaps with the orthographic projection of the second doped region of the active layer 12 on the substrate, and the first end of the second electrode 15 is connected to the second doped region of the active layer 12 through a second via 22. The second end of the second electrode 15 extends in the direction opposite to the first direction X and can be connected to a pixel electrode (not shown) through a third via 23.

[0074] FIG2 is a schematic diagram of a cross-sectional structure of a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in FIG2 , the display substrate includes at least a light shielding layer 11 disposed on a substrate 101, a first inorganic dielectric layer 41 disposed on a side of the light shielding layer 11 away from the substrate 101, an active layer 12 disposed on a side of the first inorganic dielectric layer 41 away from the substrate 101, a gate insulating layer disposed on a side of the active layer 12 away from the substrate 101, a gate 13 disposed on a side of the gate insulating layer away from the substrate 101, a second inorganic dielectric layer 42 disposed on a side of the gate 13 away from the substrate 101, a first electrode 14 and a second electrode 15 disposed on a side of the second inorganic dielectric layer 42 away from the substrate 101, and a gate electrode 15 disposed on a side of the second inorganic dielectric layer 42 away from the substrate 101. The third inorganic dielectric layer 43 is disposed on a side of the first electrode 14 and the second electrode 15 away from the substrate 101; the organic dielectric layer 46 is disposed on a side of the third inorganic dielectric layer 43 away from the substrate 101; the common electrode 16 is disposed on a side of the organic dielectric layer 46 away from the substrate 101; the fourth inorganic dielectric layer 44 is disposed on a side of the common electrode 16 away from the substrate 101; the touch electrode 17 is disposed on a side of the fourth inorganic dielectric layer 44 away from the substrate 101; the fifth inorganic dielectric layer 45 is disposed on a side of the touch electrode 17 away from the substrate 101; and the pixel electrode 18 is disposed on a side of the fifth inorganic dielectric layer 45 away from the substrate 101.

[0075] In an exemplary embodiment, the display substrate further includes a first via hole 21 , a second via hole 22 , a third via hole 23 , a fourth via hole 24 , and a fifth via hole 25 disposed on one side of the base 101 .

[0076] In an exemplary embodiment, the first via 21 is disposed in the second inorganic dielectric layer 42 , and the first via 21 extends from the surface of the second inorganic dielectric layer 42 away from the substrate 101 to the surface of the first doping region of the active layer 12 . The first via 21 exposes at least a portion of the surface of the first doping region, and the first electrode 14 is connected to the first doping region of the active layer 12 through the first via 21 .

[0077] In an exemplary embodiment, the second via 22 is disposed in the second inorganic dielectric layer 42 , and the second via 22 extends from the surface of the second inorganic dielectric layer 42 on the side away from the substrate 101 to the surface of the second doping region of the active layer 12 . The second via 22 exposes at least a portion of the surface of the second doping region, and the second electrode 15 is connected to the second doping region of the active layer 12 through the second via 22 .

[0078] In an exemplary embodiment, the third via 23 extends from the surface of the fifth inorganic dielectric layer 45 away from the substrate 101, sequentially passes through the fifth inorganic dielectric layer 45, the fourth inorganic dielectric layer 44, the organic dielectric layer 46, and the third inorganic dielectric layer 43, and extends to the surface of the second electrode 15. The third via 23 exposes at least a portion of the surface of the second electrode 15, and the pixel electrode 18 is connected to the second electrode 15 through the third via 23.

[0079] In an exemplary embodiment, the fourth via hole 24 is disposed in the organic medium layer 46 and penetrates the organic medium layer 46. The area of ​​the orthographic projection of the fourth via hole 24 on the substrate is larger than the area of ​​the orthographic projection of the third via hole 23 on the substrate, and the orthographic projection of the third via hole 23 on the substrate is located within the orthographic projection of the fourth via hole 24 on the substrate.

[0080] The embodiment of the present disclosure shows that the substrate is formed by first forming a fourth via hole 24 in the organic dielectric layer 46 and then filling the fourth inorganic dielectric layer 44 in the fourth via hole 24, so that the third via hole 23 passes through the organic dielectric layer 46 through the fourth inorganic dielectric layer 44 in the fourth via hole 24, so that the third via hole 23 can be formed through a single dry etching process, simplifying the process steps.

[0081] In an exemplary embodiment, the fifth via 25 extends from the surface of the fifth inorganic dielectric layer 45 on the side away from the substrate 101, sequentially penetrates the fifth inorganic dielectric layer 45 and the fourth inorganic dielectric layer 44, and extends to the common electrode 16. The fifth via 25 exposes at least a portion of the surface of the touch electrode 17 and at least a portion of the surface of the common electrode 16. The touch electrode 17 and the common electrode 16 are connected to the pixel electrode 18 through the fifth via 25.

[0082] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0083] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0084] (11) Forming a light shielding layer. In an exemplary embodiment, forming the light shielding layer may include: depositing a metal thin film on the substrate 101, and patterning the metal thin film through a patterning process to form the light shielding layer 11, as shown in FIG3a.

[0085] In an exemplary embodiment, the light shielding layer 11 may be made of molybdenum and its alloys, or a composite metal of aluminum and copper.

[0086] (12) Forming an active layer. In an exemplary embodiment, forming the active layer may include: on the substrate having the aforementioned pattern formed thereon, sequentially depositing a first inorganic insulating film and a semiconductor film on the substrate 101, patterning the first inorganic insulating film and the semiconductor film through a patterning process to form a first inorganic dielectric layer 41 covering the light shielding layer 11, and an active layer 12 disposed on the first inorganic dielectric layer 41, as shown in FIG3b.

[0087] In an exemplary embodiment, the first inorganic dielectric layer 41 may be made of silicon oxide (SiO), or a composite film layer of silicon nitride (SiN) and silicon oxide (SiO), and the thickness of the first inorganic dielectric layer 41 may be 200 nm to 500 nm.

[0088] In an exemplary embodiment, the active layer 12 may be made of a high-mobility oxide material, such as metal oxides such as IGZTO and IGO.

[0089] (13) Forming a gate. In an exemplary embodiment, forming the gate may include: depositing a gate insulating film and a first conductive film in sequence on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a gate 13 disposed on the gate insulating film, wherein the gate 13 overlaps with an orthographic projection of the active layer 12 on the substrate 101;

[0090] Subsequently, the gate insulating film is patterned and etched using the gate 13 as a mask, so that the gate insulating film forms a gate insulating layer 47 disposed on the active layer 12, and the gate insulating layer 47 exposes both ends of the active layer;

[0091] Subsequently, the two ends of the exposed active layer are conductively connected to form a first doping region and a second doping region. The portion of the active layer 12 covered by the gate 13 forms a channel region, as shown in FIG3 c .

[0092] In an exemplary embodiment, the orthographic projection of the channel region of the active layer 12 on the substrate 101 is located within the orthographic projection of the light shielding layer 11 on the substrate 101 , so that the light shielding layer 11 can completely shield the channel region of the active layer 12 .

[0093] In an exemplary embodiment, the first doping region and the second doping region may be formed by a plasma process using one or a mixture of helium (He), argon (Ar), hydrogen, and methane.

[0094] In an exemplary embodiment, the gate insulating layer 47 may be formed of silicon oxide, and the thickness of the gate insulating layer 47 may be 10 nm to 30 nm.

[0095] In an exemplary embodiment, the gate electrode 13 may be made of molybdenum and its alloys, or a composite metal of aluminum and copper.

[0096] (14) Forming the first electrode and the second electrode. In an exemplary embodiment, forming the first electrode and the second electrode may include: depositing a second inorganic insulating film on the substrate on which the aforementioned pattern is formed to form a second inorganic dielectric layer 42 covering the gate 13; then, forming a first via hole 21 and a second via hole 22 in the second inorganic dielectric layer 42 by an etching process, wherein the first via hole 21 and the second via hole 22 both penetrate the second inorganic dielectric layer 42, the first via hole 21 exposes the surface of the first doping region of the active layer 12, and the second via hole 22 exposes the surface of the second doping region of the active layer 12; then, depositing a second conductive film on the second inorganic dielectric layer 42, patterning the second conductive film by a patterning process to form a first electrode 14 and a second electrode 15 disposed on the second inorganic dielectric layer 42, the first electrode 14 being connected to the first doping region of the active layer 12 through the first via hole 21, and the second electrode 15 being connected to the second doping region of the active layer 12 through the second via hole 22, as shown in FIG. 3d.

[0097] In an exemplary embodiment, the second inorganic dielectric layer 42 may be made of silicon oxide (SiO), or a composite film layer of silicon nitride (SiN) and silicon oxide (SiO), and the thickness of the first inorganic dielectric layer 41 may be 300 nm to 600 nm.

[0098] In an exemplary embodiment, the first electrode 14 and the second electrode 15 may both be made of molybdenum and its alloys, or a composite metal of aluminum and copper.

[0099] (15) Forming a third inorganic dielectric layer, an organic dielectric layer, and a fourth via. In an exemplary embodiment, forming the third inorganic dielectric layer, the organic dielectric layer, and the fourth via includes: on the substrate formed with the aforementioned pattern, sequentially depositing a third inorganic insulating film and an organic film on the first electrode 14 and the second electrode 15 to form a third inorganic dielectric layer 43 covering the first electrode 14 and the second electrode 15, and forming an organic dielectric layer 46 disposed on the third inorganic dielectric layer 43; subsequently, forming a fourth via 24 in the organic dielectric layer 46 through a photolithography process, the fourth via 24 penetrating the organic dielectric layer 46 and exposing the surface of the third inorganic dielectric layer 43, as shown in FIG. 3e.

[0100] (16) Forming a common electrode. In an exemplary embodiment, forming the common electrode includes: depositing a third conductive film on the organic dielectric layer 46 on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film through a patterning process to form a common electrode 16 disposed on the organic dielectric layer 46, as shown in FIG. 3f.

[0101] In an exemplary embodiment, the common electrode 16 may be made of a transparent conductive material such as indium tin oxide (ITO).

[0102] In an exemplary embodiment, the common electrode 16 does not overlap with the orthographic projection of the fourth via hole 24 on the substrate 101 .

[0103] (17) Forming a touch electrode. In an exemplary embodiment, forming the touch electrode includes: sequentially depositing a fourth inorganic insulating film and a fourth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fourth inorganic insulating film and the fourth conductive film through a patterning process to form a fourth inorganic dielectric layer 44 covering the common electrode 16, and forming a touch electrode 17 disposed on the fourth inorganic dielectric layer 44, as shown in FIG. 3g .

[0104] In an exemplary embodiment, the touch electrode 17 may be made of molybdenum and its alloys, or a composite metal of aluminum and copper.

[0105] (18) Forming the third and fifth via holes. The formation of the third and fifth via holes includes: depositing a fifth inorganic insulating film on the substrate having the aforementioned pattern to form a fourth fifth-organic dielectric layer 45 covering the touch electrode 17; then, forming the third and fifth via holes 23 and 25 in the fourth fifth-organic dielectric layer 45 by dry etching, as shown in FIG3h.

[0106] In an exemplary embodiment, the third via 23 extends from the surface of the fifth inorganic dielectric layer 45 away from the substrate 101, sequentially passing through the fifth inorganic dielectric layer 45, the fourth inorganic dielectric layer 44, the organic dielectric layer 46, and the third inorganic dielectric layer 43, to the surface of the second electrode 15. The third via 23 exposes at least a portion of the surface of the second electrode 15. The orthographic projection of the third via 23 on the substrate is located within the orthographic projection of the fourth via 24 on the substrate.

[0107] In an exemplary embodiment, the fifth via 25 extends from the surface of the fifth inorganic dielectric layer 45 away from the substrate 101, sequentially passes through the fifth inorganic dielectric layer 45 and the fourth inorganic dielectric layer 44, and extends to the common electrode 16. The fifth via 25 exposes at least a portion of the surface of the touch electrode 17 and at least a portion of the surface of the common electrode 16.

[0108] (19) Forming a pixel electrode. Forming the pixel electrode includes: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fifth conductive film through a patterning process, and forming a pixel electrode 18 disposed on the fifth inorganic dielectric layer 45. The pixel electrode 18 is connected to the second electrode 15 through the third via 23, and the pixel electrode 18 is connected to the touch electrode 17 and the common electrode 16 through the fifth via 25, as shown in FIG. 2 .

[0109] In an exemplary embodiment, a slit is provided in the pixel electrode 18 , and the orthographic projections of the pixel electrode 18 and the common electrode 16 on the substrate overlap, thereby forming an electric field.

[0110] In some embodiments, the preparation process of the substrate shown in this embodiment may not form the touch layer and the fourth inorganic dielectric layer, and the embodiments of the present disclosure will not be described in detail here.

[0111] Figure 4 is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure. The inventors of the present disclosure have discovered that, as shown in Figure 4 , light A can be reflected from the lower surface of gate 13 to the upper surface of shielding layer 11, and then from the upper surface of shielding layer 11 to the channel region of active layer 12, affecting the performance of the thin-film transistor.

[0112] Figure 5 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 6 is a schematic diagram of the planar structure of the gate electrode in Figure 5. As shown in Figures 5 and 6, the structure of the display substrate in this exemplary embodiment is substantially the same as that of the display substrate shown in Figure 1, with the difference being that the gate electrode 13 in this exemplary embodiment includes a main portion 131 and an extension 132 disposed on the main portion 131. The extension 132 overlaps with the orthographic projection of the channel region of the active layer 12 onto the substrate, while the main portion 131 does not overlap with the orthographic projection of the channel region of the active layer 12 onto the substrate.

[0113] In an exemplary embodiment, the active layer 12 may be in a strip shape, and the active layer 12 extends along the first direction X.

[0114] In an exemplary embodiment, the main body portion 131 of the gate 13 may be in a strip shape, and the main body portion 131 extends along the first direction X. The extending direction of the main body portion 131 is substantially the same as the extending direction of the active layer 12 .

[0115] In an exemplary embodiment, a space is provided between an edge of the main portion 131 of the gate 13 on a side close to the channel region and an edge of the channel region on a side close to the main portion 131 .

[0116] In an exemplary embodiment, the extension portion 132 of the gate 13 is strip-shaped, extending along the second direction Y, a first end of the extension portion 132 is perpendicularly connected to the main portion 131, and a second end of the extension portion 132 extends in the opposite direction of the second direction Y, overlapping with the positive projection of the channel region of the active layer 12 on the substrate.

[0117] In some embodiments, the extension portion 132 of the gate 13 may be in a block shape.

[0118] In an exemplary embodiment, the first electrode 14 and the second electrode 15 are located on opposite sides of the protruding portion 132 of the gate 13 in the first direction X.

[0119] The embodiment of the present disclosure shows that the substrate overlaps with the channel region through the extension portion 132 of the gate 13, so that the main portion 131 of the gate 13 is away from the channel region, thereby preventing light from being reflected through the main portion 131 of the gate 13 and the shielding layer 11 to the channel region of the active layer 12, thereby reducing the reflected light from irradiating the channel region of the active layer 12.

[0120] Figure 7 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 8 is a schematic diagram of the cross-sectional structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figures 7 and 8, the structure of the display substrate according to this exemplary embodiment is substantially the same as that of the display substrate shown in Figure 5, except that the orthographic projections of the second via 22 and the third via 23 in the display substrate according to this exemplary embodiment overlap on the substrate.

[0121] In an exemplary embodiment, the third via hole 23 overlaps the second via hole 22 at an orthographic projection portion of the substrate.

[0122] In the embodiment of the present disclosure, the display substrate reduces the space occupied by the second via hole 22 and the third via hole 23 by overlapping the orthographic projections of the second via hole 22 and the third via hole 23 on the base, thereby improving the space utilization of the display substrate.

[0123] The present disclosure also provides a method for preparing a display substrate, comprising:

[0124] forming a light-shielding layer on the substrate;

[0125] forming an active layer on a side of the light-shielding layer away from the substrate, wherein the active layer includes a channel region, and at least a portion of the light-shielding layer overlaps with an orthographic projection of the channel region on the substrate;

[0126] A gate is formed on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate.

[0127] In an exemplary embodiment, the method for preparing a display substrate further includes:

[0128] forming a second via hole and a second electrode on a side of the active layer away from the substrate, wherein the second via hole exposes the active layer, and the second electrode is connected to the active layer through the second via hole;

[0129] A third via hole and a pixel electrode are formed on a side of the second electrode away from the substrate, the third via hole exposes the second electrode, the pixel electrode is connected to the second electrode through the third via hole, and the orthographic projections of the second via hole and the third via hole on the substrate overlap.

[0130] Embodiments of the present invention further provide a display device comprising any of the aforementioned display substrates. Such display devices include mobile phones, tablet computers, smart wearable products (e.g., smart watches, wristbands, etc.), personal digital assistants (PDAs), and in-vehicle computers. The presently disclosed embodiments do not impose any particular limitations on the specific form of the foldable display device.

[0131] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to general designs. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, may be combined with each other to obtain new embodiments.

[0132] It should be understood by those skilled in the art that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, wherein: include: an active layer disposed on one side of the substrate, wherein the active layer includes a channel region; a gate, disposed on a side of the active layer away from the substrate, wherein at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate; A light shielding layer is provided on a side of the active layer close to the substrate, and at least a portion of the light shielding layer overlaps with an orthographic projection of the channel region on the substrate.

2. The display substrate according to claim 1, wherein The gate includes a main body portion and a protruding portion provided on the main body portion, the protruding portion overlaps with an orthographic projection of the channel region on the substrate, and the main body portion does not overlap with an orthographic projection of the channel region on the substrate.

3. The display substrate according to claim 2, wherein: A gap is provided between an edge of the main body portion close to the channel region and an edge of the channel region close to the main body portion.

4. The display substrate according to claim 2, wherein: The main body portion is in a strip shape, the active layer is in a strip shape, and an extension direction of the main body portion is substantially the same as an extension direction of the active layer.

5. The display substrate according to claim 2, wherein: The protruding portion may be in a block or strip shape. The display substrate according to claim 1 , wherein: The active layer has a strip shape and extends along the second direction. The gate has a strip shape and extends along the first direction. The first direction intersects the second direction.

7. The display substrate according to any one of claims 1 to 6, wherein: The active layer further includes a first doping region and a second doping region, and the first doping region and the second doping region are connected through the channel region.

8. The display substrate according to claim 7, wherein: It also includes a first electrode and a second electrode, both of which are arranged on the side of the active layer away from the substrate, the first electrode is connected to the first doped region through a first via hole, and the second electrode is connected to the second doped region through a second via hole.

9. The display substrate according to claim 8, wherein: It also includes a pixel electrode, which is arranged on a side of the first electrode and the second electrode away from the substrate, and the pixel electrode is connected to the second electrode through a third via hole.

10. The display substrate according to claim 9, wherein: The orthographic projections of the second via hole and the third via hole on the substrate overlap.

11. The display substrate according to claim 9, wherein: It also includes an organic medium layer, which is arranged between the pixel electrode and the second electrode. A fourth via hole is arranged in the organic medium layer, and the orthographic projection of the third via hole on the substrate is located within the orthographic projection of the fourth via hole on the substrate.

12. The display substrate according to claim 9, wherein: It also includes a common electrode, which is arranged on a side of the pixel electrode close to the substrate, and is connected to the pixel electrode through a fifth via hole.

13. The display substrate according to claim 12, wherein: The device further includes a touch electrode, which is disposed between the common electrode and the pixel electrode, and is connected to the pixel electrode through the fifth via hole.

14. A display device comprising the display substrate according to any one of claims 1 to 13.

15. A method for preparing a display substrate, comprising: forming a light-shielding layer on the substrate; forming an active layer on a side of the light-shielding layer away from the substrate, wherein the active layer includes a channel region, and at least a portion of the light-shielding layer overlaps with an orthographic projection of the channel region on the substrate; A gate is formed on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate.

16. The method for preparing a display substrate according to claim 15, further comprising: forming a second via hole and a second electrode on a side of the active layer away from the substrate, wherein the second via hole exposes the active layer, and the second electrode is connected to the active layer through the second via hole; A third via hole and a pixel electrode are formed on a side of the second electrode away from the substrate, the third via hole exposes the second electrode, the pixel electrode is connected to the second electrode through the third via hole, and the second via hole and the third via hole have overlapping orthographic projections on the substrate.

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