Semiconductor device and manufacturing method therefor

Abstract

Provided in the present application are a semiconductor device and a manufacturing method therefor. The manufacturing method comprises: providing a substrate, wherein a first metal wire, a second metal wire and an insulating layer are formed in the substrate; forming several trenches in the insulating layer; forming a capacitor, wherein the capacitor comprises a first electrode, a first dielectric layer and a second electrode, which are arranged in a stacked manner, the first electrode at least covers the trenches and the insulating layer on the peripheries of the trenches, and at least part of the first electrode, which is located on one side of a trench at the outermost side, is exposed; forming a second dielectric layer, which covers the insulating layer, the first electrode and the second electrode; forming several through holes in the second dielectric layer and the insulating layer; and forming a third metal wire and a fourth metal wire, wherein the third metal wire is electrically connected to the first metal wire and the first electrode, and the fourth metal wire is electrically connected to the second metal wire and the second electrode. In the semiconductor device of the present application, the two electrodes of the capacitor are led out downwards by using the first metal wire and the second metal wire in the substrate, thereby reducing the process integration difficulty, and facilitating the improvement in the degree of freedom for the design of the capacitor in the semiconductor device.

Description

Semiconductor device and method for manufacturing the same

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310948094.4 and application name “Semiconductor device and manufacturing method thereof”; and priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310948090.6 and application name “Capacitor device and manufacturing method thereof”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of integrated circuit process technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0003] Capacitors are common passive components widely used in integrated circuits. In some specialized applications, high-capacitance capacitors are required to improve product performance, such as signal storage, noise reduction, and coupling reduction. Planar capacitors require a large area to achieve high capacitance, sacrificing design space. Therefore, trench capacitors are the optimal choice for high-capacitance capacitors.

[0004] In the related art, the electrodes of the capacitors in the capacitor device are usually electrically led upward, and the trenches thereof need to be filled with metal, resulting in a complicated structure and process for electrically leading the trench capacitors, which is not conducive to the design of the trench capacitors.

[0005] Summary of the Invention

[0006] The purpose of this application is to overcome the above-mentioned defects in the prior art and to provide a semiconductor device and a method for manufacturing the same.

[0007] To achieve the above objectives, the technical solutions of this application are as follows:

[0008] A first aspect of the present application provides a method for manufacturing a semiconductor device, comprising:

[0009] Providing a substrate, wherein a first metal line and a second metal line arranged in the same layer and an insulating layer covering the first metal line and the second metal line are formed on the substrate;

[0010] forming a plurality of trenches in the insulating layer between the first metal line and the second metal line;

[0011] A capacitor is formed in the trench and on the insulating layer surrounding the trench, the capacitor comprising a first electrode, a first dielectric layer, and a second electrode stacked in layers; the first electrode at least covers the trench and the insulating layer surrounding the trench, and at least a portion of the first electrode on an outermost side of the trench is exposed;

[0012] forming a second dielectric layer, wherein the second dielectric layer covers exposed surfaces of the insulating layer, the first electrode, and the second electrode;

[0013] patterning the second dielectric layer and the insulating layer to form a plurality of through holes in the second dielectric layer, wherein the plurality of through holes respectively expose the first metal line, the second metal line, the first electrode, and the second electrode;

[0014] A third metal line and a fourth metal line are formed; the third metal line electrically connects the first metal line and one of the first electrode and the second electrode, and the fourth metal line electrically connects the second metal line and the other of the first electrode and the second electrode.

[0015] A second aspect of the present application provides a semiconductor device, comprising:

[0016] substrate;

[0017] A first metal line and a second metal line are arranged in the substrate in the same layer;

[0018] an insulating layer covering the first metal line and the second metal, wherein a plurality of grooves are formed in the insulating layer;

[0019] a capacitor formed in the trench and on the insulating layer around it, comprising a first electrode, a first dielectric layer, and a second electrode that are conformally formed in sequence;

[0020] a second dielectric layer covering the capacitor, wherein a plurality of through holes are formed in the second dielectric layer and the insulating layer to expose the first electrode, the second electrode, the first metal line, and the second metal line respectively;

[0021] A third metal wire and a fourth metal wire, wherein the third metal wire electrically connects the first metal wire and one of the first electrode and the second electrode using the through hole, and the fourth metal wire electrically connects the second metal wire and the other of the first electrode and the second electrode using the through hole.

[0022] In the semiconductor device and its manufacturing method provided by the embodiments of the present application, a plurality of trenches are provided in the insulating layer between the first metal wire and the second metal wire, and a capacitor is formed in the trench and on the insulating layer around the trench, wherein the capacitor includes a first electrode, a first dielectric layer and a second electrode formed conformally in sequence, the first electrode and the second electrode respectively extending to the sides of the trench capacitor and both exposed upward; a second dielectric layer is then formed to cover the capacitor and the insulating layer, and through holes are formed in the second dielectric layer and the insulating layer to expose the first metal wire, the second metal wire, the first electrode and the second electrode respectively; a third metal wire is then formed using the through holes to electrically connect the first electrode and the first metal wire, and a fourth metal wire is formed to electrically connect the second electrode and the second metal wire; thereby, the two electrodes of the capacitor in the semiconductor device are led downward using the first metal wire and the second metal wire in the substrate, and the lead-out of the capacitor in the semiconductor device and the wiring of the metal wires on the insulating layer are completed without adding additional process steps, thereby reducing the difficulty of process integration and facilitating the improvement of the capacitance density and design freedom of the capacitor in the semiconductor device. In addition, compared with the related art method in which trench capacitors require metal to fill the trench, the two electrodes of the trench capacitor in this embodiment extend to both sides to achieve electrical lead-out, and do not need to be filled with metal, that is, voids are allowed to exist, which is conducive to improving the freedom of capacitor design in semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0024] FIG2 is a second flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0025] 3a to 3m are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a semiconductor device provided in Example 1;

[0026] 4a to 41 are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a semiconductor device provided in Example 2;

[0027] FIG5 is a third flow chart of the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0028] 6a to 61 are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a semiconductor device provided in the third embodiment.

[0029] Reference numerals:

[0030] 10: substrate; 11: first metal line; 12: second metal line;

[0031] 21: dielectric barrier layer; 22: insulating layer; 23: trench; 24: first electrode material layer; 24a: first electrode; 25: first mask; 26: first dielectric material layer; 27: second electrode material layer; 26a: first dielectric layer; 27a: second electrode; 28: second mask;

[0032] 31: second dielectric layer; 32: first through hole; 33: second through hole; 34: metal material layer; 35: third metal line; 36: fourth metal line;

[0033] 40: third mask; 50: fourth mask. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. Unless otherwise defined, the technical terms or scientific terms used herein should be the usual meanings understood by people with general skills in the field to which this application belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0035] Referring to FIG. 1 , an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising the following steps:

[0036] S01: providing a substrate, in which a first metal wire and a second metal wire arranged in the same layer and an insulating layer covering the first metal wire and the second metal wire are formed.

[0037] S02: forming a plurality of trenches in the insulating layer between the first metal line and the second metal line.

[0038] S03: forming a capacitor in the trench and on the insulating layer around the trench, the capacitor comprising a first electrode, a first dielectric layer, and a second electrode stacked together; the first electrode at least covers the trench and the insulating layer around the trench, and at least a portion of the first electrode on one side of the outermost trench is exposed.

[0039] S04: forming a second dielectric layer, wherein the second dielectric layer covers the exposed surfaces of the insulating layer, the first electrode, and the second electrode.

[0040] S05: patterning the second dielectric layer and the insulating layer to form a plurality of through holes in the second dielectric layer, wherein the plurality of through holes respectively expose the first metal line, the second metal line, the first electrode, and the second electrode;

[0041] S06: forming a third metal line and a fourth metal line; the third metal line electrically connects the first metal line and one of the first electrode and the second electrode, and the fourth metal line electrically connects the second metal line and the other of the first electrode and the second electrode.

[0042] It should be noted that the outermost trench mentioned in this example can be understood as the trench with the shortest distance to the first metal line or the second metal line. Taking Figure 3b as an example, from left to right, the outermost trenches can be understood as the first trench and the third trench.

[0043] In the semiconductor device provided in this embodiment, the two electrodes of the capacitor are led downward using the first and second metal lines in the substrate. This completes the lead-out of the capacitor in the semiconductor device and the wiring of the metal lines on the insulating layer without adding additional process steps, reducing the difficulty of process integration and facilitating an increase in the capacitance density and design freedom of the capacitor in the semiconductor device. In addition, compared to the trench capacitor method in the related art that requires metal to fill the trench, the two electrodes of the trench capacitor in this embodiment extend to both sides to achieve electrical lead-out, and do not need to be filled with metal, that is, voids are allowed, which facilitates increasing the design freedom of the capacitor in the semiconductor device.

[0044] In this embodiment, a capacitor region AA is provided on the insulating layer 22 between the first metal line 11 and the second metal line 12. For example, the plurality of trenches 23 and the surrounding region of the insulating layer 22 may constitute the capacitor region AA, for subsequently forming a single-layer trench capacitor thereon. Of course, in other examples of this embodiment, the trenches 23 may not penetrate the insulating layer 22.

[0045] In addition, as needed, the capacitor area AA may further extend into the insulating layer 22 on the first metal line 11 and / or the second metal line 12 , that is, a trench 23 may be further formed in the insulating layer 22 on the first metal line 11 and / or the second metal line 12 .

[0046] It should be noted that the method for manufacturing a semiconductor device provided in this embodiment may have different implementation methods. The following description will be given using different embodiments as examples to facilitate a detailed description of the method for manufacturing a semiconductor device.

[0047] Example 1

[0048] FIG2 is a flow chart of a method for manufacturing a semiconductor device provided in the first embodiment.

[0049] As shown in FIG2 , the method for manufacturing a semiconductor device provided in this embodiment includes:

[0050] S01: providing a substrate, in which a first metal wire and a second metal wire arranged in the same layer and an insulating layer covering the first metal wire and the second metal wire are formed.

[0051] S02: forming a plurality of trenches in the insulating layer between the first metal line and the second metal line.

[0052] S03a: forming a first electrode to at least cover the trench and an insulating layer around the trench.

[0053] S03b: forming a first dielectric layer and a second electrode to conformally cover the trench and the first electrode around the trench, and exposing a portion of the first electrode.

[0054] S04: forming a second dielectric layer, where the second dielectric layer covers the insulating layer, the first electrode, the second electrode and the trench.

[0055] S05: forming a plurality of through holes in the second dielectric layer and the insulating layer to expose the first metal line, the second metal line, the first electrode, and the second electrode.

[0056] S06: forming a third metal line and a fourth metal line, wherein the third metal line electrically connects the first metal line and the first electrode, and the fourth metal line electrically connects the second metal line and the second electrode.

[0057] 3a to 3m are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a semiconductor device provided in this embodiment. Next, the method for manufacturing the semiconductor device will be described in detail with reference to FIG. 3a to 3m.

[0058] First, referring to FIG. 3 a , step S01 is performed to provide a substrate 10 , in which first metal wires 11 and second metal wires 12 arranged in the same layer and an insulating layer 22 covering the first metal wires 11 and the second metal wires 12 are formed.

[0059] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SiOI), silicon-germanium-on-insulator (SiGeO), silicon-germanium-on-insulator (SiGeO), and germanium-on-insulator (GeO). In this embodiment, the material of the substrate 10 is described using silicon (silicon substrate) as an example.

[0060] A device layer and an interconnection layer electrically connected to the device layer are formed in the substrate 10. The interconnection layer is located above the device layer and can be formed using a Damascene process. The first metal line 11 and the second metal line 12 can be two metal wirings spaced apart in the Nth layer (N is greater than or equal to 1) in the interconnection layer, and their materials can include, for example, copper. In this embodiment, the first metal line 11 and the second metal line 12 can be two top-layer metal wirings spaced apart. A dielectric barrier layer 21 and an insulating layer 22 are sequentially formed on the first metal line 11 and the second metal line 12. The material of the dielectric barrier layer 21 is used to block the escape of metal ions and serves as an etching stop layer during etching. The material of the dielectric barrier layer 21 can include, for example, silicon nitride or silicon carbonitride. The material of the insulating layer 22 is different from that of the dielectric barrier layer 21, and can include, for example, silicon oxide or silicon oxynitride.

[0061] In addition, in other examples of this embodiment, as needed, multiple (at least two) first metal wires 11 and multiple second metal wires 12 can be set, and multiple identical metal wires are connected in parallel; other metal wires can also be arranged between the first metal wire 11 and the second metal wire 12.

[0062] Next, referring to FIG. 3 b , step S02 is performed to form a plurality of trenches 23 in the insulating layer 22 between the first metal line 11 and the second metal line 12 .

[0063] For example, a photolithography process can be used to define a plurality of openings in the insulating layer 22 between the first metal line 11 and the second metal line 12. A dry etching process can be performed to etch the insulating layer 22 to form a plurality of spaced trenches 23, thereby exposing the surface of the dielectric barrier layer 21. The plurality of trenches 23 and the surrounding region of the insulating layer 22 can be capacitor area AA, for subsequently forming a single-layer trench capacitor thereon. Of course, in other examples of this embodiment, the trenches 23 may not penetrate the insulating layer 22.

[0064] Furthermore, as needed, the capacitor region AA may further extend into the insulating layer 22 on the first metal line 11 and / or the second metal line 12, i.e., trenches 23 may be further formed in the insulating layer 22 on the first metal line 11 and / or the second metal line 12. In other words, a plurality of trenches 23 are formed within the capacitor region AA.

[0065] Next, step S03 a is performed to form a first electrode 24 a . The first electrode 24 a at least covers the trench 23 and the insulating layer 22 around the trench 23 .

[0066] For example, referring to FIG. 3 c , a first electrode material layer 24 is formed to conformally cover the surface of the insulating layer 22 and the inner wall of the trench 23. Any suitable process can be used to form a thin film conductive layer serving as the first electrode material layer 24. The first electrode material layer 24 may include one or more thin film conductive layers, and the material may be, for example, titanium, titanium nitride, tantalum, or tantalum nitride. The formation process may include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The thickness of the first electrode material layer 24 may, for example, be 100 to 400 angstroms.

[0067] Referring to Figure 3d , a first mask 25 is formed. The first mask 25 covers at least the capacitor area AA. Preferably, the first mask 25 may also appropriately extend to cover the first electrode material layer 24 on a portion of the side of the capacitor area AA near the first metal line 11 (e.g., the first extension region BB) to facilitate subsequent electrical extraction. However, it should be noted that the first extension region BB cannot extend above the first metal line 11. In this embodiment, the first extension region BB is located on the side of the capacitor area AA near the first metal line 11.

[0068] Referring to Figure 3e, the first mask 25 is used, i.e., the first mask 25 is used as a mask to etch away the exposed first electrode material layer 24. The remaining first electrode material layer 24 serves as the first electrode 24a, and the first mask 25 is then removed. The first electrode 24a conformally covers the inner wall of the trench 23 and the surface of the insulating layer 22 in the capacitor area AA, and also covers the insulating layer 22 in the first extension area BB.

[0069] Next, step S03b is performed to form a first dielectric layer 26a and a second electrode 27a. The first dielectric layer 26a and the second electrode 27a conformally cover the trench 23 and the first electrode 24a around the trench 23, and partially expose the first electrode 24a.

[0070] For example, referring to FIG. 3 f , a first dielectric material layer 26 and a second electrode material layer 27 are conformally formed in sequence. Specifically, the first dielectric material layer 26 and the second electrode material layer 27 are stacked and cover the surfaces of the insulating layer 22 and the first electrode 24 a. The first dielectric material layer 26 can be made of a dielectric material with a relatively high dielectric constant, such as greater than or equal to 3.9, such as silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide. The second electrode material layer 27 can be made of a material similar to that of the first electrode material layer 24 .

[0071] Referring to Figure 3g, a second mask 28 is formed. The second mask 28 covers at least the second electrode material layer 27 in the capacitor area AA and exposes a portion of the second electrode material layer 27 located above the first electrode 24a. The second mask 28 covers the second electrode material layer 27 in the capacitor area AA and at least partially exposes the second electrode material layer 27 in the first extension area BB, that is, at least partially exposes the second electrode material layer 27 on the first electrode 24a. It is also preferred to cover a portion of the second electrode material layer 27 located on the other side of the capacitor area AA relative to the first extension area BB (the second extension area CC) to facilitate subsequent electrical routing. Similar to the first extension area BB, the second extension area CC must not extend above the second metal line 12.

[0072] Referring to Figure 3h, a dry etching process is performed using a second mask 28 to sequentially remove the exposed second electrode material layer 27 and the first dielectric material layer 26. The remaining second electrode material layer 27 serves as the second electrode 27a, and the remaining first dielectric material layer 26 serves as the first dielectric layer 26a. The surface of a portion (first extension region BB) of the first electrode 24a is exposed, and the second mask 28 is then removed.

[0073] Thus, a single-layer trench capacitor consisting of a first electrode 24a, a first dielectric layer 26a and a second electrode 27a is formed on the insulating layer 22 in the trench 23 and around the trench 23 (capacitor area AA), thereby increasing the capacitance value (capacitance density) on the same substrate area.

[0074] Next, referring to FIG. 3 i , step S04 is performed to form a second dielectric layer 31 covering the insulating layer 22 , the first electrode 24 a , the second electrode 27 a and the trench 23 .

[0075] Among them, the second dielectric layer 31 may include a single-layer dielectric or a multi-layer dielectric, and its material may include suitable insulating materials such as silicon oxide, silicon nitride, silicon carbonitride or silicon oxynitride, and may be formed by a suitable process including chemical vapor deposition or atomic layer deposition. In addition to covering the insulating layer 22, the first electrode 24a and the second electrode 27a, the second dielectric layer 31 also fills the groove 23. Compared with the related art that uses electrode materials to fill the groove 23 used to form the capacitor, this embodiment uses the second dielectric layer 31 to fill the groove 23, which is not only conducive to saving electrode materials, but also provides greater freedom for the design of capacitors in semiconductor devices. It should be understood that the single-layer trench capacitor in this embodiment does not lead the electrode out of the trench 23. Therefore, it is not necessary to use electrode materials to fill the trench 23. That is, this embodiment allows the single-layer trench capacitor a

[0076] For example, referring to FIG. 3j , a plurality of first through-holes 32 are formed in the second dielectric layer 31. Each of the first through-holes 32 exposes the first electrode 24a and the second electrode 27a. Some of the first through-holes 32 are located in the second dielectric layer 31 above the first extension region BB to expose one of the first electrode 24a and the second electrode 27a, while other first through-holes 32 are located in the second dielectric layer 31 above the second extension region CC to expose the other of the first electrode 24a and the second electrode 27a. In this embodiment, the first through-holes 32 near the first metal line 11 can expose the first electrode 24a, while the first through-holes 32 near the second metal line 12 can expose the second electrode 27a. In this embodiment, there are two first through-holes 32, one of which exposes the first electrode 24a, and the other exposes the second electrode 27a.

[0077] Referring to Figure 3k , a plurality of second through-holes 33 are formed in the insulating layer 22 and the second dielectric layer 31. These second through-holes 33 expose the first metal line 11 and the second metal line 12, respectively. Some of the second through-holes 33 may be located above the first metal line 11 to expose the first metal line 11, while others may be located above the second metal line 12 to expose the second metal line 12. In this embodiment, the second through-holes 33 also penetrate the dielectric barrier layer 21 beneath the insulating layer 22. When etching to form the second through-holes 33, the dielectric barrier layer 21 also serves as an etch stop layer for etching the second dielectric layer 31 and the insulating layer 22, thereby reducing damage to the metal lines. In this embodiment, there are two second through-holes 33, one of which exposes the first metal line 11, and the other exposes the second metal line 12.

[0078] Next, step S06 is performed to form a third metal line 35 and a fourth metal line 36 . The third metal line 35 electrically connects the first metal line 11 and the first electrode 24 a , and the fourth metal line 36 electrically connects the second metal line 12 and the second electrode 27 a .

[0079] Referring to Figure 31 , a metal material layer 34 is formed. The metal material layer 34 covers the surface of the second dielectric layer 31, the inner walls of the first through-hole 32, and the second through-hole 33. The metal material layer 34 can be a metal material suitable for connection to an external circuit, such as aluminum or an aluminum alloy. In this embodiment, the first metal wire 11 and the second metal wire 12 are made of copper, and the metal material layer 34 includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer, and a titanium nitride layer, which are sequentially conformally formed. In practice, because the size (depth and opening width) of the first through-hole 32 is smaller and the size of the second through-hole 33 is larger, the metal material layer 34 can completely fill the first through-hole 32, while the metal material layer 34 can only cover the inner wall of the second through-hole 33 without completely filling the second through-hole 33.

[0080] 3m, a patterning process is performed on the metal material layer 34 to form a third metal line 35 connecting the first metal line 11 and the first electrode 24a, and a fourth metal line 36 connecting the second metal line 12 and the second electrode 27a. Specifically, the patterning process of the metal material layer 34 includes disconnecting the metal material layer 34 connecting the two sides of the capacitor area AA, using the metal material layer 34 covering the second through-hole 33 on the first metal line 11 to the first through-hole 32 near the first metal line 11 as the third metal line 35, and using the metal material layer 34 covering the second through-hole 33 on the second metal line 12 to the first through-hole 32 near the second metal line 12 as the fourth metal line 36.

[0081] In addition, during the process of performing the patterning process on the metal material layer 34, the metal material layer 34 can also be used to simultaneously form a metal pad on the second dielectric layer 31, and other top-layer metal lines can be electrically led out to the metal pad for connection to an external circuit. In other words, the electrical lead-out (downward lead-out) of the single-layer trench capacitor of this embodiment can be achieved in the step of forming the metal pad, and no additional device structure and process steps are required.

[0082] It is worth mentioning that in other examples of this embodiment, the first extension region BB may also be located on the side of the capacitor region AA away from the first metal wire 11, and the second extension region CC is located on the side of the capacitor region AA away from the second metal wire 12, so that a portion of the first electrode 24a in the single-layer capacitor is exposed to the side close to the second metal wire 12, thereby forming the third metal wire 35 electrically connecting the first metal wire 11 and the second electrode 27a, and the fourth metal wire 36 electrically connecting the second metal wire 12 and the first electrode 24a.

[0083] Example 2

[0084] As shown in FIG2 , the method for manufacturing a semiconductor device provided in this embodiment includes:

[0085] S01: providing a substrate, in which a first metal wire and a second metal wire arranged in the same layer and an insulating layer covering the first metal wire and the second metal wire are formed.

[0086] S02: forming a plurality of trenches in the insulating layer between the first metal line and the second metal line.

[0087] S03a: forming a first electrode to at least cover the trench and an insulating layer around the trench.

[0088] S03b: forming a first dielectric layer and a second electrode to conformally cover the trench and the first electrode around the trench, and exposing a portion of the first electrode.

[0089] S04: forming a second dielectric layer, where the second dielectric layer covers the insulating layer, the first electrode, the second electrode and the trench.

[0090] S05: forming a plurality of through holes in the second dielectric layer and the insulating layer to expose the first metal line, the second metal line, the first electrode, and the second electrode.

[0091] S06: forming a third metal line and a fourth metal line, wherein the third metal line electrically connects the first metal line and the first electrode, and the fourth metal line electrically connects the second metal line and the second electrode.

[0092] 4a to 41 are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a semiconductor device provided in this embodiment. Next, the method for manufacturing the semiconductor device will be described in detail with reference to FIG. 4a to FIG. 41 .

[0093] First, referring to FIG. 4 a , step S01 is performed to provide a substrate 10 , in which first metal wires 11 and second metal wires 12 arranged in the same layer and an insulating layer 22 covering the first metal wires 11 and the second metal wires 12 are formed.

[0094] Next, referring to FIG. 4 b , step S02 is performed to form a plurality of trenches 23 in the insulating layer 22 between the first metal line 11 and the second metal line 12 .

[0095] Next, step S031 is performed to form a first electrode 24 a . The first electrode 24 a at least covers the trench 23 and the insulating layer 22 around the trench 23 .

[0096] For example, referring to FIG. 4 c , a first electrode material layer 24 is formed to conformally cover the surface of the insulating layer 22 and the inner wall of the trench 23. That is, the first electrode material layer 24 covers the inner wall of the trench 23 and the exposed surface of the insulating layer 22. Any suitable process can be used to form a thin film conductive layer as the first electrode material layer 24. The first electrode material layer 24 may include one or more thin film conductive layers, and the material may include, for example, one or more of titanium, titanium nitride, tantalum, or tantalum nitride. The formation process may include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The thickness of the first electrode material layer 24 may be, for example, 100 to 400 angstroms.

[0097] Referring to FIG. 4 d , a first mask 25 is formed, covering the capacitor region AA to the first electrode material layer 24 above the first metal line 11. The first mask 25 covers the first electrode material layer 24 in the capacitor region AA and also extends to cover the first electrode material layer 24 above the first metal line 11, i.e., including the first electrode material layer 24 between the capacitor region AA and the first metal line 11 and the first electrode material layer 24 on the first metal line 11.

[0098] Referring to Figure 4e, the first mask 25 is used, i.e., the first mask 25 is used as a mask to etch away the exposed first electrode material layer 24. The remaining first electrode material layer 24 serves as the first electrode 24a, and the first mask 25 is then removed. The first electrode 24a conformally covers the inner wall of the trench 23 in the capacitor area AA and the surface of the insulating layer 22, and extends to cover the insulating layer 22 above the first metal line 11.

[0099] Next, step S03b is performed to form a first dielectric layer 26a and a second electrode 27a to conformally cover the trench 23 and the first electrode 24a around the trench 23, and expose a portion of the first electrode 24a.

[0100] Specifically, referring to FIG. 4f , a first dielectric material layer 26 and a second electrode material layer 27 are conformally formed sequentially to cover the surfaces of the insulating layer 22 and the first electrode 24a. The first dielectric material layer 26 can be made of a dielectric material with a relatively high dielectric constant, such as greater than or equal to 3.9, and can be made of, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide. The second electrode material layer 27 can be made of a material similar to that of the first electrode material layer 24.

[0101] Referring to FIG. 4 g , a second mask 28 is formed to cover the capacitor area AA and the second electrode material layer 27 above the second metal line 12. The second mask 28 covers the second electrode material layer 27 in the capacitor area AA and also extends to cover the second electrode material layer 27 above the second metal line 12. Specifically, the second mask 28 includes the second electrode material layer 27 between the capacitor area AA and the second metal line 12 and the second electrode material layer 27 on the second metal line 12.

[0102] 4h, a dry etching process is performed using the second mask 28 to sequentially remove the exposed second electrode material layer 27 and the first dielectric material layer 26, leaving the remaining second electrode material layer 27 as the second electrode 27a and the remaining first dielectric material layer 26 as the first dielectric layer 26a, and then removing the second mask 28.

[0103] Thus, a single-layer trench capacitor consisting of a first electrode 24a, a first dielectric layer 26a, and a second electrode 27a is formed on the insulating layer 22 in the trench 23 and around the trench 23 (capacitor area AA), thereby increasing the capacitance value (capacitance density) per the same substrate area. Furthermore, the first electrode 24a extends from the capacitor area AA to above the first metal line 11, and the second electrode 27a extends from the capacitor area AA to above the second metal line 12, thereby exposing the first electrode 24a and the second electrode 27a for subsequent electrical extraction.

[0104] Next, referring to FIG. 4 i , step S04 is performed to form a second dielectric layer 31 covering the insulating layer 22 , the first electrode 24 a , the second electrode 27 a and the trench 23 .

[0105] Among them, the second dielectric layer 31 may include a single-layer dielectric or a multi-layer dielectric, and its material may include a suitable insulating material such as silicon oxide, silicon nitride, silicon carbonitride or silicon oxynitride, and may be formed by a suitable process including chemical vapor deposition or atomic layer deposition. In addition to covering the insulating layer 22, the first electrode 24a and the second electrode 27a, the second dielectric layer 31 also fills the groove 23. Compared with the related art that uses electrode materials to fill the groove 23 used to form the capacitor, this embodiment uses the second dielectric layer 31 to fill the groove 23, which not only helps to save electrode materials, but also provides greater freedom for the design of the trench capacitor. It should be understood that the single-layer trench capacitor in this embodiment does not lead the electrode out of the trench 23. Therefore, it is not necessary to use electrode materials to fill the trench 23. That is, in this embodiment, voids are allowed to exist in the single-layer trench capacitor (the second dielectric layer can be used to fill the voids later).

[0106] Next, step S05 is performed to form a plurality of through holes in the second dielectric layer 31 and the insulating layer 22 to expose the first metal line 11 , the second metal line 12 , the first electrode 24 a and the second electrode 27 a .

[0107] 4j , a plurality of through-holes (second through-holes 33) are formed through the insulating layer 22, the second dielectric layer 31, the first electrode 24a, and the second electrode 27a, respectively, to expose the first metal line 11 and the second metal line 12 at the bottom walls of the plurality of second through-holes 33, and to expose the first electrode 24a and the second electrode 27a at the side walls of the plurality of second through-holes 33. Specifically, a plurality of second through-holes 33 are formed above the first metal line 11 through the dielectric barrier layer 21, the insulating layer 22, the first electrode 24a, and the second dielectric layer 31, respectively, to expose the first metal line 11 at the bottom walls of the second through-holes 33 and the first electrode 24a at the side walls of the second through-holes 33. Similarly, a plurality of second through-holes 33 are formed above the second metal line 12 through the dielectric barrier layer 21, the insulating layer 22, the second electrode 27a, and the second dielectric layer 31, respectively, to expose the second metal line 12 at the bottom walls of the second through-holes 33 and the second electrode 27a at the side walls of the second through-holes 33.

[0108] Referring to Figure 4k , a metal material layer 34 is formed. The metal material layer 34 covers the surface of the second dielectric layer 31 and the inner wall of the second through-hole 33. The metal material layer 34 covers the bottom wall and sidewalls of the second through-hole 33 to electrically connect the first metal line 11, the second metal line 12, the first electrode 24a, and the second electrode 27a. The metal material layer 34 can be made of a metal material suitable for connection to an external circuit, such as aluminum or an aluminum alloy. In this embodiment, the first metal line 11 and the second metal line 12 are made of copper. The metal material layer 34 includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer, and a titanium nitride layer, which are sequentially conformally formed.

[0109] 41 , a patterning process is performed on the metal material layer 34 to form a third metal wire 35 connecting the first metal wire 11 and the first electrode 24 a, and a fourth metal wire 36 connecting the second metal wire 12 and the second electrode 27 a. Specifically, the patterning process of the metal material layer 34 includes disconnecting the metal material layer 34 connecting the two sides of the capacitor area AA, utilizing the metal material layer 34 covering the inner wall of the second through hole 33 on the first metal wire 11 as the third metal wire 35, and utilizing the metal material layer 34 covering the inner wall of the second through hole 33 on the second metal wire 12 as the fourth metal wire 36.

[0110] In addition, during the process of performing the patterning process on the metal material layer 34, the metal material layer 34 can also be used to simultaneously form a metal pad on the second dielectric layer 31, and other top-level metal lines can be electrically led out to the metal pad for connection to an external circuit. In other words, the electrical lead-out (downward lead-out) of the capacitor in the semiconductor device of this embodiment can be achieved in the step of forming the metal pad (combined with the top-level metal wiring), and no additional device structure and process steps are required.

[0111] It is worth mentioning that in other examples of this embodiment, the first electrode in the capacitor can also extend to the second metal wire, and the second electrode extends above the first metal wire, so that the third metal wire formed is electrically connected to the first metal wire and the second electrode, and the fourth metal wire is electrically connected to the second metal wire and the first electrode.

[0112] Example 3

[0113] FIG5 is a flow chart of a method for manufacturing a semiconductor device provided in the third embodiment.

[0114] As shown in FIG5 , the method for manufacturing a semiconductor device provided in this embodiment includes:

[0115] S01: providing a substrate, in which a first metal wire and a second metal wire arranged in the same layer and an insulating layer covering the first metal wire and the second metal wire are formed.

[0116] S02: forming a plurality of trenches in the insulating layer between the first metal line and the second metal line.

[0117] S03a: forming a first electrode material layer, a first dielectric material layer and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the trench.

[0118] S03b: performing a patterning process on the second electrode material layer, the first dielectric material layer and the first electrode material layer to form a first electrode, a first dielectric layer and a second electrode covering the trench and the insulating layer around the trench, and exposing the surfaces of the second electrode and a portion of the first electrode.

[0119] S04: forming a second dielectric layer, where the second dielectric layer covers the insulating layer, the first electrode, the second electrode and the trench.

[0120] S05: forming a plurality of through holes in the second dielectric layer and the insulating layer to expose the first metal line, the second metal line, the first electrode, and the second electrode.

[0121] S06: forming a third metal line and a fourth metal line, wherein the third metal line electrically connects the first metal line and the second electrode, and the fourth metal line electrically connects the second metal line and the first electrode.

[0122] 6a to 61 are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a capacitive device provided in this embodiment. Next, the method for manufacturing the capacitive device will be described in detail with reference to FIG. 6a to FIG. 61 .

[0123] First, referring to FIG. 6 a , step S01 is performed to provide a substrate 10 , in which first metal wires 11 and second metal wires 12 arranged in the same layer and an insulating layer 22 covering the first metal wires 11 and the second metal wires 12 are formed.

[0124] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SiOI), silicon-germanium-on-insulator (SiGeO), silicon-germanium-on-insulator (SiGeO), and germanium-on-insulator (GeO). In this embodiment, the material of the substrate 10 is described using silicon (silicon substrate) as an example.

[0125] A device layer and an interconnection layer electrically connected to the device layer are formed in the substrate 10. The interconnection layer is located above the device layer and can be formed using a Damascene process. The first metal line 11 and the second metal line 12 can be two metal wirings spaced apart in the Nth layer (N is greater than or equal to 1) in the interconnection layer, and their materials can include, for example, copper. In this embodiment, the first metal line 11 and the second metal line 12 can be two top-layer metal wirings spaced apart. A dielectric barrier layer 21 and an insulating layer 22 are sequentially formed on the first metal line 11 and the second metal line 12. The material of the dielectric barrier layer 21 is used to block the escape of metal ions and serves as an etching stop layer during etching. The material of the dielectric barrier layer 21 can include, for example, silicon nitride or silicon carbonitride. The material of the insulating layer 22 is different from that of the dielectric barrier layer 21, and can include, for example, silicon oxide or silicon oxynitride.

[0126] In addition, in other examples of this embodiment, as needed, multiple (at least two) first metal wires 11 and multiple second metal wires 12 can be set, and multiple identical metal wires are connected in parallel; other metal wires can also be arranged between the first metal wire 11 and the second metal wire 12.

[0127] Next, referring to FIG. 6 b , step S02 is performed to form a plurality of trenches 23 in the insulating layer 22 between the first metal line 11 and the second metal line 12 .

[0128] A capacitor area AA is provided on the insulating layer 22 between the first metal line 11 and the second metal line 12, and a plurality of grooves 23 are formed in the grooves 23 for subsequently forming a single-layer capacitor thereon. Specifically, a fifth mask (not shown) can be first formed to cover the surface of the insulating layer 22, and a plurality of openings are formed on the area of ​​the fifth mask opposite to the capacitor area AA; using the first mask, the dielectric barrier layer 21 is used as an etching stop layer, and the insulating layer 22 is dry-etched to form a plurality of grooves 23 in the capacitor area AA; and then the fifth mask is removed. Among them, the capacitor area AA may include a plurality of grooves 23 and a portion of the insulating layer 22 around them. Of course, in other examples of this embodiment, the grooves 23 may not penetrate the insulating layer 22.

[0129] In addition, as needed, the capacitor area AA may further extend into the insulating layer 22 on the first metal line 11 and / or the second metal line 12 , that is, a trench 23 may be further formed in the insulating layer 22 on the first metal line 11 and / or the second metal line 12 .

[0130] Next, referring to FIG. 6 c , step S03 a is performed to sequentially form a first electrode material layer 24 , a first dielectric material layer 26 , and a second electrode material layer 27 to conformally cover the surface of the insulating layer 22 and the inner wall of the trench 23 . In other words, the first electrode material layer 24 , the first dielectric material layer 26 , and the second electrode material layer 27 are sequentially stacked. Any suitable process can be used to form a thin film conductive layer serving as the first electrode material layer 24 . The first electrode material layer 24 may include one or more thin film conductive layers, and the material may include, for example, one or more of titanium, titanium nitride, tantalum, or tantalum nitride. The formation process may include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The thickness of the first electrode material layer 24 may, for example, be 100 angstroms to 400 angstroms. The material of the first dielectric material layer 26 can be a dielectric material with a relatively high dielectric constant, for example, greater than or equal to 3.9, and can be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide; the material of the second electrode material layer 27 can be similar to that of the first electrode material layer 24.

[0131] Next, step S03b is performed to perform a patterning process on the second electrode material layer 27, the first dielectric material layer 26 and the first electrode material layer 24 to form a first electrode 24a, a first dielectric layer 26a and a second electrode 27a covering the trench 23 and the insulating layer 22 around the trench 23, and exposing the surface of the second electrode 27a and a portion of the first electrode 24a.

[0132] For example, referring to FIG. 6 d , the capacitor region AA has a first side A1 and a second side A2 respectively close to the first metal line 11 and the second metal line 12 (opposite to each other).

[0133] A third mask 40 is formed to cover the second electrode material layer 27 of capacitor area AA. The third mask 40 may also preferably extend to cover the second electrode material layer 27 near the first side A1 to facilitate subsequent electrical lead-out. However, it should be noted that the third mask 40 should avoid extending above the first metal line 11 or the second metal line 12 to prevent short circuits. In this embodiment, the first side A1 of capacitor area AA is close to the first metal line 11, and the third mask 40 may cover the second electrode material layer 27 of capacitor area AA and the second electrode material layer 27 between capacitor area AA and the first metal line 11.

[0134] Referring to Figure 6e, the second electrode material layer 27 and the first dielectric material layer 26 are sequentially etched using the third mask 40, exposing the surface of the first electrode material layer 24. The remaining second electrode material layer 27 serves as the second electrode 27a, and the remaining first dielectric material layer 26 serves as the first dielectric layer 26a. The third mask 40 is then removed. The second electrode 27a and the first dielectric layer 26a have as close coverage areas as possible, both covering the capacitor area AA and the area near the first side A1.

[0135] Referring to Figure 6f, a fourth mask 50 is formed to cover the second electrode 27a, and the fourth mask 50 extends to cover the first electrode material layer 24 near the second side A2. Preferably, the edge of the fourth mask 50 near the first side A1 can be aligned with the second electrode 27a as much as possible, and the edge of the fourth mask 50 on the other side of the capacitor area AA (near the second side A2) can extend onto the first electrode material layer 24. In other words, the fourth mask 50 can extend to cover the first electrode material layer 24 near the second side A2.

[0136] Referring to FIG. 6g , the first electrode material layer 24 is etched using the fourth mask 50 to expose the surface of the insulating layer 22. The remaining first electrode material layer 24 serves as the first electrode 24a, and the fourth mask 50 is then removed. The first electrode 24a includes the first electrode material layer 24 located below the second electrode 27a (or the first dielectric layer 26a) and the remaining first electrode material layer 24 on the insulating layer 22 near the second side A2.

[0137] Thus, a trench capacitor consisting of a first electrode 24a, a first dielectric layer 26a, and a second electrode 27a is formed on the insulating layer 22 within the trench 23 and around the trench 23 (capacitor region AA), thereby increasing the capacitance value (capacitance density) within the same area of ​​the substrate 10. Furthermore, the first electrode 24a and the second electrode 27a extend from the capacitor region AA toward the first metal line 11 and the second metal line 12, respectively, and are exposed to facilitate subsequent electrical extraction.

[0138] Next, referring to FIG6h, step S04 is performed to form a second dielectric layer 31, which covers the insulating layer 22, the first electrode 24a, the second electrode 27a, and the trench 23. The second dielectric layer 31 may include a single-layer dielectric or a multi-layer dielectric, and its material may include a suitable insulating material such as silicon oxide, silicon nitride, silicon carbon nitride, or silicon oxynitride, and may be formed using a suitable process including chemical vapor deposition or atomic layer deposition. In addition to covering the insulating layer 22, the first electrode 24a, and the second electrode 27a, the second dielectric layer 31 also fills the trench 23. Compared to the related art that uses electrode material to fill the trench 23 used to form the capacitor, the present embodiment uses the second dielectric layer 31 to fill the trench 23, which not only helps save electrode material but also provides greater freedom in the design of the trench capacitor. It should be understood that the trench capacitor in this embodiment does not lead the electrode out of the trench 23. Therefore, it is not necessary to fill the trench 23 with electrode material. That is, this embodiment allows the existence of voids in the trench capacitor (the void can be subsequently filled with a second dielectric layer).

[0139] Next, step S05 is performed to form a plurality of through holes in the second dielectric layer 31 and the insulating layer 22 to expose the first electrode 24 a , the second electrode 27 a , the first metal line 11 , and the second metal line 12 .

[0140] Referring to Figure 6i , the second electrode 27a is formed with a plurality of first through-holes 32 in the second dielectric layer 31, respectively exposing the first electrode 24a and the second electrode 27a. Some of the first through-holes 32 are located in the second dielectric layer 31 near the first side A1 to expose one of the first electrode 24a and the second electrode 27a, while other first through-holes 32 are located in the second dielectric layer 31 near the second side A2 to expose the other of the first electrode 24a and the second electrode 27a. In this embodiment, the first through-holes 32 near the first side A1 can expose the first electrode 24a, while the first through-holes 32 near the second side A2 can expose the second electrode 27a.

[0141] Referring to Figure 6j, a plurality of second through-holes 33 are formed in the insulating layer 22 and the second dielectric layer 31 to expose the first metal line 11 and the second metal line 12, respectively. Some of the second through-holes 33 may be located above the first metal line 11 to expose the first metal line 11, while other portions of the second through-holes 33 may be located above the second metal line 12 to expose the second metal line 12. In this embodiment, the second through-holes 33 also penetrate the dielectric barrier layer 21 beneath the insulating layer 22. When etching to form the second through-holes 33, the dielectric barrier layer 21 also serves as an etch-stop layer for etching the second dielectric layer 31 and the insulating layer 22, thereby reducing damage to the metal lines.

[0142] Next, step S06 is performed to form a third metal line 35 and a fourth metal line 36 . The third metal line 35 electrically connects the first metal line 11 and the second electrode 27 a , and the fourth metal line 36 electrically connects the second metal line 12 and the first electrode 24 a .

[0143] Referring to Figure 6k, a metal material layer 34 is formed to cover the surface of the second dielectric layer 31, the inner walls of the first through-hole 32, and the second through-hole 33. The metal material layer 34 can be a metal material suitable for connection to an external circuit, such as aluminum or an aluminum alloy. In this embodiment, the first metal wire 11 and the second metal wire 12 are made of copper, and the metal material layer 34 includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer, and a titanium nitride layer, which are formed conformally in sequence. In practice, since the size (depth and opening width) of the first through-hole 32 is smaller and the size of the second through-hole 33 is larger, the metal material layer 34 can completely fill the first through-hole 32, while the metal material layer 34 can only cover the inner wall of the second through-hole 33 without completely filling the second through-hole 33.

[0144] 61 , a patterning process is performed on the metal material layer 34 to form a third metal line 35 connecting the first metal line 11 and the second electrode 27 a, and a fourth metal line 36 connecting the second metal line 12 and the first electrode 24 a. Specifically, the patterning process of the metal material layer 34 includes disconnecting the metal material layer 34 connecting the two sides of the capacitor area AA, utilizing the metal material layer 34 covering the second through hole 33 on the first metal line 11 to the first through hole 32 near the first side A1 as the third metal line 35, and utilizing the metal material layer 34 covering the second through hole 33 on the second metal line 12 to the first through hole 32 near the second side A2 as the fourth metal line 36.

[0145] In addition, during the process of performing the patterning process on the metal material layer 34, the metal material layer 34 can also be used to simultaneously form a metal pad on the second dielectric layer 31, and other top-layer metal lines can be electrically led out to the metal pad for connection to an external circuit. In other words, the electrical lead-out (downward lead-out) of the trench capacitor of this embodiment can be achieved in the step of forming the metal pad, and no additional device structure and process steps are required.

[0146] It is worth mentioning that in other examples of this embodiment, the first electrode in the trench capacitor can also extend a portion of its length from the capacitor area to the first metal wire, and the second electrode can extend a portion of its length from the capacitor area to the second metal wire, so that the third metal wire formed is electrically connected to the first metal wire and the first electrode, and the fourth metal wire is electrically connected to the second metal wire and the second electrode.

[0147] Example 4

[0148] An embodiment of the present application also provides a semiconductor device.

[0149] FIG3m is a schematic structural diagram of a semiconductor device provided in Example 4.

[0150] The semiconductor device provided in this example can be formed using the method provided in Example 1. Specifically, as shown in FIG3 m , the semiconductor device may include a substrate 10 , a first metal line 11 , a second metal line 12 , an insulating layer 22 , a capacitor, a second dielectric layer 31 , a third metal line 35 , and a fourth metal line 36 .

[0151] The first metal line 11 and the second metal line 12 are arranged in the same layer in the substrate 10. The first metal line 11 and the second metal line 12 are covered by an insulating layer 22, and a plurality of trenches 23 are formed in the insulating layer 22 between the first metal line 11 and the second metal line 12.

[0152] The capacitor is formed in the trench 23 and on the insulating layer 22 around it (capacitor area AA), and includes a first electrode 24a, a first dielectric layer 26a, and a second electrode 27a that are conformally formed in sequence. The first electrode 24a extends a portion of the length from the capacitor area AA toward the first metal line 11 (i.e., a first extension area BB). The second electrode 27a (which may also include the first electrode 24a and the first dielectric layer 26a) extends a portion of the length from the capacitor area AA toward the second metal line 12 (i.e., a second extension area CC).

[0153] The second dielectric layer 31 covers the surface of the capacitor and the insulating layer 22. A plurality of through holes are formed in the second dielectric layer 31, and the plurality of through holes respectively expose the first electrode 24a, the second electrode 27a, the first metal wire 11 and the second metal wire 12; as an example, the plurality of through holes include a plurality of first through holes 32 and a plurality of second through holes 33.

[0154] Among them, a plurality of first through holes 32 respectively expose the first electrode 24a (for example, above the first extension region BB) and the second electrode 27a (for example, above the second extension region CC), and a plurality of second through holes 33 are formed in the second dielectric layer 31 and the insulating layer 22 respectively expose the first metal wire 11 and the second metal wire 12; the third metal wire 35 uses the first through hole 32 and the second through hole 33 near the first metal wire 11 to electrically connect the first metal wire 11 and the first electrode 24a, and the fourth metal wire 36 uses the first through hole 32 and the second through hole 33 near the second metal wire 12 to electrically connect the second metal wire 12 and the second electrode 27a.

[0155] FIG41 is a schematic structural diagram of another semiconductor device provided in the fourth embodiment.

[0156] The semiconductor device provided in this example can be formed using the method provided in Example 2. Specifically, as shown in FIG41 , the semiconductor device may include a substrate 10 , a first metal line 11 , a second metal line 12 , an insulating layer 22 , a capacitor, a second dielectric layer 31 , a third metal line 35 , and a fourth metal line 36 .

[0157] The first metal line 11 and the second metal line 12 are arranged in the same layer in the substrate 10. An insulating layer 22 covers the first metal line 11 and the second metal, and a plurality of trenches 23 are formed in the insulating layer 22 between the first metal line 11 and the second metal line 12.

[0158] The capacitor is formed in the trench 23 and on the insulating layer 22 around it, including a first electrode 24a, a first dielectric layer 26a and a second electrode 27a formed in sequence. The first electrode 24a and the second electrode 27a extend from the capacitor to the sides above the first metal line 11 and the second metal line 12 respectively.

[0159] A second dielectric layer 31 covers the surface of the capacitor and insulating layer 22. A plurality of through-holes (second through-holes 33) are formed in the second dielectric layer 31 and the insulating layer 22, respectively penetrating the first electrode 24a and the second electrode 27a and exposing the first metal line 11 and the second metal line 12. Specifically, the bottom wall of the second through-hole 33 above the first metal line 11 exposes the first metal line 11, and the sidewall thereof exposes the first electrode 24a. The bottom wall of the second through-hole 33 above the second metal line 12 exposes the second metal line 12, and the sidewall thereof exposes the second electrode 27a. A third metal line 35 covers the second through-hole 33 above the first metal line 11 to electrically connect the first metal line 11 and the first electrode 24a. A fourth metal line 36 covers the second through-hole 33 above the second metal line 12 to electrically connect the second metal line 12 and the second electrode 27a.

[0160] FIG61 is a schematic structural diagram of another semiconductor device provided in the fourth embodiment.

[0161] The capacitor device provided in this embodiment can be formed using the method provided in Example 3. Specifically, as shown in FIG61 , the capacitor device may include a substrate 10, a first metal wire 11 and a second metal wire 12, an insulating layer 22, a capacitor, a second dielectric layer 31, a third metal wire 35, and a fourth metal wire 36. The first metal wire 11 and the second metal wire 12 are arranged in the same layer in the substrate 10. The insulating layer 22 covers the first metal wire 11 and the second metal wire 12, and a plurality of grooves 23 are formed in the insulating layer 22 between the first metal wire 11 and the second metal wire 12.

[0162] The capacitor is formed in the insulating layer 22 in and around the trench 23 (capacitor region AA), and includes a first electrode 24a, a first dielectric layer 26a, and a second electrode 27a, which are conformally formed in sequence. The first electrode 24a extends partially from the capacitor region AA toward the second metal line 12 (i.e., the second side A2). The second electrode 27a and the first dielectric layer 26a extend partially from the capacitor region AA toward the first metal line 11 (i.e., the first side A1).

[0163] The second dielectric layer 31 covers the surface of the capacitor and the insulating layer 22. A plurality of through holes are formed in the second dielectric layer 31, and the plurality of through holes respectively expose the first electrode 24a, the second electrode 27a, the first metal wire 11 and the second metal wire 12; as an example, the plurality of through holes include a plurality of first through holes 32 and a plurality of second through holes 33.

[0164] Among them, a plurality of first through holes 32 expose the first electrode 24a and the second electrode 27a respectively, and a plurality of second through holes 33 are formed in the second dielectric layer 31 and the insulating layer 22 on the first metal wire 11 and the second metal wire 12 respectively to expose the first metal wire 11 and the second metal wire 12; the third metal wire 35 uses the first through hole 32 and the second through hole 33 close to the first metal wire 11 to electrically connect the first metal wire 11 and the second electrode 27a, and the fourth metal wire 36 uses the first through hole 32 and the second through hole 33 close to the second metal wire 12 to electrically connect the second metal wire 12 and the first electrode 24a.

[0165] In summary, the present invention provides a plurality of trenches in an insulating layer between a first metal line and a second metal line, and forms a capacitor in the trenches and on the insulating layer around the trenches. The capacitor includes a first electrode, a first dielectric layer, and a second electrode, which are conformally formed in sequence. The first electrode and the second electrode extend to both sides of the capacitor and are exposed upward. A second dielectric layer is then formed to cover the capacitor and the insulating layer, and through holes are formed in the second dielectric layer and the insulating layer to expose the first metal line, the second metal line, the first electrode, and the second electrode, respectively. A third metal line is then formed using the through holes to electrically connect the first electrode and the first metal line, and a fourth metal line is formed to electrically connect the second electrode and the second metal line. Thus, the two electrodes of the capacitor in the semiconductor device are led downward using the first metal line and the second metal line in the substrate. The lead-out of the capacitor in the semiconductor device and the wiring of the metal lines on the insulating layer are completed without adding additional process steps, thereby reducing the difficulty of process integration and facilitating an improvement in the capacitance density and design freedom of the capacitor in the semiconductor device. In addition, compared with the related art method in which trench capacitors require metal to fill the trench, the two electrodes of the capacitor in this embodiment extend to both sides to achieve electrical lead-out, and do not need to be filled with metal, that is, voids are allowed to exist, which is conducive to improving the freedom of trench capacitor design.

[0166] While the embodiments of the present application have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations may be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present application as set forth in the claims. Furthermore, the present application described herein may have other embodiments and may be implemented or carried out in a variety of ways.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, wherein a first metal line and a second metal line arranged in the same layer and an insulating layer covering the first metal line and the second metal line are formed in the substrate; forming a plurality of grooves in the insulating layer between the first metal line and the second metal line; A capacitor is formed in the groove and on the insulating layer around the groove, the capacitor comprising a first electrode, a first dielectric layer and a second electrode which are stacked; the first electrode at least covers the groove and the insulating layer around the groove, and at least a portion of one side of the groove on the outermost side of the first electrode is exposed; forming a second dielectric layer, wherein the second dielectric layer covers the exposed surfaces of the insulating layer, the first electrode and the second electrode; Patterning the second dielectric layer and the insulating layer to form a plurality of through holes in the second dielectric layer, wherein the plurality of through holes respectively expose the first metal line, the second metal line, the first electrode, and the second electrode; A third metal line and a fourth metal line are formed; the third metal line electrically connects the first metal line and one of the first electrode and the second electrode, and the fourth metal line electrically connects the second metal line and the other of the first electrode and the second electrode.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming the capacitor include: forming a first electrode, wherein the first electrode at least covers the trench and the insulating layer around the trench; A first dielectric layer and a second electrode are formed, wherein the first dielectric layer and the second electrode conformally cover the trench and the first electrode around the trench and expose a portion of the first electrode.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: A capacitor region is provided on the insulating layer between the first metal wire and the second metal wire, a plurality of grooves are formed in the capacitor region, and the step of forming the first electrode includes: forming a first electrode material layer to cover the surface of the insulating layer and the inner wall of the groove; forming a first mask, wherein the first mask covers the capacitor region and a first electrode material layer in a partial region close to one side of the first metal line; Using the first mask, etching away the exposed first electrode material layer, and using the remaining first electrode material layer as the first electrode; The first mask is removed.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The steps of forming the first dielectric layer and the second electrode include: forming a first dielectric material layer and a second electrode material layer in sequence to cover the surfaces of the insulating layer and the first electrode; forming a second mask, wherein the second mask covers the capacitor region and a portion of the second electrode material layer near one side of the second metal line, and the second mask exposes a portion of the second electrode material layer located on the first electrode; Using the second mask, performing a dry etching process to sequentially remove the exposed second electrode material layer and the first dielectric material layer, using the remaining second electrode material layer as the second electrode and the remaining first dielectric material layer as the first dielectric layer, and exposing a portion of the surface of the first electrode; The second mask is removed.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: A capacitor region is provided on the insulating layer between the first metal wire and the second metal wire, a plurality of grooves are formed in the capacitor region, and the step of forming the first electrode includes: forming a first electrode material layer to cover the surface of the insulating layer and the inner wall of the groove; forming a first mask, wherein the first mask covers the first electrode material layer from the capacitor region to above the first metal line; Using the first mask, etching away the exposed first electrode material layer, and using the first electrode material layer from the capacitor region to above the first metal line as the first electrode, wherein the first electrode extends from the capacitor region to above the first metal line; The first mask is removed.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The steps of forming the first dielectric layer and the second electrode include: forming a first dielectric material layer and a second electrode material layer in sequence to cover the surfaces of the insulating layer and the first electrode; forming a second mask, wherein the second mask covers the second electrode material layer from the capacitor region to above the second metal line; Using the second mask, performing a dry etching process to sequentially remove the exposed second electrode material layer and the first dielectric material layer, using the remaining second electrode material layer as the second electrode, and the remaining first dielectric material layer as the first dielectric layer, wherein the second electrode extends from the capacitor region to above the second metal line; The second mask is removed.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming the capacitor include: forming a first electrode material layer, a first dielectric material layer and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the groove; The second electrode material layer, the first dielectric material layer and the first electrode material layer are patterned to form a first electrode, a first dielectric layer and a second electrode covering the trench and the insulating layer around the trench, and exposing the second electrode and a portion of the first electrode.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: A capacitor region is provided on the insulating layer between the first metal line and the second metal line, a plurality of grooves are formed in the capacitor region, the capacitor region has a first side and a second side respectively close to the first metal line and the second metal line, and the steps of forming the second electrode and the first dielectric layer include: forming a third mask, wherein the third mask covers the second electrode material layer in the capacitor region, and the third mask extends to cover the second electrode material layer close to the first side; Using the third mask, etching the second electrode material layer and the first dielectric material layer to expose the surface of the first electrode material layer, and using the remaining second electrode material layer as the second electrode, and using the remaining first dielectric material layer as the first dielectric layer; The third mask is removed.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The step of forming the first electrode comprises: forming a fourth mask, wherein the fourth mask covers the second electrode and the fourth mask extends to cover the first electrode material layer close to the second side; Using the fourth mask, etching the first electrode material layer to expose the surface of the insulating layer, and using the remaining first electrode material layer as the first electrode; The fourth mask is removed.

10. The method for manufacturing a semiconductor device according to claim 4 or 7, characterized in that: The steps of forming a plurality of the through holes include: forming a plurality of first through holes in the second dielectric layer, wherein the plurality of first through holes expose the first electrode and the second electrode respectively; A plurality of second through holes are formed in the insulating layer and the second dielectric layer, and the plurality of second through holes expose the first metal wire and the second metal wire respectively.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The steps of forming the third metal line and the fourth metal line include: forming a metal material layer to cover the surface of the second dielectric layer, the first through hole and the inner wall of the second through hole; A patterning process is performed on the metal material layer to form a third metal line and a fourth metal line; wherein the third metal line electrically connects the first metal line and one of the first electrode and the second electrode, and the fourth metal line electrically connects the second metal line and the other of the first electrode and the second electrode.

12. The method for manufacturing a semiconductor device according to claim 6, wherein: The steps of forming the plurality of through holes, the third metal wire and the fourth metal wire include: Forming a plurality of through holes penetrating the insulating layer, the second dielectric layer, the first electrode, and the second electrode, so as to expose the first metal wire and the second metal wire at the bottom walls of the plurality of through holes, and to expose the first electrode and the second electrode at the side walls of the plurality of through holes; forming a metal material layer to cover the surface of the second dielectric layer and the inner wall of the through hole; A patterning process is performed on the metal material layer to form the third metal line electrically connecting the first metal line and the second electrode, and to form the fourth metal line electrically connecting the second metal line and the first electrode.

13. The method for manufacturing a semiconductor device according to any one of claims 1 to 12, characterized in that: A dielectric barrier layer is also provided between the substrate and the insulating layer.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The step of forming a plurality of the grooves in the capacitor region comprises: forming a fifth mask, wherein the fifth mask covers the surface of the insulating layer and has a plurality of openings formed in the capacitor region; Using the fifth mask and the dielectric barrier layer as an etching stop layer, dry etching the insulating layer to form a plurality of the grooves in the capacitor region; The fifth mask is removed.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: When the metal material layer is patterned, a metal pad is also formed on the surface of the insulating layer for connection with an external circuit.

16. The method for manufacturing a semiconductor device according to any one of claims 3 to 9, characterized in that: The materials of the first electrode material layer and the second electrode material layer include one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

17. A semiconductor device, characterized in that: include: substrate; A first metal line and a second metal line are arranged in the substrate in the same layer; an insulating layer, covering the first metal line and the second metal, wherein a plurality of grooves are formed in the insulating layer; A capacitor formed in the trench and on the insulating layer around it, comprising a first electrode, a first dielectric layer and a second electrode formed conformally in sequence; A second dielectric layer covers the capacitor, and a plurality of through holes are formed in the second dielectric layer and the insulating layer to expose the first electrode, the second electrode, the first metal wire, and the second metal wire respectively; A third metal wire and a fourth metal wire, wherein the third metal wire electrically connects the first metal wire and one of the first electrode and the second electrode by using the through hole, and the fourth metal wire electrically connects the second metal wire and the other of the first electrode and the second electrode by using the through hole.

18. The semiconductor device according to claim 17, wherein: The plurality of through holes include a plurality of the first through holes and a plurality of the second through holes; The first through holes respectively expose the first electrode and the second electrode, and the second through holes respectively expose the first metal line and the second metal line.

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