MIM capacitor and manufacturing method therefor

Abstract

An MIM capacitor and a manufacturing method therefor. The manufacturing method comprises: providing a substrate comprising a device area and a peripheral area, wherein the device area is provided with a metal line, the peripheral area is provided with a metal bonding pad which is arranged on the same layer as the metal line, and an insulating layer covers the metal line and the metal bonding pad; forming a trench in the insulating layer, wherein the trench exposes the metal line; sequentially conformally forming a first electrode and a first dielectric layer on the trench and the insulating layer on the periphery of the trench, wherein the first electrode is electrically connected to the metal line by means of the trench; forming a second electrode to cover the first dielectric layer so as to be electrically connected to the metal bonding pad; and forming a second dielectric layer to cover the insulating layer and the surface of the second electrode, and filling the trench. The lead-out and electrical connection of a first electrode and a second electrode of a single-layer capacitor are completed while the single-layer capacitor is formed, thereby optimizing the formation, lead-out, and electrical connection processes of the single-layer capacitor.

Description

MIM capacitor and method for manufacturing the same

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310948099.7 and application name “MIM capacitor and its manufacturing method”, and the priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310948111.4 and application name “Metal-insulator-metal capacitor and its manufacturing method”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and more specifically, to a MIM capacitor and a manufacturing method thereof. Background Art

[0003] With the continuous development of semiconductor technology, the application of metal-insulator-metal capacitors (MIM) integrated between back-end metal layers is becoming more and more widespread. The application of metal-insulator-metal capacitor structures can reduce the size of semiconductor devices and make semiconductor devices more functional. However, the preparation process of semiconductor devices with metal-insulator-metal capacitor structures is cumbersome, which makes the production efficiency of semiconductor devices with metal-insulator-metal capacitor structures low.

[0004] Metal-insulator-metal capacitors (MIM) planar capacitors require a large area to achieve high capacitance, sacrificing design area. Therefore, MEM trench capacitors become the best choice for high capacitance.

[0005] In the related art, taking the formation of a metal-insulator-metal capacitor trench capacitor as an example, the trench capacitor is typically formed in a dielectric layer, the dielectric layer is then opened multiple times to form several openings to expose the top and bottom electrodes of the trench capacitor, as well as the metal lines corresponding to the trench capacitor. Aluminum is then deposited to form aluminum lines connecting the top and bottom electrodes of the trench capacitor and the corresponding metal lines. It is not difficult to see that the process of forming a metal-insulator-metal capacitor trench capacitor in the related art requires many mask layers, is complex, and is costly.

[0006] Summary of the Invention

[0007] The purpose of this application is to provide a MIM capacitor and a manufacturing method thereof to solve the problems of complex manufacturing process and high cost of current MIM capacitors.

[0008] In a first aspect, the present application discloses a method for manufacturing a MIM capacitor, comprising:

[0009] Providing a substrate, comprising a device area and a peripheral area, wherein the device area has a first metal line, the peripheral area has a metal pad arranged in the same layer as the first metal line, and an insulating layer covers the first metal line and the metal pad;

[0010] forming a trench in the insulating layer, wherein the trench exposes the first metal line;

[0011] forming a first electrode and a first dielectric layer conformally in sequence on the trench and the insulating layer around it, wherein the first electrode is electrically connected to the first metal wire via the trench;

[0012] forming a second electrode covering the first dielectric layer, wherein the second electrode is electrically connected to the metal pad;

[0013] A second dielectric layer is formed to cover the surfaces of the insulating layer and the second electrode and to fill the trench.

[0014] In a second aspect, the present application discloses a MIM capacitor, comprising:

[0015] A substrate having a device region and a peripheral region;

[0016] a first metal line and a metal pad, wherein the first metal line is provided in the device area, and the metal pad and the first metal line are arranged in the peripheral area in the same layer;

[0017] an insulating layer covering the first metal line and the metal pad, wherein a groove is formed in the insulating layer to expose the first metal line, and a through hole is formed to expose the metal pad;

[0018] A capacitor comprising a first electrode, a first dielectric layer, and a second electrode conformally covering the trench and the surrounding insulating layer, wherein the first electrode is electrically connected to the first metal line via the trench, and the second electrode extends from the trench to cover the inner wall of the through hole to be electrically connected to the metal pad;

[0019] The second dielectric layer covers the surfaces of the insulating layer and the second electrode and fills the trench and the through hole.

[0020] In a third aspect, the present application discloses a MIM capacitor, comprising:

[0021] A substrate having a device region and a peripheral region;

[0022] a first metal line and a metal pad, wherein the first metal line is provided in the device area, and the metal pad and the first metal line are arranged in the peripheral area in the same layer;

[0023] an insulating layer covering the first metal line and the metal pad, wherein a groove is formed in the insulating layer to expose the first metal line;

[0024] The MIM capacitor comprises a first electrode, a first dielectric layer, and a second electrode that conformally cover the trench and the surrounding insulating layer, wherein the first electrode is electrically connected to the first metal line via the trench;

[0025] a second dielectric layer covering the surfaces of the insulating layer and the second electrode and filling the trench, wherein the second dielectric layer between the trenches is provided with a first opening exposing the second electrode, and a second opening is provided in the second dielectric layer and the insulating layer on the metal pad to expose the metal pad;

[0026] The second metal wire covers the surface of the second dielectric layer, the first opening, and the inner wall of the second opening to electrically connect the second electrode and the metal pad.

[0027] In combination with the above technical solution, the present application exposes the first metal wire in a groove in the insulating layer on the first metal wire, forms a trench capacitor consisting of a first electrode, a first dielectric layer and a second electrode on the trench and the insulating layer around the trench, and uses the first metal wire exposed at the bottom of the trench to complete the lead-out and electrical connection between the first electrode of the trench capacitor and the first metal wire. This allows the present embodiment to complete the formation, lead-out and electrical connection of the MIM trench capacitor with fewer photolithography processes, thereby having a simple and efficient process flow, which is conducive to reducing costs. Compared to the related art that uses metal materials to fill the gaps in the trench capacitor for lead-out, the present invention uses a second dielectric layer to fill the gaps in the trench, which is not only conducive to saving electrode materials, but also helps to reduce the corresponding process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a flow chart of a method for manufacturing a MIM capacitor according to Embodiment 1 and Embodiment 2;

[0029] 2a to 2f are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a MIM capacitor provided in Example 1;

[0030] 3a to 3c are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a MIM capacitor provided in Example 2;

[0031] FIG4 is a flow chart of a method for manufacturing a MIM capacitor according to Embodiment 3 and Embodiment 4;

[0032] FIG2a and FIG5a to FIG5g are structural schematic diagrams corresponding to corresponding steps of the method for manufacturing a MIM capacitor provided in Example 3;

[0033] 6a to 6c are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a MIM capacitor provided in the fourth embodiment.

[0034] 10-substrate; 11-first metal wire; 12-metal pad; AA-device area; BB-peripheral area; 21-dielectric barrier layer; 22-insulating layer; 23-groove; 24-through hole; 31-first electrode material layer; 31a-first electrode; 32-first dielectric material layer; 32a-first dielectric layer; 33-second electrode material layer; 33a-second electrode; 34-gap; 35-second dielectric layer; 36a-first opening; 36b-second opening; 37-second metal wire; 38-third dielectric layer. DETAILED DESCRIPTION

[0035] In embodiments of the present invention, the term "and / or" describes the association relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0036] In the embodiments of the present application, the term "plurality" refers to two or more than two, and other quantifiers are similar.

[0037] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0038] The embodiments of the present application provide a MIM capacitor and a method for manufacturing the same, to solve the problems of complex manufacturing processes and high costs of current MIM capacitors.

[0039] FIG1 is a flow chart of a method for manufacturing a MIM capacitor provided in Example 1 of the present application.

[0040] As shown in FIG1 , the method for manufacturing a MIM container provided in this embodiment includes:

[0041] S01: Providing a substrate, comprising a device area and a peripheral area, wherein the device area has metal lines, the peripheral area has metal pads arranged in the same layer as the metal lines, and an insulating layer covers the metal lines and the metal pads;

[0042] S02: forming a groove and a through hole in the insulating layer, wherein the groove exposes the metal line, and the through hole exposes the metal pad;

[0043] S03: conformally forming a first electrode and a first dielectric layer on the trench and the insulating layer around it, wherein the first electrode is electrically connected to the metal wire via the trench;

[0044] S04: forming a second electrode to cover the first dielectric layer and extend to cover the inner wall of the through hole to be electrically connected to the metal pad;

[0045] S05: forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode, and filling the trench and the through hole.

[0046] 2a to 2f are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a MIM capacitor provided in this embodiment. Next, the method for manufacturing the MIM capacitor will be described in detail with reference to FIG. 2a to 2f.

[0047] First, referring to FIG. 2 a , step S01 is performed to provide a substrate 10 including a device area AA and a peripheral area BB. The device area AA has a metal line 11 , and the peripheral area BB has a metal pad 12 arranged in the same layer as the metal line 11 . The insulating layer 22 covers the metal line 11 and the metal pad 12 .

[0048] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGIO), silicon-germanium-on-insulator (SGIO), and germanium-on-insulator (GeO). In this embodiment, the material of the substrate 10 is described using silicon as an example.

[0049] Substrate 10 may include a device area AA and a peripheral area BB. Device area AA is used to form a semiconductor device, and peripheral area BB is used to form a peripheral circuit. Interconnect layers are formed on both the semiconductor device and the peripheral circuit. Metal line 11 may be a metal wiring located in the Nth layer of the interconnect layer in device area AA, and may be used to connect to the bottom electrode of the trench capacitor. Metal pad 12 may be a metal wiring located in the same layer as metal line 11 in the interconnect layer in peripheral area BB, and may be used to connect to the top electrode of the trench capacitor. In one example, metal pad 12 may be, for example, a common ground terminal.

[0050] A dielectric barrier layer 21 and an insulating layer 22 are sequentially formed over the metal line 11 and the metal pad 12. The dielectric barrier layer 21 is formed of a different material than the insulating layer 22. The dielectric barrier layer 21 can be used to block the escape of metal ions and serve as an etch stop during etching. The dielectric barrier layer 21 can be made of, for example, silicon nitride or silicon carbonitride. In this embodiment, the metal line 11 and the metal pad 12 can be top-layer metal wiring and can be made of copper. The dielectric barrier layer 21 can be made of silicon nitride or silicon oxynitride, and the insulating layer 22 can be made of silicon oxide.

[0051] In addition, in other examples of this embodiment, as needed, multiple metal wires 11 and multiple metal pads 12 can be provided to form multiple trench capacitors respectively connected in parallel to one or at least two metal pads 12 , and each trench capacitor can also include one or at least two metal wires 11 .

[0052] Next, referring to FIG. 2 b , step S02 is performed to form a trench 23 and a through hole 24 in the insulating layer 22 . The trench 23 exposes the metal line 11 , and the through hole 24 exposes the metal pad 12 .

[0053] Specifically, a first mask can be formed to cover the surface of the insulating layer 22. The first mask has a plurality of first openings and a plurality of second openings. Using the first mask, a first etching process is performed on the insulating layer 22 and the dielectric barrier layer 21. The first openings are used to form a plurality of trenches 23 penetrating the insulating layer 22 and the dielectric barrier layer 21 to expose the surface of the metal line 11. Simultaneously, the second openings are used to form a plurality of vias 24 penetrating the insulating layer 22 and the dielectric barrier layer 21 to expose the surface of the metal pad 12. The first mask is then removed. At least one trench 23 is located above the metal line 11 to expose the surface of the metal line 11. Some trenches 23 may also be located in the insulating layer 22 surrounding the metal line 11. All vias 24 are located above the metal pad 12.

[0054] Next, step S03 is performed to conformally form a first electrode 31 and a first dielectric layer 33 on the trench 23 and the insulating layer 22 around it. The first electrode 31 is electrically connected to the metal line 11 via the trench 23 .

[0055] Specifically, referring to Figure 2c, the first electrode 31 is formed. The specific steps include forming a first electrode material layer 32 to cover the surface of the insulating layer 22, the inner walls of the trench 23, and the through-hole 24. Any suitable process can be used to form a thin film conductive layer as the first electrode material layer 32. The first electrode material layer 32 may include one or more thin film conductive layers, and the material may be, for example, titanium, titanium nitride, tantalum, or tantalum nitride. The formation process may include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The thickness of the first electrode material layer 32 may be, for example, 100 to 400 angstroms. Next, a second mask is formed to cover the first electrode material layer 32 on the insulating layer 22 surrounding the trench 23, the through-hole 24, and the surrounding trenches 23 and the through-hole 24. Next, using a second mask, a second etching process is performed on the first electrode material layer 32 to remove the exposed first electrode material layer 32, and then the second mask is removed, so that the first electrode material layer 32 on the groove 23 and the insulating layer 22 around it serves as the first electrode 31, and the first electrode material layer 32 is retained to cover the inner wall of the through hole 24 and the surrounding insulating layer 22 to be electrically connected to the metal pad 12.

[0056] Next, referring to Figure 2d, a first dielectric layer 33 is formed on the first electrode 31. The specific steps include: forming a first dielectric material layer to cover the surface of the substrate 10, namely, the insulating layer 22, the surface of the first electrode 31, and the inner wall of the through-hole 24. The material of the first dielectric material layer can be a dielectric material with a relatively high dielectric constant, such as greater than or equal to 3.9, and can be made of, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide. Next, a third mask is formed to cover the first electrode 31 and the insulating layer 22 surrounding it, exposing the first dielectric material layer in the through-hole 24 and its surrounding area. Next, a third etching process is performed on the first dielectric material layer using the third mask to remove the exposed first dielectric material layer. The third mask is then removed, leaving the first dielectric material layer on the first electrode 31 and the insulating layer 22 surrounding it as the first dielectric layer 33, and exposing at least the first electrode material layer 32 on the bottom wall of the through-hole 24. The formed first dielectric layer 33 covers the first electrode 31 and extends to cover the insulating layer 22 around the first electrode 31 to completely enclose the first electrode 31 to form better electrical isolation.

[0057] In some embodiments, the cross-sectional shape of the through-hole 24 may be an inverted trapezoidal shape. A first electrode material layer 32 is coated on the inner wall of the through-hole 24 as a protective layer. The etching strength of the first dielectric material layer 34 is appropriately increased. This allows the first dielectric material layer 34 on the bottom and sidewalls of the through-hole 24 to be removed simultaneously with the first dielectric material layer 34 exposed on the insulating layer 22. This allows the first electrode material layer 32 on the inner wall of the through-hole 24 to be exposed as much as possible, thereby facilitating reduced contact resistance. In practice, however, a portion of the first dielectric material layer 34 may remain on the sidewalls of the through-hole 24.

[0058] Next, referring to FIG. 2 e , step S04 is performed to form a second electrode 35 covering the first dielectric layer 33 and extending to cover the inner wall of the through hole 24 to be electrically connected to the metal pad 12 .

[0059] Specifically, a second electrode 35 material layer can first be formed to cover the surface of the substrate 10, namely, the surface of the insulating layer 22, the surface of the first dielectric layer 33, and the inner wall of the through-hole 24. The material of the second electrode 35 material layer can be similar to that of the first electrode material layer 32. Next, a fourth mask is formed to cover the first dielectric layer 33, the through-hole 24, and the second electrode 35 material layer on the insulating layer 22 from the trench 23 to the through-hole 24. Next, a fourth etching process is performed on the second electrode 35 material layer to remove the exposed second electrode 35 material layer, and the fourth mask is then removed. The remaining second electrode 35 material layer on the first dielectric layer 33, the inner wall of the through-hole 24, and the insulating layer 22 between the trench 23 and the through-hole 24 serves as the second electrode 35. The second electrode 35 extends from above the trench 23 to above the through-hole 24 and is electrically connected to the metal pad 12 using the first electrode material layer 32 in the through-hole 24.

[0060] Thus, a trench capacitor consisting of a first electrode 31, a first dielectric layer 33, and a second electrode 35 is formed in the trench 23 and on the insulating layer 22 around the trench 23. The metal line 11 is exposed at the bottom of the trench 23 to complete the lead-out and electrical connection between the first electrode 31 of the trench capacitor and the metal line 11. After the through hole 24 is formed to expose the first electrode material layer 32, the second electrode 35 is formed extending from the trench 23 to the through hole 24 to simultaneously form the lead-out of the second electrode 35 of the trench capacitor and the electrical connection with the metal pad 12. Moreover, the above-mentioned trench 23 and through hole 24 are formed in the same photolithography process, so that this embodiment only requires four etching processes to complete the formation, lead-out, and electrical connection of the trench capacitor with the metal line 11 and the metal pad 12, thereby having a simple and efficient process flow, which is conducive to reducing costs.

[0061] Next, referring to FIG. 2 f , step S05 is performed to form a second dielectric layer 36 to cover the surfaces of the insulating layer 22 and the second electrode 35 , and to fill the trench 23 and the through hole 24 .

[0062] The material of the second dielectric layer 36 can be any suitable passivation layer material, such as silicon oxide and / or silicon nitride. The second dielectric layer 36 can also fill the groove 23 and the through hole 24 until it is substantially flush with the surface of the surrounding second dielectric layer 36. Compared with the use of metal materials in the related art to fill the gap 37 used to form the trench capacitor for extraction, this embodiment uses the second dielectric layer 36 to fill the gap 37 in the trench 23, which is not only conducive to saving electrode materials, but also conducive to reducing the corresponding process difficulty. It should be understood that since metal aluminum is usually formed by a sputtering process, it has high requirements for the aluminum sputtering process when filling the gap 37. The trench capacitor in this embodiment does not extract the electrode from the trench 23. Therefore, it is not necessary to use a metal material to fill the gap 37 in the trench 23. That is, the present embodiment allows the presence of a gap 37 in the trench capacitor.

[0063] Embodiment 2 of the present application also provides a method for manufacturing a MIM capacitor.

[0064] FIG1 is a flow chart of a method for manufacturing a MIM capacitor provided in a second embodiment.

[0065] As shown in FIG1 , the method for manufacturing a MIM capacitor provided in this embodiment includes:

[0066] S01: Providing a substrate, comprising a device area and a peripheral area, wherein the device area has metal lines, the peripheral area has metal pads arranged in the same layer as the metal lines, and an insulating layer covers the metal lines and the metal pads;

[0067] S02: forming a groove and a through hole in the insulating layer, wherein the groove exposes the metal line, and the through hole exposes the metal pad;

[0068] S03: conformally forming a first electrode and a first dielectric layer on the trench and the insulating layer around it, wherein the first electrode is electrically connected to the metal wire via the trench;

[0069] S04: forming a second electrode to cover the first dielectric layer and extend to cover the inner wall of the through hole to be electrically connected to the metal pad;

[0070] S05: forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode, and filling the trench and the through hole.

[0071] The manufacturing method of the MIM capacitor provided in this second embodiment is similar to the method provided in the above first embodiment, with the main difference being the step of forming the first electrode in step S03 of the second embodiment. Figures 3a to 3c are structural schematic diagrams corresponding to the corresponding steps of forming the MIM capacitor provided in the second embodiment. Next, the manufacturing method of the MIM capacitor will be described in detail with reference to Figures 3a to 3c.

[0072] Referring to Figure 3a, the first electrode 31 is formed. The specific steps include forming a first electrode material layer 32 to cover the surface of the insulating layer 22, the trench 23, and the inner wall of the through-hole 24. Next, a second mask is formed to cover the trench 23 and the first electrode material layer 32 on the insulating layer 22 surrounding it. Unlike the second mask in the first embodiment, the second mask in this embodiment also exposes the first electrode material layer 32 on the through-hole 24 and its surrounding area. Next, a second etching process is performed on the first electrode material layer 32 using the second mask to remove the exposed first electrode material layer 32. The second mask is then removed, leaving the first electrode material layer 32 on the insulating layer 22 in the trench 23 and its surrounding area as the first electrode 31. Since the first electrode material layer 32 on the through-hole 24 and its surrounding area is not protected by the mask, the first electrode material layer 32 on the bottom wall of the through-hole 24 can be removed to expose the surface of the metal pad 12, while a larger amount of the first electrode material layer 32 on the sidewalls of the through-hole 24 can remain. Of course, it is also possible to retain a portion of the first electrode material layer 32 on the bottom wall of the through-hole 24.

[0073] Referring to Figure 3b , the first dielectric layer 33 is formed. Specifically, the steps include forming a first dielectric material layer 34 to cover the surface of the substrate 10, namely, the surface of the insulating layer 22, the surface of the first electrode 31, and the inner wall of the through-hole 24. Next, a third mask is formed to cover the first electrode 31 and the surrounding insulating layer 22, exposing the first dielectric material layer 34 in the through-hole 24 and its surrounding area. Next, a third etching process is performed on the first dielectric material layer 34 using the third mask to remove the exposed first dielectric material layer 34. The third mask is then removed, leaving the remaining first dielectric material layer 34 on the first electrode 31 and the surrounding insulating layer 22 as the first dielectric layer 33, while at least partially exposing the metal pad 12 and / or the first electrode material layer 32 on the bottom wall of the through-hole 24. Portions of the first dielectric material layer 34 may also remain on the sidewalls of the through-hole 24. The formed first dielectric layer 33 covers the first electrode 31 and extends to cover the insulating layer 22 surrounding the first electrode 31, completely encapsulating the first electrode 31 and providing better electrical isolation.

[0074] 3 c , a second electrode 35 and a second dielectric layer 36 are formed in sequence.

[0075] An embodiment of the present application also provides a MIM capacitor.

[0076] The MIM capacitor provided in this embodiment can be formed using the manufacturing method of the MIM capacitor provided in the above-mentioned embodiment 1 and embodiment 2. Specifically, as shown in Figure 2f or Figure 3c, the MIM capacitor provided in this embodiment may include a substrate 10, a metal wire 11, a metal pad 12, an insulating layer 22, a trench capacitor and a second dielectric layer 36. Among them, the substrate 10 has a device area AA and a peripheral area BB, the device area AA is used to form a semiconductor device, and the peripheral area BB is used to form a peripheral circuit. The metal wire 11 is provided in the device area AA of the substrate 10, and the metal pad 12 is arranged in the same layer as the metal wire 11 in the peripheral area BB of the substrate 10. The insulating layer 22 covers the device area AA and the peripheral area BB of the substrate 10, that is, covers the surface of the metal wire 11 and the metal pad 12. A plurality of grooves 23 are formed in the insulating layer 22 on the metal wire 11 to expose the metal wire 11, and a plurality of through holes 24 are formed in the insulating layer 22 on the metal pad 12 to expose the metal pad 12. The trench capacitor is formed on the trench 23 and the insulating layer 22 surrounding it. It includes a first electrode 31, a first dielectric layer 33, and a second electrode 35, which are formed conformally in sequence. The first electrode 31 is electrically connected to the metal line 11 at the bottom of the trench 23. The second electrode 35 covers the surface of the first dielectric layer 33 and extends from the trench 23 to the inner wall of the through-hole 24 to electrically connect to the metal pad 12. The second dielectric layer 36 covers the surface of the insulating layer 22 and the second electrode 35, and fills the trench 23 and the through-hole 24.

[0077] In summary, the present invention simultaneously forms a trench and a through-hole in an insulating layer, utilizes the trench to expose a metal line, utilizes the through-hole to expose a metal pad, and then conformally forms a first electrode, a first dielectric layer, and a second electrode on the trench and the insulating layer surrounding it to form a trench capacitor, and extends the second electrode from the device region to the peripheral region, that is, extends from the trench capacitor to cover the inner wall of the through-hole, so that the second electrode is electrically connected to the metal pad, thereby completing the extraction and electrical connection of the first electrode and the second electrode of the capacitor while forming the capacitor. That is, when forming the first electrode, the metal line exposed at the bottom of the trench is utilized to complete the extraction of the first electrode of the trench capacitor and the electrical connection to the metal line, and when forming the second electrode, the second electrode is utilized to extend from the trench to the through-hole to achieve the extraction of the second electrode and the electrical connection to the metal pad. As a result, this embodiment only requires four photolithography processes to complete the formation, extraction, and electrical connection of the capacitor to the metal line and the metal pad, thereby having a simple and efficient process flow, which is conducive to reducing costs. Compared with the related art that uses metal materials to fill the gaps in the trench capacitors for lead-out, the present invention uses a second dielectric layer to fill the gaps in the trenches, which not only helps save electrode materials but also helps reduce the corresponding process difficulty.

[0078] An embodiment of the present application also provides a method for manufacturing a MIM capacitor.

[0079] FIG4 is a flow chart of a method for manufacturing a MIM capacitor provided in the third embodiment.

[0080] As shown in FIG4 , the method for manufacturing a MIM capacitor provided in this embodiment includes:

[0081] S01: Providing a substrate, comprising a device area and a peripheral area, wherein the device area has a first metal line, and the peripheral area has a metal pad arranged in the same layer as the first metal line, wherein the first metal line and the metal pad are covered with an insulating layer;

[0082] S02: forming a trench in the insulating layer on the first metal line to expose the first metal line;

[0083] S03: forming a first electrode material layer, a first dielectric material layer, and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the trench, and performing photolithography and etching to sequentially form a second electrode, a first dielectric layer, and an insulating layer covering the trench and its surroundings by the first electrode to form a MIM capacitor, wherein the first electrode is electrically connected to the first metal wire via the trench;

[0084] S04: forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode, and filling the trench;

[0085] S05: forming a first opening in the second dielectric layer to expose the second electrode, and forming a second opening in the second dielectric layer and the insulating layer to expose the metal pad;

[0086] S06: forming a second metal line to electrically connect the second electrode and the metal pad using the first opening and the second opening.

[0087] FIG2a and FIG5a to FIG5e are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a MIM capacitor provided in this embodiment. Next, the method for manufacturing the MIM capacitor will be described in detail with reference to FIG2a and FIG5a to FIG5e.

[0088] First, please refer to Figure 2a and perform step S01 to provide a substrate 10, including a device area AA and a peripheral area BB. The device area AA has a first metal wire 11, and the peripheral area BB has a metal pad 12 arranged in the same layer as the first metal wire 11. The first metal wire 11 and the metal pad 12 are covered with an insulating layer 22.

[0089] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGIO), silicon-germanium-on-insulator (SGIO), and germanium-on-insulator (GeO). In this embodiment, the material of the substrate 10 is described using silicon as an example.

[0090] Substrate 10 may include a device area AA and a peripheral area BB. Device area AA is used to form a semiconductor device, and peripheral area BB is used to form a peripheral circuit. Interconnect layers are formed on both the semiconductor device and the peripheral circuit. First metal line 11 may be a metal wiring in the Nth layer of the interconnect layer in device area AA, and may be used to connect to the bottom electrode of the MIM trench capacitor. Metal pad 12 may be a metal wiring arranged in the same layer as first metal line 11 in the interconnect layer in peripheral area BB, and may be used to connect to the top electrode of the MIM trench capacitor. In one example, metal pad 12 may be, for example, a common ground terminal.

[0091] A dielectric barrier layer 21 and an insulating layer 22 are sequentially formed on the first metal line 11 and the metal pad 12. The material of the dielectric barrier layer 21 is different from that of the insulating layer 22. The dielectric barrier layer 21 can be used to block the escape of metal ions and serve as an etch stop layer during etching. The material of the dielectric barrier layer 21 can include, for example, silicon nitride or silicon carbonitride. In this embodiment, the first metal line 11 and the metal pad 12 can be top-layer metal wiring and can be made of copper. The dielectric barrier layer 21 can be made of silicon nitride or silicon oxynitride, and the insulating layer 22 can be made of silicon oxide.

[0092] In addition, in other examples of this embodiment, as needed, multiple first metal wires 11 and multiple metal pads 12 can be set to form multiple trench capacitors connected in parallel to one or at least two metal pads 12, and each trench capacitor can also include one or at least two first metal wires 11.

[0093] Next, referring to FIG. 5 a , step S02 is performed to form a trench 23 in the insulating layer 22 on the first metal line 11 to expose the first metal line 11 .

[0094] Specifically, a first mask can be formed to cover the surface of the insulating layer 22. The first mask has a plurality of openings. Using the first mask, a first etching process is performed on the insulating layer 22 and the dielectric barrier layer 21. The first openings 36a are used to form a plurality of trenches 23 penetrating the insulating layer 22 and the dielectric barrier layer 21 to expose the surface of the first metal line 11. The first mask is then removed. At least one trench 23 is located above the first metal line 11 to expose the surface of the first metal line 11. Some trenches 23 may also be located in the insulating layer 22 surrounding the first metal line 11.

[0095] Next, step S03 is performed to sequentially form a first electrode material layer 31, a first dielectric material layer 32, and a second electrode material layer 33 to conformally cover the surface of the insulating layer 22 and the inner wall of the trench 23. Photolithography is then performed to sequentially form a second electrode 33a, a first dielectric layer 32a, and a first electrode 31a to cover the trench 23 and the insulating layer 22 surrounding it to form a trench capacitor. The first electrode 31a is electrically connected to the first metal line 11 via the trench 23.

[0096] Specifically, referring to FIG5b , a first electrode material layer 31, a first dielectric material layer 32, and a second electrode material layer 33 are sequentially formed to conformally cover the surface of the substrate 10, namely, the surface of the insulating layer 22 and the inner wall of the trench 23. Any suitable process can be used to form a thin film conductive layer serving as the first electrode material layer 31. The first electrode material layer 31 may include one or more thin film conductive layers, and the material may be, for example, titanium, titanium nitride, tantalum, or tantalum nitride. The formation process may include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The thickness of the first electrode material layer 31 may be, for example, 100 to 400 angstroms. The first dielectric material layer 32 may be made of a dielectric material with a relatively high dielectric constant, such as greater than or equal to 3.9. The material may be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide. The material of the second electrode material layer 33 may be similar to that of the first electrode material layer 31.

[0097] Next, referring to Figure 5c, a second mask is formed to cover the trench 23 and the second electrode material layer 33 on the surrounding insulating layer 22. Using the second mask, a second etching process is performed to sequentially etch the second electrode material layer 33, the first dielectric material layer 32, and the first electrode material layer 31 to form a second electrode 33a, the first dielectric layer 32a, and the first electrode 31a. The second mask is then removed. The second electrode 33a, the first dielectric layer 32a, and the first electrode 31a can have approximately the same coverage area to form a trench capacitor. The first electrode 31a of the trench capacitor is then led out and electrically connected to the first metal line 11 at the bottom of the trench 23.

[0098] Next, referring to FIG. 5 d , step S04 is performed to form a second dielectric layer 35 to cover the surfaces of the insulating layer 22 and the second electrode 33 a and to fill the trench 23 .

[0099] The material of the second dielectric layer 35 can be any suitable passivation layer material, such as silicon oxide and / or silicon nitride. The second dielectric layer 35 can also fill the gap 34 in the groove 23 until it is substantially flush with the surface of the second dielectric layer 35 around it. Compared with the use of metal materials in the related art to fill the gap 34 used to form the trench capacitor for extraction, this embodiment uses the second dielectric layer 35 to fill the gap 34 in the trench 23, which is not only conducive to saving electrode materials, but also conducive to reducing the corresponding process difficulty. It should be understood that since metal aluminum is usually formed by a sputtering process, it has high requirements for the aluminum sputtering process when filling the gap 34. The trench capacitor in this embodiment does not extract the electrode from the trench 23. Therefore, it is not necessary to use a metal material to fill the gap 34 in the trench 23. That is, the trench capacitor is allowed to have a gap 34 in this embodiment.

[0100] Next, step S05 is performed to form a first opening 36 a in the second dielectric layer 35 to expose the second electrode 33 a , and a second opening 36 b in the second dielectric layer 35 and the insulating layer 22 to expose the metal pad 12 .

[0101] 5e, a first opening 36a may be formed in the second dielectric layer 35 to expose the second electrode 33a. Specifically, the steps include: first, forming a third mask to cover the surface of the second dielectric layer 35, wherein the third mask has a plurality of openings exposing at least a portion of the second dielectric layer 35 between the trenches 23; then, performing a third etching process using the third mask to etch the exposed second dielectric layer 35 to form the first opening 36a exposing the surface of the second electrode 33a between the trenches 23; and then removing the third mask.

[0102] Referring to Figure 5f, a second opening 36b is formed in the second dielectric layer 35 and the insulating layer 22 to expose the metal pad 12. The specific steps include: first, forming a fourth mask to cover the surface of the second dielectric layer 35, and the fourth mask has a plurality of openings to expose at least a portion of the second dielectric layer 35 above the metal pad 12; using the fourth mask to perform a fourth etching process to sequentially etch the second dielectric layer 35, the insulating layer 22 and the dielectric barrier layer 21 to form a second opening 36b to expose the surface of the metal pad 12; and then removing the fourth mask.

[0103] In addition, this embodiment does not limit the order of forming the first opening 36a and the second opening 36b. That is, it is also feasible to first form the second opening 36b in the second dielectric layer 35 and the insulating layer 22 to expose the metal pad 12, and then form the first opening 36a in the second dielectric layer 35 to expose the second electrode 33a.

[0104] Next, referring to FIG. 5 g , step S06 is performed to form a second metal line 37 to electrically connect the second electrode 33 a and the metal pad 12 using the first opening 36 a and the second opening 36 b .

[0105] The specific steps may include: first, forming a metal material layer to cover the surface of the second dielectric layer 35, the inner wall of the first opening 36a and the second opening 36b. The metal material layer can be a metal material suitable for electrical connection with the metal pad 12, such as aluminum. In this embodiment, the metal material layer includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer and a titanium nitride layer formed in sequence in a conformal manner, and can all be formed using a sputtering process. Then, a fifth mask is formed to cover the first opening 36a, the second opening 36b and the metal material layer on the second dielectric layer 35 therebetween. The fifth mask is then used to perform a fifth etching process to remove the exposed metal material layer, and the remaining metal material layer is used as the second metal wire 37. The second metal wire 37 extends from the device area AA to the peripheral area BB and electrically connects the second electrode 33a of the trench capacitor to the metal pad 12.

[0106] Thus, a trench capacitor consisting of the first electrode 31a, the first dielectric layer 32a, and the second electrode 33a is formed on the trench 23 and the insulating layer 22 around the trench 23. The first metal line 11 is exposed at the bottom of the trench 23 to complete the lead-out and electrical connection between the first electrode 31a of the trench capacitor and the first metal line 11. The metal pad 12 is exposed by the second opening 36b provided on the metal pad 12, and the second electrode 33a is exposed by the first opening 36a provided above the second electrode 33a between the trenches 23 to lead out and electrically connect the metal pad 12 and the second electrode 33a. As a result, this embodiment only requires five photolithography processes to complete the formation, lead-out, and electrical connection of the trench capacitor to the first metal line 11 and the metal pad 12, thereby having a simple and efficient process flow and helping to reduce costs.

[0107] 5g, after forming the second metal line 37, a third dielectric layer 38 may be formed to cover the second metal line 37 and the second dielectric layer 35 to serve as a protective layer. The third dielectric layer 38 may be made of any suitable passivation layer material, such as silicon oxide and / or silicon nitride.

[0108] Embodiment 4 of the present application also provides a method for manufacturing a MIM capacitor.

[0109] FIG1 is a flow chart of a method for manufacturing a MIM capacitor provided in the fourth embodiment.

[0110] As shown in FIG1 , the method for manufacturing a MIM capacitor provided in this embodiment includes:

[0111] S01: Providing a substrate, comprising a device area and a peripheral area, wherein the device area has a first metal line, and the peripheral area has a metal pad arranged in the same layer as the first metal line, wherein the first metal line and the metal pad are covered with an insulating layer;

[0112] S02: forming a trench in the insulating layer on the first metal line to expose the first metal line;

[0113] S03: forming a first electrode material layer, a first dielectric material layer, and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the trench, and performing photolithography and etching to sequentially form a second electrode, a first dielectric layer, and an insulating layer covering the trench and its surroundings by the first electrode to form a MIM capacitor, wherein the first electrode is electrically connected to the first metal wire via the trench;

[0114] S04: forming a second dielectric layer to cover the surfaces of the insulating layer and the second electrode, and filling the trench;

[0115] S05: forming a first opening in the second dielectric layer to expose the second electrode, and forming a second opening in the second dielectric layer and the insulating layer to expose the metal pad;

[0116] S06: forming a second metal line to electrically connect the second electrode and the metal pad using the first opening and the second opening.

[0117] The manufacturing method of the MIM capacitor provided in the fourth embodiment is similar to the method provided in the third embodiment above, and the difference lies mainly in the step of forming the second mask in step S03 of the fourth embodiment. Next, the manufacturing method of the MIM capacitor will be described in detail with reference to Figures 6a to 6c.

[0118] In step S03 , referring to FIG. 6 a , first, a first electrode material layer 31 , a first dielectric material layer 32 and a second electrode material layer 33 are sequentially formed to conformally cover the surface of the substrate 10 , ie, the surface of the insulating layer 22 and the inner wall of the trench 23 .

[0119] Referring to Figure 6b, a second mask is formed to cover the trench 23 and the second electrode material layer 33 on the surrounding insulating layer 22. Using the second mask, a second etching process is performed to sequentially etch the second electrode material layer 33, the first dielectric material layer 32, and the first electrode material layer 31 to form a second electrode 33a, a first dielectric layer 32a, and a first electrode 31a. The second mask is then removed. Unlike the first embodiment, which uses a single second mask to form a trench capacitor, in this embodiment, at least two second masks are used to form a trench capacitor. Adjacent second masks have gaps 34 on the second electrode material layer 33 between the trenches 23, so that after the second etching process, at least two trench capacitors are formed, connected in parallel between the first metal line 11 and the metal pad 12, thereby improving the overall performance of the capacitor. That is, in this embodiment, at least two first electrodes 31a, at least two first dielectric layers 32a, and at least two second electrodes 33a are formed above the first metal line 11 to form at least two trench capacitors. The first electrode 31a of each trench capacitor is connected via the first metal line 11. It should be understood that, compared with a single trench capacitor with the same capacitance, using at least two trench capacitors in parallel can have performance advantages such as lower parasitic inductance, and this technical effect is very easy to achieve in the above manufacturing process.

[0120] 6c, step S06 is performed to form a second metal line 37 that utilizes the first opening 36a and the second opening 36b to electrically connect the second electrode 33a and the metal pad 12. After forming at least two trench capacitors above the first metal line 11, at least one first opening 36a can be formed above the second electrode 33a of each trench capacitor.

[0121] An embodiment of the present application also provides a MIM capacitor.

[0122] FIG5g and FIG6c are schematic structural diagrams of a MIM capacitor provided in the above embodiment.

[0123] The MIM capacitor provided in this embodiment can be formed using the method provided in the above embodiment. Specifically, as shown in Figure 5g or Figure 6c, the MIM capacitor may include a substrate 10, a first metal wire 11, a metal pad 12, an insulating layer 22, a MIM capacitor, a second dielectric layer 35 and a second metal wire 37. The substrate 10 has a device area AA and a peripheral area BB, the device area AA is used to form a semiconductor device, and the peripheral area BB is used to form a peripheral circuit. The first metal wire 11 is arranged in the device area AA of the substrate 10, and the metal pad 12 is arranged in the same layer as the metal wire in the peripheral area BB of the substrate 10. The insulating layer 22 covers the surface of the substrate 10, that is, covers the first metal wire 11 and the metal pad 12, and a number of grooves 23 are formed in the insulating layer 22 on the first metal wire 11 to expose the first metal wire 11. The MIM capacitor is formed on the trench 23 and the insulating layer 22 surrounding it. It includes a first electrode 31a, a first dielectric layer 32a, and a second electrode 33a, which conformally cover the trench 23 and the surrounding insulating layer 22. The first electrode 31a is electrically connected to the first metal line 11 via the trench 23. A second dielectric layer 35 covers the surfaces of the insulating layer 22 and the second electrode 33a and fills the trench 23. A first opening 36a is defined in the second dielectric layer 35 between the trenches 23, penetrating the second dielectric layer 35 to expose the second electrode 33a of the trench capacitor. A second opening 36b is defined in the second dielectric layer 35 and the insulating layer 22 above the metal pad 12, penetrating the second dielectric layer 35 and the insulating layer 22 to expose the metal pad 12. A second metal line 37 covers the surface of the second dielectric layer 35, the inner walls of the first opening 36a, and the second opening 36b, electrically connecting the second electrode 33a to the metal pad 12.

[0124] In summary, the present invention exposes the first metal wire in a trench in the insulating layer on the first metal wire, forms a trench capacitor consisting of a first electrode, a first dielectric layer and a second electrode on the trench and the insulating layer around the trench, utilizes the bottom of the trench to expose the first metal wire to complete the extraction and electrical connection of the first electrode of the trench capacitor and the first metal wire, and utilizes the second opening provided on the metal pad to expose the metal pad and the first opening provided above the second electrode between the trenches to expose the second electrode to extract and electrically connect the metal pad and the second electrode, so that this embodiment only requires five photolithography processes to complete the formation, extraction and electrical connection of the MIM trench capacitor with the first metal wire and the metal pad, thereby having a simple and efficient process flow and helping to reduce costs. Compared with the related art that uses metal materials to fill the gaps in the trench capacitor for extraction, the present invention uses a second dielectric layer to fill the gaps in the trench, which not only helps to save electrode materials but also helps to reduce the corresponding process difficulty.

[0125] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A method for manufacturing a MIM capacitor, characterized in that: include: Providing a substrate, comprising a device area and a peripheral area, wherein the device area has a first metal line, the peripheral area has a metal pad arranged in the same layer as the first metal line, and an insulating layer covers the first metal line and the metal pad; forming a trench in the insulating layer, the trench exposing the first metal line; Conformally forming a first electrode and a first dielectric layer on the trench and the insulating layer around it, wherein the first electrode is electrically connected to the first metal wire via the trench; forming a second electrode covering the first dielectric layer, wherein the second electrode is electrically connected to the metal pad; A second dielectric layer is formed to cover the surfaces of the insulating layer and the second electrode and fill the trench.

2. The method for manufacturing a MIM capacitor according to claim 1, characterized in that: A dielectric barrier layer is also provided between the first metal line, the metal pad and the insulating layer.

3. The method for manufacturing a MIM capacitor according to claim 2, characterized in that: The step of forming a second electrode to cover the first dielectric layer, wherein the second electrode is electrically connected to the metal pad, further comprises: forming a through hole in the insulating layer, the through hole exposing the metal pad; Extending the second electrode to cover the inner wall of the through hole to be electrically connected to the metal pad; The through hole is filled with the second dielectric layer.

4. The method for manufacturing a MIM capacitor according to claim 3, characterized in that: The steps of forming the groove and the through hole include: Forming a first mask to cover the surface of the insulating layer, wherein the first mask has a first opening and a second opening; Performing a first etching process on the insulating layer and the dielectric barrier layer, forming the trench using the first opening, and simultaneously forming the through hole using the second opening, wherein the through hole is located above the metal pad, and at least one of the trenches is located above the first metal line; The first mask is removed.

5. The method for manufacturing a MIM capacitor according to claim 4, characterized in that: The step of forming the first electrode comprises: forming a first electrode material layer to cover the surface of the insulating layer, the groove and the inner wall of the through hole; forming a second mask to cover the trench, the through hole and the first electrode material layer on the surrounding insulating layer of the trench and the through hole; Using the second mask, performing a second etching process on the exposed first electrode material layer, using the first electrode material layer on the trench and the insulating layer around it as the first electrode, and retaining the first electrode material layer covering the inner wall of the through hole and the insulating layer around it; The second mask is removed.

6. The method for manufacturing a MIM capacitor according to claim 5, characterized in that: The step of forming the first dielectric layer comprises: forming a first dielectric material layer to cover the insulating layer, the first electrode and the through hole; forming a third mask to cover the first electrode and the first dielectric material layer on the insulating layer around the first electrode; Using the third mask, performing a third etching process on the exposed first dielectric material layer, using the first dielectric material layer on the first electrode and the surrounding insulating layer as the first dielectric layer, and exposing at least the first electrode material layer on the bottom wall of the through hole; The third mask is removed.

7. The method for manufacturing a MIM capacitor according to claim 4, characterized in that: The step of forming the first electrode comprises: forming a first electrode material layer to cover the surface of the insulating layer, the groove and the inner wall of the through hole; forming a second mask to cover the first electrode material layer on the trench and the surrounding insulating layer; Using the second mask, performing a second etching process on the exposed first electrode material layer, using the first electrode material layer on the insulating layer around the trench and surrounding it as the first electrode, and at least partially exposing the metal pad on the bottom wall of the through hole; The second mask is removed.

8. The method for manufacturing a MIM capacitor according to claim 7, characterized in that: The step of forming the first dielectric layer comprises: forming a first dielectric material layer to cover the insulating layer, the first electrode and the through hole; forming a third mask to cover the first electrode and the first dielectric material layer on the insulating layer around the first electrode; Using the third mask, performing a third etching process on the exposed first dielectric material layer, using the first dielectric material layer on the first electrode and the surrounding insulating layer as the first dielectric layer, and at least partially exposing the metal pad on the bottom wall of the through hole; The third mask is removed.

9. The method for manufacturing a MIM capacitor according to claim 5, characterized in that: The step of forming the second electrode comprises: forming a second electrode material layer to cover the insulating layer, the first dielectric layer and the through hole; forming a fourth mask to cover the first dielectric layer, the through hole, and the second electrode material layer on the insulating layer from the trench to the through hole; Using the fourth mask, performing a fourth etching process on the exposed second electrode material layer, so that the first dielectric layer, the inner wall of the through hole and the second electrode material layer on the insulating layer from the trench to the through hole serve as the second electrode; The fourth mask is removed.

10. The method for manufacturing a MIM capacitor according to claim 9, characterized in that: The materials of the first electrode material layer and the second electrode material layer include one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

11. The method according to claim 2, characterized in that After the step of forming a second dielectric layer to cover the surface of the insulating layer and the second electrode and filling the groove, the method further includes: Forming a first opening in the second dielectric layer to expose the second electrode, and forming a second opening in the second dielectric layer and the insulating layer to expose the metal pad; A second metal line is formed to electrically connect the second electrode and the metal pad using the first opening and the second opening.

12. The method for manufacturing a MIM capacitor according to claim 11, characterized in that: The steps of forming the groove include: forming a first mask to cover the surface of the insulating layer, wherein the first mask has a plurality of openings; Performing a first etching process on the insulating layer and the dielectric barrier layer to form the trenches using the openings, wherein at least one of the trenches exposes the first metal line; The first mask is removed.

13. The method for manufacturing a MIM capacitor according to claim 11, characterized in that: The steps of forming the second electrode, the first dielectric layer and the first electrode include: forming a first electrode material layer, a first dielectric material layer and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the groove; forming a second mask to cover the trench and the second electrode material layer on the insulating layer around the trench; Using the second mask, performing a second etching process to sequentially etch the exposed second electrode material layer, the first dielectric material layer, and the first electrode material layer to form the second electrode, the first dielectric layer, and the first electrode; The second mask is removed.

14. The method for manufacturing a MIM capacitor according to claim 11, characterized in that: The steps of forming the second electrode, the first dielectric layer and the first electrode include: forming a first electrode material layer, a first dielectric material layer and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the groove; forming a second mask to cover the trench and the second electrode material layer on the surrounding insulating layer, and exposing a portion of the second electrode material layer between the trenches; Using the second mask, performing a second etching process to sequentially etch the exposed second electrode material layer, the first dielectric material layer, and the first electrode material layer to form a plurality of second electrodes, a plurality of first dielectric layers, and a plurality of first electrodes to form a plurality of trench capacitors connected in parallel to the first metal line; The second mask is removed.

15. The method for manufacturing a MIM capacitor according to claim 11, characterized in that: The step of forming the first opening comprises: forming a third mask to cover the surface of the second dielectric layer and expose at least a portion of the second dielectric layer between the grooves; Performing a third etching process using the third mask to etch the exposed second dielectric layer to expose a surface of the second electrode; The third mask is removed.

16. The method for manufacturing a MIM capacitor according to claim 11 or 15, characterized in that: The step of forming the second opening comprises: forming a fourth mask to cover the surface of the second dielectric layer and expose at least a portion of the second dielectric layer above the metal pad; Performing a fourth etching process using the fourth mask to sequentially etch the exposed second dielectric layer and the insulating layer to expose the surface of the metal pad; The fourth mask is removed.

17. The method for manufacturing a MIM capacitor according to claim 11, characterized in that: The step of forming the second metal line includes: forming a metal material layer to cover the surface of the second dielectric layer, the first opening and the inner wall of the second opening; forming a fifth mask to cover the first opening, the second opening and the metal material layer on the second dielectric layer therebetween; A fifth etching process is performed using the fifth mask to remove the exposed metal material layer, and the remaining metal material layer serves as the second metal line.

18. The method for manufacturing a MIM capacitor according to claim 11, characterized in that: After forming the second metal line, a third dielectric layer is formed to cover the second metal line and the second dielectric layer.

19. A MIM capacitor, characterized in that: include: A substrate having a device region and a peripheral region; A first metal line and a metal pad, wherein the first metal line is disposed in the device region, and the metal pad and the first metal line are arranged in the peripheral region in the same layer; an insulating layer covering the first metal line and the metal pad, wherein a groove is formed in the insulating layer to expose the first metal line, and a through hole is formed to expose the metal pad; A capacitor, comprising a first electrode, a first dielectric layer and a second electrode, which sequentially conformally cover the groove and the surrounding insulating layer, wherein the first electrode is electrically connected to the first metal line by using the groove, and the second electrode extends from the groove to cover the inner wall of the through hole to be electrically connected to the metal pad; The second dielectric layer covers the surface of the insulating layer and the second electrode and fills the groove and the through hole. hole.

20. A MIM capacitor, characterized in that: include: A substrate having a device region and a peripheral region; A first metal line and a metal pad, wherein the first metal line is disposed in the device region, and the metal pad and the first metal line are arranged in the peripheral region in the same layer; an insulating layer, covering the first metal line and the metal pad, wherein a groove is formed in the insulating layer to expose the first metal line; The MIM capacitor comprises a first electrode, a first dielectric layer and a second electrode which sequentially conformally cover the groove and the surrounding insulating layer, wherein the first electrode is electrically connected to the first metal line via the groove; a second dielectric layer covering the surfaces of the insulating layer and the second electrode and filling the grooves, wherein the second dielectric layer between the grooves is provided with a first opening to expose the second electrode, and the second dielectric layer and the insulating layer on the metal pad are provided with a second opening to expose the metal pad; The second metal wire covers the surface of the second dielectric layer, the first opening and the inner wall of the second opening to electrically connect the second electrode and the metal pad.

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