2d TDC arrangement

Abstract

A sensor arrangement for high-resolution imaging using a shared single-photon avalanche diode (SPAD) to time-to-digital converter (TDC) interconnect, comprising: a) a two-dimensional array of SPADs arranged in rows and columns, wherein each SPAD is associated with a quench circuitry (QU) that generates a digital pulse for each SPAD event; b) a row interconnect and a column interconnect, wherein each QU of the SPAD array is connected to the row and column interconnects; c) a plurality of TDC channels, each associated with either a specific row or a specific column of the SPAD array, wherein the TDC channels are driven by a common clock generator and have N-stages, and wherein the TDC channels are configured to measure the time interval between the occurrence of a SPAD event and the clock signal; d) synchronization means to ensure synchronous operation of the TDC channels associated with the rows and columns of the SPAD array; e) a measurement means to capture the measurement results from the TDC channels associated with the rows and columns of the SPAD array; f) a comparison means to compare the measurement results from the row and column TDC channels to identify the source SPAD associated with a particular SPAD event; and g) a sorting means to allocate the identified SPAD event to the corresponding histogram of the source SPAD.

Description

[0001] 2D TDC arrangement

[0002] DESCRIPTION

[0003] TECHNICAL FIELD

[0004] The present invention relates to a sensor arrangement for high-resolution imaging using a shared single-photon avalanche diode ( SPAD) to time-to-digital converter ( TDC ) interconnect , a method for detecting an event in a high- resolution imaging system using a shared single-photon avalanche diode ( SPAD) to time-to-digital converter ( TDC ) interconnect , a use of a system for event detection in a high-resolution imaging device , the system comprising such sensor arrangement .

[0005] BACKGROUND

[0006] Time-of-Flight ( ToF) systems are commonly used in the art . Usually, prior art TOF systems use a dedicated TDC channel for each SPAD or a group of SPADs (macropixel ) . Large SPAD arrays therefore require multiple TDCs or multi-channel TDCs which increases area demands of the system signi ficantly . Alternatively, TDC channels are shared among multiple macropixies which requires time multiplexing within one frame , and which causes a drop in framerate as a result .

[0007] Accordingly, it is common to use a dedicated TDC channel for each pixel or SPAD in a ToF system to achieve maximum resolution . However, due to the signi ficant si ze of TDCs , multiple SPADs are typically assigned to a single TDC channel in practice . Usually, each SPAD is equipped with a quench circuitry ( QU) that generates a digital pulse for each SPAD event .

[0008] However, when multiple SPADs are combined into a pixel , for example , using a compression tree or "OR tree" , the information about which SPAD within the array actually fired is lost . However, identifying the active SPAD is crucial for achieving higher resolution or measurement accuracy .

[0009] Conventional approaches to increase resolution utili ze time multiplexing techniques where the SPADs are sequentially activated . However, this leads to issues such as rolling shutter ef fects and a fixed integration time per SPAD, resulting in limitations on temporal resolution and achievable light intensity .

[0010] SUMMARY

[0011] The present invention aims to overcome the information losses of conventional systems and restore the identi fication of the active SPAD without the use of time multiplexing . This allows for higher resolution and flexibility in event capture within a ToF system .

[0012] The document "An all-in-one 64- zone SPAD-based Direct-Timeof-Flight Ranging Sensor with Embedded I llumination" of FMartin et al . ( 2021 IEEE Sensors | DOI : 10 . 1109 / SENSORS47087 . 2021 . 9639840 ) describes a SPAD-based, direct time of flight , multi- zone parallel ranging device using STMicroelectronics 40nm CMOS SPAD technology .

[0013] The document "A 32 x 128 SPAD-257 TDC Receiver IC for Pulsed TOF Solid-State 3-D Imaging" of Jahromi et al . ( 1960 IEEE JOURNAL OF SOLID-STATE CIRCUITS , VOL . 55 , NO . 7 , JULY 2020 ) discloses a single-chip receiver for pulsed laser direct time-of- f light 3-D imaging applications reali zed in a 0 . 35-pm HV CMOS technology .

[0014] However, the prior art still reveals a lack of high- resolution imaging capabilities , flexibility in array configuration, enhanced synchroni zation and timing accuracy, improved source SPAD identi fication, and adaptability to various aspect ratios .

[0015] Thus , one obj ective of the present invention is to provide an ToF sensor arrangement with a more precise and ef ficient imaging performance , particularly making it suitable for advanced imaging applications and systems . It is a further obj ect of the present invention to provide an area ef ficient implementation of high resolution SPAD arrays with global shutter like data processing and particularly without time multiplexing . It is a still further obj ect of the present invention to provide a method and arrangement to overcome the issue of information loss in the use of shared Single-Photon Avalanche Diode ( SPAD) to Time-to-Digital Converter ( TDC ) interconnects and to increase the resolution of the system without the need for time multiplexing .

[0016] With respect to the sensor arrangement according to the present invention, the obj ectives are met by a sensor arrangement for high-resolution imaging using a shared single-photon avalanche diode ( SPAD) to time-to-digital converter ( TDC ) interconnect according to the present invention . Such sensor arrangement comprises : a) a two-dimensional array of SPADs arranged in rows and columns , wherein each SPAD is associated with a quench circuitry ( QU) that generates a digital pulse for each SPAD event ; b ) a row interconnect and a column interconnect , wherein each QU of the SPAD array is connected to the row and column interconnects ; c ) a plurality of TDC channels , each associated with either a speci fic row or a speci fic column of the SPAD array, wherein the TDC channels are driven by a common clock generator and have N-stages , and wherein the TDC channels are configured to measure the time interval between the occurrence of a SPAD event and the clock signal ; d) synchroni zation means to ensure synchronous operation of the TDC channels associated with the rows and columns of the SPAD array; e ) a measurement means to capture the measurement results from the TDC channels associated with the rows and columns of the SPAD array; f ) a comparison means to compare the measurement results from the row and column TDC channels to identi fy the source SPAD associated with a particular SPAD event ; and g) a sorting means to allocate the identi fied SPAD event to the corresponding histogram of the source SPAD .

[0017] The present invention thus provides a shared interconnect of multiple SPADs to TDC channels in the form of a two- dimensional implementation of multi event TDC channels , i . e . one for each row and column . Such two-dimensional implementation advantageously allows the identi fication and location of the individual SPAD that was generating the event . Therefor, each pulse can be assigned to a dedicated SPAD . In other words , implementing TDC channels per row and column in accordance with the present invention, allows for the identi fication of the source of the SPAD event . As a result , single SPAD resolution operation o f all SPADs in parallel - within a frame - is possible in a shared interconnect and TDC environment .

[0018] The present inventors thereby surprisingly found that such sensor arrangement of the present invention advantageously provides a structured setup for capturing high-resolution images using SPADs and TDCs and thus being able not only to identi fy the source of the SPAD event , but also to allow data collection with single SPAD resolution without timemultiplexing by sharing the SPAD to TDC interconnect and TDC channels .

[0019] In a advantageous embodiment of the sensor arrangement according to the present invention, the SPAD array comprises a plurality of SPADs arranged in an MxN configuration, where M and N are positive integers greater than 1 .

[0020] This advantageously allows flexibility to configure the SPAD array with di f ferent dimensions (M rows and N columns ) , allowing for scalability and adaptability to various imaging requirements .

[0021] In a further advantageous embodiment of the sensor arrangement according to the present invention, the quench circuitry ( QU) comprises a pulse generation circuit that generates a digital pulse of a predetermined duration in response to a SPAD event .

[0022] This advantageously allows that the quench circuitry generates a digital pulse of a predetermined duration in response to a SPAD event , enabling accurate detection and measurement of photon events .

[0023] In a further advantageous embodiment of the sensor arrangement according to the present invention, the NMOS transistors connected between the QU and the row and column interconnects operate as switches to selectively connect the QU to the interconnects .

[0024] This advantageously allows that the transistors act as switches , allowing selective connection of the quench circuitry to the interconnects , which enables ef ficient routing of signals within the sensor arrangement . In a further advantageous embodiment of the sensor arrangement according to the present invention, the pull-up resistors connected to the row and column interconnects facilitate voltage level restoration of the interconnects .

[0025] This advantageously allows that the pull-up resistors ensure proper voltage levels in the interconnects , enhancing signal integrity and minimi zing signal degradation during transmission .

[0026] In a further advantageous embodiment of the sensor arrangement according to the present invention, the TDC channels are implemented using a delay line or a ring oscillator with N stages , where N is a positive integer greater than 1 .

[0027] This advantageously allows that the TDC channels employ a delay line or a ring oscillator to measure the time interval between a SPAD event and a clock signal accurately . This allows for precise time measurements , crucial for high- resolution imaging applications .

[0028] In a further advantageous embodiment of the sensor arrangement according to the present invention, further comprises an of fset adj ustment means for compensating for any timing of fset between the TDC channels associated with the rows and columns of the SPAD array .

[0029] This advantageously allows that the of fset adj ustment means compensates for any timing of fset between the TDC channels associated with the rows and columns of the SPAD array, ensuring accurate synchroni zation and reducing timing errors .

[0030] In a further advantageous embodiment of the sensor arrangement according to the present invention, the synchroni zation means comprises a global synchroni zation signal that ensures simultaneous operation of the TDC channels associated with the rows and columns of the SPAD array . This advantageously allows that the global synchroni zation signal enables simultaneous operation of the TDC channels associated with the rows and columns of the SPAD array . This synchronous operation ensures coordinated measurements across the entire array, avoiding timing discrepancies .

[0031] In a further advantageous embodiment of the sensor arrangement according to the present invention, the measurement means comprises analog-to-digital converters (ADCs ) that convert the measurement results from the TDC channels into digital values .

[0032] This advantageously allows that the ADCs convert the measurement results from the TDC channels into digital values , allowing for easy processing, analysis , and storage of the captured data .

[0033] In a further advantageous embodiment of the sensor arrangement according to the present invention, the comparison means comprises a comparator circuit that compares the measurement results from the row and column TDC channels to determine the relative timing of the SPAD event .

[0034] This advantageously allows that the comparator circuit compares the measurement results from the row and column TDC channels , determining the relative timing of the SPAD event accurately . This comparison aids in identi fying the source SPAD associated with a particular event .

[0035] In a further advantageous embodiment of the sensor arrangement according to the present invention, the sorting means comprises a histogram memory that stores the occurrence counts of SPAD events associated with each SPAD in the SPAD array .

[0036] This advantageously allows that the sorting means comprises a histogram memory . The advantage of this claim is that the histogram memory stores the occurrence counts of SPAD events associated with each SPAD in the array . This facilitates statistical analysis , visuali zation, and ef ficient storage of event data, which is valuable for various imaging applications .

[0037] In a further advantageous embodiment of the sensor arrangement according to the present invention, the transistor that connects each QU of the SPAD array to the row and column interconnects is a respective NMOS transistor and / or wherein the resistor that connects each interconnect is a pull-up resistor .

[0038] This advantageously allows that the speci fic choice of NMOS transistors and pull-up resistors provides optimal circuit characteristics and performance for the sensor arrangement .

[0039] In a further advantageous embodiment of the sensor arrangement according to the present invention, the SPAD array comprises a plurality of SPADs arranged in an MxN configuration, wherein the MxN configuration is selected from the group comprising 3x4 , 4x3 , 16X9 or 9x16 .

[0040] This advantageously allows that the sensor arrangement can be designed with dimensions that conform to commonly used aspect ratios , such as those found in standard display formats . This facilitates compatibility and integration with existing imaging systems .

[0041] The above-described problems are also advantageously solved by a method for detecting an event in a high-resolution imaging system using a shared single-photon avalanche diode ( SPAD) to time-to-digital converter ( TDC ) interconnect according to the present invention .

[0042] The method comprises at least the following steps : a step a ) of providing a two-dimensional array of SPADs arranged in rows and columns , each SPAD associated with a quench circuitry ( QU) that generates a digital pulse for each SPAD event , preferably a sensor arrangement according to any one of claims 1 to 13 ; a step b ) of connecting each QU of the SPAD array to a row and column interconnect wire via a transistor and connecting the interconnect wire to a resistor ; a step c ) of associating each row and column of the SPAD array with a dedicated TDC channel , the TDC channels driven by a common clock generator with N-stages ; a step d) of synchroni zing the operation of the TDC channels associated with the rows and columns of the SPAD array; a step e ) of receiving incident photons by the SPADs , generating SPAD events , and producing digital pulses via the associated QU for each SPAD event ; a step f ) of propagating the digital pulses through the row and column interconnects to the respective TDC channels associated with the row and column of the SPAD generating the event ; a step g) of measuring the time interval between the occurrence of a SPAD event and the clock signal in each of the TDC channels ; a step h) of capturing the measurement results from the TDC channels associated with the rows and columns of the SPAD array; a step i ) of comparing the measurement results obtained from the row and column TDC channels to identi fy the source SPAD associated with the particular SPAD event ; a step j ) of sorting the identi fied SPAD event into the corresponding histogram of the source SPAD . It shall be noted, that the steps given above do not necessarily have to be carried out in the given order . The provided steps may be carried out in any other suitable order . However, the order as given above may apply for particular variants of the method .

[0043] The advantage of such method, particularly is that the method provides a systematic approach for event detection in a high- resolution imaging system . Thereby, the method ensures accurate detection of events in a high-resolution imaging system . By utili zing the shared SPAD to TDC interconnect , it captures precise timing information for each SPAD event , allowing for accurate event detection . This level of accuracy is crucial in high-resolution imaging applications where precise event identi fication is necessary . Furthermore , ef ficient data capture and processing i s facilitated in that he method according to the invention captures measurement results from the TDC channels associated with the rows and columns of the SPAD array . These measurement results can be ef ficiently processed and analyzed for further use . By converting the measurement results into digital values using analog-to-digital converters (ADCs ) , the method enables easy manipulation, storage , and transmission of the captured data . Still further, a real-time event sorting is advantageously achieved . The method of the invention includes a sorting means that allocates the identi fied SPAD event to the corresponding histogram of the source SPAD . This allows for real-time event sorting and organi zation, facilitating further analysis and visuali zation of the captured data . Real-time event sorting enables immediate feedback and response in applications that require real-time processing or monitoring . Furthermore , compensation for timing of fset can be advantageously achieved with the inventive method, that incorporates an of fset adj ustment means to compensate for any timing of fset between the TDC channels associated with the rows and columns of the SPAD array . This compensation ensures precise synchroni zation and alignment of the timing measurements , reducing timing errors and improving the overall accuracy of the imaging system . Still further, the method of the present invention utili zes a synchroni zation means , such as a global synchroni zation signal , to ensure simultaneous operation of the TDC channels associated with the rows and columns of the SPAD array . Simultaneous operation eliminates timing discrepancies and enables coordinated measurements across the entire array, resulting in more accurate and reliable imaging outcomes .

[0044] Furthermore , the inventive method allows for high-speed imaging capabilities by utili zing a common clock generator and TDC channels with multiple stages . This design enables fast and ef ficient measurement of time intervals between SPAD events and the clock signal . The high-speed performance is particularly beneficial in applications that require realtime imaging or rapid data acquisition .

[0045] In summary, the method according to the invention provides advantages such as accurate event detection, ef ficient data capture and processing, real-time event sorting, compensation for timing of fset , simultaneous operation, and high-speed performance . These advantages contribute to the ef fectiveness , precision, and reliability of the high- resolution imaging system employing the method .

[0046] The above-described problems are also advantageously solved by a use of a system for event detection in a high-resolution imaging device according to the present invention . Thereby, the system comprises a sensor arrangement according to the present invention .

[0047] A skilled person will immediately acknowledge the various uses of the described sensor arrangement and / or method according to the present invention . The sensor arrangement and method according to the present invention may be applied to various uses in high-resolution imaging and related applications . Without being bound thereto , some possible uses include the use of the present invention in medical imaging applications , such as high-resolution microscopy, fluorescence imaging, or tissue imaging, there it enables precise and accurate imaging of biological samples , facilitating diagnostic processes , research, and medical interventions ; the use in in industrial inspection scenarios , such as quality control , defect detection, and dimensional measurement , there it may advantageously allow for high- resolution imaging of manufactured products , enabling detailed analysis , identi fication of defects , and ensuring product quality; the use in in security and surveillance systems for high-resolution imaging and event detection, there it may advantageously enable accurate monitoring, tracking, and identi fication of obj ects or individuals , making it valuable in applications like video surveillance , facial recognition, or perimeter security; the use in robotics and autonomous systems that require precise perception and obj ect recognition capabilities , there it may advantageously enable high-resolution imaging for obj ect detection, locali zation, and mapping, aiding in autonomous navigation, obj ect manipulation, or intelligent robotic systems ; the use in virtual and augmented reality applications by providing high-resolution imaging for realistic visuali zation and immersive experiences , there it may advantageously enable the capture of detailed 3D scenes , obj ect reconstruction, and tracking, enhancing the quality and accuracy of virtual and augmented reality environments ; the use in various scienti fic research fields , such as astronomy, physics , or biology, there it may advantageously enable detailed imaging and analysis of celestial obj ects , particle detection, or cellular imaging, providing valuable data for scienti fic discoveries and advancements ; the use in remote sensing and Earth observation applications , where enables high-resolution imaging of the Earth ' s surface , vegetation monitoring, environmental assessment , or disaster management , providing critical information for agriculture , forestry, urban planning, and natural resource management ; the use in autonomous vehicles for advanced perception capabilities , there it may advantageously allow for high- resolution imaging for obj ect detection, obstacle avoidance , and environment mapping, enhancing the safety and performance of autonomous driving systems .

[0048] It will be immediately acknowledged by a person skilled in the art that a feature , embodiment , ef fect , or advantage described herein in connection with the inventive sensor arrangement , may also be a feature , embodiment , ef fect or advantage of the inventive method or inventive use , respectively, and vice versa .

[0049] In the context of the present invention the term "SPAD" , as used herein, preferably refers to a Single-Photon Avalanche Diode . A Single-Photon Avalanche Diode is a type of solid- state photodetector that operates in a highly sensitive mode , allowing it to detect and measure single photons of light . It is designed to detect very low levels of light and convert them into electrical signals for further processing . Thereby, a SPAD preferably consists of a p-n j unction, similar to a standard diode , but it may include additional features that enable it to operate in the avalanche breakdown region . When a photon of suf ficient energy strikes the SPAD, it generates an electron-hole pair, initiating an avalanche multiplication process . This process results in a rapid and signi ficant increase in the number of charge carriers , producing a measurable electrical current pulse .

[0050] In the context of the patent application, the term " SPAD" more preferably refers to the speci fic type of photodetector employed in the sensor arrangement and method according to the present invention . It signi fies the use of single-photon avalanche diodes within the system for the purpose of photon detection, timing measurements , and event identi fication .

[0051] The term " time-to-digital converter, or TDC" as used herein, preferably refers to a device that converts time intervals into digital representations . Such TDCs are known to the skilled person as commonly used for measuring time di f ferences or converting continuous time signals into discrete digital values . The term " SPAD array, " as used herein, preferably refers to an array or matrix of Single-Photon Avalanche Diodes ( SPADs ) , which are photodetectors capable of detecting and measuring single photons of light , arranged in a two-dimensional configuration .

[0052] The term "Quench circuitry ( QU) , " as used herein, preferably refers to the circuitry associated with each Single-Photon Avalanche Diode ( SPAD) in the sensor arrangement , which generates a digital pulse for each SPAD event and aids in resetting the SPAD for subsequent photon detection .

[0053] The terms "row interconnect" and "column interconnect , " as used herein, preferably refer to the wiring or conductive pathways that connect the components associated with the rows and columns , respectively, of the SPAD array, facilitating the trans fer of signals and data between the SPADs and other circuitry in the sensor arrangement .

[0054] These and other features , embodiments , obj ectives , and advantages of the invention will become apparent from the subsequent description .

[0055] BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Exemplary embodiments of the invention are discussed below with reference to the accompanying drawings .

[0057] FIG . 1 illustrates schematically a sensor arrangement according to the prior art , whrein a typical SPAD / Quench readout architecture is used, in an example of 16 SPADs per TDC channel ;

[0058] FIG . 2 illustrates schematically a sensor arrangement according to a first embodiment of the present invention, wherein a TDC column and row arrangement for a 2x2 SPAD array is depicted; FIG. 3 illustrates schematically a sensor arrangement according to the first embodiment of the present invention, in the event of example case 1;

[0059] FIG. 4 illustrates schematically a sensor arrangement according to a second embodiment of the present invention, in the event of a single conflict on separated rows and / or columns, respectively.

[0060] DETAILED DESCRIPTION

[0061] In FIG. 1 a sensor arrangement 1 in accordance with the prior art is shown. Each SPAD is associated with a quench circuitry (QU) 3. Here a 4x4 SPAD arrangement is shown. Since layout area restrictions usually do not allow to implement for each SPAD a dedicated TDC multiple SPADs, here 16, are typically merged by using a compression tree (logic OR) 5 and connected to a single TDC channel 2. As a result, a single TDC channel 2 is shared among multiple pixels. In order to operate the system in high resolution mode (single SPAD resolution) timemultiplexing is used which is similar to rolling shutter operation. In time-multiplexed operation, one after the other of the 16 SPADs is enabled - while all other 15 SPADs are disabled - and integration is done for a certain period of time. In order to capture a full frame each of the 16 SPADs has to be selected in a sequential way and the integration repeated. As a result, the frame drops by 1 / N with the number of SPADs, here 1 / 16, connected to a single TDC 2. This results in a huge reduction in performance and efficiency. In the present example of the prior art, only 1 / 16 (1 / N) SPAD is enabled while 16-1 (N-l) SPADs receive emitted light but do not detect it.

[0062] In FIG. 2 a sensor arrangement 1 according to the present invention is shown in a simple version, particularly for explanatory reasons. In the shown embodiment a two- dimensional TDC arrangement 1 (rows 71 and 72 and columns 81 and 82) is used to allow identification of the source of SPAD events in a shared SPAD to TDC interconnect. The principle is explained based on a 2x2 SPAD array, but the benefit becomes visible in larger SPAD arrays only.

[0063] The sensor arrangement 1 for high-resolution imaging using a shared single-photon avalanche diode (SPAD) to time-to- digital converter (TDC) interconnect, comprises a two- dimensional array of 2x2 SPADs 3 arranged in two rows, 71 and 72, and two columns, 81 and 82, wherein each SPAD is associated with a quench circuitry (QU) - depicted with a single reference numeral for the SPAD-QU 3 - that generates a digital pulse for each SPAD event. Thereby, a row interconnect and a column interconnect, wherein each QU of the SPAD array is connected to the row and column interconnects. A plurality of TDC channels 21, 22, 25 and 26 is provided, each associated with either a specific row (21 to 71; 22 to 72) or a specific column (25 to 81, 26 to 82) of the SPAD array 1, wherein the TDC channels 21, 22, 25, and 26 are driven by a common clock generator 4 and have N-stages, and wherein the TDC channels 21, 22, 25, and 26 are configured to measure the time interval between the occurrence of a SPAD event and the clock signal 6. Further provided are synchronization means (not depicted in detail in the Figure) to ensure synchronous operation of the TDC channels 21, 22, 25, and 26 associated with the rows 71 and 72 and columns 81 and 82 of the SPAD array 1. Thereby, a measurement means is provided (not depicted in detail in the Figure) to capture the measurement results from the TDC channels 21, 22, 25, and 26 associated with the rows 71 and 72 and columns 81 and 82 of the SPAD array 1. A comparison means (not depicted in detail in the Figure) is provided to compare the measurement results from the row and column TDC channels 21 and 22, and, 25 and 26, respectively to identify the source SPAD associated with a particular SPAD event. Furthermore, a sorting means (not depicted in detail in the Figure) is provided to allocate the identified SPAD event to the corresponding histogram of the source SPAD.

[0064] In FIG. 1, each SPAD is represented by a quench circuitry (QU) 3 which generates a digital pulse for each event of the SPAD. The output of each quench cell is connected to a row and column interconnect wire using an NMOS transistor. This interconnect wire is connected to a pull up resistor. The location of the SPAD can be identified by a column and row address like Al = row 71, column 81, Bl = row 71, column 82, A2 = row 72, column 81 and B2 = row 72, column 82.

[0065] For each row 71 and 72, respectively, and each column 81 and 82, respectively, a dedicated TDC channel (row 71 - TDC channel 21, row 72 - TDC channel 22, row 81 - TDC channel 25, row 82 - TDC channel 26) , which is driven from a common elk generator 4 (i.e. delayline or ring oscillator) with N- stages. For this approach a multi event / multi channel TDC is required. The TDC channels can advantageously be named according to their implementation (e.g., TDC channel A, B or 1,2) . The SPADs are generating randomly event based on incident photon rate. Each SPAD event will generate a pulse on the corresponding row and column interconnect line. As usual in SPAD to TDC interconnects, best possible balancing of SPAD to TDC interconnect is implemented.

[0066] In the present shown example, the SPAD array 1 comprises a plurality of SPADs 3 arranged in an MxN configuration, where M and N are positive integers greater than 1, here M is 2, and N is 2. Thereby, each of the quench circuitry (QU) 3 comprises a pulse generation circuit that generates a digital pulse of a predetermined duration in response to a SPAD event. The NMOS transistors connected between the QU 3 and the row and column interconnects operate as switches to selectively connect the QU 3 to the interconnects (not shown in the schematic drawing in detail) . Thereby, the pull-up resistors connected to the row and column interconnects facilitate voltage level restoration of the interconnects. The TDC channels 21, 22, 25 and 26 respectively, are implemented using a delay line or a ring oscillator with N stages, where N is a positive integer greater than 1. Her the sensor arrangement 1, further comprises an offset adjustment means for compensating for any timing offset between the TDC channels 21, 22, 25 and 26 associated with the rows 71 and 72 and columns 81 and 82 of the SPAD array 1. The synchronization means comprises a global synchronization signal that ensures simultaneous operation of the TDC channels 21, 22, 25 and 26, respectively, associated with the rows 71 and 72 and columns 81 and 82 of the SPAD array. The measurement means comprises analog-to-digital converters (ADCs) that convert the measurement results from the TDC channels 21, 22, 25 and 26 into digital values. The comparison means comprises a comparator circuit that compares the measurement results from the row (21, 22) and column (25, 26) TDC channels to determine the relative timing of the SPAD event. The sorting means comprises a histogram memory that stores the occurrence counts of SPAD events associated with each SPAD 3 in the SPAD array 1. The transistor that connects each QU 3 of the SPAD array 1 to the row and column interconnects is a respective NMOS transistor and / or wherein the resistor that connects each interconnect is a pull-up resistor. The number of columns and the number of rows can be realized in other than 2x2, and namely in an MxN ratio of 3x4, 4x3, 16x9 or 9x16.

[0067] With such an arrangement as shown in FIG. 1 a method according to the present invention for detecting an event in a high-resolution imaging system using a shared single-photon avalanche diode (SPAD) to time-to-digital converter (TDC) interconnect advantageously can be carried out. Such method comprising at least the following steps: a step a) of providing a two-dimensional array 1 of SPADs 3 arranged in rows 71, 72 and columns 81, 82, each SPAD associated with a quench circuitry (QU) 3 that generates a digital pulse for each SPAD event; a step b) of connecting each QU 3 of the SPAD array 1 to a row 71, 72 and column 81, 82 interconnect wire via a transistor and connecting the interconnect wire to a resistor; a step c) of associating each row 71, 72 and column 81, 82 of the SPAD array 1 with a dedicated TDC channel 21, 22, 25, 26, the TDC channels driven by a common clock generator 4 with N- stages ; a step d) of synchronizing the operation of the TDC channels

[0068] 21, 22, 25, 26, associated with the rows 71, 72 and columns 81, 82 of the SPAD array 1; a step e) of receiving incident photons by the SPADs 3, generating SPAD events, and producing digital pulses via the associated QU 3 for each SPAD event; a step f) of propagating the digital pulses through the row and column interconnects to the respective TDC channels 21,

[0069] 22, 25, 26, associated with the row 71, 72 and column 81, 82 of the SPAD generating the event; a step g) of measuring the time interval between the occurrence of a SPAD event and the clock signal in each of the TDC channels 21, 22, 25, 26; a step h) of capturing the measurement results from the TDC channels 21, 22, 25, 26, associated with the rows 71, 72 and columns 81, 82 of the SPAD array 1; a step i) of comparing the measurement results obtained from the row (21, 22) and column (25, 26) TDC channels to identify the source SPAD 3 associated with the particular SPAD event; a step j) of sorting the identified SPAD event into the corresponding histogram of the source SPAD 3.

[0070] In FIG. 3 a particular example is shown, where SPAD Al, i.e. in position row 71, column 81, is triggered (in this and other figs, a trigger event is depicted in the form of a lightning symbol) : In case a photon triggers said SPAD Al a pulse will propagate from SPAD / Quench 3 to TDC channel 21 and 25 on row and column interconnect. Therefore, TDC channel 25 and TDC channel 21 will capture the event. For simplicity reasons, a perfectly synchronous operation of all channels (column channels 25 and 26 and row channels 21 and 22) is assumed, however in reality is not even needed. Even in case of an offset between different TDC channels, the chronological order of event in row and column channels represents a certain SPAD event. Thereby, the lowest TDC count of row and column represents the first event. In case of perfect "in phase" operation of all TDC channels, the generated SPAD event will lead to a measurement result of "X" e.g. "5", at TDC channels 21 and 25. After readout of all TDC channels 21, 22 and 25, 26 and comparing the measurement result of row (21, 22) and column channels (25, 26) allows to identify the source of the event, in this case SPAD Al. The event can therefore be sorted into the histogram of SPAD Al.

[0071] In Example 2, it is assumed that SPAD Al (column 81, row 71) , Bl (column 82, row 71) and A2 (column 81, row 72) is triggering sequentially in the exemplary first embodiment as shown in Figs. 2 and 3:

[0072] Event signal from SPAD Al will propagate to TDC channels 25 and 21 and a TDC result "X" (e.g. 5) is captured in both channels. Afterwards SPAD Bl is triggering and generates a TDC results at TDC channels 26 and 71 "X" (e.g. 7) . Finally TDC channels 25 and 22 are triggered by SPAD A2 with "X" (e.g. 9) . After finishing the period following TDC contend is present .

[0073] During readout the common result in multiple TDCs allow identification of the source:

[0074] Event 1 at timestamp 5 from SPAD Al

[0075] Event 2 at timestamp 7 from SPAD Bl

[0076] Event 3 at timestamp 9 from SPAD A2 The principle can be scaled to higher resolution and MxN ratios, of course. While number of pixels increases squared (NA2) with resolution, the number of TDC channels required increase only by 2*N.

[0077] All embodiments of the present invention as described above in the claims and description and in relation to the Figures here, provide advantages in that the single SPAD pixel resolution is available without time-multiplexing, and in a scalable setup, wherein the number of SPADs / Pixels increase NA2, while number of TDC channels only by ~2* Thereby, the reduced number of TDC channels reduces layout area and power consumption .

[0078] Thereby, also conflicts of triggering on shared SPAD to TDC interconnects like multiple events simultaneously (Al and A2 ) can be advantageously resolved with the sensor arrangement of the present invention. In FIG. 4 such conflict is schematically demonstrated using the sensor arrangement according to the first embodiment shown in Figs. 2 and 3 above .

[0079] In FIG. 4 a further embodiment of an MxN, 4x4 SPAD array, according to the present invention is schematically shown. In this embodiment in FIG. 4 a conflict situation is shown, on multiple rows / columns . During readout the common result in multiple TDCs allows identification of the source.

[0080] In this scenario, it is not possible to identify the source ready from the start, as following scenarios would lead to the same result:

[0081] Event at Al (81, 71) and D4 (84, 74)

[0082] Event at A4 (81, 74) and DI (71, 84)

[0083] Events at all combinations of Al (81, 71) , A4 (81, 71) , DI (71, 84) and D4 (84, 74)

[0084] Thereby, two potential solutions are shown below:

[0085] 1.) skip all frames were multiple (2+) row and column TDC channels do have the same count. This will only slightly reduce the bandwidth since especially in cross talk and target generate correlated pulses .

[0086] 2 . ) add additional observation capability to readout interconnect by adding a current comparator circuitry on diagonally arranged SPADs . Current on columns and rows will scale with number of events on the same channel . 1 event -> 1 x I , 2 events -> 2 x I , Since in this scenario 2 x current is observed on upper-left to lower-right observer and no current on upper-right to lower-left current observation comparator the source of the event can be identi fied . Alternative solution based on digital logic would be a chain of full adders for diagonal arranged quench circuitries , which digitally indicates multiple events on a certain diagonal .

[0087] With such simple correction methods , the sensor arrangement according to the present invention can be advantageously used even in the event of conflicting SPAD triggers .

[0088] The embodiments in the figures may relate to preferred embodiments , while all elements and features described in connection with embodiments may be used, as far as appropriate , in combination with any other embodiment and feature as discussed herein, in particular related to any other embodiment discussed further above .

[0089] LIST OF REFERENCE SIGNS sensor arrangement 1

[0090] TDC Channel 2

[0091] TDC Channel 1 21

[0092] TDC Channel 2 22

[0093] TDC Channel 3 23

[0094] TDC Channel 4 24

[0095] TDC Channel A 25

[0096] TDC Channel B 26

[0097] TDC Channel C 27

[0098] TDC Channel D 28

[0099] SPAD+QU 3

[0100] TDC Core CLK Gen 4

[0101] 16 to 1 "OR Tree" 5

[0102] Channel elk (Nphases ) 6

[0103] Row 1 71

[0104] Row 2 72

[0105] Row 3 73

[0106] Row 4 74

[0107] Column A 81

[0108] Column B 82

[0109] Column C 83

[0110] Column B 84

Claims

CLAIMS1 . A sensor arrangement for high-resolution imaging using a shared single-photon avalanche diode ( SPAD) to time-to- digital converter ( TDC ) interconnect , comprising : a) a two-dimensional array of SPADs arranged in rows and columns , wherein each SPAD is associated with a quench circuitry ( QU) that generates a digital pulse for each SPAD event ; b ) a row interconnect and a column interconnect , wherein each QU of the SPAD array is connected to the row and column interconnects ; c ) a plurality of TDC channels , each associated with either a speci fic row or a speci fic column of the SPAD array, wherein the TDC channels are driven by a common clock generator and have N-stages , and wherein the TDC channels are configured to measure the time interval between the occurrence of a SPAD event and the clock signal ; d) synchroni zation means to ensure synchronous operation of the TDC channels associated with the rows and columns of the SPAD array; e ) a measurement means to capture the measurement results from the TDC channels associated with the rows and columns of the SPAD array; f ) a comparison means to compare the measurement results from the row and column TDC channels to identi fy the source SPAD associated with a particular SPAD event ; and g) a sorting means to allocate the identi fied SPAD event to the corresponding histogram of the source SPAD .2 . The sensor arrangement according to claim 1 , wherein the SPAD array comprises a plurality of SPADs arranged in an MxN configuration, where M and N are positive integers greater than 1 .3 . The sensor arrangement according to any one of claims 1 or 2 , wherein the quench circuitry ( QU) comprises a pulse generation circuit that generates a digital pulse of a predetermined duration in response to a SPAD event .4 . The sensor arrangement according to any one of claims 1 to 3 , wherein the NMOS transistors connected between the QU and the row and column interconnects operate as switches to selectively connect the QU to the interconnects .

5. The sensor arrangement according to any one of claims 1 to 4 , wherein the pull-up resistors connected to the row and column interconnects facilitate voltage level restoration of the interconnects .

6. The sensor arrangement according to any one of claims 1 to 5 , wherein the TDC channels are implemented using a delay line or a ring oscillator with N stages , where N is a positive integer greater than 1 .7 . The sensor arrangement according to any one of claims 1 to 6 , further comprising an of fset adj ustment means for compensating for any timing of fset between the TDC channels associated with the rows and columns of the SPAD array .8 . The sensor arrangement according to any one of claims 1 to 7 , wherein the synchroni zation means comprises a global synchroni zation signal that ensures simultaneous operation of the TDC channels associated with the rows and columns of the SPAD array .

9. The sensor arrangement according to any one of claims 1 to 8 , wherein the measurement means comprises analog-to-digital converters (ADCs ) that convert the measurement results from the TDC channels into digital values10 . The sensor arrangement according to any one of claims 1 to 9 , wherein the comparison means comprises a comparator circuit that compares the measurement results from the row and column TDC channels to determine the relative timing of the SPAD event .11 . The sensor arrangement according to any one of claims 1 to 10 , wherein the sorting means comprises a histogram memory that stores the occurrence counts of SPAD events associated with each SPAD in the SPAD array .12 . The sensor arrangement according to any one of claims 1 to 11 , wherein the transistor that connects each QU of the SPAD array to the row and column interconnects is a respective NMOS transistor and / or wherein the resistor that connects each interconnect is a pull-up resistor .13 . The sensor arrangement according to any one of claims 1 to 12 , wherein the SPAD array comprises a plurality of SPADs arranged in an MxN configuration, wherein the MxN configuration is selected from the group comprising 3x4 , 4x3 , 16X9 or 9x16 .14 . A method for detecting an event in a high-resolution imaging system using a shared single-photon avalanche diode ( SPAD) to time-to-digital converter ( TDC ) interconnect , the method comprising at least the following steps : a step a ) of providing a two-dimensional array of SPADs arranged in rows and columns , each SPAD associated with a quench circuitry ( QU) that generates a digital pulse for each SPAD event , preferably a sensor arrangement according to any one of claims 1 to 13 ;a step b ) of connecting each QU of the SPAD array to a row and column interconnect wire via a transistor and connecting the interconnect wire to a resistor ; a step c ) of associating each row and column of the SPAD array with a dedicated TDC channel , the TDC channels driven by a common clock generator with N-stages ; a step d) of synchroni zing the operation of the TDC channels associated with the rows and columns of the SPAD array; a step e ) of receiving incident photons by the SPADs , generating SPAD events , and producing digital pulses via the associated QU for each SPAD event ; a step f ) of propagating the digital pulses through the row and column interconnects to the respective TDC channels associated with the row and column of the SPAD generating the event ; a step g) of measuring the time interval between the occurrence of a SPAD event and the clock signal in each of the TDC channels ; a step h) of capturing the measurement results from the TDC channels associated with the rows and columns of the SPAD array; a step i ) of comparing the measurement results obtained from the row and column TDC channels to identi fy the source SPAD associated with the particular SPAD event ; a step j ) of sorting the identi fied SPAD event into the corresponding histogram of the source SPAD .15 . Use of a system for event detection in a high-resolution imaging device , the system comprising a sensor arrangement according to any one of claims 1 to 13 .

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