Laminated ceramic capacitor

Abstract

In this laminated ceramic capacitor, which is small-sized and has three terminals, ESL is reduced. A three-terminal type laminated ceramic capacitor 1 comprises: a laminate that is provided with an inner layer portion 11 which has a plurality of dielectric layers 14 and internal electrodes 15 alternately laminated therein, and which has a first outer layer portion 12a disposed on one side in the lamination direction of the inner layer portion 11 and has a second outer layer portion 12b2 disposed on the other side; end-face external electrodes 3 that are provided on both longitudinal end faces of the laminate 2; and lateral-face external electrodes 4 that are provided on widthwise lateral faces of the laminate. The dimension LC in the longitudinal direction is 0.1 mm ≤ LC ≤ 0.70 mm, the dimension WC in the width direction is 0.05 mm ≤ WC ≤ 0.40 mm, the dimension TC in the lamination direction is 0.10 mm ≤ TC ≤ 0.55 mm, and the second outer layer portion 12b is on the mounting surface side. When the thickness of the first outer layer portion 12a is denoted by t1, and the thickness of the second outer layer portion 12b by t2, t2 < t1 is satisfied.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Recently, reducing the impedance of electronic circuit lines has become increasingly important, particularly in mobile device products. To achieve this, three-terminal multilayer ceramic capacitors are widely used for decoupling purposes. A three-terminal multilayer ceramic capacitor includes a laminate having an inner layer section formed by alternating multiple dielectric layers each having an end face internal electrode exposed on the end face and a side face internal electrode exposed on the side face, and outer layer sections disposed on one side and the other side of the inner layer section in the lamination direction, as well as end face external electrodes disposed on the end faces and side face external electrodes disposed on the side faces (see Patent Document 1). Miniaturization of a three-terminal multilayer ceramic capacitor enables further reduction in impedance at high frequencies. The reduction in impedance due to miniaturization results from a reduction in the equivalent series inductance (ESL) of the multilayer ceramic capacitor, which is achieved by shortening the current path within the multilayer ceramic capacitor.

[0003] Japanese Patent Application Laid-Open No. 2013-201417

[0004] In recent years, multilayer ceramic capacitors have become increasingly smaller. The smaller the multilayer ceramic capacitor, the greater the effect of reducing ESL per unit current path length. The present application aims to further reduce ESL in a small, three-terminal multilayer ceramic capacitor.

[0005] In order to solve the above problems, the present invention provides a three-terminal multilayer ceramic capacitor comprising a laminate having inner layer portions in which dielectric layers and internal electrodes are alternately stacked, and a first outer layer portion arranged on one side of the stacking direction of the inner layer portions and a second outer layer portion arranged on the other side thereof, end face external electrodes provided on both end faces of the laminate in a length direction intersecting with the stacking direction, and a side face external electrode provided on at least one of the side faces of the laminate in a width direction intersecting with the stacking direction and the length direction. the lengthwise dimension LC is 0.1 mm≦LC≦0.70 mm or less, the widthwise dimension WC is 0.05 mm≦WC≦0.40 mm or less, and the lamination direction dimension TC is 0.10 mm≦TC≦0.55 mm or less, the second outer layer portion is on the mounting surface side, and when the thickness of the first outer layer portion is t1 and the thickness of the second outer layer portion is t2, t2<t1, 10 μm≦t1≦30 μm, and 0.1≦t2 / t1≦0.9.

[0006] According to the present invention, the ESL can be further reduced in a small, three-terminal multilayer ceramic capacitor.

[0007] 1 is a schematic perspective view of a multilayer ceramic capacitor 1. FIG. 2 is a cross-sectional view of a first embodiment of the multilayer ceramic capacitor 1 taken in the II-II direction in FIG. 1. FIG. 3 is a cross-sectional view of a first embodiment of the multilayer ceramic capacitor 1 taken in the III-III direction in FIG. 1. FIG. 4 is a cross-sectional view along an end face exposed internal electrode 15A of the multilayer ceramic capacitor 1. FIG. 5 is a cross-sectional view along a side face exposed internal electrode 15B of the multilayer ceramic capacitor 1. FIG. 6 is a diagram illustrating a manufacturing process of a laminate 2 in a manufacturing method of the multilayer ceramic capacitor 1. FIG. 7 is a flowchart illustrating a manufacturing method of the multilayer ceramic capacitor 1.

[0008] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present invention will be described. Fig. 1 is a schematic perspective view of the multilayer ceramic capacitor 1. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to a first embodiment taken along the II-II direction in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the III-III direction in Fig. 1.

[0009] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 is a multilayer ceramic capacitor 1 with a three-terminal structure, including a laminate 2, end surface external electrodes 3 provided on both end surfaces C of the laminate 2 in the length direction L, and side surface external electrodes 4 provided on both side surfaces B of the laminate 2 in the width direction W. The laminate 2 includes an inner layer portion 11 in which dielectric layers 14 and internal electrodes 15 are stacked, and an outer layer portion 12.

[0010] In this specification, the term indicating the orientation of the multilayer ceramic capacitor 1 refers to the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 as the stacking direction T. The direction that intersects with the stacking direction T and in which the pair of end face external electrodes 3 are provided is referred to as the length direction L. The direction that intersects with both the length direction L and the stacking direction T is referred to as the width direction W. In the embodiment, the stacking direction T, the length direction L, and the width direction W are perpendicular to one another.

[0011] In the following description, of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides of the stacking direction T will be referred to as main surfaces A, a pair of outer surfaces extending in the stacking direction T and on both sides of the width direction W will be referred to as side surfaces B, and a pair of outer surfaces extending in the stacking direction T and on both sides of the length direction L will be referred to as end surfaces C.

[0012] As shown in FIG. 2 or 3, the multilayer ceramic capacitor 1 has a length L dimension LC of 0.1 mm or more and 0.70 mm or less, a width W dimension WC of 0.05 mm or more and 0.40 mm or less, and a stacking direction T dimension TC of 0.10 mm or more and 0.55 mm or less.

[0013] Furthermore, the capacitance of the multilayer ceramic capacitor 1 is 0.022 μF to 10 μF, and preferably 1.0 μF to 2.2 μF. The ESL of the multilayer ceramic capacitor 1 is preferably 65 pH or less at 100 MHz, and preferably 50 pH or less at 1 GHz.

[0014] The capacitance of the multilayer ceramic capacitor 1 can be measured using an LCR meter (manufactured by Agilent Technologies, model number: E4980A) under conditions of 1 kHz and 0.5 Vrms. The ESL of the multilayer ceramic capacitor 1 can be calculated from the measured impedance value at a predetermined frequency using a network analyzer (manufactured by Agilent Technologies, model number: E5080A).

[0015] (Laminate 2) The laminate 2 includes an inner layer portion 11 and outer layer portions 12 disposed on both sides of the inner layer portion 11 in the stacking direction T. The laminate 2 preferably has rounded corners and ridges. A corner is a portion where three surfaces of the laminate 2 intersect, and a ridge is a portion where two surfaces of the laminate 2 intersect.

[0016] The dimensions of the laminate 2 are as shown in Figure 2 or Figure 3: the length direction L dimension LL is 0.09 mm or more and 0.69 mm or less, the width direction W dimension WL is 0.04 mm or more and 0.39 mm or less, and the stacking direction T dimension TL is 0.09 mm or more and 0.54 mm or less.

[0017] (Inner Layer Portion 11) The inner layer portion 11 is formed by laminating a plurality of dielectric layers 14 and internal electrodes 15 along the lamination direction T.

[0018] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material. The ceramic material is mainly composed of a ceramic material containing at least one of Ca, Zr, and Ti. Specifically, for example, a ceramic material containing Ca and Zr and having the general formula ABO ３ The ceramic material having such a perovskite structure is mainly composed of a ceramic material having a perovskite structure represented by the formula: BaTiO ３ (barium titanate) and CaZrO ３However, the ceramic material forming the dielectric layer 14 may contain all of Ca, Zr, and Ti as its main components.

[0019] (Internal Electrode 15) The internal electrode 15 is preferably made of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.

[0020] The internal electrode 15 has a plurality of end-exposed internal electrodes 15A and a plurality of side-exposed internal electrodes 15B arranged alternately. When there is no need to particularly distinguish between the end-exposed internal electrodes 15A and the side-exposed internal electrodes 15B, they will be collectively referred to as the internal electrode 15.

[0021] Fig. 4 is a cross-sectional view taken along an end surface exposed internal electrode 15A of the multilayer ceramic capacitor 1. Fig. 5 is a cross-sectional view taken along a side surface exposed internal electrode 15B of the multilayer ceramic capacitor 1.

[0022] (End-face-exposed internal electrode 15A) As shown in Fig. 4, the end-face-exposed internal electrode 15A extends between both end faces C in the length direction L of the laminate 2 and is spaced a certain distance from both side faces B in the width direction W. The end-face-exposed internal electrode 15A has an end-face facing portion 15Aa located in the center between both end faces C and end-face drawn portions 15Ab extending from the end-face facing portion 15Aa to both end faces C. In the embodiment, the end-face facing portion 15Aa and the end-face drawn portions 15Ab have the same dimension in the width direction W, and the end-face-exposed internal electrode 15A, including the end-face facing portion 15Aa and the end-face drawn portions 15Ab, has a substantially rectangular shape as a whole. The end-face drawn portions 15Ab extending from the end-face facing portion 15Aa to both end faces C extend to both end faces C on both sides, are exposed at the end faces C of the laminate 2, and are connected to the end-face external electrodes 3 provided on both end faces C in the length direction L of the laminate 2.

[0023] 5, the side surface exposed internal electrode 15B has a side surface facing portion 15Ba located in the center between both side surfaces B, and side surface drawn-out portions 15Bb extending from the side surface facing portion 15Ba to both side surfaces B. The side surface facing portion 15Ba is a substantially rectangular shape slightly smaller than the laminate 2, and is spaced a certain distance from both side surfaces B in the width direction W.

[0024] The dimension of the side lead portion 15Bb in the length direction L is smaller than the dimension of the side facing portion 15Ba in the length direction L. The side lead portion 15Bb extends to both side surfaces B, is exposed at the side surfaces B of the laminate 2, and is connected to the side surface external electrodes 4 provided on both side surfaces of the laminate 2 in the width direction W.

[0025] The end surface facing portion 15Aa and the side surface facing portion 15Ba face each other to form a capacitor portion.

[0026] The dielectric layer 14 is formed by alternately stacking multiple layers of a first dielectric layer 14A on which an end-face-exposed internal electrode 15A exposed on the end face C is arranged, and a second dielectric layer 14B on which a side-face-exposed internal electrode 15B exposed on a portion of the side face B is arranged.

[0027] 2 and 3 , the outer layer portion 12 is a dielectric layer disposed on the principal surface A side of the inner layer portion 11. The outer layer portion 12 is made of the same material as the dielectric layer 14 of the inner layer portion 11. The outer layer portion 12 includes a first outer layer portion 12a disposed on the first principal surface A side of the inner layer portion 11, and a second outer layer portion 12b disposed on the second principal surface A side of the inner layer portion 11. Note that when there is no need to particularly distinguish between the first outer layer portion 12a and the second outer layer portion 12b, they will be collectively referred to as the outer layer portion 12.

[0028] In this embodiment, the first outer layer portion 12 a and the second outer layer portion 12 b have different thicknesses, and when the thickness of the first outer layer portion 12 a is t1 and the thickness of the second outer layer portion 12 b is t2, the following relationship holds: t2<t1. Here, when the multilayer ceramic capacitor 1 is attached to the land 5 of the mounting board, the second outer layer portion 12 b is on the mounting surface side.

[0029] Furthermore, in the embodiment, 10 μm≦t1≦30 μm, and 0.1≦t2 / t1≦0.9.

[0030] (End Face External Electrodes 3) End face external electrodes 3 are arranged on both end faces C of the laminate 2. End face drawn portions 15Ab of the end face exposed internal electrodes 15A are connected to the end face external electrodes 3. The end face external electrodes 3 cover not only the end faces C but also parts of the main faces A and side faces B on the end face C side.

[0031] (Side surface external electrodes 4) Side surface external electrodes 4 are arranged on both side surfaces B of the laminate 2. The side surface external electrodes 4 are connected to the side surface drawn portions 15Bb of the side surface exposed internal electrodes 15B. The side surface external electrodes 4 cover not only the side surfaces B but also a portion of the side surface B side of the main surface A.

[0032] The end surface external electrode 3 and the side surface external electrode 4 include a base electrode layer 31 and a plating layer 32 disposed on the base electrode layer 31. The plating layer 32 includes a Ni (nickel) plating layer 321 disposed on the base electrode layer 31, and a Sn (tin) plating layer 322 disposed on the Ni plating layer 321. However, without being limited thereto, the end surface external electrode 3 and the side surface external electrode 4 may have a structure in which, for example, the base electrode layer 31 is made of Ni, and a Cu plating layer, a Ni plating layer, and a Sn plating layer are disposed thereon in this order.

[0033] (Manufacturing Method of Multilayer Ceramic Capacitor 1) Next, a manufacturing method of the multilayer ceramic capacitor 1 according to the embodiment will be described. Fig. 6 is a diagram illustrating the manufacturing steps of the laminate 2 in the manufacturing method of the multilayer ceramic capacitor 1. Fig. 7 is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 1.

[0034] (Internal electrode pattern forming step S1) An end-face exposed internal electrode 15A is formed with a conductive paste on a ceramic green sheet 14A' that will become the first dielectric layer 14A. Similarly, a side-face exposed internal electrode 15B is formed with a conductive paste on a ceramic green sheet 14B' that will become the second dielectric layer 14B.

[0035] The ceramic green sheets 14A' and 14B' are strip-shaped sheets formed by forming a ceramic slurry containing ceramic powder, a binder, and a solvent onto a carrier film using a die coater, gravure coater, microgravure coater, or the like.

[0036] The end-face exposed internal electrodes 15A and side-face exposed internal electrodes 15B are formed by printing, such as screen printing, gravure printing, or letterpress printing.

[0037] (Stacking step S2) Ceramic green sheets 14A' to become the first dielectric layers 14A on which the end-face exposed internal electrodes 15A are arranged and ceramic green sheets 14B' to become the second dielectric layers 14B on which the side-face exposed internal electrodes 15B are arranged are stacked alternately.

[0038] Next, a ceramic green sheet 12a' for the first outer layer portion 12a and a ceramic green sheet 12b' for the second outer layer portion 12b are arranged one above the other and thermocompression bonded to form a mother block.

[0039] In this embodiment, the ceramic green sheet 12a' for the first outer layer portion 12a and the ceramic green sheet 12b' for the second outer layer portion 12b have different thicknesses. The ceramic green sheet 12a' for the first outer layer portion 12a has a thickness t1 after firing, while the ceramic green sheet 12b' for the second outer layer portion 12b is made of the same material as the ceramic green sheet 12a' for the first outer layer portion 12a but has a different thickness, t2, after firing, which is thinner than t1. Furthermore, t1 is a thickness that satisfies 10 μm≦t1≦30 μm and 0.1≦t2 / t1≦0.9.

[0040] However, the present invention is not limited to this, and the ceramic green sheet 12b' for the second outer layer portion 12b may have a lower inorganic component ratio than the ceramic green sheet 12a' for the first outer layer portion 12a. In this case, even if the ceramic green sheet 12a' for the first outer layer portion 12a and the ceramic green sheet 12b' for the second outer layer portion 12b have the same thickness, the shrinkage rate of the second outer layer portion 12b is greater during firing, so that the second outer layer portion 12b can be made thinner than the first outer layer portion 12a after firing.

[0041] Alternatively, the ceramic green sheet 12b' for the second outer layer portion 12b may be made of the same material and of the same thickness as the ceramic green sheet 12a' for the first outer layer portion 12a, and a firing process may be further carried out before the external electrodes are formed. After firing, the second outer layer portion 12b side may be polished, thereby making the second outer layer portion 12b thinner than the first outer layer portion 12a.

[0042] (Mother Block Cutting Step S3) Next, the mother block is cut and divided in the length direction L and width direction W to manufacture a plurality of rectangular parallelepiped laminates 2.

[0043] (External electrode forming process S4) Next, side surface external electrodes 4 are formed on both side surfaces B of the laminate 2. The side surface drawn portions 15Bb of the side surface exposed internal electrodes 15B are connected to the side surface external electrodes 4. The side surface external electrodes 4 are formed so as to cover not only the side surfaces B but also part of the side surface B side of the main surface A.

[0044] Then, end surface external electrodes 3 are formed on both end surfaces C of the laminate 2. End surface drawn portions 15Ab of the end surface exposed internal electrodes 15A are connected to the end surface external electrodes 3. The end surface external electrodes 3 are formed so as to cover not only the end surfaces C but also parts of the main surfaces A and side surfaces B on the end surface C side.

[0045] (Firing step S5) Then, the laminate is heated in a nitrogen atmosphere at a set firing temperature for a predetermined time, thereby firing the end surface external electrodes 3 and the side surface external electrodes 4 onto the laminate 2, and producing the multilayer ceramic capacitor 1 shown in FIG.

[0046] (Taping) When transporting the multilayer ceramic capacitors 1 manufactured in this manner, for example, they are accommodated one by one in each of a plurality of accommodation recesses formed in a carrier tape. Then, the openings of the accommodation recesses are covered with a top tape, and the multilayer ceramic capacitors 1 are transported in the state of a packaging tape.

[0047] When the multilayer ceramic capacitors 1 are accommodated in the accommodation recesses of the carrier tape, it is preferable that all of the multilayer ceramic capacitors 1 are accommodated so that they face the same direction. Therefore, for example, when accommodating the multilayer ceramic capacitors 1, the multilayer ceramic capacitors 1 are placed in a magnetic field. This causes the amount of magnetic flux to differ between the first outer layer portion 12a and the second outer layer portion 12b. By selecting the orientation of the lamination direction T of the multilayer ceramic capacitors 1 based on this difference in magnetic flux, the multilayer ceramic capacitors 1 can be accommodated in the accommodation recesses in a fixed direction.

[0048] Alternatively, the first outer layer portion 12a and the second outer layer portion 12b have different thicknesses, and therefore have different shades of color. The orientation of the lamination direction T of the multilayer ceramic capacitor 1 can be determined from the difference in shade.

[0049] Furthermore, to indicate that the second outer layer 12b, which is thinner than the first outer layer 12a, is the mounting surface, the main surface A on the second outer layer 12b side may be printed with, for example, the letter "m" to indicate that it is the mounting side.

[0050] Furthermore, the second outer layer portion 12b, which is the mounting surface, is thinner than the first outer layer portion 12a, and therefore has sharper corners than the first outer layer portion 12a. Therefore, the second outer layer portion 12b, which is the mounting surface, may be identified based on the difference in roundness of the corners.

[0051] (Mounting) The multilayer ceramic capacitor 1 is mounted on a substrate, for example, as follows. First, the top tape is peeled off while the carrier tape is moved in one direction. In this state, the multilayer ceramic capacitor 1 is removed from the storage recess of the carrier tape using a mounter nozzle and mounted via solder onto lands 5 (shown in FIG. 1) made of a conductive material and formed on the surface of the substrate. In this case, the second outer layer 12b is the surface that will be mounted on the substrate.

[0052] Here, if the thickness of the first outer layer portion 12a is t1<10 μm, there is a possibility that the multilayer ceramic capacitor 1 will be damaged by the impact of the mounter nozzle when placing the capacitor on the land 5. However, in the embodiment, 10 μm≦t1, so the multilayer ceramic capacitor 1 is less likely to be damaged by this impact. Furthermore, if the thickness of the first outer layer portion 12a is 30 μm<t1, the area of ​​the inner layer portion 11 will be narrowed, which is undesirable as it reduces the capacitance of the multilayer ceramic capacitor 1. However, in the embodiment, t1≦30 μm, so the area of ​​the inner layer portion 11 will not be narrowed more than necessary.

[0053] Effect of the Embodiment In the end-face-exposed internal electrode 15A (through electrode) of the multilayer ceramic capacitor 1 arranged on the substrate in this manner, a current flows from the substrate through the end-face external electrode 3, and charge accumulates. In this embodiment, the first external layer portion 12a and the second external layer portion 12b have different thicknesses. When the thickness of the first external layer portion 12a is t1 and the thickness of the second external layer portion 12b is t2, t2<t1 holds. Furthermore, when the multilayer ceramic capacitor 1 is attached to the land 5 of the mounting substrate, the second external layer portion 12b is on the mounting surface side. That is, the second external layer portion 12b on the mounting surface side of the multilayer ceramic capacitor 1 is thinner. Therefore, the length in the lamination direction T of the end-face external electrode 3 on the end surface of the second external layer portion 12b is also shortened. Therefore, the path of the current flowing from the substrate to the end-face-exposed internal electrode 15A is shortened. This reduces the ESL of the multilayer ceramic capacitor 1.

[0054] The thickness t1 of the first outer layer portion 12a is in the range of 10 μm≦t1≦30 μm.

[0055] Unlike the embodiment, if the thickness t1 of the first outer layer portion 12a is t1<10 μm, there is a possibility that the multilayer ceramic capacitor 1 will not be able to withstand the impact when it is sucked by a mounter nozzle and placed on the land 5 during mounting on a mounting board. However, in the embodiment, 10 μm≦t1 is satisfied, and therefore the capacitor has the strength to withstand the impact during mounting.

[0056] Furthermore, when the thickness t1 of the first outer layer portion 12a is 30 μm<t1, in a laminate 2 having a dimension TL in the stacking direction T of 0.54 mm or less, the first outer layer portion 12a becomes thick and the inner layer portion 11 becomes relatively thin. However, in this embodiment, t1≦30 μm, so that the thickness of the inner layer portion 11 can be ensured to be sufficient.

[0057] The ratio of the thickness t2 of the second outer layer portion 12b to the thickness t1 of the first outer layer portion 12a is 0.1≦t2 / t1≦0.9.

[0058] Unlike the embodiment, when 0.9<t2 / t1, the effect of improving ESL is small. However, in the embodiment, t2 / t1≦0.9, so that a sufficient effect of improving ESL can be obtained.

[0059] If t2 / t1<0.1, it is difficult to form the second outer layer portion 12b uniformly. However, in this embodiment, since 0.1≦t2 / t1, the second outer layer portion 12b can be formed uniformly.

[0060] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible, including the following, for example.

[0061] <1> A three-terminal multilayer ceramic capacitor comprising: a laminate having inner layer portions in which dielectric layers and internal electrodes are alternately laminated multiple times, and first outer layer portions arranged on one side of a lamination direction of the inner layer portions and second outer layer portions arranged on the other side; end face external electrodes provided on both end faces in a length direction intersecting the lamination direction of the laminate; and a side face external electrode provided on at least one of the side faces in a width direction intersecting the lamination direction and the length direction of the laminate, wherein the multilayer ceramic capacitor has: a dimension LC in the length direction of 0.1 mm≦LC≦0.70 mm or less; a dimension WC in the width direction of 0.05 mm≦WC≦0.40 mm or less; and a dimension TC in the lamination direction of 0.10 mm≦TC≦0.55 mm or less; the second outer layer portion is on the mounting surface side; and when a thickness of the first outer layer portion is t1 and a thickness of the second outer layer portion is t2, t2<t1.

[0062] <2> The multilayer ceramic capacitor according to <1>, wherein 10 μm≦t1≦30 μm and 0.1≦t2 / t1≦0.9.

[0063] <3> The multilayer ceramic capacitor according to <1> or <2>, having a capacitance of 0.022 μF or more and 10 μF or less.

[0064] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the equivalent series inductance is 65 pH or less at 100 MHz and 50 pH or less at 1 GHz.

[0065] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 End face external electrode 4 Side face external electrode 11 Inner layer portion 12a First outer layer portion 12 Outer layer portion 12a First outer layer portion 12b Second outer layer portion 14 Dielectric layer 14A First dielectric layer 14B Second dielectric layer 15 Internal electrode 15A End face exposed internal electrode 15Aa End face opposing portion 15Ab End face drawn portion 15B Side face exposed internal electrode 15Ba Side face opposing portion 15Bb Side face drawn portion

Claims

1. A three-terminal multilayer ceramic capacitor comprising: a laminate having an inner layer portion in which a plurality of dielectric layers and internal electrodes are alternately laminated, and a first outer layer portion arranged on one side of a lamination direction of the inner layer portion and a second outer layer portion arranged on the other side; end face external electrodes provided on both end faces in a length direction intersecting with the lamination direction of the laminate; and a side face external electrode provided on at least one of the side faces in a width direction intersecting with the lamination direction of the laminate, wherein the length direction dimension LC is 0.1 mm≦LC≦0.70 mm or less, the width direction dimension WC is 0.05 mm≦WC≦0.40 mm or less, and the lamination direction dimension TC is 0.10 mm≦TC≦0.55 mm or less, the second outer layer portion is on the mounting surface side, and when the thickness of the first outer layer portion is t1 and the thickness of the second outer layer portion is t2, the relationship t2<t1 is satisfied.

2. The multilayer ceramic capacitor according to claim 1, wherein 10 μm≦t1≦30 μm and 0.1≦t2 / t1≦0.

9.

3. The multilayer ceramic capacitor according to claim 1 or 2, having a capacitance of 0.022 μF or more and 10 μF or less.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, having an equivalent series inductance of 65 pH or less at 100 MHz and 50 pH or less at 1 GHz.

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